arch/arm/mach-pxa/zeus.c

   1 /*
   2  *  Support for the Arcom ZEUS.
   3  *
   4  *  Copyright (C) 2006 Arcom Control Systems Ltd.
   5  *
   6  *  Loosely based on Arcom's 2.6.16.28.
   7  *  Maintained by Marc Zyngier <maz@misterjones.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/cpufreq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/pm.h>
  18 #include <linux/gpio.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/dm9000.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/pxa2xx_spi.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/pxa-i2c.h>
  29 #include <linux/i2c/pca953x.h>
  30 #include <linux/apm-emulation.h>
  31 #include <linux/can/platform/mcp251x.h>
  32
  33 #include <asm/mach-types.h>
  34 #include <asm/suspend.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37
  38 #include <mach/pxa2xx-regs.h>
  39 #include <mach/regs-uart.h>
  40 #include <mach/ohci.h>
  41 #include <mach/mmc.h>
  42 #include <mach/pxa27x-udc.h>
  43 #include <mach/udc.h>
  44 #include <mach/pxafb.h>
  45 #include <mach/mfp-pxa27x.h>
  46 #include <mach/pm.h>
  47 #include <mach/audio.h>
  48 #include <mach/arcom-pcmcia.h>
  49 #include <mach/zeus.h>
  50 #include <mach/smemc.h>
  51
  52 #include "generic.h"
  53
  54 /*
  55  * Interrupt handling
  56  */
  57
  58 static unsigned long zeus_irq_enabled_mask;
  59 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
  60 static const int zeus_isa_irq_map[] = {
  61         0,              /* ISA irq #0, invalid */
  62         0,              /* ISA irq #1, invalid */
  63         0,              /* ISA irq #2, invalid */
  64         1 << 0,         /* ISA irq #3 */
  65         1 << 1,         /* ISA irq #4 */
  66         1 << 2,         /* ISA irq #5 */
  67         1 << 3,         /* ISA irq #6 */
  68         1 << 4,         /* ISA irq #7 */
  69         0,              /* ISA irq #8, invalid */
  70         0,              /* ISA irq #9, invalid */
  71         1 << 5,         /* ISA irq #10 */
  72         1 << 6,         /* ISA irq #11 */
  73         1 << 7,         /* ISA irq #12 */
  74 };
  75
  76 static inline int zeus_irq_to_bitmask(unsigned int irq)
  77 {
  78         return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
  79 }
  80
  81 static inline int zeus_bit_to_irq(int bit)
  82 {
  83         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
  84 }
  85
  86 static void zeus_ack_irq(struct irq_data *d)
  87 {
  88         __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
  89 }
  90
  91 static void zeus_mask_irq(struct irq_data *d)
  92 {
  93         zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
  94 }
  95
  96 static void zeus_unmask_irq(struct irq_data *d)
  97 {
  98         zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
  99 }
 100
 101 static inline unsigned long zeus_irq_pending(void)
 102 {
 103         return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
 104 }
 105
 106 static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
 107 {
 108         unsigned long pending;
 109
 110         pending = zeus_irq_pending();
 111         do {
 112                 /* we're in a chained irq handler,
 113                  * so ack the interrupt by hand */
 114                 desc->irq_data.chip->irq_ack(&desc->irq_data);
 115
 116                 if (likely(pending)) {
 117                         irq = zeus_bit_to_irq(__ffs(pending));
 118                         generic_handle_irq(irq);
 119                 }
 120                 pending = zeus_irq_pending();
 121         } while (pending);
 122 }
 123
 124 static struct irq_chip zeus_irq_chip = {
 125         .name           = "ISA",
 126         .irq_ack        = zeus_ack_irq,
 127         .irq_mask       = zeus_mask_irq,
 128         .irq_unmask     = zeus_unmask_irq,
 129 };
 130
 131 static void __init zeus_init_irq(void)
 132 {
 133         int level;
 134         int isa_irq;
 135
 136         pxa27x_init_irq();
 137
 138         /* Peripheral IRQs. It would be nice to move those inside driver
 139            configuration, but it is not supported at the moment. */
 140         irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
 141         irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
 142         irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
 143         irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
 144                          IRQ_TYPE_EDGE_FALLING);
 145         irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
 146
 147         /* Setup ISA IRQs */
 148         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
 149                 isa_irq = zeus_bit_to_irq(level);
 150                 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
 151                                          handle_edge_irq);
 152                 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
 153         }
 154
 155         irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
 156         irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
 157 }
 158
 159
 160 /*
 161  * Platform devices
 162  */
 163
 164 /* Flash */
 165 static struct resource zeus_mtd_resources[] = {
 166         [0] = { /* NOR Flash (up to 64MB) */
 167                 .start  = ZEUS_FLASH_PHYS,
 168                 .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
 169                 .flags  = IORESOURCE_MEM,
 170         },
 171         [1] = { /* SRAM */
 172                 .start  = ZEUS_SRAM_PHYS,
 173                 .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
 174                 .flags  = IORESOURCE_MEM,
 175         },
 176 };
 177
 178 static struct physmap_flash_data zeus_flash_data[] = {
 179         [0] = {
 180                 .width          = 2,
 181                 .parts          = NULL,
 182                 .nr_parts       = 0,
 183         },
 184 };
 185
 186 static struct platform_device zeus_mtd_devices[] = {
 187         [0] = {
 188                 .name           = "physmap-flash",
 189                 .id             = 0,
 190                 .dev            = {
 191                         .platform_data = &zeus_flash_data[0],
 192                 },
 193                 .resource       = &zeus_mtd_resources[0],
 194                 .num_resources  = 1,
 195         },
 196 };
 197
 198 /* Serial */
 199 static struct resource zeus_serial_resources[] = {
 200         {
 201                 .start  = 0x10000000,
 202                 .end    = 0x1000000f,
 203                 .flags  = IORESOURCE_MEM,
 204         },
 205         {
 206                 .start  = 0x10800000,
 207                 .end    = 0x1080000f,
 208                 .flags  = IORESOURCE_MEM,
 209         },
 210         {
 211                 .start  = 0x11000000,
 212                 .end    = 0x1100000f,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         {
 216                 .start  = 0x40100000,
 217                 .end    = 0x4010001f,
 218                 .flags  = IORESOURCE_MEM,
 219         },
 220         {
 221                 .start  = 0x40200000,
 222                 .end    = 0x4020001f,
 223                 .flags  = IORESOURCE_MEM,
 224         },
 225         {
 226                 .start  = 0x40700000,
 227                 .end    = 0x4070001f,
 228                 .flags  = IORESOURCE_MEM,
 229         },
 230 };
 231
 232 static struct plat_serial8250_port serial_platform_data[] = {
 233         /* External UARTs */
 234         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
 235         { /* COM1 */
 236                 .mapbase        = 0x10000000,
 237                 .irq            = gpio_to_irq(ZEUS_UARTA_GPIO),
 238                 .irqflags       = IRQF_TRIGGER_RISING,
 239                 .uartclk        = 14745600,
 240                 .regshift       = 1,
 241                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 242                 .iotype         = UPIO_MEM,
 243         },
 244         { /* COM2 */
 245                 .mapbase        = 0x10800000,
 246                 .irq            = gpio_to_irq(ZEUS_UARTB_GPIO),
 247                 .irqflags       = IRQF_TRIGGER_RISING,
 248                 .uartclk        = 14745600,
 249                 .regshift       = 1,
 250                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 251                 .iotype         = UPIO_MEM,
 252         },
 253         { /* COM3 */
 254                 .mapbase        = 0x11000000,
 255                 .irq            = gpio_to_irq(ZEUS_UARTC_GPIO),
 256                 .irqflags       = IRQF_TRIGGER_RISING,
 257                 .uartclk        = 14745600,
 258                 .regshift       = 1,
 259                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 260                 .iotype         = UPIO_MEM,
 261         },
 262         { /* COM4 */
 263                 .mapbase        = 0x11800000,
 264                 .irq            = gpio_to_irq(ZEUS_UARTD_GPIO),
 265                 .irqflags       = IRQF_TRIGGER_RISING,
 266                 .uartclk        = 14745600,
 267                 .regshift       = 1,
 268                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 269                 .iotype         = UPIO_MEM,
 270         },
 271         /* Internal UARTs */
 272         { /* FFUART */
 273                 .membase        = (void *)&FFUART,
 274                 .mapbase        = __PREG(FFUART),
 275                 .irq            = IRQ_FFUART,
 276                 .uartclk        = 921600 * 16,
 277                 .regshift       = 2,
 278                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 279                 .iotype         = UPIO_MEM,
 280         },
 281         { /* BTUART */
 282                 .membase        = (void *)&BTUART,
 283                 .mapbase        = __PREG(BTUART),
 284                 .irq            = IRQ_BTUART,
 285                 .uartclk        = 921600 * 16,
 286                 .regshift       = 2,
 287                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 288                 .iotype         = UPIO_MEM,
 289         },
 290         { /* STUART */
 291                 .membase        = (void *)&STUART,
 292                 .mapbase        = __PREG(STUART),
 293                 .irq            = IRQ_STUART,
 294                 .uartclk        = 921600 * 16,
 295                 .regshift       = 2,
 296                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 297                 .iotype         = UPIO_MEM,
 298         },
 299         { },
 300 };
 301
 302 static struct platform_device zeus_serial_device = {
 303         .name = "serial8250",
 304         .id   = PLAT8250_DEV_PLATFORM,
 305         .dev  = {
 306                 .platform_data = serial_platform_data,
 307         },
 308         .num_resources  = ARRAY_SIZE(zeus_serial_resources),
 309         .resource       = zeus_serial_resources,
 310 };
 311
 312 /* Ethernet */
 313 static struct resource zeus_dm9k0_resource[] = {
 314         [0] = {
 315                 .start = ZEUS_ETH0_PHYS,
 316                 .end   = ZEUS_ETH0_PHYS + 1,
 317                 .flags = IORESOURCE_MEM
 318         },
 319         [1] = {
 320                 .start = ZEUS_ETH0_PHYS + 2,
 321                 .end   = ZEUS_ETH0_PHYS + 3,
 322                 .flags = IORESOURCE_MEM
 323         },
 324         [2] = {
 325                 .start = gpio_to_irq(ZEUS_ETH0_GPIO),
 326                 .end   = gpio_to_irq(ZEUS_ETH0_GPIO),
 327                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 328         },
 329 };
 330
 331 static struct resource zeus_dm9k1_resource[] = {
 332         [0] = {
 333                 .start = ZEUS_ETH1_PHYS,
 334                 .end   = ZEUS_ETH1_PHYS + 1,
 335                 .flags = IORESOURCE_MEM
 336         },
 337         [1] = {
 338                 .start = ZEUS_ETH1_PHYS + 2,
 339                 .end   = ZEUS_ETH1_PHYS + 3,
 340                 .flags = IORESOURCE_MEM,
 341         },
 342         [2] = {
 343                 .start = gpio_to_irq(ZEUS_ETH1_GPIO),
 344                 .end   = gpio_to_irq(ZEUS_ETH1_GPIO),
 345                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 346         },
 347 };
 348
 349 static struct dm9000_plat_data zeus_dm9k_platdata = {
 350         .flags          = DM9000_PLATF_16BITONLY,
 351 };
 352
 353 static struct platform_device zeus_dm9k0_device = {
 354         .name           = "dm9000",
 355         .id             = 0,
 356         .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
 357         .resource       = zeus_dm9k0_resource,
 358         .dev            = {
 359                 .platform_data = &zeus_dm9k_platdata,
 360         }
 361 };
 362
 363 static struct platform_device zeus_dm9k1_device = {
 364         .name           = "dm9000",
 365         .id             = 1,
 366         .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
 367         .resource       = zeus_dm9k1_resource,
 368         .dev            = {
 369                 .platform_data = &zeus_dm9k_platdata,
 370         }
 371 };
 372
 373 /* External SRAM */
 374 static struct resource zeus_sram_resource = {
 375         .start          = ZEUS_SRAM_PHYS,
 376         .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
 377         .flags          = IORESOURCE_MEM,
 378 };
 379
 380 static struct platform_device zeus_sram_device = {
 381         .name           = "pxa2xx-8bit-sram",
 382         .id             = 0,
 383         .num_resources  = 1,
 384         .resource       = &zeus_sram_resource,
 385 };
 386
 387 /* SPI interface on SSP3 */
 388 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
 389         .num_chipselect = 1,
 390         .enable_dma     = 1,
 391 };
 392
 393 /* CAN bus on SPI */
 394 static int zeus_mcp2515_setup(struct spi_device *sdev)
 395 {
 396         int err;
 397
 398         err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown");
 399         if (err)
 400                 return err;
 401
 402         err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1);
 403         if (err) {
 404                 gpio_free(ZEUS_CAN_SHDN_GPIO);
 405                 return err;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int zeus_mcp2515_transceiver_enable(int enable)
 412 {
 413         gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable);
 414         return 0;
 415 }
 416
 417 static struct mcp251x_platform_data zeus_mcp2515_pdata = {
 418         .oscillator_frequency   = 16*1000*1000,
 419         .board_specific_setup   = zeus_mcp2515_setup,
 420         .power_enable           = zeus_mcp2515_transceiver_enable,
 421 };
 422
 423 static struct spi_board_info zeus_spi_board_info[] = {
 424         [0] = {
 425                 .modalias       = "mcp2515",
 426                 .platform_data  = &zeus_mcp2515_pdata,
 427                 .irq            = gpio_to_irq(ZEUS_CAN_GPIO),
 428                 .max_speed_hz   = 1*1000*1000,
 429                 .bus_num        = 3,
 430                 .mode           = SPI_MODE_0,
 431                 .chip_select    = 0,
 432         },
 433 };
 434
 435 /* Leds */
 436 static struct gpio_led zeus_leds[] = {
 437         [0] = {
 438                 .name            = "zeus:yellow:1",
 439                 .default_trigger = "heartbeat",
 440                 .gpio            = ZEUS_EXT0_GPIO(3),
 441                 .active_low      = 1,
 442         },
 443         [1] = {
 444                 .name            = "zeus:yellow:2",
 445                 .default_trigger = "default-on",
 446                 .gpio            = ZEUS_EXT0_GPIO(4),
 447                 .active_low      = 1,
 448         },
 449         [2] = {
 450                 .name            = "zeus:yellow:3",
 451                 .default_trigger = "default-on",
 452                 .gpio            = ZEUS_EXT0_GPIO(5),
 453                 .active_low      = 1,
 454         },
 455 };
 456
 457 static struct gpio_led_platform_data zeus_leds_info = {
 458         .leds           = zeus_leds,
 459         .num_leds       = ARRAY_SIZE(zeus_leds),
 460 };
 461
 462 static struct platform_device zeus_leds_device = {
 463         .name           = "leds-gpio",
 464         .id             = -1,
 465         .dev            = {
 466                 .platform_data  = &zeus_leds_info,
 467         },
 468 };
 469
 470 static void zeus_cf_reset(int state)
 471 {
 472         u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
 473
 474         if (state)
 475                 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
 476         else
 477                 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
 478
 479         __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
 480 }
 481
 482 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
 483         .cd_gpio        = ZEUS_CF_CD_GPIO,
 484         .rdy_gpio       = ZEUS_CF_RDY_GPIO,
 485         .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
 486         .reset          = zeus_cf_reset,
 487 };
 488
 489 static struct platform_device zeus_pcmcia_device = {
 490         .name           = "zeus-pcmcia",
 491         .id             = -1,
 492         .dev            = {
 493                 .platform_data  = &zeus_pcmcia_info,
 494         },
 495 };
 496
 497 static struct resource zeus_max6369_resource = {
 498         .start          = ZEUS_CPLD_EXTWDOG_PHYS,
 499         .end            = ZEUS_CPLD_EXTWDOG_PHYS,
 500         .flags          = IORESOURCE_MEM,
 501 };
 502
 503 struct platform_device zeus_max6369_device = {
 504         .name           = "max6369_wdt",
 505         .id             = -1,
 506         .resource       = &zeus_max6369_resource,
 507         .num_resources  = 1,
 508 };
 509
 510 static struct platform_device *zeus_devices[] __initdata = {
 511         &zeus_serial_device,
 512         &zeus_mtd_devices[0],
 513         &zeus_dm9k0_device,
 514         &zeus_dm9k1_device,
 515         &zeus_sram_device,
 516         &zeus_leds_device,
 517         &zeus_pcmcia_device,
 518         &zeus_max6369_device,
 519 };
 520
 521 /* AC'97 */
 522 static pxa2xx_audio_ops_t zeus_ac97_info = {
 523         .reset_gpio = 95,
 524 };
 525
 526
 527 /*
 528  * USB host
 529  */
 530
 531 static int zeus_ohci_init(struct device *dev)
 532 {
 533         int err;
 534
 535         /* Switch on port 2. */
 536         if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
 537                 dev_err(dev, "Can't request USB2_PWREN\n");
 538                 return err;
 539         }
 540
 541         if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
 542                 gpio_free(ZEUS_USB2_PWREN_GPIO);
 543                 dev_err(dev, "Can't enable USB2_PWREN\n");
 544                 return err;
 545         }
 546
 547         /* Port 2 is shared between host and client interface. */
 548         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 549
 550         return 0;
 551 }
 552
 553 static void zeus_ohci_exit(struct device *dev)
 554 {
 555         /* Power-off port 2 */
 556         gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
 557         gpio_free(ZEUS_USB2_PWREN_GPIO);
 558 }
 559
 560 static struct pxaohci_platform_data zeus_ohci_platform_data = {
 561         .port_mode      = PMM_NPS_MODE,
 562         /* Clear Power Control Polarity Low and set Power Sense
 563          * Polarity Low. Supply power to USB ports. */
 564         .flags          = ENABLE_PORT_ALL | POWER_SENSE_LOW,
 565         .init           = zeus_ohci_init,
 566         .exit           = zeus_ohci_exit,
 567 };
 568
 569 /*
 570  * Flat Panel
 571  */
 572
 573 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
 574 {
 575         gpio_set_value(ZEUS_LCD_EN_GPIO, on);
 576 }
 577
 578 static void zeus_backlight_power(int on)
 579 {
 580         gpio_set_value(ZEUS_BKLEN_GPIO, on);
 581 }
 582
 583 static int zeus_setup_fb_gpios(void)
 584 {
 585         int err;
 586
 587         if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
 588                 goto out_err;
 589
 590         if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
 591                 goto out_err_lcd;
 592
 593         if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
 594                 goto out_err_lcd;
 595
 596         if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
 597                 goto out_err_bkl;
 598
 599         return 0;
 600
 601 out_err_bkl:
 602         gpio_free(ZEUS_BKLEN_GPIO);
 603 out_err_lcd:
 604         gpio_free(ZEUS_LCD_EN_GPIO);
 605 out_err:
 606         return err;
 607 }
 608
 609 static struct pxafb_mode_info zeus_fb_mode_info[] = {
 610         {
 611                 .pixclock       = 39722,
 612
 613                 .xres           = 640,
 614                 .yres           = 480,
 615
 616                 .bpp            = 16,
 617
 618                 .hsync_len      = 63,
 619                 .left_margin    = 16,
 620                 .right_margin   = 81,
 621
 622                 .vsync_len      = 2,
 623                 .upper_margin   = 12,
 624                 .lower_margin   = 31,
 625
 626                 .sync           = 0,
 627         },
 628 };
 629
 630 static struct pxafb_mach_info zeus_fb_info = {
 631         .modes                  = zeus_fb_mode_info,
 632         .num_modes              = 1,
 633         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 634         .pxafb_lcd_power        = zeus_lcd_power,
 635         .pxafb_backlight_power  = zeus_backlight_power,
 636 };
 637
 638 /*
 639  * MMC/SD Device
 640  *
 641  * The card detect interrupt isn't debounced so we delay it by 250ms
 642  * to give the card a chance to fully insert/eject.
 643  */
 644
 645 static struct pxamci_platform_data zeus_mci_platform_data = {
 646         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
 647         .detect_delay_ms        = 250,
 648         .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
 649         .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
 650         .gpio_card_ro_invert    = 1,
 651         .gpio_power             = -1
 652 };
 653
 654 /*
 655  * USB Device Controller
 656  */
 657 static void zeus_udc_command(int cmd)
 658 {
 659         switch (cmd) {
 660         case PXA2XX_UDC_CMD_DISCONNECT:
 661                 pr_info("zeus: disconnecting USB client\n");
 662                 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 663                 break;
 664
 665         case PXA2XX_UDC_CMD_CONNECT:
 666                 pr_info("zeus: connecting USB client\n");
 667                 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
 668                 break;
 669         }
 670 }
 671
 672 static struct pxa2xx_udc_mach_info zeus_udc_info = {
 673         .udc_command = zeus_udc_command,
 674 };
 675
 676 #ifdef CONFIG_PM
 677 static void zeus_power_off(void)
 678 {
 679         local_irq_disable();
 680         cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
 681 }
 682 #else
 683 #define zeus_power_off   NULL
 684 #endif
 685
 686 #ifdef CONFIG_APM_EMULATION
 687 static void zeus_get_power_status(struct apm_power_info *info)
 688 {
 689         /* Power supply is always present */
 690         info->ac_line_status    = APM_AC_ONLINE;
 691         info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
 692         info->battery_flag      = APM_BATTERY_FLAG_NOT_PRESENT;
 693 }
 694
 695 static inline void zeus_setup_apm(void)
 696 {
 697         apm_get_power_status = zeus_get_power_status;
 698 }
 699 #else
 700 static inline void zeus_setup_apm(void)
 701 {
 702 }
 703 #endif
 704
 705 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
 706                              unsigned ngpio, void *context)
 707 {
 708         int i;
 709         u8 pcb_info = 0;
 710
 711         for (i = 0; i < 8; i++) {
 712                 int pcb_bit = gpio + i + 8;
 713
 714                 if (gpio_request(pcb_bit, "pcb info")) {
 715                         dev_err(&client->dev, "Can't request pcb info %d\n", i);
 716                         continue;
 717                 }
 718
 719                 if (gpio_direction_input(pcb_bit)) {
 720                         dev_err(&client->dev, "Can't read pcb info %d\n", i);
 721                         gpio_free(pcb_bit);
 722                         continue;
 723                 }
 724
 725                 pcb_info |= !!gpio_get_value(pcb_bit) << i;
 726
 727                 gpio_free(pcb_bit);
 728         }
 729
 730         dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
 731                  pcb_info >> 4, pcb_info & 0xf);
 732
 733         return 0;
 734 }
 735
 736 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
 737         [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
 738         [1] = {
 739                 .gpio_base      = ZEUS_EXT1_GPIO_BASE,
 740                 .setup          = zeus_get_pcb_info,
 741         },
 742         [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
 743 };
 744
 745 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
 746         {
 747                 I2C_BOARD_INFO("pca9535",       0x21),
 748                 .platform_data  = &zeus_pca953x_pdata[0],
 749         },
 750         {
 751                 I2C_BOARD_INFO("pca9535",       0x22),
 752                 .platform_data  = &zeus_pca953x_pdata[1],
 753         },
 754         {
 755                 I2C_BOARD_INFO("pca9535",       0x20),
 756                 .platform_data  = &zeus_pca953x_pdata[2],
 757                 .irq            = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
 758         },
 759         { I2C_BOARD_INFO("lm75a",       0x48) },
 760         { I2C_BOARD_INFO("24c01",       0x50) },
 761         { I2C_BOARD_INFO("isl1208",     0x6f) },
 762 };
 763
 764 static mfp_cfg_t zeus_pin_config[] __initdata = {
 765         /* AC97 */
 766         GPIO28_AC97_BITCLK,
 767         GPIO29_AC97_SDATA_IN_0,
 768         GPIO30_AC97_SDATA_OUT,
 769         GPIO31_AC97_SYNC,
 770
 771         GPIO15_nCS_1,
 772         GPIO78_nCS_2,
 773         GPIO80_nCS_4,
 774         GPIO33_nCS_5,
 775
 776         GPIO22_GPIO,
 777         GPIO32_MMC_CLK,
 778         GPIO92_MMC_DAT_0,
 779         GPIO109_MMC_DAT_1,
 780         GPIO110_MMC_DAT_2,
 781         GPIO111_MMC_DAT_3,
 782         GPIO112_MMC_CMD,
 783
 784         GPIO88_USBH1_PWR,
 785         GPIO89_USBH1_PEN,
 786         GPIO119_USBH2_PWR,
 787         GPIO120_USBH2_PEN,
 788
 789         GPIO86_LCD_LDD_16,
 790         GPIO87_LCD_LDD_17,
 791
 792         GPIO102_GPIO,
 793         GPIO104_CIF_DD_2,
 794         GPIO105_CIF_DD_1,
 795
 796         GPIO81_SSP3_TXD,
 797         GPIO82_SSP3_RXD,
 798         GPIO83_SSP3_SFRM,
 799         GPIO84_SSP3_SCLK,
 800
 801         GPIO48_nPOE,
 802         GPIO49_nPWE,
 803         GPIO50_nPIOR,
 804         GPIO51_nPIOW,
 805         GPIO85_nPCE_1,
 806         GPIO54_nPCE_2,
 807         GPIO79_PSKTSEL,
 808         GPIO55_nPREG,
 809         GPIO56_nPWAIT,
 810         GPIO57_nIOIS16,
 811         GPIO36_GPIO,            /* CF CD */
 812         GPIO97_GPIO,            /* CF PWREN */
 813         GPIO99_GPIO,            /* CF RDY */
 814 };
 815
 816 /*
 817  * DM9k MSCx settings:  SRAM, 16 bits
 818  *                      17 cycles delay first access
 819  *                       5 cycles delay next access
 820  *                      13 cycles recovery time
 821  *                      faster device
 822  */
 823 #define DM9K_MSC_VALUE          0xe4c9
 824
 825 static void __init zeus_init(void)
 826 {
 827         u16 dm9000_msc = DM9K_MSC_VALUE;
 828         u32 msc0, msc1;
 829
 830         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
 831         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 832
 833         /* Fix timings for dm9000s (CS1/CS2)*/
 834         msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
 835         msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
 836         __raw_writel(msc0, MSC0);
 837         __raw_writel(msc1, MSC1);
 838
 839         pm_power_off = zeus_power_off;
 840         zeus_setup_apm();
 841
 842         pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
 843
 844         platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
 845
 846         pxa_set_ohci_info(&zeus_ohci_platform_data);
 847
 848         if (zeus_setup_fb_gpios())
 849                 pr_err("Failed to setup fb gpios\n");
 850         else
 851                 pxa_set_fb_info(NULL, &zeus_fb_info);
 852
 853         pxa_set_mci_info(&zeus_mci_platform_data);
 854         pxa_set_udc_info(&zeus_udc_info);
 855         pxa_set_ac97_info(&zeus_ac97_info);
 856         pxa_set_i2c_info(NULL);
 857         i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
 858         pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
 859         spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
 860 }
 861
 862 static struct map_desc zeus_io_desc[] __initdata = {
 863         {
 864                 .virtual = ZEUS_CPLD_VERSION,
 865                 .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
 866                 .length  = 0x1000,
 867                 .type    = MT_DEVICE,
 868         },
 869         {
 870                 .virtual = ZEUS_CPLD_ISA_IRQ,
 871                 .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
 872                 .length  = 0x1000,
 873                 .type    = MT_DEVICE,
 874         },
 875         {
 876                 .virtual = ZEUS_CPLD_CONTROL,
 877                 .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
 878                 .length  = 0x1000,
 879                 .type    = MT_DEVICE,
 880         },
 881         {
 882                 .virtual = ZEUS_PC104IO,
 883                 .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
 884                 .length  = 0x00800000,
 885                 .type    = MT_DEVICE,
 886         },
 887 };
 888
 889 static void __init zeus_map_io(void)
 890 {
 891         pxa27x_map_io();
 892
 893         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
 894
 895         /* Clear PSPR to ensure a full restart on wake-up. */
 896         PMCR = PSPR = 0;
 897
 898         /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
 899         OSCC |= OSCC_OON;
 900
 901         /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
 902          * float chip selects and PCMCIA */
 903         PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
 904 }
 905
 906 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
 907         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
 908         .boot_params    = 0xa0000100,
 909         .map_io         = zeus_map_io,
 910         .nr_irqs        = ZEUS_NR_IRQS,
 911         .init_irq       = zeus_init_irq,
 912         .timer          = &pxa_timer,
 913         .init_machine   = zeus_init,
 914 MACHINE_END
 915