arch/arm/mach-pxa/include/mach/balloon3.h

   1 /*
   2  *  linux/include/asm-arm/arch-pxa/balloon3.h
   3  *
   4  *  Authors:    Nick Bane and Wookey
   5  *  Created:    Oct, 2005
   6  *  Copyright:  Toby Churchill Ltd
   7  *  Cribbed from mainstone.c, by Nicholas Pitre
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef ASM_ARCH_BALLOON3_H
  15 #define ASM_ARCH_BALLOON3_H
  16
  17 enum balloon3_features {
  18         BALLOON3_FEATURE_OHCI,
  19         BALLOON3_FEATURE_MMC,
  20         BALLOON3_FEATURE_CF,
  21         BALLOON3_FEATURE_AUDIO,
  22         BALLOON3_FEATURE_TOPPOLY,
  23 };
  24
  25 #define BALLOON3_FPGA_PHYS      PXA_CS4_PHYS
  26 #define BALLOON3_FPGA_VIRT      (0xf1000000)    /* as per balloon2 */
  27 #define BALLOON3_FPGA_LENGTH    0x01000000
  28
  29 /* FPGA/CPLD registers */
  30 #define BALLOON3_PCMCIA0_REG            (BALLOON3_FPGA_VIRT + 0x00e00008)
  31 /* fixme - same for now */
  32 #define BALLOON3_PCMCIA1_REG            (BALLOON3_FPGA_VIRT + 0x00e00008)
  33 #define BALLOON3_NANDIO_IO_REG          (BALLOON3_FPGA_VIRT + 0x00e00000)
  34 /* fpga/cpld interrupt control register */
  35 #define BALLOON3_INT_CONTROL_REG        (BALLOON3_FPGA_VIRT + 0x00e0000C)
  36 #define BALLOON3_NANDIO_CTL2_REG        (BALLOON3_FPGA_VIRT + 0x00e00010)
  37 #define BALLOON3_NANDIO_CTL_REG         (BALLOON3_FPGA_VIRT + 0x00e00014)
  38 #define BALLOON3_VERSION_REG            (BALLOON3_FPGA_VIRT + 0x00e0001c)
  39
  40 #define BALLOON3_SAMOSA_ADDR_REG        (BALLOON3_FPGA_VIRT + 0x00c00000)
  41 #define BALLOON3_SAMOSA_DATA_REG        (BALLOON3_FPGA_VIRT + 0x00c00004)
  42 #define BALLOON3_SAMOSA_STATUS_REG      (BALLOON3_FPGA_VIRT + 0x00c0001c)
  43
  44 /* GPIOs for irqs */
  45 #define BALLOON3_GPIO_AUX_NIRQ          (94)
  46 #define BALLOON3_GPIO_CODEC_IRQ         (95)
  47
  48 /* Timer and Idle LED locations */
  49 #define BALLOON3_GPIO_LED_NAND          (9)
  50 #define BALLOON3_GPIO_LED_IDLE          (10)
  51
  52 /* backlight control */
  53 #define BALLOON3_GPIO_RUN_BACKLIGHT     (99)
  54
  55 #define BALLOON3_GPIO_S0_CD             (105)
  56
  57 /* FPGA Interrupt Mask/Acknowledge Register */
  58 #define BALLOON3_INT_S0_IRQ             (1 << 0)  /* PCMCIA 0 IRQ */
  59 #define BALLOON3_INT_S0_STSCHG          (1 << 1)  /* PCMCIA 0 status changed */
  60
  61 /* CF Status Register */
  62 #define BALLOON3_PCMCIA_nIRQ            (1 << 0)  /* IRQ / ready signal */
  63 #define BALLOON3_PCMCIA_nSTSCHG_BVD1    (1 << 1)
  64                                         /* VDD sense / card status changed */
  65
  66 /* CF control register (write) */
  67 #define BALLOON3_PCMCIA_RESET           (1 << 0)   /* Card reset signal */
  68 #define BALLOON3_PCMCIA_ENABLE          (1 << 1)
  69 #define BALLOON3_PCMCIA_ADD_ENABLE      (1 << 2)
  70
  71 /* CPLD (and FPGA) interface definitions */
  72 #define CPLD_LCD0_DATA_SET             0x00
  73 #define CPLD_LCD0_DATA_CLR             0x10
  74 #define CPLD_LCD0_COMMAND_SET          0x01
  75 #define CPLD_LCD0_COMMAND_CLR          0x11
  76 #define CPLD_LCD1_DATA_SET             0x02
  77 #define CPLD_LCD1_DATA_CLR             0x12
  78 #define CPLD_LCD1_COMMAND_SET          0x03
  79 #define CPLD_LCD1_COMMAND_CLR          0x13
  80
  81 #define CPLD_MISC_SET                  0x07
  82 #define CPLD_MISC_CLR                  0x17
  83 #define CPLD_MISC_LOON_NRESET_BIT      0
  84 #define CPLD_MISC_LOON_UNSUSP_BIT      1
  85 #define CPLD_MISC_RUN_5V_BIT           2
  86 #define CPLD_MISC_CHG_D0_BIT           3
  87 #define CPLD_MISC_CHG_D1_BIT           4
  88 #define CPLD_MISC_DAC_NCS_BIT          5
  89
  90 #define CPLD_LCD_SET                   0x08
  91 #define CPLD_LCD_CLR                   0x18
  92 #define CPLD_LCD_BACKLIGHT_EN_0_BIT    0
  93 #define CPLD_LCD_BACKLIGHT_EN_1_BIT    1
  94 #define CPLD_LCD_LED_RED_BIT           4
  95 #define CPLD_LCD_LED_GREEN_BIT         5
  96 #define CPLD_LCD_NRESET_BIT            7
  97
  98 #define CPLD_LCD_RO_SET                0x09
  99 #define CPLD_LCD_RO_CLR                0x19
 100 #define CPLD_LCD_RO_LCD0_nWAIT_BIT     0
 101 #define CPLD_LCD_RO_LCD1_nWAIT_BIT     1
 102
 103 #define CPLD_SERIAL_SET                0x0a
 104 #define CPLD_SERIAL_CLR                0x1a
 105 #define CPLD_SERIAL_GSM_RI_BIT         0
 106 #define CPLD_SERIAL_GSM_CTS_BIT        1
 107 #define CPLD_SERIAL_GSM_DTR_BIT        2
 108 #define CPLD_SERIAL_LPR_CTS_BIT        3
 109 #define CPLD_SERIAL_TC232_CTS_BIT      4
 110 #define CPLD_SERIAL_TC232_DSR_BIT      5
 111
 112 #define CPLD_SROUTING_SET              0x0b
 113 #define CPLD_SROUTING_CLR              0x1b
 114 #define CPLD_SROUTING_MSP430_LPR       0
 115 #define CPLD_SROUTING_MSP430_TC232     1
 116 #define CPLD_SROUTING_MSP430_GSM       2
 117 #define CPLD_SROUTING_LOON_LPR         (0 << 4)
 118 #define CPLD_SROUTING_LOON_TC232       (1 << 4)
 119 #define CPLD_SROUTING_LOON_GSM         (2 << 4)
 120
 121 #define CPLD_AROUTING_SET              0x0c
 122 #define CPLD_AROUTING_CLR              0x1c
 123 #define CPLD_AROUTING_MIC2PHONE_BIT    0
 124 #define CPLD_AROUTING_PHONE2INT_BIT    1
 125 #define CPLD_AROUTING_PHONE2EXT_BIT    2
 126 #define CPLD_AROUTING_LOONL2INT_BIT    3
 127 #define CPLD_AROUTING_LOONL2EXT_BIT    4
 128 #define CPLD_AROUTING_LOONR2PHONE_BIT  5
 129 #define CPLD_AROUTING_LOONR2INT_BIT    6
 130 #define CPLD_AROUTING_LOONR2EXT_BIT    7
 131
 132 /* Balloon3 Interrupts */
 133 #define BALLOON3_IRQ(x)         (IRQ_BOARD_START + (x))
 134
 135 #define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
 136 #define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
 137
 138 #define BALLOON3_AUX_NIRQ       IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
 139 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 140 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 141
 142 extern int balloon3_has(enum balloon3_features feature);
 143
 144 #endif