arch/arm/mach-pxa/corgi_lcd.c

   1 /*
   2  * linux/arch/arm/mach-pxa/corgi_lcd.c
   3  *
   4  * Corgi/Spitz LCD Specific Code
   5  *
   6  * Copyright (C) 2005 Richard Purdie
   7  *
   8  * Connectivity:
   9  *   Corgi - LCD to ATI Imageon w100 (Wallaby)
  10  *   Spitz - LCD to PXA Framebuffer
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  */
  17
  18 #include <linux/delay.h>
  19 #include <linux/kernel.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/module.h>
  22 #include <linux/string.h>
  23 #include <asm/arch/akita.h>
  24 #include <asm/arch/corgi.h>
  25 #include <asm/hardware.h>
  26 #include <asm/arch/pxa-regs.h>
  27 #include <asm/arch/sharpsl.h>
  28 #include <asm/arch/spitz.h>
  29 #include <asm/hardware/scoop.h>
  30 #include <asm/mach/sharpsl_param.h>
  31 #include "generic.h"
  32
  33 /* Register Addresses */
  34 #define RESCTL_ADRS     0x00
  35 #define PHACTRL_ADRS    0x01
  36 #define DUTYCTRL_ADRS   0x02
  37 #define POWERREG0_ADRS  0x03
  38 #define POWERREG1_ADRS  0x04
  39 #define GPOR3_ADRS      0x05
  40 #define PICTRL_ADRS     0x06
  41 #define POLCTRL_ADRS    0x07
  42
  43 /* Register Bit Definitions */
  44 #define RESCTL_QVGA     0x01
  45 #define RESCTL_VGA      0x00
  46
  47 #define POWER1_VW_ON    0x01  /* VW Supply FET ON */
  48 #define POWER1_GVSS_ON  0x02  /* GVSS(-8V) Power Supply ON */
  49 #define POWER1_VDD_ON   0x04  /* VDD(8V),SVSS(-4V) Power Supply ON */
  50
  51 #define POWER1_VW_OFF   0x00  /* VW Supply FET OFF */
  52 #define POWER1_GVSS_OFF 0x00  /* GVSS(-8V) Power Supply OFF */
  53 #define POWER1_VDD_OFF  0x00  /* VDD(8V),SVSS(-4V) Power Supply OFF */
  54
  55 #define POWER0_COM_DCLK 0x01  /* COM Voltage DC Bias DAC Serial Data Clock */
  56 #define POWER0_COM_DOUT 0x02  /* COM Voltage DC Bias DAC Serial Data Out */
  57 #define POWER0_DAC_ON   0x04  /* DAC Power Supply ON */
  58 #define POWER0_COM_ON   0x08  /* COM Power Supply ON */
  59 #define POWER0_VCC5_ON  0x10  /* VCC5 Power Supply ON */
  60
  61 #define POWER0_DAC_OFF  0x00  /* DAC Power Supply OFF */
  62 #define POWER0_COM_OFF  0x00  /* COM Power Supply OFF */
  63 #define POWER0_VCC5_OFF 0x00  /* VCC5 Power Supply OFF */
  64
  65 #define PICTRL_INIT_STATE      0x01
  66 #define PICTRL_INIOFF          0x02
  67 #define PICTRL_POWER_DOWN      0x04
  68 #define PICTRL_COM_SIGNAL_OFF  0x08
  69 #define PICTRL_DAC_SIGNAL_OFF  0x10
  70
  71 #define POLCTRL_SYNC_POL_FALL  0x01
  72 #define POLCTRL_EN_POL_FALL    0x02
  73 #define POLCTRL_DATA_POL_FALL  0x04
  74 #define POLCTRL_SYNC_ACT_H     0x08
  75 #define POLCTRL_EN_ACT_L       0x10
  76
  77 #define POLCTRL_SYNC_POL_RISE  0x00
  78 #define POLCTRL_EN_POL_RISE    0x00
  79 #define POLCTRL_DATA_POL_RISE  0x00
  80 #define POLCTRL_SYNC_ACT_L     0x00
  81 #define POLCTRL_EN_ACT_H       0x00
  82
  83 #define PHACTRL_PHASE_MANUAL   0x01
  84 #define DEFAULT_PHAD_QVGA     (9)
  85 #define DEFAULT_COMADJ        (125)
  86
  87 /*
  88  * This is only a psuedo I2C interface. We can't use the standard kernel
  89  * routines as the interface is write only. We just assume the data is acked...
  90  */
  91 static void lcdtg_ssp_i2c_send(u8 data)
  92 {
  93         corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
  94         udelay(10);
  95 }
  96
  97 static void lcdtg_i2c_send_bit(u8 data)
  98 {
  99         lcdtg_ssp_i2c_send(data);
 100         lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
 101         lcdtg_ssp_i2c_send(data);
 102 }
 103
 104 static void lcdtg_i2c_send_start(u8 base)
 105 {
 106         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
 107         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
 108         lcdtg_ssp_i2c_send(base);
 109 }
 110
 111 static void lcdtg_i2c_send_stop(u8 base)
 112 {
 113         lcdtg_ssp_i2c_send(base);
 114         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
 115         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
 116 }
 117
 118 static void lcdtg_i2c_send_byte(u8 base, u8 data)
 119 {
 120         int i;
 121         for (i = 0; i < 8; i++) {
 122                 if (data & 0x80)
 123                         lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
 124                 else
 125                         lcdtg_i2c_send_bit(base);
 126                 data <<= 1;
 127         }
 128 }
 129
 130 static void lcdtg_i2c_wait_ack(u8 base)
 131 {
 132         lcdtg_i2c_send_bit(base);
 133 }
 134
 135 static void lcdtg_set_common_voltage(u8 base_data, u8 data)
 136 {
 137         /* Set Common Voltage to M62332FP via I2C */
 138         lcdtg_i2c_send_start(base_data);
 139         lcdtg_i2c_send_byte(base_data, 0x9c);
 140         lcdtg_i2c_wait_ack(base_data);
 141         lcdtg_i2c_send_byte(base_data, 0x00);
 142         lcdtg_i2c_wait_ack(base_data);
 143         lcdtg_i2c_send_byte(base_data, data);
 144         lcdtg_i2c_wait_ack(base_data);
 145         lcdtg_i2c_send_stop(base_data);
 146 }
 147
 148 /* Set Phase Adjust */
 149 static void lcdtg_set_phadadj(int mode)
 150 {
 151         int adj;
 152         switch(mode) {
 153                 case 480:
 154                 case 640:
 155                         /* Setting for VGA */
 156                         adj = sharpsl_param.phadadj;
 157                         if (adj < 0) {
 158                                 adj = PHACTRL_PHASE_MANUAL;
 159                         } else {
 160                                 adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
 161                         }
 162                         break;
 163                 case 240:
 164                 case 320:
 165                 default:
 166                         /* Setting for QVGA */
 167                         adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
 168                         break;
 169         }
 170
 171         corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
 172 }
 173
 174 static int lcd_inited;
 175
 176 void corgi_lcdtg_hw_init(int mode)
 177 {
 178         if (!lcd_inited) {
 179                 int comadj;
 180
 181                 /* Initialize Internal Logic & Port */
 182                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
 183                                 | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
 184
 185                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
 186                                 | POWER0_COM_OFF | POWER0_VCC5_OFF);
 187
 188                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
 189
 190                 /* VDD(+8V), SVSS(-4V) ON */
 191                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
 192                 mdelay(3);
 193
 194                 /* DAC ON */
 195                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
 196                                 | POWER0_COM_OFF | POWER0_VCC5_OFF);
 197
 198                 /* INIB = H, INI = L  */
 199                 /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
 200                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
 201
 202                 /* Set Common Voltage */
 203                 comadj = sharpsl_param.comadj;
 204                 if (comadj < 0)
 205                         comadj = DEFAULT_COMADJ;
 206                 lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
 207
 208                 /* VCC5 ON, DAC ON */
 209                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
 210                                 POWER0_COM_OFF | POWER0_VCC5_ON);
 211
 212                 /* GVSS(-8V) ON, VDD ON */
 213                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
 214                 mdelay(2);
 215
 216                 /* COM SIGNAL ON (PICTL[3] = L) */
 217                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
 218
 219                 /* COM ON, DAC ON, VCC5_ON */
 220                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
 221                                 | POWER0_COM_ON | POWER0_VCC5_ON);
 222
 223                 /* VW ON, GVSS ON, VDD ON */
 224                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
 225
 226                 /* Signals output enable */
 227                 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
 228
 229                 /* Set Phase Adjust */
 230                 lcdtg_set_phadadj(mode);
 231
 232                 /* Initialize for Input Signals from ATI */
 233                 corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
 234                                 | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
 235                 udelay(1000);
 236
 237                 lcd_inited=1;
 238         } else {
 239                 lcdtg_set_phadadj(mode);
 240         }
 241
 242         switch(mode) {
 243                 case 480:
 244                 case 640:
 245                         /* Set Lcd Resolution (VGA) */
 246                         corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
 247                         break;
 248                 case 240:
 249                 case 320:
 250                 default:
 251                         /* Set Lcd Resolution (QVGA) */
 252                         corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
 253                         break;
 254         }
 255 }
 256
 257 void corgi_lcdtg_suspend(void)
 258 {
 259         /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
 260         mdelay(34);
 261
 262         /* (1)VW OFF */
 263         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
 264
 265         /* (2)COM OFF */
 266         corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
 267         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
 268
 269         /* (3)Set Common Voltage Bias 0V */
 270         lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
 271
 272         /* (4)GVSS OFF */
 273         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
 274
 275         /* (5)VCC5 OFF */
 276         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
 277
 278         /* (6)Set PDWN, INIOFF, DACOFF */
 279         corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
 280                         PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
 281
 282         /* (7)DAC OFF */
 283         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
 284
 285         /* (8)VDD OFF */
 286         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
 287
 288         lcd_inited = 0;
 289 }
 290