arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39
  40 #include <asm/mach/time.h>
  41 #include <plat/dmtimer.h>
  42 #include <asm/localtimer.h>
  43 #include <asm/sched_clock.h>
  44 #include <plat/common.h>
  45 #include <plat/omap_hwmod.h>
  46 #include <plat/omap_device.h>
  47 #include <plat/omap-pm.h>
  48
  49 #include "powerdomain.h"
  50
  51 /* Parent clocks, eventually these will come from the clock framework */
  52
  53 #define OMAP2_MPU_SOURCE        "sys_ck"
  54 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  55 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  56 #define OMAP2_32K_SOURCE        "func_32k_ck"
  57 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  58 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  59
  60 #ifdef CONFIG_OMAP_32K_TIMER
  61 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  62 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  63 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  64 #define OMAP3_SECURE_TIMER      12
  65 #else
  66 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  67 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  68 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  69 #define OMAP3_SECURE_TIMER      1
  70 #endif
  71
  72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  73 #define MAX_GPTIMER_ID          12
  74
  75 static u32 sys_timer_reserved;
  76
  77 /* Clockevent code */
  78
  79 static struct omap_dm_timer clkev;
  80 static struct clock_event_device clockevent_gpt;
  81
  82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  83 {
  84         struct clock_event_device *evt = &clockevent_gpt;
  85
  86         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  87
  88         evt->event_handler(evt);
  89         return IRQ_HANDLED;
  90 }
  91
  92 static struct irqaction omap2_gp_timer_irq = {
  93         .name           = "gp_timer",
  94         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  95         .handler        = omap2_gp_timer_interrupt,
  96 };
  97
  98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  99                                          struct clock_event_device *evt)
 100 {
 101         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 102                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 103
 104         return 0;
 105 }
 106
 107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 108                                     struct clock_event_device *evt)
 109 {
 110         u32 period;
 111
 112         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 113
 114         switch (mode) {
 115         case CLOCK_EVT_MODE_PERIODIC:
 116                 period = clkev.rate / HZ;
 117                 period -= 1;
 118                 /* Looks like we need to first set the load value separately */
 119                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 120                                       0xffffffff - period, OMAP_TIMER_POSTED);
 121                 __omap_dm_timer_load_start(&clkev,
 122                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 123                                         0xffffffff - period, OMAP_TIMER_POSTED);
 124                 break;
 125         case CLOCK_EVT_MODE_ONESHOT:
 126                 break;
 127         case CLOCK_EVT_MODE_UNUSED:
 128         case CLOCK_EVT_MODE_SHUTDOWN:
 129         case CLOCK_EVT_MODE_RESUME:
 130                 break;
 131         }
 132 }
 133
 134 static struct clock_event_device clockevent_gpt = {
 135         .name           = "gp_timer",
 136         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 137         .shift          = 32,
 138         .set_next_event = omap2_gp_timer_set_next_event,
 139         .set_mode       = omap2_gp_timer_set_mode,
 140 };
 141
 142 /**
 143  * omap_dm_timer_get_errata - get errata flags for a timer
 144  *
 145  * Get the timer errata flags that are specific to the OMAP device being used.
 146  */
 147 u32 __init omap_dm_timer_get_errata(void)
 148 {
 149         if (cpu_is_omap24xx())
 150                 return 0;
 151
 152         return OMAP_TIMER_ERRATA_I103_I767;
 153 }
 154
 155 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 156                                                 int gptimer_id,
 157                                                 const char *fck_source,
 158                                                 int posted)
 159 {
 160         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 161         struct omap_hwmod *oh;
 162         size_t size;
 163         int res = 0;
 164
 165         sprintf(name, "timer%d", gptimer_id);
 166         omap_hwmod_setup_one(name);
 167         oh = omap_hwmod_lookup(name);
 168         if (!oh)
 169                 return -ENODEV;
 170
 171         timer->irq = oh->mpu_irqs[0].irq;
 172         timer->phys_base = oh->slaves[0]->addr->pa_start;
 173         size = oh->slaves[0]->addr->pa_end - timer->phys_base;
 174
 175         /* Static mapping, never released */
 176         timer->io_base = ioremap(timer->phys_base, size);
 177         if (!timer->io_base)
 178                 return -ENXIO;
 179
 180         /* After the dmtimer is using hwmod these clocks won't be needed */
 181         sprintf(name, "gpt%d_fck", gptimer_id);
 182         timer->fclk = clk_get(NULL, name);
 183         if (IS_ERR(timer->fclk))
 184                 return -ENODEV;
 185
 186         omap_hwmod_enable(oh);
 187
 188         sys_timer_reserved |= (1 << (gptimer_id - 1));
 189
 190         if (gptimer_id != 12) {
 191                 struct clk *src;
 192
 193                 src = clk_get(NULL, fck_source);
 194                 if (IS_ERR(src)) {
 195                         res = -EINVAL;
 196                 } else {
 197                         res = __omap_dm_timer_set_source(timer->fclk, src);
 198                         if (IS_ERR_VALUE(res))
 199                                 pr_warning("%s: timer%i cannot set source\n",
 200                                                 __func__, gptimer_id);
 201                         clk_put(src);
 202                 }
 203         }
 204         __omap_dm_timer_init_regs(timer);
 205         __omap_dm_timer_reset(timer, 1, 1);
 206
 207         if (posted)
 208                 __omap_dm_timer_enable_posted(timer);
 209
 210         /* Check that the intended posted configuration matches the actual */
 211         if (posted != timer->posted)
 212                 return -EINVAL;
 213
 214         timer->rate = clk_get_rate(timer->fclk);
 215         timer->reserved = 1;
 216
 217         return res;
 218 }
 219
 220 static void __init omap2_gp_clockevent_init(int gptimer_id,
 221                                                 const char *fck_source)
 222 {
 223         int res;
 224
 225         clkev.errata = omap_dm_timer_get_errata();
 226
 227         /*
 228          * For clock-event timers we never read the timer counter and
 229          * so we are not impacted by errata i103 and i767. Therefore,
 230          * we can safely ignore this errata for clock-event timers.
 231          */
 232         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 233
 234         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source,
 235                                      OMAP_TIMER_POSTED);
 236         BUG_ON(res);
 237
 238         omap2_gp_timer_irq.dev_id = (void *)&clkev;
 239         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 240
 241         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 242
 243         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 244                                      clockevent_gpt.shift);
 245         clockevent_gpt.max_delta_ns =
 246                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 247         clockevent_gpt.min_delta_ns =
 248                 clockevent_delta2ns(3, &clockevent_gpt);
 249                 /* Timer internal resynch latency. */
 250
 251         clockevent_gpt.cpumask = cpumask_of(0);
 252         clockevents_register_device(&clockevent_gpt);
 253
 254         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 255                 gptimer_id, clkev.rate);
 256 }
 257
 258 /* Clocksource code */
 259
 260 #ifdef CONFIG_OMAP_32K_TIMER
 261 /*
 262  * When 32k-timer is enabled, don't use GPTimer for clocksource
 263  * instead, just leave default clocksource which uses the 32k
 264  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 265  */
 266
 267 static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
 268 {
 269         omap_init_clocksource_32k();
 270 }
 271
 272 #else
 273
 274 static struct omap_dm_timer clksrc;
 275
 276 /*
 277  * clocksource
 278  */
 279 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 280 {
 281         return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 282                                                      OMAP_TIMER_NONPOSTED);
 283 }
 284
 285 static struct clocksource clocksource_gpt = {
 286         .name           = "gp_timer",
 287         .rating         = 300,
 288         .read           = clocksource_read_cycles,
 289         .mask           = CLOCKSOURCE_MASK(32),
 290         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 291 };
 292
 293 static u32 notrace dmtimer_read_sched_clock(void)
 294 {
 295         if (clksrc.reserved)
 296                 return __omap_dm_timer_read_counter(&clksrc,
 297                                                     OMAP_TIMER_NONPOSTED);
 298
 299         return 0;
 300 }
 301
 302 /* Setup free-running counter for clocksource */
 303 static void __init omap2_gp_clocksource_init(int gptimer_id,
 304                                                 const char *fck_source)
 305 {
 306         int res;
 307
 308         clksrc.errata = omap_dm_timer_get_errata();
 309
 310         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source,
 311                                      OMAP_TIMER_NONPOSTED);
 312         BUG_ON(res);
 313
 314         pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 315                 gptimer_id, clksrc.rate);
 316
 317         __omap_dm_timer_load_start(&clksrc,
 318                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 319                                    OMAP_TIMER_NONPOSTED);
 320         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
 321
 322         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 323                 pr_err("Could not register clocksource %s\n",
 324                         clocksource_gpt.name);
 325 }
 326 #endif
 327
 328 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
 329                                 clksrc_nr, clksrc_src)                  \
 330 static void __init omap##name##_timer_init(void)                        \
 331 {                                                                       \
 332         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
 333         omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
 334 }
 335
 336 #define OMAP_SYS_TIMER(name)                                            \
 337 struct sys_timer omap##name##_timer = {                                 \
 338         .init   = omap##name##_timer_init,                              \
 339 };
 340
 341 #ifdef CONFIG_ARCH_OMAP2
 342 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
 343 OMAP_SYS_TIMER(2)
 344 #endif
 345
 346 #ifdef CONFIG_ARCH_OMAP3
 347 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
 348 OMAP_SYS_TIMER(3)
 349 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 350                         2, OMAP3_MPU_SOURCE)
 351 OMAP_SYS_TIMER(3_secure)
 352 #endif
 353
 354 #ifdef CONFIG_ARCH_OMAP4
 355 static void __init omap4_timer_init(void)
 356 {
 357 #ifdef CONFIG_LOCAL_TIMERS
 358         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 359         BUG_ON(!twd_base);
 360 #endif
 361         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 362         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
 363 }
 364 OMAP_SYS_TIMER(4)
 365 #endif
 366
 367 /**
 368  * omap2_dm_timer_set_src - change the timer input clock source
 369  * @pdev:       timer platform device pointer
 370  * @source:     array index of parent clock source
 371  */
 372 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
 373 {
 374         int ret;
 375         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 376         struct clk *fclk, *parent;
 377         char *parent_name = NULL;
 378
 379         fclk = clk_get(&pdev->dev, "fck");
 380         if (IS_ERR_OR_NULL(fclk)) {
 381                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
 382                                 __func__, __LINE__);
 383                 return -EINVAL;
 384         }
 385
 386         switch (source) {
 387         case OMAP_TIMER_SRC_SYS_CLK:
 388                 parent_name = "sys_ck";
 389                 break;
 390
 391         case OMAP_TIMER_SRC_32_KHZ:
 392                 parent_name = "32k_ck";
 393                 break;
 394
 395         case OMAP_TIMER_SRC_EXT_CLK:
 396                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
 397                         parent_name = "alt_ck";
 398                         break;
 399                 }
 400                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
 401                         __func__, __LINE__);
 402                 clk_put(fclk);
 403                 return -EINVAL;
 404         }
 405
 406         parent = clk_get(&pdev->dev, parent_name);
 407         if (IS_ERR_OR_NULL(parent)) {
 408                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
 409                         __func__, __LINE__, parent_name);
 410                 clk_put(fclk);
 411                 return -EINVAL;
 412         }
 413
 414         ret = clk_set_parent(fclk, parent);
 415         if (IS_ERR_VALUE(ret)) {
 416                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
 417                         __func__, parent_name);
 418                 ret = -EINVAL;
 419         }
 420
 421         clk_put(parent);
 422         clk_put(fclk);
 423
 424         return ret;
 425 }
 426
 427 /**
 428  * omap_timer_init - build and register timer device with an
 429  * associated timer hwmod
 430  * @oh: timer hwmod pointer to be used to build timer device
 431  * @user:       parameter that can be passed from calling hwmod API
 432  *
 433  * Called by omap_hwmod_for_each_by_class to register each of the timer
 434  * devices present in the system. The number of timer devices is known
 435  * by parsing through the hwmod database for a given class name. At the
 436  * end of function call memory is allocated for timer device and it is
 437  * registered to the framework ready to be proved by the driver.
 438  */
 439 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 440 {
 441         int id;
 442         int ret = 0;
 443         char *name = "omap_timer";
 444         struct dmtimer_platform_data *pdata;
 445         struct platform_device *pdev;
 446         struct omap_timer_capability_dev_attr *timer_dev_attr;
 447         struct powerdomain *pwrdm;
 448
 449         pr_debug("%s: %s\n", __func__, oh->name);
 450
 451         /* on secure device, do not register secure timer */
 452         timer_dev_attr = oh->dev_attr;
 453         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 454                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 455                         return ret;
 456
 457         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 458         if (!pdata) {
 459                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 460                 return -ENOMEM;
 461         }
 462
 463         /*
 464          * Extract the IDs from name field in hwmod database
 465          * and use the same for constructing ids' for the
 466          * timer devices. In a way, we are avoiding usage of
 467          * static variable witin the function to do the same.
 468          * CAUTION: We have to be careful and make sure the
 469          * name in hwmod database does not change in which case
 470          * we might either make corresponding change here or
 471          * switch back static variable mechanism.
 472          */
 473         sscanf(oh->name, "timer%2d", &id);
 474
 475         pdata->set_timer_src = omap2_dm_timer_set_src;
 476         pdata->timer_ip_version = oh->class->rev;
 477
 478         /* Mark clocksource and clockevent timers as reserved */
 479         if ((sys_timer_reserved >> (id - 1)) & 0x1)
 480                 pdata->reserved = 1;
 481
 482         pdata->timer_errata = omap_dm_timer_get_errata();
 483         pwrdm = omap_hwmod_get_pwrdm(oh);
 484         pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
 485 #ifdef CONFIG_PM
 486         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 487 #endif
 488         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 489                                  NULL, 0, 0);
 490
 491         if (IS_ERR(pdev)) {
 492                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 493                         __func__, name, oh->name);
 494                 ret = -EINVAL;
 495         }
 496
 497         kfree(pdata);
 498
 499         return ret;
 500 }
 501
 502 /**
 503  * omap2_dm_timer_init - top level regular device initialization
 504  *
 505  * Uses dedicated hwmod api to parse through hwmod database for
 506  * given class name and then build and register the timer device.
 507  */
 508 static int __init omap2_dm_timer_init(void)
 509 {
 510         int ret;
 511
 512         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 513         if (unlikely(ret)) {
 514                 pr_err("%s: device registration failed.\n", __func__);
 515                 return -EINVAL;
 516         }
 517
 518         return 0;
 519 }
 520 arch_initcall(omap2_dm_timer_init);