3f7aa624692080a6893c5bfc1be6678ca98ed1f2
[pandora-kernel.git] / arch / arm / mach-omap2 / timer.c
1 /*
2  * linux/arch/arm/mach-omap2/timer.c
3  *
4  * OMAP2 GP timer support.
5  *
6  * Copyright (C) 2009 Nokia Corporation
7  *
8  * Update to use new clocksource/clockevent layers
9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10  * Copyright (C) 2007 MontaVista Software, Inc.
11  *
12  * Original driver:
13  * Copyright (C) 2005 Nokia Corporation
14  * Author: Paul Mundt <paul.mundt@nokia.com>
15  *         Juha Yrjölä <juha.yrjola@nokia.com>
16  * OMAP Dual-mode timer framework support by Timo Teras
17  *
18  * Some parts based off of TI's 24xx code:
19  *
20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
21  *
22  * Roughly modelled after the OMAP1 MPU timer code.
23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24  *
25  * This file is subject to the terms and conditions of the GNU General Public
26  * License. See the file "COPYING" in the main directory of this archive
27  * for more details.
28  */
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
39
40 #include <asm/mach/time.h>
41 #include <plat/dmtimer.h>
42 #include <asm/localtimer.h>
43 #include <asm/sched_clock.h>
44 #include <plat/common.h>
45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h>
47 #include <plat/omap-pm.h>
48
49 #include "powerdomain.h"
50
51 /* Parent clocks, eventually these will come from the clock framework */
52
53 #define OMAP2_MPU_SOURCE        "sys_ck"
54 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
55 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
56 #define OMAP2_32K_SOURCE        "func_32k_ck"
57 #define OMAP3_32K_SOURCE        "omap_32k_fck"
58 #define OMAP4_32K_SOURCE        "sys_32k_ck"
59
60 #ifdef CONFIG_OMAP_32K_TIMER
61 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
62 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
63 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
64 #define OMAP3_SECURE_TIMER      12
65 #else
66 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
67 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
68 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
69 #define OMAP3_SECURE_TIMER      1
70 #endif
71
72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
73 #define MAX_GPTIMER_ID          12
74
75 static u32 sys_timer_reserved;
76
77 /* Clockevent code */
78
79 static struct omap_dm_timer clkev;
80 static struct clock_event_device clockevent_gpt;
81
82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
83 {
84         struct clock_event_device *evt = &clockevent_gpt;
85
86         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
87
88         evt->event_handler(evt);
89         return IRQ_HANDLED;
90 }
91
92 static struct irqaction omap2_gp_timer_irq = {
93         .name           = "gp_timer",
94         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
95         .handler        = omap2_gp_timer_interrupt,
96 };
97
98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
99                                          struct clock_event_device *evt)
100 {
101         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
102                                                 0xffffffff - cycles, 1);
103
104         return 0;
105 }
106
107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
108                                     struct clock_event_device *evt)
109 {
110         u32 period;
111
112         __omap_dm_timer_stop(&clkev, 1, clkev.rate);
113
114         switch (mode) {
115         case CLOCK_EVT_MODE_PERIODIC:
116                 period = clkev.rate / HZ;
117                 period -= 1;
118                 /* Looks like we need to first set the load value separately */
119                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
120                                         0xffffffff - period, 1);
121                 __omap_dm_timer_load_start(&clkev,
122                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
123                                                 0xffffffff - period, 1);
124                 break;
125         case CLOCK_EVT_MODE_ONESHOT:
126                 break;
127         case CLOCK_EVT_MODE_UNUSED:
128         case CLOCK_EVT_MODE_SHUTDOWN:
129         case CLOCK_EVT_MODE_RESUME:
130                 break;
131         }
132 }
133
134 static struct clock_event_device clockevent_gpt = {
135         .name           = "gp_timer",
136         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
137         .shift          = 32,
138         .set_next_event = omap2_gp_timer_set_next_event,
139         .set_mode       = omap2_gp_timer_set_mode,
140 };
141
142 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
143                                                 int gptimer_id,
144                                                 const char *fck_source)
145 {
146         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
147         struct omap_hwmod *oh;
148         size_t size;
149         int res = 0;
150
151         sprintf(name, "timer%d", gptimer_id);
152         omap_hwmod_setup_one(name);
153         oh = omap_hwmod_lookup(name);
154         if (!oh)
155                 return -ENODEV;
156
157         timer->irq = oh->mpu_irqs[0].irq;
158         timer->phys_base = oh->slaves[0]->addr->pa_start;
159         size = oh->slaves[0]->addr->pa_end - timer->phys_base;
160
161         /* Static mapping, never released */
162         timer->io_base = ioremap(timer->phys_base, size);
163         if (!timer->io_base)
164                 return -ENXIO;
165
166         /* After the dmtimer is using hwmod these clocks won't be needed */
167         sprintf(name, "gpt%d_fck", gptimer_id);
168         timer->fclk = clk_get(NULL, name);
169         if (IS_ERR(timer->fclk))
170                 return -ENODEV;
171
172         omap_hwmod_enable(oh);
173
174         sys_timer_reserved |= (1 << (gptimer_id - 1));
175
176         if (gptimer_id != 12) {
177                 struct clk *src;
178
179                 src = clk_get(NULL, fck_source);
180                 if (IS_ERR(src)) {
181                         res = -EINVAL;
182                 } else {
183                         res = __omap_dm_timer_set_source(timer->fclk, src);
184                         if (IS_ERR_VALUE(res))
185                                 pr_warning("%s: timer%i cannot set source\n",
186                                                 __func__, gptimer_id);
187                         clk_put(src);
188                 }
189         }
190         __omap_dm_timer_init_regs(timer);
191         __omap_dm_timer_reset(timer, 1, 1);
192         timer->posted = 1;
193
194         timer->rate = clk_get_rate(timer->fclk);
195
196         timer->reserved = 1;
197
198         return res;
199 }
200
201 static void __init omap2_gp_clockevent_init(int gptimer_id,
202                                                 const char *fck_source)
203 {
204         int res;
205
206         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
207         BUG_ON(res);
208
209         omap2_gp_timer_irq.dev_id = (void *)&clkev;
210         setup_irq(clkev.irq, &omap2_gp_timer_irq);
211
212         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
213
214         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
215                                      clockevent_gpt.shift);
216         clockevent_gpt.max_delta_ns =
217                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
218         clockevent_gpt.min_delta_ns =
219                 clockevent_delta2ns(3, &clockevent_gpt);
220                 /* Timer internal resynch latency. */
221
222         clockevent_gpt.cpumask = cpumask_of(0);
223         clockevents_register_device(&clockevent_gpt);
224
225         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
226                 gptimer_id, clkev.rate);
227 }
228
229 /* Clocksource code */
230
231 #ifdef CONFIG_OMAP_32K_TIMER
232 /*
233  * When 32k-timer is enabled, don't use GPTimer for clocksource
234  * instead, just leave default clocksource which uses the 32k
235  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
236  */
237
238 static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
239 {
240         omap_init_clocksource_32k();
241 }
242
243 #else
244
245 static struct omap_dm_timer clksrc;
246
247 /*
248  * clocksource
249  */
250 static cycle_t clocksource_read_cycles(struct clocksource *cs)
251 {
252         return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
253 }
254
255 static struct clocksource clocksource_gpt = {
256         .name           = "gp_timer",
257         .rating         = 300,
258         .read           = clocksource_read_cycles,
259         .mask           = CLOCKSOURCE_MASK(32),
260         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
261 };
262
263 static u32 notrace dmtimer_read_sched_clock(void)
264 {
265         if (clksrc.reserved)
266                 return __omap_dm_timer_read_counter(&clksrc, 1);
267
268         return 0;
269 }
270
271 /* Setup free-running counter for clocksource */
272 static void __init omap2_gp_clocksource_init(int gptimer_id,
273                                                 const char *fck_source)
274 {
275         int res;
276
277         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
278         BUG_ON(res);
279
280         pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
281                 gptimer_id, clksrc.rate);
282
283         __omap_dm_timer_load_start(&clksrc,
284                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
285         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
286
287         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
288                 pr_err("Could not register clocksource %s\n",
289                         clocksource_gpt.name);
290 }
291 #endif
292
293 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
294                                 clksrc_nr, clksrc_src)                  \
295 static void __init omap##name##_timer_init(void)                        \
296 {                                                                       \
297         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
298         omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
299 }
300
301 #define OMAP_SYS_TIMER(name)                                            \
302 struct sys_timer omap##name##_timer = {                                 \
303         .init   = omap##name##_timer_init,                              \
304 };
305
306 #ifdef CONFIG_ARCH_OMAP2
307 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
308 OMAP_SYS_TIMER(2)
309 #endif
310
311 #ifdef CONFIG_ARCH_OMAP3
312 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
313 OMAP_SYS_TIMER(3)
314 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
315                         2, OMAP3_MPU_SOURCE)
316 OMAP_SYS_TIMER(3_secure)
317 #endif
318
319 #ifdef CONFIG_ARCH_OMAP4
320 static void __init omap4_timer_init(void)
321 {
322 #ifdef CONFIG_LOCAL_TIMERS
323         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
324         BUG_ON(!twd_base);
325 #endif
326         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
327         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
328 }
329 OMAP_SYS_TIMER(4)
330 #endif
331
332 /**
333  * omap2_dm_timer_set_src - change the timer input clock source
334  * @pdev:       timer platform device pointer
335  * @source:     array index of parent clock source
336  */
337 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
338 {
339         int ret;
340         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
341         struct clk *fclk, *parent;
342         char *parent_name = NULL;
343
344         fclk = clk_get(&pdev->dev, "fck");
345         if (IS_ERR_OR_NULL(fclk)) {
346                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
347                                 __func__, __LINE__);
348                 return -EINVAL;
349         }
350
351         switch (source) {
352         case OMAP_TIMER_SRC_SYS_CLK:
353                 parent_name = "sys_ck";
354                 break;
355
356         case OMAP_TIMER_SRC_32_KHZ:
357                 parent_name = "32k_ck";
358                 break;
359
360         case OMAP_TIMER_SRC_EXT_CLK:
361                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
362                         parent_name = "alt_ck";
363                         break;
364                 }
365                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
366                         __func__, __LINE__);
367                 clk_put(fclk);
368                 return -EINVAL;
369         }
370
371         parent = clk_get(&pdev->dev, parent_name);
372         if (IS_ERR_OR_NULL(parent)) {
373                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
374                         __func__, __LINE__, parent_name);
375                 clk_put(fclk);
376                 return -EINVAL;
377         }
378
379         ret = clk_set_parent(fclk, parent);
380         if (IS_ERR_VALUE(ret)) {
381                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
382                         __func__, parent_name);
383                 ret = -EINVAL;
384         }
385
386         clk_put(parent);
387         clk_put(fclk);
388
389         return ret;
390 }
391
392 /**
393  * omap_timer_init - build and register timer device with an
394  * associated timer hwmod
395  * @oh: timer hwmod pointer to be used to build timer device
396  * @user:       parameter that can be passed from calling hwmod API
397  *
398  * Called by omap_hwmod_for_each_by_class to register each of the timer
399  * devices present in the system. The number of timer devices is known
400  * by parsing through the hwmod database for a given class name. At the
401  * end of function call memory is allocated for timer device and it is
402  * registered to the framework ready to be proved by the driver.
403  */
404 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
405 {
406         int id;
407         int ret = 0;
408         char *name = "omap_timer";
409         struct dmtimer_platform_data *pdata;
410         struct platform_device *pdev;
411         struct omap_timer_capability_dev_attr *timer_dev_attr;
412         struct powerdomain *pwrdm;
413
414         pr_debug("%s: %s\n", __func__, oh->name);
415
416         /* on secure device, do not register secure timer */
417         timer_dev_attr = oh->dev_attr;
418         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
419                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
420                         return ret;
421
422         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
423         if (!pdata) {
424                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
425                 return -ENOMEM;
426         }
427
428         /*
429          * Extract the IDs from name field in hwmod database
430          * and use the same for constructing ids' for the
431          * timer devices. In a way, we are avoiding usage of
432          * static variable witin the function to do the same.
433          * CAUTION: We have to be careful and make sure the
434          * name in hwmod database does not change in which case
435          * we might either make corresponding change here or
436          * switch back static variable mechanism.
437          */
438         sscanf(oh->name, "timer%2d", &id);
439
440         pdata->set_timer_src = omap2_dm_timer_set_src;
441         pdata->timer_ip_version = oh->class->rev;
442
443         /* Mark clocksource and clockevent timers as reserved */
444         if ((sys_timer_reserved >> (id - 1)) & 0x1)
445                 pdata->reserved = 1;
446
447         pwrdm = omap_hwmod_get_pwrdm(oh);
448         pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
449 #ifdef CONFIG_PM
450         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
451 #endif
452         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
453                                  NULL, 0, 0);
454
455         if (IS_ERR(pdev)) {
456                 pr_err("%s: Can't build omap_device for %s: %s.\n",
457                         __func__, name, oh->name);
458                 ret = -EINVAL;
459         }
460
461         kfree(pdata);
462
463         return ret;
464 }
465
466 /**
467  * omap2_dm_timer_init - top level regular device initialization
468  *
469  * Uses dedicated hwmod api to parse through hwmod database for
470  * given class name and then build and register the timer device.
471  */
472 static int __init omap2_dm_timer_init(void)
473 {
474         int ret;
475
476         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
477         if (unlikely(ret)) {
478                 pr_err("%s: device registration failed.\n", __func__);
479                 return -EINVAL;
480         }
481
482         return 0;
483 }
484 arch_initcall(omap2_dm_timer_init);