arch/arm/mach-omap2/sram34xx.S

   1 /*
   2  * linux/arch/arm/mach-omap3/sram.S
   3  *
   4  * Omap3 specific functions that need to be run in internal SRAM
   5  *
   6  * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
   7  * Copyright (C) 2008 Nokia Corporation
   8  *
   9  * Rajendra Nayak <rnayak@ti.com>
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Paul Walmsley
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28 #include <linux/linkage.h>
  29 #include <asm/assembler.h>
  30 #include <mach/hardware.h>
  31
  32 #include <mach/io.h>
  33
  34 #include "sdrc.h"
  35 #include "cm.h"
  36
  37         .text
  38
  39 /* r1 parameters */
  40 #define SDRC_NO_UNLOCK_DLL              0x0
  41 #define SDRC_UNLOCK_DLL                 0x1
  42
  43 /* SDRC_DLLA_CTRL bit settings */
  44 #define FIXEDDELAY_SHIFT                24
  45 #define FIXEDDELAY_MASK                 (0xff << FIXEDDELAY_SHIFT)
  46 #define DLLIDLE_MASK                    0x4
  47
  48 /*
  49  * SDRC_DLLA_CTRL default values: TI hardware team indicates that
  50  * FIXEDDELAY should be initialized to 0xf.  This apparently was
  51  * empirically determined during process testing, so no derivation
  52  * was provided.
  53  */
  54 #define FIXEDDELAY_DEFAULT              (0x0f << FIXEDDELAY_SHIFT)
  55
  56 /* SDRC_DLLA_STATUS bit settings */
  57 #define LOCKSTATUS_MASK                 0x4
  58
  59 /* SDRC_POWER bit settings */
  60 #define SRFRONIDLEREQ_MASK              0x40
  61
  62 /* CM_IDLEST1_CORE bit settings */
  63 #define ST_SDRC_MASK                    0x2
  64
  65 /* CM_ICLKEN1_CORE bit settings */
  66 #define EN_SDRC_MASK                    0x2
  67
  68 /* CM_CLKSEL1_PLL bit settings */
  69 #define CORE_DPLL_CLKOUT_DIV_SHIFT      0x1b
  70
  71 /*
  72  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
  73  *
  74  * Params passed in registers:
  75  *  r0 = new M2 divider setting (only 1 and 2 supported right now)
  76  *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  77  *      SDRC rates < 83MHz
  78  *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  79  *      reprogramming the SDRC when switching to a slower MPU speed
  80  *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
  81  *
  82  * Params passed via the stack. The needed params will be copied in SRAM
  83  *  before use by the code in SRAM (SDRAM is not accessible during SDRC
  84  *  reconfiguration):
  85  *  new SDRC_RFR_CTRL_0 register contents
  86  *  new SDRC_ACTIM_CTRL_A_0 register contents
  87  *  new SDRC_ACTIM_CTRL_B_0 register contents
  88  *  new SDRC_MR_0 register value
  89  *  new SDRC_RFR_CTRL_1 register contents
  90  *  new SDRC_ACTIM_CTRL_A_1 register contents
  91  *  new SDRC_ACTIM_CTRL_B_1 register contents
  92  *  new SDRC_MR_1 register value
  93  *
  94  * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
  95  * the SDRC CS1 registers
  96  *
  97  * NOTE: This code no longer attempts to program the SDRC AC timing and MR
  98  * registers.  This is because the code currently cannot ensure that all
  99  * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
 100  * SDRAM when the registers are written.  If the registers are changed while
 101  * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
 102  * may enter an unpredictable state.  In the future, the intent is to
 103  * re-enable this code in cases where we can ensure that no initiators are
 104  * touching the SDRAM.  Until that time, users who know that their use case
 105  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
 106  * option.
 107  */
 108 ENTRY(omap3_sram_configure_core_dpll)
 109         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
 110
 111                                         @ pull the extra args off the stack
 112                                         @  and store them in SRAM
 113         ldr     r4, [sp, #52]
 114         str     r4, omap_sdrc_rfr_ctrl_0_val
 115         ldr     r4, [sp, #56]
 116         str     r4, omap_sdrc_actim_ctrl_a_0_val
 117         ldr     r4, [sp, #60]
 118         str     r4, omap_sdrc_actim_ctrl_b_0_val
 119         ldr     r4, [sp, #64]
 120         str     r4, omap_sdrc_mr_0_val
 121         ldr     r4, [sp, #68]
 122         str     r4, omap_sdrc_rfr_ctrl_1_val
 123         cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
 124         beq     skip_cs1_params         @  do not use cs1 params
 125         ldr     r4, [sp, #72]
 126         str     r4, omap_sdrc_actim_ctrl_a_1_val
 127         ldr     r4, [sp, #76]
 128         str     r4, omap_sdrc_actim_ctrl_b_1_val
 129         ldr     r4, [sp, #80]
 130         str     r4, omap_sdrc_mr_1_val
 131 skip_cs1_params:
 132         mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
 133         bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
 134         mcr     p15, 0, r10, c1, c0, 0  @ write ctrl register
 135         dsb                             @ flush buffered writes to interconnect
 136         isb                             @ prevent speculative exec past here
 137         cmp     r3, #1                  @ if increasing SDRC clk rate,
 138         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
 139         cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
 140         bleq    unlock_dll
 141         blne    lock_dll
 142         bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
 143         bl      configure_core_dpll     @ change the DPLL3 M2 divider
 144         mov     r12, r2
 145         bl      wait_clk_stable         @ wait for SDRC to stabilize
 146         bl      enable_sdrc             @ take SDRC out of idle
 147         cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
 148         bleq    wait_dll_unlock
 149         blne    wait_dll_lock
 150         cmp     r3, #1                  @ if increasing SDRC clk rate,
 151         beq     return_to_sdram         @ return to SDRAM code, otherwise,
 152         bl      configure_sdrc          @ reprogram SDRC regs now
 153 return_to_sdram:
 154         mcr     p15, 0, r8, c1, c0, 0   @ restore ctrl register
 155         isb                             @ prevent speculative exec past here
 156         mov     r0, #0                  @ return value
 157         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 158 unlock_dll:
 159         ldr     r11, omap3_sdrc_dlla_ctrl
 160         ldr     r12, [r11]
 161         bic     r12, r12, #FIXEDDELAY_MASK
 162         orr     r12, r12, #FIXEDDELAY_DEFAULT
 163         orr     r12, r12, #DLLIDLE_MASK
 164         str     r12, [r11]              @ (no OCP barrier needed)
 165         bx      lr
 166 lock_dll:
 167         ldr     r11, omap3_sdrc_dlla_ctrl
 168         ldr     r12, [r11]
 169         bic     r12, r12, #DLLIDLE_MASK
 170         str     r12, [r11]              @ (no OCP barrier needed)
 171         bx      lr
 172 sdram_in_selfrefresh:
 173         ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
 174         ldr     r12, [r11]              @ read the contents of SDRC_POWER
 175         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
 176         orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
 177         str     r12, [r11]              @ write back to SDRC_POWER register
 178         ldr     r12, [r11]              @ posted-write barrier for SDRC
 179 idle_sdrc:
 180         ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
 181         ldr     r12, [r11]
 182         bic     r12, r12, #EN_SDRC_MASK         @ disable iclk bit for SDRC
 183         str     r12, [r11]
 184 wait_sdrc_idle:
 185         ldr     r11, omap3_cm_idlest1_core
 186         ldr     r12, [r11]
 187         and     r12, r12, #ST_SDRC_MASK         @ check for SDRC idle
 188         cmp     r12, #ST_SDRC_MASK
 189         bne     wait_sdrc_idle
 190         bx      lr
 191 configure_core_dpll:
 192         ldr     r11, omap3_cm_clksel1_pll
 193         ldr     r12, [r11]
 194         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
 195         and     r12, r12, r10
 196         orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 197         str     r12, [r11]
 198         ldr     r12, [r11]              @ posted-write barrier for CM
 199         bx      lr
 200 wait_clk_stable:
 201         subs    r12, r12, #1
 202         bne     wait_clk_stable
 203         bx      lr
 204 enable_sdrc:
 205         ldr     r11, omap3_cm_iclken1_core
 206         ldr     r12, [r11]
 207         orr     r12, r12, #EN_SDRC_MASK         @ enable iclk bit for SDRC
 208         str     r12, [r11]
 209 wait_sdrc_idle1:
 210         ldr     r11, omap3_cm_idlest1_core
 211         ldr     r12, [r11]
 212         and     r12, r12, #ST_SDRC_MASK
 213         cmp     r12, #0
 214         bne     wait_sdrc_idle1
 215 restore_sdrc_power_val:
 216         ldr     r11, omap3_sdrc_power
 217         str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
 218         bx      lr
 219 wait_dll_lock:
 220         ldr     r11, omap3_sdrc_dlla_status
 221         ldr     r12, [r11]
 222         and     r12, r12, #LOCKSTATUS_MASK
 223         cmp     r12, #LOCKSTATUS_MASK
 224         bne     wait_dll_lock
 225         bx      lr
 226 wait_dll_unlock:
 227         ldr     r11, omap3_sdrc_dlla_status
 228         ldr     r12, [r11]
 229         and     r12, r12, #LOCKSTATUS_MASK
 230         cmp     r12, #0x0
 231         bne     wait_dll_unlock
 232         bx      lr
 233 configure_sdrc:
 234         ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
 235         ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
 236         str     r12, [r11]                      @ store
 237 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
 238         ldr     r12, omap_sdrc_actim_ctrl_a_0_val
 239         ldr     r11, omap3_sdrc_actim_ctrl_a_0
 240         str     r12, [r11]
 241         ldr     r12, omap_sdrc_actim_ctrl_b_0_val
 242         ldr     r11, omap3_sdrc_actim_ctrl_b_0
 243         str     r12, [r11]
 244         ldr     r12, omap_sdrc_mr_0_val
 245         ldr     r11, omap3_sdrc_mr_0
 246         str     r12, [r11]
 247 #endif
 248         ldr     r12, omap_sdrc_rfr_ctrl_1_val
 249         cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
 250         beq     skip_cs1_prog           @  do not program cs1 params
 251         ldr     r11, omap3_sdrc_rfr_ctrl_1
 252         str     r12, [r11]
 253 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
 254         ldr     r12, omap_sdrc_actim_ctrl_a_1_val
 255         ldr     r11, omap3_sdrc_actim_ctrl_a_1
 256         str     r12, [r11]
 257         ldr     r12, omap_sdrc_actim_ctrl_b_1_val
 258         ldr     r11, omap3_sdrc_actim_ctrl_b_1
 259         str     r12, [r11]
 260         ldr     r12, omap_sdrc_mr_1_val
 261         ldr     r11, omap3_sdrc_mr_1
 262         str     r12, [r11]
 263 #endif
 264 skip_cs1_prog:
 265         ldr     r12, [r11]              @ posted-write barrier for SDRC
 266         bx      lr
 267
 268 omap3_sdrc_power:
 269         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 270 omap3_cm_clksel1_pll:
 271         .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 272 omap3_cm_idlest1_core:
 273         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 274 omap3_cm_iclken1_core:
 275         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
 276
 277 omap3_sdrc_rfr_ctrl_0:
 278         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 279 omap3_sdrc_rfr_ctrl_1:
 280         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
 281 omap3_sdrc_actim_ctrl_a_0:
 282         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 283 omap3_sdrc_actim_ctrl_a_1:
 284         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
 285 omap3_sdrc_actim_ctrl_b_0:
 286         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
 287 omap3_sdrc_actim_ctrl_b_1:
 288         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 289 omap3_sdrc_mr_0:
 290         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
 291 omap3_sdrc_mr_1:
 292         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
 293 omap_sdrc_rfr_ctrl_0_val:
 294         .word 0xDEADBEEF
 295 omap_sdrc_rfr_ctrl_1_val:
 296         .word 0xDEADBEEF
 297 omap_sdrc_actim_ctrl_a_0_val:
 298         .word 0xDEADBEEF
 299 omap_sdrc_actim_ctrl_a_1_val:
 300         .word 0xDEADBEEF
 301 omap_sdrc_actim_ctrl_b_0_val:
 302         .word 0xDEADBEEF
 303 omap_sdrc_actim_ctrl_b_1_val:
 304         .word 0xDEADBEEF
 305 omap_sdrc_mr_0_val:
 306         .word 0xDEADBEEF
 307 omap_sdrc_mr_1_val:
 308         .word 0xDEADBEEF
 309
 310 omap3_sdrc_dlla_status:
 311         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 312 omap3_sdrc_dlla_ctrl:
 313         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 314 core_m2_mask_val:
 315         .word 0x07FFFFFF
 316
 317 ENTRY(omap3_sram_configure_core_dpll_sz)
 318         .word   . - omap3_sram_configure_core_dpll
 319