arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/console.h>
  31
  32 #ifdef CONFIG_SERIAL_OMAP
  33 #include <plat/omap-serial.h>
  34 #endif
  35
  36 #include <plat/common.h>
  37 #include <plat/board.h>
  38 #include <plat/clock.h>
  39 #include <plat/dma.h>
  40 #include <plat/omap_hwmod.h>
  41 #include <plat/omap_device.h>
  42
  43 #include "prm2xxx_3xxx.h"
  44 #include "pm.h"
  45 #include "cm2xxx_3xxx.h"
  46 #include "prm-regbits-34xx.h"
  47 #include "control.h"
  48 #include "mux.h"
  49
  50 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  51 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  52
  53 #define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
  54 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
  55
  56 /*
  57  * NOTE: By default the serial timeout is disabled as it causes lost characters
  58  * over the serial ports. This means that the UART clocks will stay on until
  59  * disabled via sysfs. This also causes that any deeper omap sleep states are
  60  * blocked.
  61  */
  62 #define DEFAULT_TIMEOUT 0
  63
  64 #define MAX_UART_HWMOD_NAME_LEN         16
  65
  66 struct omap_uart_state {
  67         int num;
  68         int can_sleep;
  69         struct timer_list timer;
  70         u32 timeout;
  71
  72         void __iomem *wk_st;
  73         void __iomem *wk_en;
  74         u32 wk_mask;
  75         u32 padconf;
  76         u32 dma_enabled;
  77
  78         struct clk *ick;
  79         struct clk *fck;
  80         int clocked;
  81
  82         int irq;
  83         int regshift;
  84         int irqflags;
  85         void __iomem *membase;
  86         resource_size_t mapbase;
  87
  88         struct list_head node;
  89         struct omap_hwmod *oh;
  90         struct platform_device *pdev;
  91
  92         u32 errata;
  93 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  94         int context_valid;
  95
  96         /* Registers to be saved/restored for OFF-mode */
  97         u16 dll;
  98         u16 dlh;
  99         u16 ier;
 100         u16 sysc;
 101         u16 scr;
 102         u16 wer;
 103         u16 mcr;
 104 #endif
 105 };
 106
 107 static LIST_HEAD(uart_list);
 108 static u8 num_uarts;
 109
 110 static inline unsigned int __serial_read_reg(struct uart_port *up,
 111                                              int offset)
 112 {
 113         offset <<= up->regshift;
 114         return (unsigned int)__raw_readb(up->membase + offset);
 115 }
 116
 117 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
 118                                            int offset)
 119 {
 120         offset <<= uart->regshift;
 121         return (unsigned int)__raw_readb(uart->membase + offset);
 122 }
 123
 124 static inline void __serial_write_reg(struct uart_port *up, int offset,
 125                 int value)
 126 {
 127         offset <<= up->regshift;
 128         __raw_writeb(value, up->membase + offset);
 129 }
 130
 131 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
 132                                     int value)
 133 {
 134         offset <<= uart->regshift;
 135         __raw_writeb(value, uart->membase + offset);
 136 }
 137
 138 /*
 139  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 140  * properly. Note that the TX watermark initialization may not be needed
 141  * once the 8250.c watermark handling code is merged.
 142  */
 143
 144 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 145 {
 146         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 147         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
 148         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 149 }
 150
 151 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 152
 153 /*
 154  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 155  * The access to uart register after MDR1 Access
 156  * causes UART to corrupt data.
 157  *
 158  * Need a delay =
 159  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 160  * give 10 times as much
 161  */
 162 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 163                 u8 fcr_val)
 164 {
 165         u8 timeout = 255;
 166
 167         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
 168         udelay(2);
 169         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
 170                         UART_FCR_CLEAR_RCVR);
 171         /*
 172          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 173          * TX_FIFO_E bit is 1.
 174          */
 175         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
 176                                 (UART_LSR_THRE | UART_LSR_DR))) {
 177                 timeout--;
 178                 if (!timeout) {
 179                         /* Should *never* happen. we warn and carry on */
 180                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
 181                         serial_read_reg(uart, UART_LSR));
 182                         break;
 183                 }
 184                 udelay(1);
 185         }
 186 }
 187
 188 static void omap_uart_save_context(struct omap_uart_state *uart)
 189 {
 190         u16 lcr = 0;
 191
 192         if (!enable_off_mode)
 193                 return;
 194
 195         lcr = serial_read_reg(uart, UART_LCR);
 196         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 197         uart->dll = serial_read_reg(uart, UART_DLL);
 198         uart->dlh = serial_read_reg(uart, UART_DLM);
 199         serial_write_reg(uart, UART_LCR, lcr);
 200         uart->ier = serial_read_reg(uart, UART_IER);
 201         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
 202         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
 203         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
 204         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 205         uart->mcr = serial_read_reg(uart, UART_MCR);
 206         serial_write_reg(uart, UART_LCR, lcr);
 207
 208         uart->context_valid = 1;
 209 }
 210
 211 static void omap_uart_restore_context(struct omap_uart_state *uart)
 212 {
 213         u16 efr = 0;
 214
 215         if (!enable_off_mode)
 216                 return;
 217
 218         if (!uart->context_valid)
 219                 return;
 220
 221         uart->context_valid = 0;
 222
 223         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 224                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
 225         else
 226                 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 227
 228         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 229         efr = serial_read_reg(uart, UART_EFR);
 230         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
 231         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 232         serial_write_reg(uart, UART_IER, 0x0);
 233         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 234         serial_write_reg(uart, UART_DLL, uart->dll);
 235         serial_write_reg(uart, UART_DLM, uart->dlh);
 236         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 237         serial_write_reg(uart, UART_IER, uart->ier);
 238         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 239         serial_write_reg(uart, UART_MCR, uart->mcr);
 240         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 241         serial_write_reg(uart, UART_EFR, efr);
 242         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
 243         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
 244         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
 245         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
 246
 247         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 248                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
 249         else
 250                 /* UART 16x mode */
 251                 serial_write_reg(uart, UART_OMAP_MDR1,
 252                                 UART_OMAP_MDR1_16X_MODE);
 253 }
 254 #else
 255 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 256 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 257 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 258
 259 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 260 {
 261         if (uart->clocked)
 262                 return;
 263
 264         omap_device_enable(uart->pdev);
 265         uart->clocked = 1;
 266         omap_uart_restore_context(uart);
 267 }
 268
 269 #ifdef CONFIG_PM
 270
 271 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 272 {
 273         if (!uart->clocked)
 274                 return;
 275
 276         omap_uart_save_context(uart);
 277         uart->clocked = 0;
 278         omap_device_idle(uart->pdev);
 279 }
 280
 281 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 282 {
 283         /* Set wake-enable bit */
 284         if (uart->wk_en && uart->wk_mask) {
 285                 u32 v = __raw_readl(uart->wk_en);
 286                 v |= uart->wk_mask;
 287                 __raw_writel(v, uart->wk_en);
 288         }
 289
 290         /* Ensure IOPAD wake-enables are set */
 291         if (cpu_is_omap34xx() && uart->padconf) {
 292                 u16 v = omap_ctrl_readw(uart->padconf);
 293                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 294                 omap_ctrl_writew(v, uart->padconf);
 295         }
 296 }
 297
 298 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 299 {
 300         /* Clear wake-enable bit */
 301         if (uart->wk_en && uart->wk_mask) {
 302                 u32 v = __raw_readl(uart->wk_en);
 303                 v &= ~uart->wk_mask;
 304                 __raw_writel(v, uart->wk_en);
 305         }
 306
 307         /* Ensure IOPAD wake-enables are cleared */
 308         if (cpu_is_omap34xx() && uart->padconf) {
 309                 u16 v = omap_ctrl_readw(uart->padconf);
 310                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 311                 omap_ctrl_writew(v, uart->padconf);
 312         }
 313 }
 314
 315 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 316                                                int enable)
 317 {
 318         u8 idlemode;
 319
 320         if (enable) {
 321                 /**
 322                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
 323                  * in Smartidle Mode When Configured for DMA Operations.
 324                  */
 325                 if (uart->dma_enabled)
 326                         idlemode = HWMOD_IDLEMODE_FORCE;
 327                 else
 328                         idlemode = HWMOD_IDLEMODE_SMART;
 329         } else {
 330                 idlemode = HWMOD_IDLEMODE_NO;
 331         }
 332
 333         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 334 }
 335
 336 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 337 {
 338         omap_uart_enable_clocks(uart);
 339
 340         omap_uart_smart_idle_enable(uart, 0);
 341         uart->can_sleep = 0;
 342         if (uart->timeout)
 343                 mod_timer(&uart->timer, jiffies + uart->timeout);
 344         else
 345                 del_timer(&uart->timer);
 346 }
 347
 348 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 349 {
 350         if (device_may_wakeup(&uart->pdev->dev))
 351                 omap_uart_enable_wakeup(uart);
 352         else
 353                 omap_uart_disable_wakeup(uart);
 354
 355         if (!uart->clocked)
 356                 return;
 357
 358         omap_uart_smart_idle_enable(uart, 1);
 359         uart->can_sleep = 1;
 360         del_timer(&uart->timer);
 361 }
 362
 363 static void omap_uart_idle_timer(unsigned long data)
 364 {
 365         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 366
 367         omap_uart_allow_sleep(uart);
 368 }
 369
 370 void omap_uart_prepare_idle(int num)
 371 {
 372         struct omap_uart_state *uart;
 373
 374         list_for_each_entry(uart, &uart_list, node) {
 375                 if (num == uart->num && uart->can_sleep) {
 376                         omap_uart_disable_clocks(uart);
 377                         return;
 378                 }
 379         }
 380 }
 381
 382 void omap_uart_resume_idle(int num)
 383 {
 384         struct omap_uart_state *uart;
 385
 386         list_for_each_entry(uart, &uart_list, node) {
 387                 if (num == uart->num && uart->can_sleep) {
 388                         omap_uart_enable_clocks(uart);
 389
 390                         /* Check for IO pad wakeup */
 391                         if (cpu_is_omap34xx() && uart->padconf) {
 392                                 u16 p = omap_ctrl_readw(uart->padconf);
 393
 394                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 395                                         omap_uart_block_sleep(uart);
 396                         }
 397
 398                         /* Check for normal UART wakeup */
 399                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 400                                 omap_uart_block_sleep(uart);
 401                         return;
 402                 }
 403         }
 404 }
 405
 406 void omap_uart_prepare_suspend(void)
 407 {
 408         struct omap_uart_state *uart;
 409
 410         list_for_each_entry(uart, &uart_list, node) {
 411                 omap_uart_allow_sleep(uart);
 412         }
 413 }
 414
 415 int omap_uart_can_sleep(void)
 416 {
 417         struct omap_uart_state *uart;
 418         int can_sleep = 1;
 419
 420         list_for_each_entry(uart, &uart_list, node) {
 421                 if (!uart->clocked)
 422                         continue;
 423
 424                 if (!uart->can_sleep) {
 425                         can_sleep = 0;
 426                         continue;
 427                 }
 428
 429                 /* This UART can now safely sleep. */
 430                 omap_uart_allow_sleep(uart);
 431         }
 432
 433         return can_sleep;
 434 }
 435
 436 /**
 437  * omap_uart_interrupt()
 438  *
 439  * This handler is used only to detect that *any* UART interrupt has
 440  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 441  * any UART interrupt will trigger the inactivity timer so the
 442  * UART will not idle or sleep for its timeout period.
 443  *
 444  **/
 445 /* static int first_interrupt; */
 446 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 447 {
 448         struct omap_uart_state *uart = dev_id;
 449
 450         omap_uart_block_sleep(uart);
 451
 452         return IRQ_NONE;
 453 }
 454
 455 static void omap_uart_idle_init(struct omap_uart_state *uart)
 456 {
 457         int ret;
 458
 459         uart->can_sleep = 0;
 460         uart->timeout = DEFAULT_TIMEOUT;
 461         setup_timer(&uart->timer, omap_uart_idle_timer,
 462                     (unsigned long) uart);
 463         if (uart->timeout)
 464                 mod_timer(&uart->timer, jiffies + uart->timeout);
 465         omap_uart_smart_idle_enable(uart, 0);
 466
 467         if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
 468                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 469                 u32 wk_mask = 0;
 470                 u32 padconf = 0;
 471
 472                 /* XXX These PRM accesses do not belong here */
 473                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 474                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 475                 switch (uart->num) {
 476                 case 0:
 477                         wk_mask = OMAP3430_ST_UART1_MASK;
 478                         padconf = 0x182;
 479                         break;
 480                 case 1:
 481                         wk_mask = OMAP3430_ST_UART2_MASK;
 482                         padconf = 0x17a;
 483                         break;
 484                 case 2:
 485                         wk_mask = OMAP3430_ST_UART3_MASK;
 486                         padconf = 0x19e;
 487                         break;
 488                 case 3:
 489                         wk_mask = OMAP3630_ST_UART4_MASK;
 490                         padconf = 0x0d2;
 491                         break;
 492                 }
 493                 uart->wk_mask = wk_mask;
 494                 uart->padconf = padconf;
 495         } else if (cpu_is_omap24xx()) {
 496                 u32 wk_mask = 0;
 497                 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 498
 499                 switch (uart->num) {
 500                 case 0:
 501                         wk_mask = OMAP24XX_ST_UART1_MASK;
 502                         break;
 503                 case 1:
 504                         wk_mask = OMAP24XX_ST_UART2_MASK;
 505                         break;
 506                 case 2:
 507                         wk_en = OMAP24XX_PM_WKEN2;
 508                         wk_st = OMAP24XX_PM_WKST2;
 509                         wk_mask = OMAP24XX_ST_UART3_MASK;
 510                         break;
 511                 }
 512                 uart->wk_mask = wk_mask;
 513                 if (cpu_is_omap2430()) {
 514                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
 515                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
 516                 } else if (cpu_is_omap2420()) {
 517                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
 518                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
 519                 }
 520         } else {
 521                 uart->wk_en = NULL;
 522                 uart->wk_st = NULL;
 523                 uart->wk_mask = 0;
 524                 uart->padconf = 0;
 525         }
 526
 527         uart->irqflags |= IRQF_SHARED;
 528         ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
 529                                    IRQF_SHARED, "serial idle", (void *)uart);
 530         WARN_ON(ret);
 531 }
 532
 533 void omap_uart_enable_irqs(int enable)
 534 {
 535         int ret;
 536         struct omap_uart_state *uart;
 537
 538         list_for_each_entry(uart, &uart_list, node) {
 539                 if (enable) {
 540                         pm_runtime_put_sync(&uart->pdev->dev);
 541                         ret = request_threaded_irq(uart->irq, NULL,
 542                                                    omap_uart_interrupt,
 543                                                    IRQF_SHARED,
 544                                                    "serial idle",
 545                                                    (void *)uart);
 546                 } else {
 547                         pm_runtime_get_noresume(&uart->pdev->dev);
 548                         free_irq(uart->irq, (void *)uart);
 549                 }
 550         }
 551 }
 552
 553 static ssize_t sleep_timeout_show(struct device *dev,
 554                                   struct device_attribute *attr,
 555                                   char *buf)
 556 {
 557         struct platform_device *pdev = to_platform_device(dev);
 558         struct omap_device *odev = to_omap_device(pdev);
 559         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 560
 561         return sprintf(buf, "%u\n", uart->timeout / HZ);
 562 }
 563
 564 static ssize_t sleep_timeout_store(struct device *dev,
 565                                    struct device_attribute *attr,
 566                                    const char *buf, size_t n)
 567 {
 568         struct platform_device *pdev = to_platform_device(dev);
 569         struct omap_device *odev = to_omap_device(pdev);
 570         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 571         unsigned int value;
 572
 573         if (sscanf(buf, "%u", &value) != 1) {
 574                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
 575                 return -EINVAL;
 576         }
 577
 578         uart->timeout = value * HZ;
 579         if (uart->timeout)
 580                 mod_timer(&uart->timer, jiffies + uart->timeout);
 581         else
 582                 /* A zero value means disable timeout feature */
 583                 omap_uart_block_sleep(uart);
 584
 585         return n;
 586 }
 587
 588 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 589                 sleep_timeout_store);
 590 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 591 #else
 592 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 593 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 594 {
 595         /* Needed to enable UART clocks when built without CONFIG_PM */
 596         omap_uart_enable_clocks(uart);
 597 }
 598 #define DEV_CREATE_FILE(dev, attr)
 599 #endif /* CONFIG_PM */
 600
 601 #ifndef CONFIG_SERIAL_OMAP
 602 /*
 603  * Override the default 8250 read handler: mem_serial_in()
 604  * Empty RX fifo read causes an abort on omap3630 and omap4
 605  * This function makes sure that an empty rx fifo is not read on these silicons
 606  * (OMAP1/2/3430 are not affected)
 607  */
 608 static unsigned int serial_in_override(struct uart_port *up, int offset)
 609 {
 610         if (UART_RX == offset) {
 611                 unsigned int lsr;
 612                 lsr = __serial_read_reg(up, UART_LSR);
 613                 if (!(lsr & UART_LSR_DR))
 614                         return -EPERM;
 615         }
 616
 617         return __serial_read_reg(up, offset);
 618 }
 619
 620 static void serial_out_override(struct uart_port *up, int offset, int value)
 621 {
 622         unsigned int status, tmout = 10000;
 623
 624         status = __serial_read_reg(up, UART_LSR);
 625         while (!(status & UART_LSR_THRE)) {
 626                 /* Wait up to 10ms for the character(s) to be sent. */
 627                 if (--tmout == 0)
 628                         break;
 629                 udelay(1);
 630                 status = __serial_read_reg(up, UART_LSR);
 631         }
 632         __serial_write_reg(up, offset, value);
 633 }
 634 #endif
 635
 636 static int __init omap_serial_early_init(void)
 637 {
 638         int i = 0;
 639
 640         do {
 641                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
 642                 struct omap_hwmod *oh;
 643                 struct omap_uart_state *uart;
 644
 645                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
 646                          "uart%d", i + 1);
 647                 oh = omap_hwmod_lookup(oh_name);
 648                 if (!oh)
 649                         break;
 650
 651                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
 652                 if (WARN_ON(!uart))
 653                         return -ENODEV;
 654
 655                 uart->oh = oh;
 656                 uart->num = i++;
 657                 list_add_tail(&uart->node, &uart_list);
 658                 num_uarts++;
 659
 660                 /*
 661                  * NOTE: omap_hwmod_setup*() has not yet been called,
 662                  *       so no hwmod functions will work yet.
 663                  */
 664
 665                 /*
 666                  * During UART early init, device need to be probed
 667                  * to determine SoC specific init before omap_device
 668                  * is ready.  Therefore, don't allow idle here
 669                  */
 670                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
 671         } while (1);
 672
 673         return 0;
 674 }
 675 core_initcall(omap_serial_early_init);
 676
 677 /**
 678  * omap_serial_init_port() - initialize single serial port
 679  * @bdata: port specific board data pointer
 680  *
 681  * This function initialies serial driver for given port only.
 682  * Platforms can call this function instead of omap_serial_init()
 683  * if they don't plan to use all available UARTs as serial ports.
 684  *
 685  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 686  * use only one of the two.
 687  */
 688 void __init omap_serial_init_port(struct omap_board_data *bdata)
 689 {
 690         struct omap_uart_state *uart;
 691         struct omap_hwmod *oh;
 692         struct platform_device *pdev;
 693         void *pdata = NULL;
 694         u32 pdata_size = 0;
 695         char *name;
 696 #ifndef CONFIG_SERIAL_OMAP
 697         struct plat_serial8250_port ports[2] = {
 698                 {},
 699                 {.flags = 0},
 700         };
 701         struct plat_serial8250_port *p = &ports[0];
 702 #else
 703         struct omap_uart_port_info omap_up;
 704 #endif
 705
 706         if (WARN_ON(!bdata))
 707                 return;
 708         if (WARN_ON(bdata->id < 0))
 709                 return;
 710         if (WARN_ON(bdata->id >= num_uarts))
 711                 return;
 712
 713         list_for_each_entry(uart, &uart_list, node)
 714                 if (bdata->id == uart->num)
 715                         break;
 716
 717         oh = uart->oh;
 718         uart->dma_enabled = 0;
 719 #ifndef CONFIG_SERIAL_OMAP
 720         name = "serial8250";
 721
 722         /*
 723          * !! 8250 driver does not use standard IORESOURCE* It
 724          * has it's own custom pdata that can be taken from
 725          * the hwmod resource data.  But, this needs to be
 726          * done after the build.
 727          *
 728          * ?? does it have to be done before the register ??
 729          * YES, because platform_device_data_add() copies
 730          * pdata, it does not use a pointer.
 731          */
 732         p->flags = UPF_BOOT_AUTOCONF;
 733         p->iotype = UPIO_MEM;
 734         p->regshift = 2;
 735         p->uartclk = OMAP24XX_BASE_BAUD * 16;
 736         p->irq = oh->mpu_irqs[0].irq;
 737         p->mapbase = oh->slaves[0]->addr->pa_start;
 738         p->membase = omap_hwmod_get_mpu_rt_va(oh);
 739         p->irqflags = IRQF_SHARED;
 740         p->private_data = uart;
 741
 742         /*
 743          * omap44xx, ti816x: Never read empty UART fifo
 744          * omap3xxx: Never read empty UART fifo on UARTs
 745          * with IP rev >=0x52
 746          */
 747         uart->regshift = p->regshift;
 748         uart->membase = p->membase;
 749         if (cpu_is_omap44xx() || cpu_is_ti816x())
 750                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 751         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
 752                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
 753                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 754
 755         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
 756                 p->serial_in = serial_in_override;
 757                 p->serial_out = serial_out_override;
 758         }
 759
 760         pdata = &ports[0];
 761         pdata_size = 2 * sizeof(struct plat_serial8250_port);
 762 #else
 763
 764         name = DRIVER_NAME;
 765
 766         omap_up.dma_enabled = uart->dma_enabled;
 767         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
 768         omap_up.mapbase = oh->slaves[0]->addr->pa_start;
 769         omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
 770         omap_up.irqflags = IRQF_SHARED;
 771         omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
 772
 773         pdata = &omap_up;
 774         pdata_size = sizeof(struct omap_uart_port_info);
 775 #endif
 776
 777         if (WARN_ON(!oh))
 778                 return;
 779
 780         pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
 781                                  NULL, 0, false);
 782         WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
 783              name, oh->name);
 784
 785         omap_device_disable_idle_on_suspend(pdev);
 786         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 787
 788         uart->irq = oh->mpu_irqs[0].irq;
 789         uart->regshift = 2;
 790         uart->mapbase = oh->slaves[0]->addr->pa_start;
 791         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
 792         uart->pdev = pdev;
 793
 794         oh->dev_attr = uart;
 795
 796         console_lock(); /* in case the earlycon is on the UART */
 797
 798         /*
 799          * Because of early UART probing, UART did not get idled
 800          * on init.  Now that omap_device is ready, ensure full idle
 801          * before doing omap_device_enable().
 802          */
 803         omap_hwmod_idle(uart->oh);
 804
 805         omap_device_enable(uart->pdev);
 806         omap_uart_idle_init(uart);
 807         omap_uart_reset(uart);
 808         omap_hwmod_enable_wakeup(uart->oh);
 809         omap_device_idle(uart->pdev);
 810
 811         /*
 812          * Need to block sleep long enough for interrupt driven
 813          * driver to start.  Console driver is in polling mode
 814          * so device needs to be kept enabled while polling driver
 815          * is in use.
 816          */
 817         if (uart->timeout)
 818                 uart->timeout = (30 * HZ);
 819         omap_uart_block_sleep(uart);
 820         uart->timeout = DEFAULT_TIMEOUT;
 821
 822         console_unlock();
 823
 824         if ((cpu_is_omap34xx() && uart->padconf) ||
 825             (uart->wk_en && uart->wk_mask)) {
 826                 device_init_wakeup(&pdev->dev, true);
 827                 DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
 828         }
 829
 830         /* Enable the MDR1 errata for OMAP3 */
 831         if (cpu_is_omap34xx() && !cpu_is_ti816x())
 832                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 833 }
 834
 835 /**
 836  * omap_serial_init() - initialize all supported serial ports
 837  *
 838  * Initializes all available UARTs as serial ports. Platforms
 839  * can call this function when they want to have default behaviour
 840  * for serial ports (e.g initialize them all as serial ports).
 841  */
 842 void __init omap_serial_init(void)
 843 {
 844         struct omap_uart_state *uart;
 845         struct omap_board_data bdata;
 846
 847         list_for_each_entry(uart, &uart_list, node) {
 848                 bdata.id = uart->num;
 849                 bdata.flags = 0;
 850                 bdata.pads = NULL;
 851                 bdata.pads_cnt = 0;
 852                 omap_serial_init_port(&bdata);
 853
 854         }
 855 }