arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/console.h>
  31
  32 #ifdef CONFIG_SERIAL_OMAP
  33 #include <plat/omap-serial.h>
  34 #endif
  35
  36 #include <plat/common.h>
  37 #include <plat/board.h>
  38 #include <plat/clock.h>
  39 #include <plat/dma.h>
  40 #include <plat/omap_hwmod.h>
  41 #include <plat/omap_device.h>
  42
  43 #include "prm2xxx_3xxx.h"
  44 #include "pm.h"
  45 #include "cm2xxx_3xxx.h"
  46 #include "prm-regbits-34xx.h"
  47 #include "control.h"
  48 #include "mux.h"
  49
  50 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  51 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  52
  53 #define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
  54 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
  55
  56 /*
  57  * NOTE: By default the serial timeout is disabled as it causes lost characters
  58  * over the serial ports. This means that the UART clocks will stay on until
  59  * disabled via sysfs. This also causes that any deeper omap sleep states are
  60  * blocked.
  61  */
  62 #define DEFAULT_TIMEOUT 0
  63
  64 #define MAX_UART_HWMOD_NAME_LEN         16
  65
  66 struct omap_uart_state {
  67         int num;
  68         int can_sleep;
  69         struct timer_list timer;
  70         u32 timeout;
  71
  72         void __iomem *wk_st;
  73         void __iomem *wk_en;
  74         u32 wk_mask;
  75         u32 padconf;
  76         u32 dma_enabled;
  77
  78         struct clk *ick;
  79         struct clk *fck;
  80         int clocked;
  81
  82         int irq;
  83         int regshift;
  84         int irqflags;
  85         void __iomem *membase;
  86         resource_size_t mapbase;
  87
  88         struct list_head node;
  89         struct omap_hwmod *oh;
  90         struct platform_device *pdev;
  91
  92         u32 errata;
  93 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  94         int context_valid;
  95
  96         /* Registers to be saved/restored for OFF-mode */
  97         u16 dll;
  98         u16 dlh;
  99         u16 ier;
 100         u16 sysc;
 101         u16 scr;
 102         u16 wer;
 103         u16 mcr;
 104 #endif
 105 };
 106
 107 static LIST_HEAD(uart_list);
 108 static u8 num_uarts;
 109
 110 static int uart_idle_hwmod(struct omap_device *od)
 111 {
 112         omap_hwmod_idle(od->hwmods[0]);
 113
 114         return 0;
 115 }
 116
 117 static int uart_enable_hwmod(struct omap_device *od)
 118 {
 119         omap_hwmod_enable(od->hwmods[0]);
 120
 121         return 0;
 122 }
 123
 124 static struct omap_device_pm_latency omap_uart_latency[] = {
 125         {
 126                 .deactivate_func = uart_idle_hwmod,
 127                 .activate_func   = uart_enable_hwmod,
 128                 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
 129         },
 130 };
 131
 132 static inline unsigned int __serial_read_reg(struct uart_port *up,
 133                                              int offset)
 134 {
 135         offset <<= up->regshift;
 136         return (unsigned int)__raw_readb(up->membase + offset);
 137 }
 138
 139 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
 140                                            int offset)
 141 {
 142         offset <<= uart->regshift;
 143         return (unsigned int)__raw_readb(uart->membase + offset);
 144 }
 145
 146 static inline void __serial_write_reg(struct uart_port *up, int offset,
 147                 int value)
 148 {
 149         offset <<= up->regshift;
 150         __raw_writeb(value, up->membase + offset);
 151 }
 152
 153 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
 154                                     int value)
 155 {
 156         offset <<= uart->regshift;
 157         __raw_writeb(value, uart->membase + offset);
 158 }
 159
 160 /*
 161  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 162  * properly. Note that the TX watermark initialization may not be needed
 163  * once the 8250.c watermark handling code is merged.
 164  */
 165
 166 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 167 {
 168         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 169         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
 170         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 171 }
 172
 173 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 174
 175 /*
 176  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 177  * The access to uart register after MDR1 Access
 178  * causes UART to corrupt data.
 179  *
 180  * Need a delay =
 181  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 182  * give 10 times as much
 183  */
 184 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 185                 u8 fcr_val)
 186 {
 187         u8 timeout = 255;
 188
 189         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
 190         udelay(2);
 191         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
 192                         UART_FCR_CLEAR_RCVR);
 193         /*
 194          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 195          * TX_FIFO_E bit is 1.
 196          */
 197         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
 198                                 (UART_LSR_THRE | UART_LSR_DR))) {
 199                 timeout--;
 200                 if (!timeout) {
 201                         /* Should *never* happen. we warn and carry on */
 202                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
 203                         serial_read_reg(uart, UART_LSR));
 204                         break;
 205                 }
 206                 udelay(1);
 207         }
 208 }
 209
 210 static void omap_uart_save_context(struct omap_uart_state *uart)
 211 {
 212         u16 lcr = 0;
 213
 214         if (!enable_off_mode)
 215                 return;
 216
 217         lcr = serial_read_reg(uart, UART_LCR);
 218         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 219         uart->dll = serial_read_reg(uart, UART_DLL);
 220         uart->dlh = serial_read_reg(uart, UART_DLM);
 221         serial_write_reg(uart, UART_LCR, lcr);
 222         uart->ier = serial_read_reg(uart, UART_IER);
 223         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
 224         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
 225         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
 226         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 227         uart->mcr = serial_read_reg(uart, UART_MCR);
 228         serial_write_reg(uart, UART_LCR, lcr);
 229
 230         uart->context_valid = 1;
 231 }
 232
 233 static void omap_uart_restore_context(struct omap_uart_state *uart)
 234 {
 235         u16 efr = 0;
 236
 237         if (!enable_off_mode)
 238                 return;
 239
 240         if (!uart->context_valid)
 241                 return;
 242
 243         uart->context_valid = 0;
 244
 245         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 246                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
 247         else
 248                 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 249
 250         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 251         efr = serial_read_reg(uart, UART_EFR);
 252         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
 253         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 254         serial_write_reg(uart, UART_IER, 0x0);
 255         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 256         serial_write_reg(uart, UART_DLL, uart->dll);
 257         serial_write_reg(uart, UART_DLM, uart->dlh);
 258         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 259         serial_write_reg(uart, UART_IER, uart->ier);
 260         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 261         serial_write_reg(uart, UART_MCR, uart->mcr);
 262         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 263         serial_write_reg(uart, UART_EFR, efr);
 264         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
 265         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
 266         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
 267         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
 268
 269         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 270                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
 271         else
 272                 /* UART 16x mode */
 273                 serial_write_reg(uart, UART_OMAP_MDR1,
 274                                 UART_OMAP_MDR1_16X_MODE);
 275 }
 276 #else
 277 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 278 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 279 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 280
 281 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 282 {
 283         if (uart->clocked)
 284                 return;
 285
 286         omap_device_enable(uart->pdev);
 287         uart->clocked = 1;
 288         omap_uart_restore_context(uart);
 289 }
 290
 291 #ifdef CONFIG_PM
 292
 293 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 294 {
 295         if (!uart->clocked)
 296                 return;
 297
 298         omap_uart_save_context(uart);
 299         uart->clocked = 0;
 300         omap_device_idle(uart->pdev);
 301 }
 302
 303 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 304 {
 305         /* Set wake-enable bit */
 306         if (uart->wk_en && uart->wk_mask) {
 307                 u32 v = __raw_readl(uart->wk_en);
 308                 v |= uart->wk_mask;
 309                 __raw_writel(v, uart->wk_en);
 310         }
 311
 312         /* Ensure IOPAD wake-enables are set */
 313         if (cpu_is_omap34xx() && uart->padconf) {
 314                 u16 v = omap_ctrl_readw(uart->padconf);
 315                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 316                 omap_ctrl_writew(v, uart->padconf);
 317         }
 318 }
 319
 320 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 321 {
 322         /* Clear wake-enable bit */
 323         if (uart->wk_en && uart->wk_mask) {
 324                 u32 v = __raw_readl(uart->wk_en);
 325                 v &= ~uart->wk_mask;
 326                 __raw_writel(v, uart->wk_en);
 327         }
 328
 329         /* Ensure IOPAD wake-enables are cleared */
 330         if (cpu_is_omap34xx() && uart->padconf) {
 331                 u16 v = omap_ctrl_readw(uart->padconf);
 332                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 333                 omap_ctrl_writew(v, uart->padconf);
 334         }
 335 }
 336
 337 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 338                                                int enable)
 339 {
 340         u8 idlemode;
 341
 342         if (enable) {
 343                 /**
 344                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
 345                  * in Smartidle Mode When Configured for DMA Operations.
 346                  */
 347                 if (uart->dma_enabled)
 348                         idlemode = HWMOD_IDLEMODE_FORCE;
 349                 else
 350                         idlemode = HWMOD_IDLEMODE_SMART;
 351         } else {
 352                 idlemode = HWMOD_IDLEMODE_NO;
 353         }
 354
 355         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 356 }
 357
 358 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 359 {
 360         omap_uart_enable_clocks(uart);
 361
 362         omap_uart_smart_idle_enable(uart, 0);
 363         uart->can_sleep = 0;
 364         if (uart->timeout)
 365                 mod_timer(&uart->timer, jiffies + uart->timeout);
 366         else
 367                 del_timer(&uart->timer);
 368 }
 369
 370 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 371 {
 372         if (device_may_wakeup(&uart->pdev->dev))
 373                 omap_uart_enable_wakeup(uart);
 374         else
 375                 omap_uart_disable_wakeup(uart);
 376
 377         if (!uart->clocked)
 378                 return;
 379
 380         omap_uart_smart_idle_enable(uart, 1);
 381         uart->can_sleep = 1;
 382         del_timer(&uart->timer);
 383 }
 384
 385 static void omap_uart_idle_timer(unsigned long data)
 386 {
 387         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 388
 389         omap_uart_allow_sleep(uart);
 390 }
 391
 392 void omap_uart_prepare_idle(int num)
 393 {
 394         struct omap_uart_state *uart;
 395
 396         list_for_each_entry(uart, &uart_list, node) {
 397                 if (num == uart->num && uart->can_sleep) {
 398                         omap_uart_disable_clocks(uart);
 399                         return;
 400                 }
 401         }
 402 }
 403
 404 void omap_uart_resume_idle(int num)
 405 {
 406         struct omap_uart_state *uart;
 407
 408         list_for_each_entry(uart, &uart_list, node) {
 409                 if (num == uart->num && uart->can_sleep) {
 410                         omap_uart_enable_clocks(uart);
 411
 412                         /* Check for IO pad wakeup */
 413                         if (cpu_is_omap34xx() && uart->padconf) {
 414                                 u16 p = omap_ctrl_readw(uart->padconf);
 415
 416                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 417                                         omap_uart_block_sleep(uart);
 418                         }
 419
 420                         /* Check for normal UART wakeup */
 421                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 422                                 omap_uart_block_sleep(uart);
 423                         return;
 424                 }
 425         }
 426 }
 427
 428 void omap_uart_prepare_suspend(void)
 429 {
 430         struct omap_uart_state *uart;
 431
 432         list_for_each_entry(uart, &uart_list, node) {
 433                 omap_uart_allow_sleep(uart);
 434         }
 435 }
 436
 437 int omap_uart_can_sleep(void)
 438 {
 439         struct omap_uart_state *uart;
 440         int can_sleep = 1;
 441
 442         list_for_each_entry(uart, &uart_list, node) {
 443                 if (!uart->clocked)
 444                         continue;
 445
 446                 if (!uart->can_sleep) {
 447                         can_sleep = 0;
 448                         continue;
 449                 }
 450
 451                 /* This UART can now safely sleep. */
 452                 omap_uart_allow_sleep(uart);
 453         }
 454
 455         return can_sleep;
 456 }
 457
 458 /**
 459  * omap_uart_interrupt()
 460  *
 461  * This handler is used only to detect that *any* UART interrupt has
 462  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 463  * any UART interrupt will trigger the inactivity timer so the
 464  * UART will not idle or sleep for its timeout period.
 465  *
 466  **/
 467 /* static int first_interrupt; */
 468 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 469 {
 470         struct omap_uart_state *uart = dev_id;
 471
 472         omap_uart_block_sleep(uart);
 473
 474         return IRQ_NONE;
 475 }
 476
 477 static void omap_uart_idle_init(struct omap_uart_state *uart)
 478 {
 479         int ret;
 480
 481         uart->can_sleep = 0;
 482         uart->timeout = DEFAULT_TIMEOUT;
 483         setup_timer(&uart->timer, omap_uart_idle_timer,
 484                     (unsigned long) uart);
 485         if (uart->timeout)
 486                 mod_timer(&uart->timer, jiffies + uart->timeout);
 487         omap_uart_smart_idle_enable(uart, 0);
 488
 489         if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
 490                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 491                 u32 wk_mask = 0;
 492                 u32 padconf = 0;
 493
 494                 /* XXX These PRM accesses do not belong here */
 495                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 496                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 497                 switch (uart->num) {
 498                 case 0:
 499                         wk_mask = OMAP3430_ST_UART1_MASK;
 500                         padconf = 0x182;
 501                         break;
 502                 case 1:
 503                         wk_mask = OMAP3430_ST_UART2_MASK;
 504                         padconf = 0x17a;
 505                         break;
 506                 case 2:
 507                         wk_mask = OMAP3430_ST_UART3_MASK;
 508                         padconf = 0x19e;
 509                         break;
 510                 case 3:
 511                         wk_mask = OMAP3630_ST_UART4_MASK;
 512                         padconf = 0x0d2;
 513                         break;
 514                 }
 515                 uart->wk_mask = wk_mask;
 516                 uart->padconf = padconf;
 517         } else if (cpu_is_omap24xx()) {
 518                 u32 wk_mask = 0;
 519                 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 520
 521                 switch (uart->num) {
 522                 case 0:
 523                         wk_mask = OMAP24XX_ST_UART1_MASK;
 524                         break;
 525                 case 1:
 526                         wk_mask = OMAP24XX_ST_UART2_MASK;
 527                         break;
 528                 case 2:
 529                         wk_en = OMAP24XX_PM_WKEN2;
 530                         wk_st = OMAP24XX_PM_WKST2;
 531                         wk_mask = OMAP24XX_ST_UART3_MASK;
 532                         break;
 533                 }
 534                 uart->wk_mask = wk_mask;
 535                 if (cpu_is_omap2430()) {
 536                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
 537                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
 538                 } else if (cpu_is_omap2420()) {
 539                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
 540                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
 541                 }
 542         } else {
 543                 uart->wk_en = NULL;
 544                 uart->wk_st = NULL;
 545                 uart->wk_mask = 0;
 546                 uart->padconf = 0;
 547         }
 548
 549         uart->irqflags |= IRQF_SHARED;
 550         ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
 551                                    IRQF_SHARED, "serial idle", (void *)uart);
 552         WARN_ON(ret);
 553 }
 554
 555 void omap_uart_enable_irqs(int enable)
 556 {
 557         int ret;
 558         struct omap_uart_state *uart;
 559
 560         list_for_each_entry(uart, &uart_list, node) {
 561                 if (enable) {
 562                         pm_runtime_put_sync(&uart->pdev->dev);
 563                         ret = request_threaded_irq(uart->irq, NULL,
 564                                                    omap_uart_interrupt,
 565                                                    IRQF_SHARED,
 566                                                    "serial idle",
 567                                                    (void *)uart);
 568                 } else {
 569                         pm_runtime_get_noresume(&uart->pdev->dev);
 570                         free_irq(uart->irq, (void *)uart);
 571                 }
 572         }
 573 }
 574
 575 static ssize_t sleep_timeout_show(struct device *dev,
 576                                   struct device_attribute *attr,
 577                                   char *buf)
 578 {
 579         struct platform_device *pdev = to_platform_device(dev);
 580         struct omap_device *odev = to_omap_device(pdev);
 581         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 582
 583         return sprintf(buf, "%u\n", uart->timeout / HZ);
 584 }
 585
 586 static ssize_t sleep_timeout_store(struct device *dev,
 587                                    struct device_attribute *attr,
 588                                    const char *buf, size_t n)
 589 {
 590         struct platform_device *pdev = to_platform_device(dev);
 591         struct omap_device *odev = to_omap_device(pdev);
 592         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 593         unsigned int value;
 594
 595         if (sscanf(buf, "%u", &value) != 1) {
 596                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
 597                 return -EINVAL;
 598         }
 599
 600         uart->timeout = value * HZ;
 601         if (uart->timeout)
 602                 mod_timer(&uart->timer, jiffies + uart->timeout);
 603         else
 604                 /* A zero value means disable timeout feature */
 605                 omap_uart_block_sleep(uart);
 606
 607         return n;
 608 }
 609
 610 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 611                 sleep_timeout_store);
 612 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 613 #else
 614 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 615 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 616 {
 617         /* Needed to enable UART clocks when built without CONFIG_PM */
 618         omap_uart_enable_clocks(uart);
 619 }
 620 #define DEV_CREATE_FILE(dev, attr)
 621 #endif /* CONFIG_PM */
 622
 623 #ifndef CONFIG_SERIAL_OMAP
 624 /*
 625  * Override the default 8250 read handler: mem_serial_in()
 626  * Empty RX fifo read causes an abort on omap3630 and omap4
 627  * This function makes sure that an empty rx fifo is not read on these silicons
 628  * (OMAP1/2/3430 are not affected)
 629  */
 630 static unsigned int serial_in_override(struct uart_port *up, int offset)
 631 {
 632         if (UART_RX == offset) {
 633                 unsigned int lsr;
 634                 lsr = __serial_read_reg(up, UART_LSR);
 635                 if (!(lsr & UART_LSR_DR))
 636                         return -EPERM;
 637         }
 638
 639         return __serial_read_reg(up, offset);
 640 }
 641
 642 static void serial_out_override(struct uart_port *up, int offset, int value)
 643 {
 644         unsigned int status, tmout = 10000;
 645
 646         status = __serial_read_reg(up, UART_LSR);
 647         while (!(status & UART_LSR_THRE)) {
 648                 /* Wait up to 10ms for the character(s) to be sent. */
 649                 if (--tmout == 0)
 650                         break;
 651                 udelay(1);
 652                 status = __serial_read_reg(up, UART_LSR);
 653         }
 654         __serial_write_reg(up, offset, value);
 655 }
 656 #endif
 657
 658 static int __init omap_serial_early_init(void)
 659 {
 660         int i = 0;
 661
 662         do {
 663                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
 664                 struct omap_hwmod *oh;
 665                 struct omap_uart_state *uart;
 666
 667                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
 668                          "uart%d", i + 1);
 669                 oh = omap_hwmod_lookup(oh_name);
 670                 if (!oh)
 671                         break;
 672
 673                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
 674                 if (WARN_ON(!uart))
 675                         return -ENODEV;
 676
 677                 uart->oh = oh;
 678                 uart->num = i++;
 679                 list_add_tail(&uart->node, &uart_list);
 680                 num_uarts++;
 681
 682                 /*
 683                  * NOTE: omap_hwmod_setup*() has not yet been called,
 684                  *       so no hwmod functions will work yet.
 685                  */
 686
 687                 /*
 688                  * During UART early init, device need to be probed
 689                  * to determine SoC specific init before omap_device
 690                  * is ready.  Therefore, don't allow idle here
 691                  */
 692                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
 693         } while (1);
 694
 695         return 0;
 696 }
 697 core_initcall(omap_serial_early_init);
 698
 699 /**
 700  * omap_serial_init_port() - initialize single serial port
 701  * @bdata: port specific board data pointer
 702  *
 703  * This function initialies serial driver for given port only.
 704  * Platforms can call this function instead of omap_serial_init()
 705  * if they don't plan to use all available UARTs as serial ports.
 706  *
 707  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 708  * use only one of the two.
 709  */
 710 void __init omap_serial_init_port(struct omap_board_data *bdata)
 711 {
 712         struct omap_uart_state *uart;
 713         struct omap_hwmod *oh;
 714         struct omap_device *od;
 715         void *pdata = NULL;
 716         u32 pdata_size = 0;
 717         char *name;
 718 #ifndef CONFIG_SERIAL_OMAP
 719         struct plat_serial8250_port ports[2] = {
 720                 {},
 721                 {.flags = 0},
 722         };
 723         struct plat_serial8250_port *p = &ports[0];
 724 #else
 725         struct omap_uart_port_info omap_up;
 726 #endif
 727
 728         if (WARN_ON(!bdata))
 729                 return;
 730         if (WARN_ON(bdata->id < 0))
 731                 return;
 732         if (WARN_ON(bdata->id >= num_uarts))
 733                 return;
 734
 735         list_for_each_entry(uart, &uart_list, node)
 736                 if (bdata->id == uart->num)
 737                         break;
 738
 739         oh = uart->oh;
 740         uart->dma_enabled = 0;
 741 #ifndef CONFIG_SERIAL_OMAP
 742         name = "serial8250";
 743
 744         /*
 745          * !! 8250 driver does not use standard IORESOURCE* It
 746          * has it's own custom pdata that can be taken from
 747          * the hwmod resource data.  But, this needs to be
 748          * done after the build.
 749          *
 750          * ?? does it have to be done before the register ??
 751          * YES, because platform_device_data_add() copies
 752          * pdata, it does not use a pointer.
 753          */
 754         p->flags = UPF_BOOT_AUTOCONF;
 755         p->iotype = UPIO_MEM;
 756         p->regshift = 2;
 757         p->uartclk = OMAP24XX_BASE_BAUD * 16;
 758         p->irq = oh->mpu_irqs[0].irq;
 759         p->mapbase = oh->slaves[0]->addr->pa_start;
 760         p->membase = omap_hwmod_get_mpu_rt_va(oh);
 761         p->irqflags = IRQF_SHARED;
 762         p->private_data = uart;
 763
 764         /*
 765          * omap44xx, ti816x: Never read empty UART fifo
 766          * omap3xxx: Never read empty UART fifo on UARTs
 767          * with IP rev >=0x52
 768          */
 769         uart->regshift = p->regshift;
 770         uart->membase = p->membase;
 771         if (cpu_is_omap44xx() || cpu_is_ti816x())
 772                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 773         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
 774                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
 775                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 776
 777         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
 778                 p->serial_in = serial_in_override;
 779                 p->serial_out = serial_out_override;
 780         }
 781
 782         pdata = &ports[0];
 783         pdata_size = 2 * sizeof(struct plat_serial8250_port);
 784 #else
 785
 786         name = DRIVER_NAME;
 787
 788         omap_up.dma_enabled = uart->dma_enabled;
 789         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
 790         omap_up.mapbase = oh->slaves[0]->addr->pa_start;
 791         omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
 792         omap_up.irqflags = IRQF_SHARED;
 793         omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
 794
 795         pdata = &omap_up;
 796         pdata_size = sizeof(struct omap_uart_port_info);
 797 #endif
 798
 799         if (WARN_ON(!oh))
 800                 return;
 801
 802         od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
 803                                omap_uart_latency,
 804                                ARRAY_SIZE(omap_uart_latency), false);
 805         WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
 806              name, oh->name);
 807
 808         omap_device_disable_idle_on_suspend(od);
 809         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 810
 811         uart->irq = oh->mpu_irqs[0].irq;
 812         uart->regshift = 2;
 813         uart->mapbase = oh->slaves[0]->addr->pa_start;
 814         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
 815         uart->pdev = &od->pdev;
 816
 817         oh->dev_attr = uart;
 818
 819         console_lock(); /* in case the earlycon is on the UART */
 820
 821         /*
 822          * Because of early UART probing, UART did not get idled
 823          * on init.  Now that omap_device is ready, ensure full idle
 824          * before doing omap_device_enable().
 825          */
 826         omap_hwmod_idle(uart->oh);
 827
 828         omap_device_enable(uart->pdev);
 829         omap_uart_idle_init(uart);
 830         omap_uart_reset(uart);
 831         omap_hwmod_enable_wakeup(uart->oh);
 832         omap_device_idle(uart->pdev);
 833
 834         /*
 835          * Need to block sleep long enough for interrupt driven
 836          * driver to start.  Console driver is in polling mode
 837          * so device needs to be kept enabled while polling driver
 838          * is in use.
 839          */
 840         if (uart->timeout)
 841                 uart->timeout = (30 * HZ);
 842         omap_uart_block_sleep(uart);
 843         uart->timeout = DEFAULT_TIMEOUT;
 844
 845         console_unlock();
 846
 847         if ((cpu_is_omap34xx() && uart->padconf) ||
 848             (uart->wk_en && uart->wk_mask)) {
 849                 device_init_wakeup(&od->pdev.dev, true);
 850                 DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
 851         }
 852
 853         /* Enable the MDR1 errata for OMAP3 */
 854         if (cpu_is_omap34xx() && !cpu_is_ti816x())
 855                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 856 }
 857
 858 /**
 859  * omap_serial_init() - initialize all supported serial ports
 860  *
 861  * Initializes all available UARTs as serial ports. Platforms
 862  * can call this function when they want to have default behaviour
 863  * for serial ports (e.g initialize them all as serial ports).
 864  */
 865 void __init omap_serial_init(void)
 866 {
 867         struct omap_uart_state *uart;
 868         struct omap_board_data bdata;
 869
 870         list_for_each_entry(uart, &uart_list, node) {
 871                 bdata.id = uart->num;
 872                 bdata.flags = 0;
 873                 bdata.pads = NULL;
 874                 bdata.pads_cnt = 0;
 875                 omap_serial_init_port(&bdata);
 876
 877         }
 878 }