arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/console.h>
  31 #include <linux/module.h>
  32
  33 #ifdef CONFIG_SERIAL_OMAP
  34 #include <plat/omap-serial.h>
  35 #endif
  36
  37 #include <plat/common.h>
  38 #include <plat/board.h>
  39 #include <plat/clock.h>
  40 #include <plat/dma.h>
  41 #include <plat/omap_hwmod.h>
  42 #include <plat/omap_device.h>
  43
  44 #include "prm2xxx_3xxx.h"
  45 #include "pm.h"
  46 #include "cm2xxx_3xxx.h"
  47 #include "prm-regbits-34xx.h"
  48 #include "control.h"
  49 #include "mux.h"
  50
  51 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  52 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  53
  54 #define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
  55 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
  56
  57 /*
  58  * NOTE: By default the serial timeout is disabled as it causes lost characters
  59  * over the serial ports. This means that the UART clocks will stay on until
  60  * disabled via sysfs. This also causes that any deeper omap sleep states are
  61  * blocked.
  62  */
  63 #define DEFAULT_TIMEOUT (10 * HZ)
  64
  65 #define MAX_UART_HWMOD_NAME_LEN         16
  66
  67 struct omap_uart_state {
  68         int num;
  69         int can_sleep;
  70         struct timer_list timer;
  71         u32 timeout;
  72
  73         void __iomem *wk_st;
  74         void __iomem *wk_en;
  75         u32 wk_mask;
  76         u32 padconf;
  77         u32 padconf2;
  78         u32 dma_enabled;
  79
  80         struct clk *ick;
  81         struct clk *fck;
  82         int clocked;
  83
  84         int irq;
  85         int regshift;
  86         int irqflags;
  87         void __iomem *membase;
  88         resource_size_t mapbase;
  89
  90         struct list_head node;
  91         struct omap_hwmod *oh;
  92         struct platform_device *pdev;
  93
  94         u32 errata;
  95 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  96         int context_valid;
  97
  98         /* Registers to be saved/restored for OFF-mode */
  99         u16 dll;
 100         u16 dlh;
 101         u16 ier;
 102         u16 sysc;
 103         u16 scr;
 104         u16 wer;
 105         u16 mcr;
 106 #endif
 107 };
 108
 109 static LIST_HEAD(uart_list);
 110 static u8 num_uarts;
 111
 112 static inline unsigned int __serial_read_reg(struct uart_port *up,
 113                                              int offset)
 114 {
 115         offset <<= up->regshift;
 116         return (unsigned int)__raw_readb(up->membase + offset);
 117 }
 118
 119 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
 120                                            int offset)
 121 {
 122         offset <<= uart->regshift;
 123         return (unsigned int)__raw_readb(uart->membase + offset);
 124 }
 125
 126 static inline void __serial_write_reg(struct uart_port *up, int offset,
 127                 int value)
 128 {
 129         offset <<= up->regshift;
 130         __raw_writeb(value, up->membase + offset);
 131 }
 132
 133 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
 134                                     int value)
 135 {
 136         offset <<= uart->regshift;
 137         __raw_writeb(value, uart->membase + offset);
 138 }
 139
 140 /*
 141  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 142  * properly. Note that the TX watermark initialization may not be needed
 143  * once the 8250.c watermark handling code is merged.
 144  */
 145
 146 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 147 {
 148         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 149         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
 150         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 151 }
 152
 153 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 154
 155 /*
 156  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 157  * The access to uart register after MDR1 Access
 158  * causes UART to corrupt data.
 159  *
 160  * Need a delay =
 161  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 162  * give 10 times as much
 163  */
 164 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 165                 u8 fcr_val)
 166 {
 167         u8 timeout = 255;
 168
 169         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
 170         udelay(2);
 171         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
 172                         UART_FCR_CLEAR_RCVR);
 173         /*
 174          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 175          * TX_FIFO_E bit is 1.
 176          */
 177         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
 178                                 (UART_LSR_THRE | UART_LSR_DR))) {
 179                 timeout--;
 180                 if (!timeout) {
 181                         /* Should *never* happen. we warn and carry on */
 182                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
 183                         serial_read_reg(uart, UART_LSR));
 184                         break;
 185                 }
 186                 udelay(1);
 187         }
 188 }
 189
 190 static void omap_uart_save_context(struct omap_uart_state *uart)
 191 {
 192         u16 lcr = 0;
 193
 194         if (!enable_off_mode)
 195                 return;
 196
 197         lcr = serial_read_reg(uart, UART_LCR);
 198         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 199         uart->dll = serial_read_reg(uart, UART_DLL);
 200         uart->dlh = serial_read_reg(uart, UART_DLM);
 201         serial_write_reg(uart, UART_LCR, lcr);
 202         uart->ier = serial_read_reg(uart, UART_IER);
 203         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
 204         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
 205         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
 206         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 207         uart->mcr = serial_read_reg(uart, UART_MCR);
 208         serial_write_reg(uart, UART_LCR, lcr);
 209
 210         uart->context_valid = 1;
 211 }
 212
 213 static void omap_uart_restore_context(struct omap_uart_state *uart)
 214 {
 215         u16 efr = 0;
 216
 217         if (!enable_off_mode)
 218                 return;
 219
 220         if (!uart->context_valid)
 221                 return;
 222
 223         uart->context_valid = 0;
 224
 225         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 226                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
 227         else
 228                 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 229
 230         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 231         efr = serial_read_reg(uart, UART_EFR);
 232         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
 233         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 234         serial_write_reg(uart, UART_IER, 0x0);
 235         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 236         serial_write_reg(uart, UART_DLL, uart->dll);
 237         serial_write_reg(uart, UART_DLM, uart->dlh);
 238         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 239         serial_write_reg(uart, UART_IER, uart->ier);
 240         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 241         serial_write_reg(uart, UART_MCR, uart->mcr);
 242         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 243         serial_write_reg(uart, UART_EFR, efr);
 244         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
 245         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
 246         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
 247         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
 248
 249         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 250                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
 251         else
 252                 /* UART 16x mode */
 253                 serial_write_reg(uart, UART_OMAP_MDR1,
 254                                 UART_OMAP_MDR1_16X_MODE);
 255 }
 256 #else
 257 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 258 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 259 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 260
 261 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 262 {
 263         if (uart->clocked)
 264                 return;
 265
 266         omap_device_enable(uart->pdev);
 267         uart->clocked = 1;
 268         omap_uart_restore_context(uart);
 269 }
 270
 271 #ifdef CONFIG_PM
 272
 273 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 274 {
 275         if (!uart->clocked)
 276                 return;
 277
 278         omap_uart_save_context(uart);
 279         uart->clocked = 0;
 280         omap_device_idle(uart->pdev);
 281 }
 282
 283 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 284 {
 285         /* Set wake-enable bit */
 286         if (uart->wk_en && uart->wk_mask) {
 287                 u32 v = __raw_readl(uart->wk_en);
 288                 v |= uart->wk_mask;
 289                 __raw_writel(v, uart->wk_en);
 290         }
 291
 292         /* Ensure IOPAD wake-enables are set */
 293         if (cpu_is_omap34xx()) {
 294                 if (uart->padconf) {
 295                         u16 v = omap_ctrl_readw(uart->padconf);
 296                         v |= OMAP3_PADCONF_WAKEUPENABLE0;
 297                         omap_ctrl_writew(v, uart->padconf);
 298                 }
 299                 if (uart->padconf2) {
 300                         u16 v = omap_ctrl_readw(uart->padconf2);
 301                         v |= OMAP3_PADCONF_WAKEUPENABLE0;
 302                         omap_ctrl_writew(v, uart->padconf2);
 303                 }
 304         }
 305 }
 306
 307 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 308 {
 309         /* Clear wake-enable bit */
 310         if (uart->wk_en && uart->wk_mask) {
 311                 u32 v = __raw_readl(uart->wk_en);
 312                 v &= ~uart->wk_mask;
 313                 __raw_writel(v, uart->wk_en);
 314         }
 315
 316         /* Ensure IOPAD wake-enables are cleared */
 317         if (cpu_is_omap34xx()) {
 318                 if (uart->padconf) {
 319                         u16 v = omap_ctrl_readw(uart->padconf);
 320                         v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 321                         omap_ctrl_writew(v, uart->padconf);
 322                 }
 323                 if (uart->padconf2) {
 324                         u16 v = omap_ctrl_readw(uart->padconf2);
 325                         v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 326                         omap_ctrl_writew(v, uart->padconf2);
 327                 }
 328         }
 329 }
 330
 331 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 332                                                int enable)
 333 {
 334         u8 idlemode;
 335
 336         if (enable) {
 337                 /**
 338                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
 339                  * in Smartidle Mode When Configured for DMA Operations.
 340                  */
 341                 if (uart->dma_enabled)
 342                         idlemode = HWMOD_IDLEMODE_FORCE;
 343                 else
 344                         idlemode = HWMOD_IDLEMODE_SMART;
 345         } else {
 346                 idlemode = HWMOD_IDLEMODE_NO;
 347         }
 348
 349         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 350 }
 351
 352 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 353 {
 354         omap_uart_enable_clocks(uart);
 355
 356         omap_uart_smart_idle_enable(uart, 0);
 357         uart->can_sleep = 0;
 358         if (uart->timeout)
 359                 mod_timer(&uart->timer, jiffies + uart->timeout);
 360         else
 361                 del_timer(&uart->timer);
 362 }
 363
 364 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 365 {
 366         if (device_may_wakeup(&uart->pdev->dev))
 367                 omap_uart_enable_wakeup(uart);
 368         else
 369                 omap_uart_disable_wakeup(uart);
 370
 371         if (!uart->clocked)
 372                 return;
 373
 374         omap_uart_smart_idle_enable(uart, 1);
 375         uart->can_sleep = 1;
 376         del_timer(&uart->timer);
 377 }
 378
 379 void omap_uart_block_sleep_id(int num)
 380 {
 381         struct omap_uart_state *uart;
 382
 383         list_for_each_entry(uart, &uart_list, node) {
 384                 if (num == uart->num && uart->can_sleep) {
 385                         omap_uart_block_sleep(uart);
 386                         return;
 387                 }
 388         }
 389 }
 390 EXPORT_SYMBOL(omap_uart_block_sleep_id);
 391
 392 static void omap_uart_idle_timer(unsigned long data)
 393 {
 394         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 395
 396         omap_uart_allow_sleep(uart);
 397 }
 398
 399 void omap_uart_prepare_idle(int num)
 400 {
 401         struct omap_uart_state *uart;
 402
 403         list_for_each_entry(uart, &uart_list, node) {
 404                 if (num == uart->num && uart->can_sleep) {
 405                         omap_uart_disable_clocks(uart);
 406                         return;
 407                 }
 408         }
 409 }
 410
 411 void omap_uart_resume_idle(int num)
 412 {
 413         struct omap_uart_state *uart;
 414
 415         list_for_each_entry(uart, &uart_list, node) {
 416                 if (num == uart->num && uart->can_sleep) {
 417                         omap_uart_enable_clocks(uart);
 418
 419                         /* Check for IO pad wakeup */
 420                         if (cpu_is_omap34xx()) {
 421                                 u16 p = 0;
 422                                 if (uart->padconf)
 423                                         p |= omap_ctrl_readw(uart->padconf);
 424                                 if (uart->padconf2)
 425                                         p |= omap_ctrl_readw(uart->padconf2);
 426
 427                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 428                                         omap_uart_block_sleep(uart);
 429                         }
 430
 431                         /* Check for normal UART wakeup */
 432                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 433                                 omap_uart_block_sleep(uart);
 434                         return;
 435                 }
 436         }
 437 }
 438
 439 void omap_uart_prepare_suspend(void)
 440 {
 441         struct omap_uart_state *uart;
 442
 443         list_for_each_entry(uart, &uart_list, node) {
 444                 omap_uart_allow_sleep(uart);
 445         }
 446 }
 447
 448 int omap_uart_can_sleep(void)
 449 {
 450         struct omap_uart_state *uart;
 451         int can_sleep = 1;
 452
 453         list_for_each_entry(uart, &uart_list, node) {
 454                 if (!uart->clocked)
 455                         continue;
 456
 457                 if (!uart->can_sleep) {
 458                         can_sleep = 0;
 459                         continue;
 460                 }
 461
 462                 /* This UART can now safely sleep. */
 463                 omap_uart_allow_sleep(uart);
 464         }
 465
 466         return can_sleep;
 467 }
 468
 469 /**
 470  * omap_uart_interrupt()
 471  *
 472  * This handler is used only to detect that *any* UART interrupt has
 473  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 474  * any UART interrupt will trigger the inactivity timer so the
 475  * UART will not idle or sleep for its timeout period.
 476  *
 477  **/
 478 /* static int first_interrupt; */
 479 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 480 {
 481         struct omap_uart_state *uart = dev_id;
 482
 483         omap_uart_block_sleep(uart);
 484
 485         return IRQ_NONE;
 486 }
 487
 488 static void omap_uart_idle_init(struct omap_uart_state *uart)
 489 {
 490         int ret;
 491
 492         uart->can_sleep = 0;
 493         uart->timeout = DEFAULT_TIMEOUT;
 494         setup_timer(&uart->timer, omap_uart_idle_timer,
 495                     (unsigned long) uart);
 496         if (uart->timeout)
 497                 mod_timer(&uart->timer, jiffies + uart->timeout);
 498         omap_uart_smart_idle_enable(uart, 0);
 499
 500         if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
 501                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 502                 u32 wk_mask = 0;
 503                 u32 padconf = 0;
 504                 u32 padconf2 = 0;
 505
 506                 /* XXX These PRM accesses do not belong here */
 507                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 508                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 509                 switch (uart->num) {
 510                 case 0:
 511                         wk_mask = OMAP3430_ST_UART1_MASK;
 512                         padconf = 0x182;
 513                         padconf2 = 0x180;
 514                         break;
 515                 case 1:
 516                         wk_mask = OMAP3430_ST_UART2_MASK;
 517                         padconf = 0x17a;
 518                         break;
 519                 case 2:
 520                         wk_mask = OMAP3430_ST_UART3_MASK;
 521                         padconf = 0x19e;
 522                         break;
 523                 case 3:
 524                         wk_mask = OMAP3630_ST_UART4_MASK;
 525                         padconf = 0x0d2;
 526                         break;
 527                 }
 528                 uart->wk_mask = wk_mask;
 529                 uart->padconf = padconf;
 530                 uart->padconf2 = padconf2;
 531         } else if (cpu_is_omap24xx()) {
 532                 u32 wk_mask = 0;
 533                 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 534
 535                 switch (uart->num) {
 536                 case 0:
 537                         wk_mask = OMAP24XX_ST_UART1_MASK;
 538                         break;
 539                 case 1:
 540                         wk_mask = OMAP24XX_ST_UART2_MASK;
 541                         break;
 542                 case 2:
 543                         wk_en = OMAP24XX_PM_WKEN2;
 544                         wk_st = OMAP24XX_PM_WKST2;
 545                         wk_mask = OMAP24XX_ST_UART3_MASK;
 546                         break;
 547                 }
 548                 uart->wk_mask = wk_mask;
 549                 if (cpu_is_omap2430()) {
 550                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
 551                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
 552                 } else if (cpu_is_omap2420()) {
 553                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
 554                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
 555                 }
 556         } else {
 557                 uart->wk_en = NULL;
 558                 uart->wk_st = NULL;
 559                 uart->wk_mask = 0;
 560                 uart->padconf = 0;
 561                 uart->padconf2 = 0;
 562         }
 563
 564         uart->irqflags |= IRQF_SHARED;
 565         ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
 566                                    IRQF_SHARED, "serial idle", (void *)uart);
 567         WARN_ON(ret);
 568 }
 569
 570 void omap_uart_enable_irqs(int enable)
 571 {
 572         int ret;
 573         struct omap_uart_state *uart;
 574
 575         list_for_each_entry(uart, &uart_list, node) {
 576                 if (enable) {
 577                         pm_runtime_put_sync(&uart->pdev->dev);
 578                         ret = request_threaded_irq(uart->irq, NULL,
 579                                                    omap_uart_interrupt,
 580                                                    IRQF_SHARED,
 581                                                    "serial idle",
 582                                                    (void *)uart);
 583                 } else {
 584                         pm_runtime_get_noresume(&uart->pdev->dev);
 585                         free_irq(uart->irq, (void *)uart);
 586                 }
 587         }
 588 }
 589
 590 static ssize_t sleep_timeout_show(struct device *dev,
 591                                   struct device_attribute *attr,
 592                                   char *buf)
 593 {
 594         struct platform_device *pdev = to_platform_device(dev);
 595         struct omap_device *odev = to_omap_device(pdev);
 596         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 597
 598         return sprintf(buf, "%u\n", uart->timeout / HZ);
 599 }
 600
 601 static ssize_t sleep_timeout_store(struct device *dev,
 602                                    struct device_attribute *attr,
 603                                    const char *buf, size_t n)
 604 {
 605         struct platform_device *pdev = to_platform_device(dev);
 606         struct omap_device *odev = to_omap_device(pdev);
 607         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 608         unsigned int value;
 609
 610         if (sscanf(buf, "%u", &value) != 1) {
 611                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
 612                 return -EINVAL;
 613         }
 614
 615         uart->timeout = value * HZ;
 616         if (uart->timeout)
 617                 mod_timer(&uart->timer, jiffies + uart->timeout);
 618         else
 619                 /* A zero value means disable timeout feature */
 620                 omap_uart_block_sleep(uart);
 621
 622         return n;
 623 }
 624
 625 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 626                 sleep_timeout_store);
 627 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 628 #else
 629 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 630 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 631 {
 632         /* Needed to enable UART clocks when built without CONFIG_PM */
 633         omap_uart_enable_clocks(uart);
 634 }
 635 #define DEV_CREATE_FILE(dev, attr)
 636 #endif /* CONFIG_PM */
 637
 638 #ifndef CONFIG_SERIAL_OMAP
 639 /*
 640  * Override the default 8250 read handler: mem_serial_in()
 641  * Empty RX fifo read causes an abort on omap3630 and omap4
 642  * This function makes sure that an empty rx fifo is not read on these silicons
 643  * (OMAP1/2/3430 are not affected)
 644  */
 645 static unsigned int serial_in_override(struct uart_port *up, int offset)
 646 {
 647         if (UART_RX == offset) {
 648                 unsigned int lsr;
 649                 lsr = __serial_read_reg(up, UART_LSR);
 650                 if (!(lsr & UART_LSR_DR))
 651                         return -EPERM;
 652         }
 653
 654         return __serial_read_reg(up, offset);
 655 }
 656
 657 static void serial_out_override(struct uart_port *up, int offset, int value)
 658 {
 659         unsigned int status, tmout = 10000;
 660
 661         status = __serial_read_reg(up, UART_LSR);
 662         while (!(status & UART_LSR_THRE)) {
 663                 /* Wait up to 10ms for the character(s) to be sent. */
 664                 if (--tmout == 0)
 665                         break;
 666                 udelay(1);
 667                 status = __serial_read_reg(up, UART_LSR);
 668         }
 669         __serial_write_reg(up, offset, value);
 670 }
 671 #endif
 672
 673 static int __init omap_serial_early_init(void)
 674 {
 675         int i = 0;
 676
 677         do {
 678                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
 679                 struct omap_hwmod *oh;
 680                 struct omap_uart_state *uart;
 681
 682                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
 683                          "uart%d", i + 1);
 684                 oh = omap_hwmod_lookup(oh_name);
 685                 if (!oh)
 686                         break;
 687
 688                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
 689                 if (WARN_ON(!uart))
 690                         return -ENODEV;
 691
 692                 uart->oh = oh;
 693                 uart->num = i++;
 694                 list_add_tail(&uart->node, &uart_list);
 695                 num_uarts++;
 696
 697                 /*
 698                  * NOTE: omap_hwmod_setup*() has not yet been called,
 699                  *       so no hwmod functions will work yet.
 700                  */
 701
 702                 /*
 703                  * During UART early init, device need to be probed
 704                  * to determine SoC specific init before omap_device
 705                  * is ready.  Therefore, don't allow idle here
 706                  */
 707                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
 708         } while (1);
 709
 710         return 0;
 711 }
 712 core_initcall(omap_serial_early_init);
 713
 714 /**
 715  * omap_serial_init_port() - initialize single serial port
 716  * @bdata: port specific board data pointer
 717  *
 718  * This function initialies serial driver for given port only.
 719  * Platforms can call this function instead of omap_serial_init()
 720  * if they don't plan to use all available UARTs as serial ports.
 721  *
 722  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 723  * use only one of the two.
 724  */
 725 void __init omap_serial_init_port(struct omap_board_data *bdata)
 726 {
 727         struct omap_uart_state *uart;
 728         struct omap_hwmod *oh;
 729         struct platform_device *pdev;
 730         void *pdata = NULL;
 731         u32 pdata_size = 0;
 732         char *name;
 733 #ifndef CONFIG_SERIAL_OMAP
 734         struct plat_serial8250_port ports[2] = {
 735                 {},
 736                 {.flags = 0},
 737         };
 738         struct plat_serial8250_port *p = &ports[0];
 739 #else
 740         struct omap_uart_port_info omap_up;
 741 #endif
 742
 743         if (WARN_ON(!bdata))
 744                 return;
 745         if (WARN_ON(bdata->id < 0))
 746                 return;
 747         if (WARN_ON(bdata->id >= num_uarts))
 748                 return;
 749
 750         list_for_each_entry(uart, &uart_list, node)
 751                 if (bdata->id == uart->num)
 752                         break;
 753
 754         oh = uart->oh;
 755         uart->dma_enabled = 0;
 756 #ifndef CONFIG_SERIAL_OMAP
 757         name = "serial8250";
 758
 759         /*
 760          * !! 8250 driver does not use standard IORESOURCE* It
 761          * has it's own custom pdata that can be taken from
 762          * the hwmod resource data.  But, this needs to be
 763          * done after the build.
 764          *
 765          * ?? does it have to be done before the register ??
 766          * YES, because platform_device_data_add() copies
 767          * pdata, it does not use a pointer.
 768          */
 769         p->flags = UPF_BOOT_AUTOCONF;
 770         p->iotype = UPIO_MEM;
 771         p->regshift = 2;
 772         p->uartclk = OMAP24XX_BASE_BAUD * 16;
 773         p->irq = oh->mpu_irqs[0].irq;
 774         p->mapbase = oh->slaves[0]->addr->pa_start;
 775         p->membase = omap_hwmod_get_mpu_rt_va(oh);
 776         p->irqflags = IRQF_SHARED;
 777         p->private_data = uart;
 778
 779         /*
 780          * omap44xx, ti816x: Never read empty UART fifo
 781          * omap3xxx: Never read empty UART fifo on UARTs
 782          * with IP rev >=0x52
 783          */
 784         uart->regshift = p->regshift;
 785         uart->membase = p->membase;
 786         if (cpu_is_omap44xx() || cpu_is_ti816x())
 787                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 788         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
 789                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
 790                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 791
 792         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
 793                 p->serial_in = serial_in_override;
 794                 p->serial_out = serial_out_override;
 795         }
 796
 797         pdata = &ports[0];
 798         pdata_size = 2 * sizeof(struct plat_serial8250_port);
 799 #else
 800
 801         name = DRIVER_NAME;
 802
 803         omap_up.dma_enabled = uart->dma_enabled;
 804         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
 805         omap_up.mapbase = oh->slaves[0]->addr->pa_start;
 806         omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
 807         omap_up.irqflags = IRQF_SHARED;
 808         omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
 809
 810         pdata = &omap_up;
 811         pdata_size = sizeof(struct omap_uart_port_info);
 812 #endif
 813
 814         if (WARN_ON(!oh))
 815                 return;
 816
 817         pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
 818                                  NULL, 0, false);
 819         WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
 820              name, oh->name);
 821
 822         omap_device_disable_idle_on_suspend(pdev);
 823         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 824
 825         uart->irq = oh->mpu_irqs[0].irq;
 826         uart->regshift = 2;
 827         uart->mapbase = oh->slaves[0]->addr->pa_start;
 828         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
 829         uart->pdev = pdev;
 830
 831         oh->dev_attr = uart;
 832
 833         console_lock(); /* in case the earlycon is on the UART */
 834
 835         /*
 836          * Because of early UART probing, UART did not get idled
 837          * on init.  Now that omap_device is ready, ensure full idle
 838          * before doing omap_device_enable().
 839          */
 840         omap_hwmod_idle(uart->oh);
 841
 842         omap_device_enable(uart->pdev);
 843         omap_uart_idle_init(uart);
 844         omap_uart_reset(uart);
 845         omap_hwmod_enable_wakeup(uart->oh);
 846         omap_device_idle(uart->pdev);
 847
 848         /*
 849          * Need to block sleep long enough for interrupt driven
 850          * driver to start.  Console driver is in polling mode
 851          * so device needs to be kept enabled while polling driver
 852          * is in use.
 853          */
 854         if (uart->timeout)
 855                 uart->timeout = (30 * HZ);
 856         omap_uart_block_sleep(uart);
 857         uart->timeout = DEFAULT_TIMEOUT;
 858
 859         console_unlock();
 860
 861         if ((cpu_is_omap34xx() && (uart->padconf || uart->padconf2)) ||
 862             (uart->wk_en && uart->wk_mask)) {
 863                 device_init_wakeup(&pdev->dev, true);
 864                 DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
 865         }
 866
 867         /* Enable the MDR1 errata for OMAP3 */
 868         if (cpu_is_omap34xx() && !cpu_is_ti816x())
 869                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 870 }
 871
 872 /**
 873  * omap_serial_init() - initialize all supported serial ports
 874  *
 875  * Initializes all available UARTs as serial ports. Platforms
 876  * can call this function when they want to have default behaviour
 877  * for serial ports (e.g initialize them all as serial ports).
 878  */
 879 void __init omap_serial_init(void)
 880 {
 881         struct omap_uart_state *uart;
 882         struct omap_board_data bdata;
 883
 884         list_for_each_entry(uart, &uart_list, node) {
 885                 bdata.id = uart->num;
 886                 bdata.flags = 0;
 887                 bdata.pads = NULL;
 888                 bdata.pads_cnt = 0;
 889                 omap_serial_init_port(&bdata);
 890
 891         }
 892 }