2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/serial_8250.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/console.h>
31 #include <linux/module.h>
33 #ifdef CONFIG_SERIAL_OMAP
34 #include <plat/omap-serial.h>
37 #include <plat/common.h>
38 #include <plat/board.h>
39 #include <plat/clock.h>
41 #include <plat/omap_hwmod.h>
42 #include <plat/omap_device.h>
44 #include "prm2xxx_3xxx.h"
46 #include "cm2xxx_3xxx.h"
47 #include "prm-regbits-34xx.h"
51 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
54 #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
55 #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
58 * NOTE: By default the serial timeout is disabled as it causes lost characters
59 * over the serial ports. This means that the UART clocks will stay on until
60 * disabled via sysfs. This also causes that any deeper omap sleep states are
63 #define DEFAULT_TIMEOUT (10 * HZ)
65 #define MAX_UART_HWMOD_NAME_LEN 16
67 struct omap_uart_state {
70 struct timer_list timer;
87 void __iomem *membase;
88 resource_size_t mapbase;
90 struct list_head node;
91 struct omap_hwmod *oh;
92 struct platform_device *pdev;
95 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
98 /* Registers to be saved/restored for OFF-mode */
109 static LIST_HEAD(uart_list);
112 static inline unsigned int __serial_read_reg(struct uart_port *up,
115 offset <<= up->regshift;
116 return (unsigned int)__raw_readb(up->membase + offset);
119 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
122 offset <<= uart->regshift;
123 return (unsigned int)__raw_readb(uart->membase + offset);
126 static inline void __serial_write_reg(struct uart_port *up, int offset,
129 offset <<= up->regshift;
130 __raw_writeb(value, up->membase + offset);
133 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
136 offset <<= uart->regshift;
137 __raw_writeb(value, uart->membase + offset);
141 * Internal UARTs need to be initialized for the 8250 autoconfig to work
142 * properly. Note that the TX watermark initialization may not be needed
143 * once the 8250.c watermark handling code is merged.
146 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
148 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
149 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
150 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
153 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
156 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
157 * The access to uart register after MDR1 Access
158 * causes UART to corrupt data.
161 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
162 * give 10 times as much
164 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
169 serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
171 serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
172 UART_FCR_CLEAR_RCVR);
174 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
175 * TX_FIFO_E bit is 1.
177 while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
178 (UART_LSR_THRE | UART_LSR_DR))) {
181 /* Should *never* happen. we warn and carry on */
182 dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
183 serial_read_reg(uart, UART_LSR));
190 static void omap_uart_save_context(struct omap_uart_state *uart)
194 if (!enable_off_mode)
197 lcr = serial_read_reg(uart, UART_LCR);
198 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
199 uart->dll = serial_read_reg(uart, UART_DLL);
200 uart->dlh = serial_read_reg(uart, UART_DLM);
201 serial_write_reg(uart, UART_LCR, lcr);
202 uart->ier = serial_read_reg(uart, UART_IER);
203 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
204 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
205 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
206 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
207 uart->mcr = serial_read_reg(uart, UART_MCR);
208 serial_write_reg(uart, UART_LCR, lcr);
210 uart->context_valid = 1;
213 static void omap_uart_restore_context(struct omap_uart_state *uart)
217 if (!enable_off_mode)
220 if (!uart->context_valid)
223 uart->context_valid = 0;
225 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
226 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
228 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
230 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
231 efr = serial_read_reg(uart, UART_EFR);
232 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
233 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
234 serial_write_reg(uart, UART_IER, 0x0);
235 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
236 serial_write_reg(uart, UART_DLL, uart->dll);
237 serial_write_reg(uart, UART_DLM, uart->dlh);
238 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
239 serial_write_reg(uart, UART_IER, uart->ier);
240 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
241 serial_write_reg(uart, UART_MCR, uart->mcr);
242 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
243 serial_write_reg(uart, UART_EFR, efr);
244 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
245 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
246 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
247 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
249 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
250 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
253 serial_write_reg(uart, UART_OMAP_MDR1,
254 UART_OMAP_MDR1_16X_MODE);
257 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
258 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
259 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
261 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
266 omap_device_enable(uart->pdev);
268 omap_uart_restore_context(uart);
273 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
278 omap_uart_save_context(uart);
280 omap_device_idle(uart->pdev);
283 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
285 /* Set wake-enable bit */
286 if (uart->wk_en && uart->wk_mask) {
287 u32 v = __raw_readl(uart->wk_en);
289 __raw_writel(v, uart->wk_en);
292 /* Ensure IOPAD wake-enables are set */
293 if (cpu_is_omap34xx()) {
295 u16 v = omap_ctrl_readw(uart->padconf);
296 v |= OMAP3_PADCONF_WAKEUPENABLE0;
297 omap_ctrl_writew(v, uart->padconf);
299 if (uart->padconf2) {
300 u16 v = omap_ctrl_readw(uart->padconf2);
301 v |= OMAP3_PADCONF_WAKEUPENABLE0;
302 omap_ctrl_writew(v, uart->padconf2);
307 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
309 /* Clear wake-enable bit */
310 if (uart->wk_en && uart->wk_mask) {
311 u32 v = __raw_readl(uart->wk_en);
313 __raw_writel(v, uart->wk_en);
316 /* Ensure IOPAD wake-enables are cleared */
317 if (cpu_is_omap34xx()) {
319 u16 v = omap_ctrl_readw(uart->padconf);
320 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
321 omap_ctrl_writew(v, uart->padconf);
323 if (uart->padconf2) {
324 u16 v = omap_ctrl_readw(uart->padconf2);
325 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
326 omap_ctrl_writew(v, uart->padconf2);
331 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
338 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
339 * in Smartidle Mode When Configured for DMA Operations.
341 if (uart->dma_enabled)
342 idlemode = HWMOD_IDLEMODE_FORCE;
344 idlemode = HWMOD_IDLEMODE_SMART;
346 idlemode = HWMOD_IDLEMODE_NO;
349 omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
352 static void omap_uart_block_sleep(struct omap_uart_state *uart)
354 omap_uart_enable_clocks(uart);
356 omap_uart_smart_idle_enable(uart, 0);
359 mod_timer(&uart->timer, jiffies + uart->timeout);
361 del_timer(&uart->timer);
364 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
366 if (device_may_wakeup(&uart->pdev->dev))
367 omap_uart_enable_wakeup(uart);
369 omap_uart_disable_wakeup(uart);
374 omap_uart_smart_idle_enable(uart, 1);
376 del_timer(&uart->timer);
379 void omap_uart_block_sleep_id(int num)
381 struct omap_uart_state *uart;
383 list_for_each_entry(uart, &uart_list, node) {
384 if (num == uart->num && uart->can_sleep) {
385 omap_uart_block_sleep(uart);
390 EXPORT_SYMBOL(omap_uart_block_sleep_id);
392 static void omap_uart_idle_timer(unsigned long data)
394 struct omap_uart_state *uart = (struct omap_uart_state *)data;
396 omap_uart_allow_sleep(uart);
399 void omap_uart_prepare_idle(int num)
401 struct omap_uart_state *uart;
403 list_for_each_entry(uart, &uart_list, node) {
404 if (num == uart->num && uart->can_sleep) {
405 omap_uart_disable_clocks(uart);
411 void omap_uart_resume_idle(int num)
413 struct omap_uart_state *uart;
415 list_for_each_entry(uart, &uart_list, node) {
416 if (num == uart->num && uart->can_sleep) {
417 omap_uart_enable_clocks(uart);
419 /* Check for IO pad wakeup */
420 if (cpu_is_omap34xx()) {
423 p |= omap_ctrl_readw(uart->padconf);
425 p |= omap_ctrl_readw(uart->padconf2);
427 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
428 omap_uart_block_sleep(uart);
431 /* Check for normal UART wakeup */
432 if (__raw_readl(uart->wk_st) & uart->wk_mask)
433 omap_uart_block_sleep(uart);
439 void omap_uart_prepare_suspend(void)
441 struct omap_uart_state *uart;
443 list_for_each_entry(uart, &uart_list, node) {
444 omap_uart_allow_sleep(uart);
448 int omap_uart_can_sleep(void)
450 struct omap_uart_state *uart;
453 list_for_each_entry(uart, &uart_list, node) {
457 if (!uart->can_sleep) {
462 /* This UART can now safely sleep. */
463 omap_uart_allow_sleep(uart);
470 * omap_uart_interrupt()
472 * This handler is used only to detect that *any* UART interrupt has
473 * occurred. It does _nothing_ to handle the interrupt. Rather,
474 * any UART interrupt will trigger the inactivity timer so the
475 * UART will not idle or sleep for its timeout period.
478 /* static int first_interrupt; */
479 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
481 struct omap_uart_state *uart = dev_id;
483 omap_uart_block_sleep(uart);
488 static void omap_uart_idle_init(struct omap_uart_state *uart)
493 uart->timeout = DEFAULT_TIMEOUT;
494 setup_timer(&uart->timer, omap_uart_idle_timer,
495 (unsigned long) uart);
497 mod_timer(&uart->timer, jiffies + uart->timeout);
498 omap_uart_smart_idle_enable(uart, 0);
500 if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
501 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
506 /* XXX These PRM accesses do not belong here */
507 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
508 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
511 wk_mask = OMAP3430_ST_UART1_MASK;
516 wk_mask = OMAP3430_ST_UART2_MASK;
520 wk_mask = OMAP3430_ST_UART3_MASK;
524 wk_mask = OMAP3630_ST_UART4_MASK;
528 uart->wk_mask = wk_mask;
529 uart->padconf = padconf;
530 uart->padconf2 = padconf2;
531 } else if (cpu_is_omap24xx()) {
533 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
537 wk_mask = OMAP24XX_ST_UART1_MASK;
540 wk_mask = OMAP24XX_ST_UART2_MASK;
543 wk_en = OMAP24XX_PM_WKEN2;
544 wk_st = OMAP24XX_PM_WKST2;
545 wk_mask = OMAP24XX_ST_UART3_MASK;
548 uart->wk_mask = wk_mask;
549 if (cpu_is_omap2430()) {
550 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
551 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
552 } else if (cpu_is_omap2420()) {
553 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
554 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
564 uart->irqflags |= IRQF_SHARED;
565 ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
566 IRQF_SHARED, "serial idle", (void *)uart);
570 void omap_uart_enable_irqs(int enable)
573 struct omap_uart_state *uart;
575 list_for_each_entry(uart, &uart_list, node) {
577 pm_runtime_put_sync(&uart->pdev->dev);
578 ret = request_threaded_irq(uart->irq, NULL,
584 pm_runtime_get_noresume(&uart->pdev->dev);
585 free_irq(uart->irq, (void *)uart);
590 static ssize_t sleep_timeout_show(struct device *dev,
591 struct device_attribute *attr,
594 struct platform_device *pdev = to_platform_device(dev);
595 struct omap_device *odev = to_omap_device(pdev);
596 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
598 return sprintf(buf, "%u\n", uart->timeout / HZ);
601 static ssize_t sleep_timeout_store(struct device *dev,
602 struct device_attribute *attr,
603 const char *buf, size_t n)
605 struct platform_device *pdev = to_platform_device(dev);
606 struct omap_device *odev = to_omap_device(pdev);
607 struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
610 if (sscanf(buf, "%u", &value) != 1) {
611 dev_err(dev, "sleep_timeout_store: Invalid value\n");
615 uart->timeout = value * HZ;
617 mod_timer(&uart->timer, jiffies + uart->timeout);
619 /* A zero value means disable timeout feature */
620 omap_uart_block_sleep(uart);
625 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
626 sleep_timeout_store);
627 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
629 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
630 static void omap_uart_block_sleep(struct omap_uart_state *uart)
632 /* Needed to enable UART clocks when built without CONFIG_PM */
633 omap_uart_enable_clocks(uart);
635 #define DEV_CREATE_FILE(dev, attr)
636 #endif /* CONFIG_PM */
638 #ifndef CONFIG_SERIAL_OMAP
640 * Override the default 8250 read handler: mem_serial_in()
641 * Empty RX fifo read causes an abort on omap3630 and omap4
642 * This function makes sure that an empty rx fifo is not read on these silicons
643 * (OMAP1/2/3430 are not affected)
645 static unsigned int serial_in_override(struct uart_port *up, int offset)
647 if (UART_RX == offset) {
649 lsr = __serial_read_reg(up, UART_LSR);
650 if (!(lsr & UART_LSR_DR))
654 return __serial_read_reg(up, offset);
657 static void serial_out_override(struct uart_port *up, int offset, int value)
659 unsigned int status, tmout = 10000;
661 status = __serial_read_reg(up, UART_LSR);
662 while (!(status & UART_LSR_THRE)) {
663 /* Wait up to 10ms for the character(s) to be sent. */
667 status = __serial_read_reg(up, UART_LSR);
669 __serial_write_reg(up, offset, value);
673 static int __init omap_serial_early_init(void)
678 char oh_name[MAX_UART_HWMOD_NAME_LEN];
679 struct omap_hwmod *oh;
680 struct omap_uart_state *uart;
682 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
684 oh = omap_hwmod_lookup(oh_name);
688 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
694 list_add_tail(&uart->node, &uart_list);
698 * NOTE: omap_hwmod_setup*() has not yet been called,
699 * so no hwmod functions will work yet.
703 * During UART early init, device need to be probed
704 * to determine SoC specific init before omap_device
705 * is ready. Therefore, don't allow idle here
707 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
712 core_initcall(omap_serial_early_init);
715 * omap_serial_init_port() - initialize single serial port
716 * @bdata: port specific board data pointer
718 * This function initialies serial driver for given port only.
719 * Platforms can call this function instead of omap_serial_init()
720 * if they don't plan to use all available UARTs as serial ports.
722 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
723 * use only one of the two.
725 void __init omap_serial_init_port(struct omap_board_data *bdata)
727 struct omap_uart_state *uart;
728 struct omap_hwmod *oh;
729 struct platform_device *pdev;
733 #ifndef CONFIG_SERIAL_OMAP
734 struct plat_serial8250_port ports[2] = {
738 struct plat_serial8250_port *p = &ports[0];
740 struct omap_uart_port_info omap_up;
745 if (WARN_ON(bdata->id < 0))
747 if (WARN_ON(bdata->id >= num_uarts))
750 list_for_each_entry(uart, &uart_list, node)
751 if (bdata->id == uart->num)
755 uart->dma_enabled = 0;
756 #ifndef CONFIG_SERIAL_OMAP
760 * !! 8250 driver does not use standard IORESOURCE* It
761 * has it's own custom pdata that can be taken from
762 * the hwmod resource data. But, this needs to be
763 * done after the build.
765 * ?? does it have to be done before the register ??
766 * YES, because platform_device_data_add() copies
767 * pdata, it does not use a pointer.
769 p->flags = UPF_BOOT_AUTOCONF;
770 p->iotype = UPIO_MEM;
772 p->uartclk = OMAP24XX_BASE_BAUD * 16;
773 p->irq = oh->mpu_irqs[0].irq;
774 p->mapbase = oh->slaves[0]->addr->pa_start;
775 p->membase = omap_hwmod_get_mpu_rt_va(oh);
776 p->irqflags = IRQF_SHARED;
777 p->private_data = uart;
780 * omap44xx, ti816x: Never read empty UART fifo
781 * omap3xxx: Never read empty UART fifo on UARTs
784 uart->regshift = p->regshift;
785 uart->membase = p->membase;
786 if (cpu_is_omap44xx() || cpu_is_ti816x())
787 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
788 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
789 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
790 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
792 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
793 p->serial_in = serial_in_override;
794 p->serial_out = serial_out_override;
798 pdata_size = 2 * sizeof(struct plat_serial8250_port);
803 omap_up.dma_enabled = uart->dma_enabled;
804 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
805 omap_up.mapbase = oh->slaves[0]->addr->pa_start;
806 omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
807 omap_up.irqflags = IRQF_SHARED;
808 omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
811 pdata_size = sizeof(struct omap_uart_port_info);
817 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
819 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
822 omap_device_disable_idle_on_suspend(pdev);
823 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
825 uart->irq = oh->mpu_irqs[0].irq;
827 uart->mapbase = oh->slaves[0]->addr->pa_start;
828 uart->membase = omap_hwmod_get_mpu_rt_va(oh);
833 console_lock(); /* in case the earlycon is on the UART */
836 * Because of early UART probing, UART did not get idled
837 * on init. Now that omap_device is ready, ensure full idle
838 * before doing omap_device_enable().
840 omap_hwmod_idle(uart->oh);
842 omap_device_enable(uart->pdev);
843 omap_uart_idle_init(uart);
844 omap_uart_reset(uart);
845 omap_hwmod_enable_wakeup(uart->oh);
846 omap_device_idle(uart->pdev);
849 * Need to block sleep long enough for interrupt driven
850 * driver to start. Console driver is in polling mode
851 * so device needs to be kept enabled while polling driver
855 uart->timeout = (30 * HZ);
856 omap_uart_block_sleep(uart);
857 uart->timeout = DEFAULT_TIMEOUT;
861 if ((cpu_is_omap34xx() && (uart->padconf || uart->padconf2)) ||
862 (uart->wk_en && uart->wk_mask)) {
863 device_init_wakeup(&pdev->dev, true);
864 DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
867 /* Enable the MDR1 errata for OMAP3 */
868 if (cpu_is_omap34xx() && !cpu_is_ti816x())
869 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
873 * omap_serial_init() - initialize all supported serial ports
875 * Initializes all available UARTs as serial ports. Platforms
876 * can call this function when they want to have default behaviour
877 * for serial ports (e.g initialize them all as serial ports).
879 void __init omap_serial_init(void)
881 struct omap_uart_state *uart;
882 struct omap_board_data bdata;
884 list_for_each_entry(uart, &uart_list, node) {
885 bdata.id = uart->num;
889 omap_serial_init_port(&bdata);