arch/arm/mach-omap2/prcm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/prcm.c
   3  *
   4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * Copyright (C) 2007 Texas Instruments, Inc.
  11  * Rajendra Nayak <rnayak@ti.com>
  12  *
  13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  14  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/delay.h>
  25
  26 #include <plat/common.h>
  27 #include <plat/prcm.h>
  28 #include <plat/irqs.h>
  29 #include <plat/control.h>
  30
  31 #include "clock.h"
  32 #include "clock2xxx.h"
  33 #include "cm.h"
  34 #include "prm.h"
  35 #include "prm-regbits-24xx.h"
  36
  37 static void __iomem *prm_base;
  38 static void __iomem *cm_base;
  39 static void __iomem *cm2_base;
  40
  41 #define MAX_MODULE_ENABLE_WAIT          100000
  42
  43 struct omap3_prcm_regs {
  44         u32 control_padconf_sys_nirq;
  45         u32 iva2_cm_clksel1;
  46         u32 iva2_cm_clksel2;
  47         u32 cm_sysconfig;
  48         u32 sgx_cm_clksel;
  49         u32 dss_cm_clksel;
  50         u32 cam_cm_clksel;
  51         u32 per_cm_clksel;
  52         u32 emu_cm_clksel;
  53         u32 emu_cm_clkstctrl;
  54         u32 pll_cm_autoidle2;
  55         u32 pll_cm_clksel4;
  56         u32 pll_cm_clksel5;
  57         u32 pll_cm_clken2;
  58         u32 cm_polctrl;
  59         u32 iva2_cm_fclken;
  60         u32 iva2_cm_clken_pll;
  61         u32 core_cm_fclken1;
  62         u32 core_cm_fclken3;
  63         u32 sgx_cm_fclken;
  64         u32 wkup_cm_fclken;
  65         u32 dss_cm_fclken;
  66         u32 cam_cm_fclken;
  67         u32 per_cm_fclken;
  68         u32 usbhost_cm_fclken;
  69         u32 core_cm_iclken1;
  70         u32 core_cm_iclken2;
  71         u32 core_cm_iclken3;
  72         u32 sgx_cm_iclken;
  73         u32 wkup_cm_iclken;
  74         u32 dss_cm_iclken;
  75         u32 cam_cm_iclken;
  76         u32 per_cm_iclken;
  77         u32 usbhost_cm_iclken;
  78         u32 iva2_cm_autiidle2;
  79         u32 mpu_cm_autoidle2;
  80         u32 iva2_cm_clkstctrl;
  81         u32 mpu_cm_clkstctrl;
  82         u32 core_cm_clkstctrl;
  83         u32 sgx_cm_clkstctrl;
  84         u32 dss_cm_clkstctrl;
  85         u32 cam_cm_clkstctrl;
  86         u32 per_cm_clkstctrl;
  87         u32 neon_cm_clkstctrl;
  88         u32 usbhost_cm_clkstctrl;
  89         u32 core_cm_autoidle1;
  90         u32 core_cm_autoidle2;
  91         u32 core_cm_autoidle3;
  92         u32 wkup_cm_autoidle;
  93         u32 dss_cm_autoidle;
  94         u32 cam_cm_autoidle;
  95         u32 per_cm_autoidle;
  96         u32 usbhost_cm_autoidle;
  97         u32 sgx_cm_sleepdep;
  98         u32 dss_cm_sleepdep;
  99         u32 cam_cm_sleepdep;
 100         u32 per_cm_sleepdep;
 101         u32 usbhost_cm_sleepdep;
 102         u32 cm_clkout_ctrl;
 103         u32 prm_clkout_ctrl;
 104         u32 sgx_pm_wkdep;
 105         u32 dss_pm_wkdep;
 106         u32 cam_pm_wkdep;
 107         u32 per_pm_wkdep;
 108         u32 neon_pm_wkdep;
 109         u32 usbhost_pm_wkdep;
 110         u32 core_pm_mpugrpsel1;
 111         u32 iva2_pm_ivagrpsel1;
 112         u32 core_pm_mpugrpsel3;
 113         u32 core_pm_ivagrpsel3;
 114         u32 wkup_pm_mpugrpsel;
 115         u32 wkup_pm_ivagrpsel;
 116         u32 per_pm_mpugrpsel;
 117         u32 per_pm_ivagrpsel;
 118         u32 wkup_pm_wken;
 119 };
 120
 121 struct omap3_prcm_regs prcm_context;
 122
 123 u32 omap_prcm_get_reset_sources(void)
 124 {
 125         /* XXX This presumably needs modification for 34XX */
 126         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 127                 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
 128         if (cpu_is_omap44xx())
 129                 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 130
 131         return 0;
 132 }
 133 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 134
 135 /* Resets clock rates and reboots the system. Only called from system.h */
 136 void omap_prcm_arch_reset(char mode, const char *cmd)
 137 {
 138         s16 prcm_offs = 0;
 139
 140         if (cpu_is_omap24xx()) {
 141                 omap2xxx_clk_prepare_for_reboot();
 142
 143                 prcm_offs = WKUP_MOD;
 144         } else if (cpu_is_omap34xx()) {
 145                 u32 l;
 146
 147                 prcm_offs = OMAP3430_GR_MOD;
 148                 l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0);
 149                 /* Reserve the first word in scratchpad for communicating
 150                  * with the boot ROM. A pointer to a data structure
 151                  * describing the boot process can be stored there,
 152                  * cf. OMAP34xx TRM, Initialization / Software Booting
 153                  * Configuration. */
 154                 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
 155         } else if (cpu_is_omap44xx())
 156                 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
 157         else
 158                 WARN_ON(1);
 159
 160         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 161                 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
 162                                                  OMAP2_RM_RSTCTRL);
 163         if (cpu_is_omap44xx())
 164                 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
 165                                                  OMAP4_RM_RSTCTRL);
 166 }
 167
 168 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
 169 {
 170         BUG_ON(!base);
 171         return __raw_readl(base + module + reg);
 172 }
 173
 174 static inline void __omap_prcm_write(u32 value, void __iomem *base,
 175                                                 s16 module, u16 reg)
 176 {
 177         BUG_ON(!base);
 178         __raw_writel(value, base + module + reg);
 179 }
 180
 181 /* Read a register in a PRM module */
 182 u32 prm_read_mod_reg(s16 module, u16 idx)
 183 {
 184         return __omap_prcm_read(prm_base, module, idx);
 185 }
 186
 187 /* Write into a register in a PRM module */
 188 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 189 {
 190         __omap_prcm_write(val, prm_base, module, idx);
 191 }
 192
 193 /* Read-modify-write a register in a PRM module. Caller must lock */
 194 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 195 {
 196         u32 v;
 197
 198         v = prm_read_mod_reg(module, idx);
 199         v &= ~mask;
 200         v |= bits;
 201         prm_write_mod_reg(v, module, idx);
 202
 203         return v;
 204 }
 205
 206 /* Read a PRM register, AND it, and shift the result down to bit 0 */
 207 u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
 208 {
 209         u32 v;
 210
 211         v = prm_read_mod_reg(domain, idx);
 212         v &= mask;
 213         v >>= __ffs(mask);
 214
 215         return v;
 216 }
 217
 218 /* Read a register in a CM module */
 219 u32 cm_read_mod_reg(s16 module, u16 idx)
 220 {
 221         return __omap_prcm_read(cm_base, module, idx);
 222 }
 223
 224 /* Write into a register in a CM module */
 225 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 226 {
 227         __omap_prcm_write(val, cm_base, module, idx);
 228 }
 229
 230 /* Read-modify-write a register in a CM module. Caller must lock */
 231 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 232 {
 233         u32 v;
 234
 235         v = cm_read_mod_reg(module, idx);
 236         v &= ~mask;
 237         v |= bits;
 238         cm_write_mod_reg(v, module, idx);
 239
 240         return v;
 241 }
 242
 243 /**
 244  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
 245  * @reg: physical address of module IDLEST register
 246  * @mask: value to mask against to determine if the module is active
 247  * @idlest: idle state indicator (0 or 1) for the clock
 248  * @name: name of the clock (for printk)
 249  *
 250  * Returns 1 if the module indicated readiness in time, or 0 if it
 251  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
 252  */
 253 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
 254                                 const char *name)
 255 {
 256         int i = 0;
 257         int ena = 0;
 258
 259         if (idlest)
 260                 ena = 0;
 261         else
 262                 ena = mask;
 263
 264         /* Wait for lock */
 265         omap_test_timeout(((__raw_readl(reg) & mask) == ena),
 266                           MAX_MODULE_ENABLE_WAIT, i);
 267
 268         if (i < MAX_MODULE_ENABLE_WAIT)
 269                 pr_debug("cm: Module associated with clock %s ready after %d "
 270                          "loops\n", name, i);
 271         else
 272                 pr_err("cm: Module associated with clock %s didn't enable in "
 273                        "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
 274
 275         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 276 };
 277
 278 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 279 {
 280         /* Static mapping, never released */
 281         if (omap2_globals->prm) {
 282                 prm_base = ioremap(omap2_globals->prm, SZ_8K);
 283                 WARN_ON(!prm_base);
 284         }
 285         if (omap2_globals->cm) {
 286                 cm_base = ioremap(omap2_globals->cm, SZ_8K);
 287                 WARN_ON(!cm_base);
 288         }
 289         if (omap2_globals->cm2) {
 290                 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
 291                 WARN_ON(!cm2_base);
 292         }
 293 }
 294
 295 #ifdef CONFIG_ARCH_OMAP3
 296 void omap3_prcm_save_context(void)
 297 {
 298         prcm_context.control_padconf_sys_nirq =
 299                          omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 300         prcm_context.iva2_cm_clksel1 =
 301                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 302         prcm_context.iva2_cm_clksel2 =
 303                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 304         prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
 305         prcm_context.sgx_cm_clksel =
 306                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 307         prcm_context.dss_cm_clksel =
 308                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 309         prcm_context.cam_cm_clksel =
 310                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 311         prcm_context.per_cm_clksel =
 312                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 313         prcm_context.emu_cm_clksel =
 314                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 315         prcm_context.emu_cm_clkstctrl =
 316                          cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
 317         prcm_context.pll_cm_autoidle2 =
 318                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 319         prcm_context.pll_cm_clksel4 =
 320                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 321         prcm_context.pll_cm_clksel5 =
 322                          cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 323         prcm_context.pll_cm_clken2 =
 324                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 325         prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
 326         prcm_context.iva2_cm_fclken =
 327                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 328         prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
 329                         OMAP3430_CM_CLKEN_PLL);
 330         prcm_context.core_cm_fclken1 =
 331                          cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 332         prcm_context.core_cm_fclken3 =
 333                          cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 334         prcm_context.sgx_cm_fclken =
 335                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 336         prcm_context.wkup_cm_fclken =
 337                          cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 338         prcm_context.dss_cm_fclken =
 339                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 340         prcm_context.cam_cm_fclken =
 341                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 342         prcm_context.per_cm_fclken =
 343                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 344         prcm_context.usbhost_cm_fclken =
 345                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 346         prcm_context.core_cm_iclken1 =
 347                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 348         prcm_context.core_cm_iclken2 =
 349                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 350         prcm_context.core_cm_iclken3 =
 351                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 352         prcm_context.sgx_cm_iclken =
 353                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 354         prcm_context.wkup_cm_iclken =
 355                          cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 356         prcm_context.dss_cm_iclken =
 357                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 358         prcm_context.cam_cm_iclken =
 359                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 360         prcm_context.per_cm_iclken =
 361                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 362         prcm_context.usbhost_cm_iclken =
 363                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 364         prcm_context.iva2_cm_autiidle2 =
 365                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 366         prcm_context.mpu_cm_autoidle2 =
 367                          cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 368         prcm_context.iva2_cm_clkstctrl =
 369                          cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 370         prcm_context.mpu_cm_clkstctrl =
 371                          cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
 372         prcm_context.core_cm_clkstctrl =
 373                          cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
 374         prcm_context.sgx_cm_clkstctrl =
 375                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 376                                                 OMAP2_CM_CLKSTCTRL);
 377         prcm_context.dss_cm_clkstctrl =
 378                          cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
 379         prcm_context.cam_cm_clkstctrl =
 380                          cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
 381         prcm_context.per_cm_clkstctrl =
 382                          cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
 383         prcm_context.neon_cm_clkstctrl =
 384                          cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
 385         prcm_context.usbhost_cm_clkstctrl =
 386                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 387                                                 OMAP2_CM_CLKSTCTRL);
 388         prcm_context.core_cm_autoidle1 =
 389                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 390         prcm_context.core_cm_autoidle2 =
 391                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 392         prcm_context.core_cm_autoidle3 =
 393                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 394         prcm_context.wkup_cm_autoidle =
 395                          cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 396         prcm_context.dss_cm_autoidle =
 397                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 398         prcm_context.cam_cm_autoidle =
 399                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 400         prcm_context.per_cm_autoidle =
 401                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 402         prcm_context.usbhost_cm_autoidle =
 403                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 404         prcm_context.sgx_cm_sleepdep =
 405                  cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
 406         prcm_context.dss_cm_sleepdep =
 407                  cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 408         prcm_context.cam_cm_sleepdep =
 409                  cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 410         prcm_context.per_cm_sleepdep =
 411                  cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 412         prcm_context.usbhost_cm_sleepdep =
 413                  cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 414         prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
 415                  OMAP3_CM_CLKOUT_CTRL_OFFSET);
 416         prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
 417                 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 418         prcm_context.sgx_pm_wkdep =
 419                  prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
 420         prcm_context.dss_pm_wkdep =
 421                  prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
 422         prcm_context.cam_pm_wkdep =
 423                  prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
 424         prcm_context.per_pm_wkdep =
 425                  prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
 426         prcm_context.neon_pm_wkdep =
 427                  prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
 428         prcm_context.usbhost_pm_wkdep =
 429                  prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 430         prcm_context.core_pm_mpugrpsel1 =
 431                  prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
 432         prcm_context.iva2_pm_ivagrpsel1 =
 433                  prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
 434         prcm_context.core_pm_mpugrpsel3 =
 435                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
 436         prcm_context.core_pm_ivagrpsel3 =
 437                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 438         prcm_context.wkup_pm_mpugrpsel =
 439                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 440         prcm_context.wkup_pm_ivagrpsel =
 441                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 442         prcm_context.per_pm_mpugrpsel =
 443                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 444         prcm_context.per_pm_ivagrpsel =
 445                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 446         prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 447         return;
 448 }
 449
 450 void omap3_prcm_restore_context(void)
 451 {
 452         omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
 453                                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 454         cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 455                                          CM_CLKSEL1);
 456         cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 457                                          CM_CLKSEL2);
 458         __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
 459         cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 460                                          CM_CLKSEL);
 461         cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 462                                          CM_CLKSEL);
 463         cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 464                                          CM_CLKSEL);
 465         cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
 466                                          CM_CLKSEL);
 467         cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 468                                          CM_CLKSEL1);
 469         cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 470                                          OMAP2_CM_CLKSTCTRL);
 471         cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
 472                                          CM_AUTOIDLE2);
 473         cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
 474                                         OMAP3430ES2_CM_CLKSEL4);
 475         cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
 476                                          OMAP3430ES2_CM_CLKSEL5);
 477         cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
 478                                         OMAP3430ES2_CM_CLKEN2);
 479         __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
 480         cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 481                                          CM_FCLKEN);
 482         cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 483                                         OMAP3430_CM_CLKEN_PLL);
 484         cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
 485         cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
 486                                          OMAP3430ES2_CM_FCLKEN3);
 487         cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 488                                          CM_FCLKEN);
 489         cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 490         cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 491                                          CM_FCLKEN);
 492         cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 493                                          CM_FCLKEN);
 494         cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
 495                                          CM_FCLKEN);
 496         cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
 497                                          OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 498         cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
 499         cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
 500         cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
 501         cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 502                                         CM_ICLKEN);
 503         cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 504         cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 505                                         CM_ICLKEN);
 506         cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 507                                         CM_ICLKEN);
 508         cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
 509                                         CM_ICLKEN);
 510         cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
 511                                         OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 512         cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
 513                                         CM_AUTOIDLE2);
 514         cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
 515         cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 516                                         OMAP2_CM_CLKSTCTRL);
 517         cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
 518                                         OMAP2_CM_CLKSTCTRL);
 519         cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
 520                                         OMAP2_CM_CLKSTCTRL);
 521         cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 522                                         OMAP2_CM_CLKSTCTRL);
 523         cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 524                                         OMAP2_CM_CLKSTCTRL);
 525         cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 526                                         OMAP2_CM_CLKSTCTRL);
 527         cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 528                                         OMAP2_CM_CLKSTCTRL);
 529         cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 530                                         OMAP2_CM_CLKSTCTRL);
 531         cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
 532                                 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
 533         cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
 534                                         CM_AUTOIDLE1);
 535         cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
 536                                         CM_AUTOIDLE2);
 537         cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
 538                                         CM_AUTOIDLE3);
 539         cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
 540         cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 541                                         CM_AUTOIDLE);
 542         cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 543                                         CM_AUTOIDLE);
 544         cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 545                                         CM_AUTOIDLE);
 546         cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
 547                                         OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 548         cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 549                                         OMAP3430_CM_SLEEPDEP);
 550         cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 551                                         OMAP3430_CM_SLEEPDEP);
 552         cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 553                                         OMAP3430_CM_SLEEPDEP);
 554         cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 555                                         OMAP3430_CM_SLEEPDEP);
 556         cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
 557                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 558         cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 559                                         OMAP3_CM_CLKOUT_CTRL_OFFSET);
 560         prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
 561                                         OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 562         prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
 563                                         PM_WKDEP);
 564         prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
 565                                         PM_WKDEP);
 566         prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
 567                                         PM_WKDEP);
 568         prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
 569                                         PM_WKDEP);
 570         prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
 571                                         PM_WKDEP);
 572         prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
 573                                         OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 574         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
 575                                         OMAP3430_PM_MPUGRPSEL1);
 576         prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
 577                                         OMAP3430_PM_IVAGRPSEL1);
 578         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
 579                                         OMAP3430ES2_PM_MPUGRPSEL3);
 580         prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
 581                                         OMAP3430ES2_PM_IVAGRPSEL3);
 582         prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
 583                                         OMAP3430_PM_MPUGRPSEL);
 584         prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
 585                                         OMAP3430_PM_IVAGRPSEL);
 586         prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
 587                                         OMAP3430_PM_MPUGRPSEL);
 588         prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
 589                                          OMAP3430_PM_IVAGRPSEL);
 590         prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
 591         return;
 592 }
 593 #endif