2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
32 #include <trace/events/power.h>
34 #include <asm/suspend.h>
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/serial.h>
40 #include <plat/sdrc.h>
41 #include <plat/prcm.h>
42 #include <plat/gpmc.h>
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
49 #include "prm2xxx_3xxx.h"
55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
56 static inline bool is_suspending(void)
58 return (suspend_state != PM_SUSPEND_ON);
61 static inline bool is_suspending(void)
67 /* pm34xx errata defined in pm.h */
71 struct powerdomain *pwrdm;
76 struct list_head node;
79 static LIST_HEAD(pwrst_list);
81 static int (*_omap_save_secure_sram)(u32 *addr);
82 void (*omap3_do_wfi_sram)(void);
84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
85 static struct powerdomain *core_pwrdm, *per_pwrdm;
86 static struct powerdomain *cam_pwrdm;
88 static inline void omap3_per_save_context(void)
90 omap_gpio_save_context();
93 static inline void omap3_per_restore_context(void)
95 omap_gpio_restore_context();
98 static void omap3_enable_io_chain(void)
102 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
104 /* Do a readback to assure write has been done */
105 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
107 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
108 OMAP3430_ST_IO_CHAIN_MASK)) {
110 if (timeout > 1000) {
111 pr_err("Wake up daisy chain activation failed.\n");
114 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
119 static void omap3_disable_io_chain(void)
121 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
125 static void omap3_core_save_context(void)
127 omap3_ctrl_save_padconf();
130 * Force write last pad into memory, as this can fail in some
131 * cases according to errata 1.157, 1.185
133 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
134 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
136 /* Save the Interrupt controller context */
137 omap_intc_save_context();
138 /* Save the GPMC context */
139 omap3_gpmc_save_context();
140 /* Save the system control module context, padconf already save above*/
141 omap3_control_save_context();
142 omap_dma_global_context_save();
145 static void omap3_core_restore_context(void)
147 /* Restore the control module context, padconf restored by h/w */
148 omap3_control_restore_context();
149 /* Restore the GPMC context */
150 omap3_gpmc_restore_context();
151 /* Restore the interrupt controller context */
152 omap_intc_restore_context();
153 omap_dma_global_context_restore();
157 * FIXME: This function should be called before entering off-mode after
158 * OMAP3 secure services have been accessed. Currently it is only called
159 * once during boot sequence, but this works as we are not using secure
162 static void omap3_save_secure_ram_context(void)
165 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
167 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
169 * MPU next state must be set to POWER_ON temporarily,
170 * otherwise the WFI executed inside the ROM code
171 * will hang the system.
173 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
174 ret = _omap_save_secure_sram((u32 *)
175 __pa(omap3_secure_ram_storage));
176 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
177 /* Following is for error tracking, it should not happen */
179 printk(KERN_ERR "save_secure_sram() returns %08x\n",
188 * PRCM Interrupt Handler Helper Function
190 * The purpose of this function is to clear any wake-up events latched
191 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
192 * may occur whilst attempting to clear a PM_WKST_x register and thus
193 * set another bit in this register. A while loop is used to ensure
194 * that any peripheral wake-up events occurring while attempting to
195 * clear the PM_WKST_x are detected and cleared.
197 static int prcm_clear_mod_irqs(s16 module, u8 regs)
199 u32 wkst, fclk, iclk, clken;
200 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
201 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
202 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
203 u16 grpsel_off = (regs == 3) ?
204 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
207 wkst = omap2_prm_read_mod_reg(module, wkst_off);
208 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
210 iclk = omap2_cm_read_mod_reg(module, iclk_off);
211 fclk = omap2_cm_read_mod_reg(module, fclk_off);
214 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
216 * For USBHOST, we don't know whether HOST1 or
217 * HOST2 woke us up, so enable both f-clocks
219 if (module == OMAP3430ES2_USBHOST_MOD)
220 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
221 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
222 omap2_prm_write_mod_reg(wkst, module, wkst_off);
223 wkst = omap2_prm_read_mod_reg(module, wkst_off);
226 omap2_cm_write_mod_reg(iclk, module, iclk_off);
227 omap2_cm_write_mod_reg(fclk, module, fclk_off);
233 static int _prcm_int_handle_wakeup(void)
237 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
238 c += prcm_clear_mod_irqs(CORE_MOD, 1);
239 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
240 if (omap_rev() > OMAP3430_REV_ES1_0) {
241 c += prcm_clear_mod_irqs(CORE_MOD, 3);
242 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
249 * PRCM Interrupt Handler
251 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
252 * interrupts from the PRCM for the MPU. These bits must be cleared in
253 * order to clear the PRCM interrupt. The PRCM interrupt handler is
254 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
255 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
256 * register indicates that a wake-up event is pending for the MPU and
257 * this bit can only be cleared if the all the wake-up events latched
258 * in the various PM_WKST_x registers have been cleared. The interrupt
259 * handler is implemented using a do-while loop so that if a wake-up
260 * event occurred during the processing of the prcm interrupt handler
261 * (setting a bit in the corresponding PM_WKST_x register and thus
262 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
263 * this would be handled.
265 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
267 u32 irqenable_mpu, irqstatus_mpu;
270 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
271 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
272 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
273 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
274 irqstatus_mpu &= irqenable_mpu;
277 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
278 OMAP3430_IO_ST_MASK)) {
279 c = _prcm_int_handle_wakeup();
282 * Is the MPU PRCM interrupt handler racing with the
283 * IVA2 PRCM interrupt handler ?
285 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
286 "but no wakeup sources are marked\n");
288 /* XXX we need to expand our PRCM interrupt handler */
289 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
290 "no code to handle it (%08x)\n", irqstatus_mpu);
293 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
294 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
296 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
297 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
298 irqstatus_mpu &= irqenable_mpu;
300 } while (irqstatus_mpu);
305 static void omap34xx_save_context(u32 *save)
309 /* Read Auxiliary Control Register */
310 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
314 /* Read L2 AUX ctrl register */
315 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
320 static int omap34xx_do_sram_idle(unsigned long save_state)
322 omap34xx_cpu_suspend(save_state);
326 void omap_sram_idle(void)
328 /* Variable to tell what needs to be saved and restored
329 * in omap_sram_idle*/
330 /* save_state = 0 => Nothing to save and restored */
331 /* save_state = 1 => Only L1 and logic lost */
332 /* save_state = 2 => Only L2 lost */
333 /* save_state = 3 => L1, L2 and logic lost */
335 int mpu_next_state = PWRDM_POWER_ON;
336 int per_next_state = PWRDM_POWER_ON;
337 int core_next_state = PWRDM_POWER_ON;
339 int core_prev_state, per_prev_state;
342 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
343 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
344 pwrdm_clear_all_prev_pwrst(core_pwrdm);
345 pwrdm_clear_all_prev_pwrst(per_pwrdm);
347 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
348 switch (mpu_next_state) {
350 case PWRDM_POWER_RET:
351 /* No need to save context */
354 case PWRDM_POWER_OFF:
359 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
364 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
365 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
367 /* Enable IO-PAD and IO-CHAIN wakeups */
368 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
369 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
370 if (omap3_has_io_wakeup() &&
371 (per_next_state < PWRDM_POWER_ON ||
372 core_next_state < PWRDM_POWER_ON)) {
373 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
374 if (omap3_has_io_chain_ctrl())
375 omap3_enable_io_chain();
378 /* Block console output in case it is on one of the OMAP UARTs */
379 if (!is_suspending())
380 if (per_next_state < PWRDM_POWER_ON ||
381 core_next_state < PWRDM_POWER_ON)
382 if (!console_trylock())
383 goto console_still_active;
385 pwrdm_pre_transition();
388 if (per_next_state < PWRDM_POWER_ON) {
389 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
390 omap_uart_prepare_idle(2);
391 omap_uart_prepare_idle(3);
392 omap2_gpio_prepare_for_idle(per_going_off);
393 if (per_next_state == PWRDM_POWER_OFF)
394 omap3_per_save_context();
398 if (core_next_state < PWRDM_POWER_ON) {
399 omap_uart_prepare_idle(0);
400 omap_uart_prepare_idle(1);
401 if (core_next_state == PWRDM_POWER_OFF) {
402 omap3_core_save_context();
403 omap3_cm_save_context();
407 omap3_intc_prepare_idle();
410 * On EMU/HS devices ROM code restores a SRDC value
411 * from scratchpad which has automatic self refresh on timeout
412 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
413 * Hence store/restore the SDRC_POWER register here.
415 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
416 omap_type() != OMAP2_DEVICE_TYPE_GP &&
417 core_next_state == PWRDM_POWER_OFF)
418 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
421 * omap3_arm_context is the location where some ARM context
422 * get saved. The rest is placed on the stack, and restored
423 * from there before resuming.
426 omap34xx_save_context(omap3_arm_context);
427 if (save_state == 1 || save_state == 3)
428 cpu_suspend(save_state, omap34xx_do_sram_idle);
430 omap34xx_do_sram_idle(save_state);
432 /* Restore normal SDRC POWER settings */
433 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
434 omap_type() != OMAP2_DEVICE_TYPE_GP &&
435 core_next_state == PWRDM_POWER_OFF)
436 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
439 if (core_next_state < PWRDM_POWER_ON) {
440 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
441 if (core_prev_state == PWRDM_POWER_OFF) {
442 omap3_core_restore_context();
443 omap3_cm_restore_context();
444 omap3_sram_restore_context();
445 omap2_sms_restore_context();
447 omap_uart_resume_idle(0);
448 omap_uart_resume_idle(1);
449 if (core_next_state == PWRDM_POWER_OFF)
450 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
452 OMAP3_PRM_VOLTCTRL_OFFSET);
454 omap3_intc_resume_idle();
456 pwrdm_post_transition();
459 if (per_next_state < PWRDM_POWER_ON) {
460 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
461 omap2_gpio_resume_after_idle();
462 if (per_prev_state == PWRDM_POWER_OFF)
463 omap3_per_restore_context();
464 omap_uart_resume_idle(2);
465 omap_uart_resume_idle(3);
468 if (!is_suspending())
471 console_still_active:
472 /* Disable IO-PAD and IO-CHAIN wakeup */
473 if (omap3_has_io_wakeup() &&
474 (per_next_state < PWRDM_POWER_ON ||
475 core_next_state < PWRDM_POWER_ON)) {
476 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
478 if (omap3_has_io_chain_ctrl())
479 omap3_disable_io_chain();
482 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
485 int omap3_can_sleep(void)
487 if (!omap_uart_can_sleep())
492 static void omap3_pm_idle(void)
497 if (!omap3_can_sleep())
500 if (omap_irq_pending() || need_resched())
503 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
504 trace_cpu_idle(1, smp_processor_id());
508 trace_power_end(smp_processor_id());
509 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
516 #ifdef CONFIG_SUSPEND
517 static int omap3_pm_suspend(void)
519 struct power_state *pwrst;
522 /* Read current next_pwrsts */
523 list_for_each_entry(pwrst, &pwrst_list, node)
524 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
525 /* Set ones wanted by suspend */
526 list_for_each_entry(pwrst, &pwrst_list, node) {
527 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
529 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
533 omap_uart_prepare_suspend();
534 omap3_intc_suspend();
539 /* Restore next_pwrsts */
540 list_for_each_entry(pwrst, &pwrst_list, node) {
541 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
542 if (state > pwrst->next_state) {
543 printk(KERN_INFO "Powerdomain (%s) didn't enter "
545 pwrst->pwrdm->name, pwrst->next_state);
548 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
551 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
553 printk(KERN_INFO "Successfully put all powerdomains "
554 "to target state\n");
559 static int omap3_pm_enter(suspend_state_t unused)
563 switch (suspend_state) {
564 case PM_SUSPEND_STANDBY:
566 ret = omap3_pm_suspend();
575 /* Hooks to enable / disable UART interrupts during suspend */
576 static int omap3_pm_begin(suspend_state_t state)
579 suspend_state = state;
580 omap_uart_enable_irqs(0);
584 static void omap3_pm_end(void)
586 suspend_state = PM_SUSPEND_ON;
587 omap_uart_enable_irqs(1);
592 static const struct platform_suspend_ops omap_pm_ops = {
593 .begin = omap3_pm_begin,
595 .enter = omap3_pm_enter,
596 .valid = suspend_valid_only_mem,
598 #endif /* CONFIG_SUSPEND */
602 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
605 * In cases where IVA2 is activated by bootcode, it may prevent
606 * full-chip retention or off-mode because it is not idle. This
607 * function forces the IVA2 into idle state so it can go
608 * into retention/off and thus allow full-chip retention/off.
611 static void __init omap3_iva_idle(void)
613 /* ensure IVA2 clock is disabled */
614 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
616 /* if no clock activity, nothing else to do */
617 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
618 OMAP3430_CLKACTIVITY_IVA2_MASK))
622 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
623 OMAP3430_RST2_IVA2_MASK |
624 OMAP3430_RST3_IVA2_MASK,
625 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
627 /* Enable IVA2 clock */
628 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
629 OMAP3430_IVA2_MOD, CM_FCLKEN);
631 /* Set IVA2 boot mode to 'idle' */
632 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
633 OMAP343X_CONTROL_IVA2_BOOTMOD);
636 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
638 /* Disable IVA2 clock */
639 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
642 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
643 OMAP3430_RST2_IVA2_MASK |
644 OMAP3430_RST3_IVA2_MASK,
645 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
648 static void __init omap3_d2d_idle(void)
652 /* In a stand alone OMAP3430 where there is not a stacked
653 * modem for the D2D Idle Ack and D2D MStandby must be pulled
654 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
655 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
656 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
657 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
659 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
661 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
663 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
666 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
667 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
668 CORE_MOD, OMAP2_RM_RSTCTRL);
669 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
672 static void __init prcm_setup_regs(void)
674 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
675 OMAP3630_EN_UART4_MASK : 0;
676 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
677 OMAP3630_GRPSEL_UART4_MASK : 0;
679 /* XXX This should be handled by hwmod code or SCM init code */
680 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
683 * Enable control of expternal oscillator through
684 * sys_clkreq. In the long run clock framework should
687 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
688 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
690 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
692 /* setup wakup source */
693 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
694 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
696 /* No need to write EN_IO, that is always enabled */
697 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
698 OMAP3430_GRPSEL_GPT1_MASK |
699 OMAP3430_GRPSEL_GPT12_MASK,
700 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
701 /* For some reason IO doesn't generate wakeup event even if
702 * it is selected to mpu wakeup goup */
703 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
704 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
706 /* Enable PM_WKEN to support DSS LPR */
707 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
708 OMAP3430_DSS_MOD, PM_WKEN);
710 /* Enable wakeups in PER */
711 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
712 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
713 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
714 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
715 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
716 OMAP3430_EN_MCBSP4_MASK,
717 OMAP3430_PER_MOD, PM_WKEN);
718 /* and allow them to wake up MPU */
719 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
720 OMAP3430_GRPSEL_GPIO2_MASK |
721 OMAP3430_GRPSEL_GPIO3_MASK |
722 OMAP3430_GRPSEL_GPIO4_MASK |
723 OMAP3430_GRPSEL_GPIO5_MASK |
724 OMAP3430_GRPSEL_GPIO6_MASK |
725 OMAP3430_GRPSEL_UART3_MASK |
726 OMAP3430_GRPSEL_MCBSP2_MASK |
727 OMAP3430_GRPSEL_MCBSP3_MASK |
728 OMAP3430_GRPSEL_MCBSP4_MASK,
729 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
731 /* Don't attach IVA interrupts */
732 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
733 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
734 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
735 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
737 /* Clear any pending 'reset' flags */
738 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
739 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
740 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
741 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
742 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
743 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
744 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
746 /* Clear any pending PRCM interrupts */
747 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
753 void omap3_pm_off_mode_enable(int enable)
755 struct power_state *pwrst;
759 state = PWRDM_POWER_OFF;
761 state = PWRDM_POWER_RET;
763 list_for_each_entry(pwrst, &pwrst_list, node) {
764 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
765 pwrst->pwrdm == core_pwrdm &&
766 state == PWRDM_POWER_OFF) {
767 pwrst->next_state = PWRDM_POWER_RET;
768 pr_warn("%s: Core OFF disabled due to errata i583\n",
771 pwrst->next_state = state;
773 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
777 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
779 struct power_state *pwrst;
781 list_for_each_entry(pwrst, &pwrst_list, node) {
782 if (pwrst->pwrdm == pwrdm)
783 return pwrst->next_state;
788 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
790 struct power_state *pwrst;
792 list_for_each_entry(pwrst, &pwrst_list, node) {
793 if (pwrst->pwrdm == pwrdm) {
794 pwrst->next_state = state;
801 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
803 struct power_state *pwrst;
808 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
811 pwrst->pwrdm = pwrdm;
812 pwrst->next_state = PWRDM_POWER_RET;
813 list_add(&pwrst->node, &pwrst_list);
815 if (pwrdm_has_hdwr_sar(pwrdm))
816 pwrdm_enable_hdwr_sar(pwrdm);
818 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
822 * Enable hw supervised mode for all clockdomains if it's
823 * supported. Initiate sleep transition for other clockdomains, if
826 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
828 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
829 clkdm_allow_idle(clkdm);
830 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
831 atomic_read(&clkdm->usecount) == 0)
837 * Push functions to SRAM
839 * The minimum set of functions is pushed to SRAM for execution:
840 * - omap3_do_wfi for erratum i581 WA,
841 * - save_secure_ram_context for security extensions.
843 void omap_push_sram_idle(void)
845 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
847 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
848 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
849 save_secure_ram_context_sz);
852 static void __init pm_errata_configure(void)
854 if (cpu_is_omap3630()) {
855 pm34xx_errata |= PM_RTA_ERRATUM_i608;
856 /* Enable the l2 cache toggling in sleep logic */
857 enable_omap3630_toggle_l2_on_restore();
858 if (omap_rev() < OMAP3630_REV_ES1_2)
859 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
863 static int __init omap3_pm_init(void)
865 struct power_state *pwrst, *tmp;
866 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
869 if (!cpu_is_omap34xx())
872 if (!omap3_has_io_chain_ctrl())
873 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
875 pm_errata_configure();
877 /* XXX prcm_setup_regs needs to be before enabling hw
878 * supervised mode for powerdomains */
881 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
882 (irq_handler_t)prcm_interrupt_handler,
883 IRQF_DISABLED, "prcm", NULL);
885 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
886 INT_34XX_PRCM_MPU_IRQ);
890 ret = pwrdm_for_each(pwrdms_setup, NULL);
892 printk(KERN_ERR "Failed to setup powerdomains\n");
896 (void) clkdm_for_each(clkdms_setup, NULL);
898 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
899 if (mpu_pwrdm == NULL) {
900 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
904 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
905 per_pwrdm = pwrdm_lookup("per_pwrdm");
906 core_pwrdm = pwrdm_lookup("core_pwrdm");
907 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
909 neon_clkdm = clkdm_lookup("neon_clkdm");
910 mpu_clkdm = clkdm_lookup("mpu_clkdm");
911 per_clkdm = clkdm_lookup("per_clkdm");
912 core_clkdm = clkdm_lookup("core_clkdm");
914 #ifdef CONFIG_SUSPEND
915 suspend_set_ops(&omap_pm_ops);
916 #endif /* CONFIG_SUSPEND */
918 pm_idle = omap3_pm_idle;
922 * RTA is disabled during initialization as per erratum i608
923 * it is safer to disable RTA by the bootloader, but we would like
924 * to be doubly sure here and prevent any mishaps.
926 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
927 omap3630_ctrl_disable_rta();
929 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
930 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
931 omap3_secure_ram_storage =
932 kmalloc(0x803F, GFP_KERNEL);
933 if (!omap3_secure_ram_storage)
934 printk(KERN_ERR "Memory allocation failed when"
935 "allocating for secure sram context\n");
940 omap_dma_global_context_save();
941 omap3_save_secure_ram_context();
942 omap_dma_global_context_restore();
948 omap3_save_scratchpad_contents();
952 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
953 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
954 list_del(&pwrst->node);
960 late_initcall(omap3_pm_init);