arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 #ifdef CONFIG_SUSPEND
  55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  56 static inline bool is_suspending(void)
  57 {
  58         return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
  59 }
  60 #else
  61 static inline bool is_suspending(void)
  62 {
  63         return false;
  64 }
  65 #endif
  66
  67 /* pm34xx errata defined in pm.h */
  68 u16 pm34xx_errata;
  69
  70 struct power_state {
  71         struct powerdomain *pwrdm;
  72         u32 next_state;
  73 #ifdef CONFIG_SUSPEND
  74         u32 saved_state;
  75 #endif
  76         struct list_head node;
  77 };
  78
  79 static LIST_HEAD(pwrst_list);
  80
  81 static int (*_omap_save_secure_sram)(u32 *addr);
  82 void (*omap3_do_wfi_sram)(void);
  83
  84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  85 static struct powerdomain *core_pwrdm, *per_pwrdm;
  86
  87 static inline void omap3_per_save_context(void)
  88 {
  89         omap_gpio_save_context();
  90 }
  91
  92 static inline void omap3_per_restore_context(void)
  93 {
  94         omap_gpio_restore_context();
  95 }
  96
  97 static void omap3_enable_io_chain(void)
  98 {
  99         int timeout = 0;
 100
 101         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 102                                    PM_WKEN);
 103         /* Do a readback to assure write has been done */
 104         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 105
 106         while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 107                  OMAP3430_ST_IO_CHAIN_MASK)) {
 108                 timeout++;
 109                 if (timeout > 1000) {
 110                         pr_err("Wake up daisy chain activation failed.\n");
 111                         return;
 112                 }
 113                 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 114                                            WKUP_MOD, PM_WKEN);
 115         }
 116 }
 117
 118 static void omap3_disable_io_chain(void)
 119 {
 120         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 121                                      PM_WKEN);
 122 }
 123
 124 static void omap3_core_save_context(void)
 125 {
 126         omap3_ctrl_save_padconf();
 127
 128         /*
 129          * Force write last pad into memory, as this can fail in some
 130          * cases according to errata 1.157, 1.185
 131          */
 132         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 133                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 134
 135         /* Save the Interrupt controller context */
 136         omap_intc_save_context();
 137         /* Save the GPMC context */
 138         omap3_gpmc_save_context();
 139         /* Save the system control module context, padconf already save above*/
 140         omap3_control_save_context();
 141         omap_dma_global_context_save();
 142 }
 143
 144 static void omap3_core_restore_context(void)
 145 {
 146         /* Restore the control module context, padconf restored by h/w */
 147         omap3_control_restore_context();
 148         /* Restore the GPMC context */
 149         omap3_gpmc_restore_context();
 150         /* Restore the interrupt controller context */
 151         omap_intc_restore_context();
 152         omap_dma_global_context_restore();
 153 }
 154
 155 /*
 156  * FIXME: This function should be called before entering off-mode after
 157  * OMAP3 secure services have been accessed. Currently it is only called
 158  * once during boot sequence, but this works as we are not using secure
 159  * services.
 160  */
 161 static void omap3_save_secure_ram_context(void)
 162 {
 163         u32 ret;
 164         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 165
 166         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 167                 /*
 168                  * MPU next state must be set to POWER_ON temporarily,
 169                  * otherwise the WFI executed inside the ROM code
 170                  * will hang the system.
 171                  */
 172                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 173                 ret = _omap_save_secure_sram((u32 *)
 174                                 __pa(omap3_secure_ram_storage));
 175                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 176                 /* Following is for error tracking, it should not happen */
 177                 if (ret) {
 178                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 179                                 ret);
 180                         while (1)
 181                                 ;
 182                 }
 183         }
 184 }
 185
 186 /*
 187  * PRCM Interrupt Handler Helper Function
 188  *
 189  * The purpose of this function is to clear any wake-up events latched
 190  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 191  * may occur whilst attempting to clear a PM_WKST_x register and thus
 192  * set another bit in this register. A while loop is used to ensure
 193  * that any peripheral wake-up events occurring while attempting to
 194  * clear the PM_WKST_x are detected and cleared.
 195  */
 196 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 197 {
 198         u32 wkst, fclk, iclk, clken;
 199         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 200         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 201         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 202         u16 grpsel_off = (regs == 3) ?
 203                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 204         int c = 0;
 205
 206         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 207         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 208         if (wkst) {
 209                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 210                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 211                 while (wkst) {
 212                         clken = wkst;
 213                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 214                         /*
 215                          * For USBHOST, we don't know whether HOST1 or
 216                          * HOST2 woke us up, so enable both f-clocks
 217                          */
 218                         if (module == OMAP3430ES2_USBHOST_MOD)
 219                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 220                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 221                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 222                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 223                         c++;
 224                 }
 225                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 226                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 227         }
 228
 229         return c;
 230 }
 231
 232 static int _prcm_int_handle_wakeup(void)
 233 {
 234         int c;
 235
 236         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 237         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 238         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 239         if (omap_rev() > OMAP3430_REV_ES1_0) {
 240                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 241                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 242         }
 243
 244         return c;
 245 }
 246
 247 /*
 248  * PRCM Interrupt Handler
 249  *
 250  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 251  * interrupts from the PRCM for the MPU. These bits must be cleared in
 252  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 253  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 254  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 255  * register indicates that a wake-up event is pending for the MPU and
 256  * this bit can only be cleared if the all the wake-up events latched
 257  * in the various PM_WKST_x registers have been cleared. The interrupt
 258  * handler is implemented using a do-while loop so that if a wake-up
 259  * event occurred during the processing of the prcm interrupt handler
 260  * (setting a bit in the corresponding PM_WKST_x register and thus
 261  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 262  * this would be handled.
 263  */
 264 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 265 {
 266         u32 irqenable_mpu, irqstatus_mpu;
 267         int c = 0;
 268
 269         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 270                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 271         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 272                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 273         irqstatus_mpu &= irqenable_mpu;
 274
 275         do {
 276                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 277                                      OMAP3430_IO_ST_MASK)) {
 278                         c = _prcm_int_handle_wakeup();
 279
 280                         /*
 281                          * Is the MPU PRCM interrupt handler racing with the
 282                          * IVA2 PRCM interrupt handler ?
 283                          */
 284                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 285                              "but no wakeup sources are marked\n");
 286                 } else {
 287                         /* XXX we need to expand our PRCM interrupt handler */
 288                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 289                              "no code to handle it (%08x)\n", irqstatus_mpu);
 290                 }
 291
 292                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 293                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 294
 295                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 296                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 297                 irqstatus_mpu &= irqenable_mpu;
 298
 299         } while (irqstatus_mpu);
 300
 301         return IRQ_HANDLED;
 302 }
 303
 304 static void omap34xx_save_context(u32 *save)
 305 {
 306         u32 val;
 307
 308         /* Read Auxiliary Control Register */
 309         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 310         *save++ = 1;
 311         *save++ = val;
 312
 313         /* Read L2 AUX ctrl register */
 314         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 315         *save++ = 1;
 316         *save++ = val;
 317 }
 318
 319 static int omap34xx_do_sram_idle(unsigned long save_state)
 320 {
 321         omap34xx_cpu_suspend(save_state);
 322         return 0;
 323 }
 324
 325 void omap_sram_idle(void)
 326 {
 327         /* Variable to tell what needs to be saved and restored
 328          * in omap_sram_idle*/
 329         /* save_state = 0 => Nothing to save and restored */
 330         /* save_state = 1 => Only L1 and logic lost */
 331         /* save_state = 2 => Only L2 lost */
 332         /* save_state = 3 => L1, L2 and logic lost */
 333         int save_state = 0;
 334         int mpu_next_state = PWRDM_POWER_ON;
 335         int per_next_state = PWRDM_POWER_ON;
 336         int core_next_state = PWRDM_POWER_ON;
 337         int per_going_off;
 338         int core_prev_state, per_prev_state;
 339         u32 sdrc_pwr = 0;
 340
 341         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 342         switch (mpu_next_state) {
 343         case PWRDM_POWER_ON:
 344         case PWRDM_POWER_RET:
 345                 /* No need to save context */
 346                 save_state = 0;
 347                 break;
 348         case PWRDM_POWER_OFF:
 349                 save_state = 3;
 350                 break;
 351         default:
 352                 /* Invalid state */
 353                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 354                 return;
 355         }
 356
 357         /* NEON control */
 358         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 359                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 360
 361         /* Enable IO-PAD and IO-CHAIN wakeups */
 362         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 363         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 364         if (omap3_has_io_wakeup() &&
 365             (per_next_state < PWRDM_POWER_ON ||
 366              core_next_state < PWRDM_POWER_ON)) {
 367                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 368                 if (omap3_has_io_chain_ctrl())
 369                         omap3_enable_io_chain();
 370         }
 371
 372         /* Block console output in case it is on one of the OMAP UARTs */
 373         if (!is_suspending())
 374                 if (per_next_state < PWRDM_POWER_ON ||
 375                     core_next_state < PWRDM_POWER_ON)
 376                         if (!console_trylock())
 377                                 goto console_still_active;
 378
 379         if (mpu_next_state < PWRDM_POWER_ON)
 380                 pwrdm_pre_transition(mpu_pwrdm);
 381
 382         /* PER */
 383         if (per_next_state < PWRDM_POWER_ON) {
 384                 pwrdm_pre_transition(per_pwrdm);
 385                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 386                 omap_uart_prepare_idle(2);
 387                 omap_uart_prepare_idle(3);
 388                 omap2_gpio_prepare_for_idle(per_going_off);
 389                 if (per_next_state == PWRDM_POWER_OFF)
 390                                 omap3_per_save_context();
 391         }
 392
 393         /* CORE */
 394         if (core_next_state < PWRDM_POWER_ON) {
 395                 omap_uart_prepare_idle(0);
 396                 omap_uart_prepare_idle(1);
 397                 pwrdm_pre_transition(core_pwrdm);
 398                 if (core_next_state == PWRDM_POWER_OFF) {
 399                         omap3_core_save_context();
 400                         omap3_cm_save_context();
 401                 }
 402         }
 403
 404         omap3_intc_prepare_idle();
 405
 406         /*
 407          * On EMU/HS devices ROM code restores a SRDC value
 408          * from scratchpad which has automatic self refresh on timeout
 409          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 410          * Hence store/restore the SDRC_POWER register here.
 411          */
 412         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 413             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 414              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 415             core_next_state == PWRDM_POWER_OFF)
 416                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 417
 418         /*
 419          * omap3_arm_context is the location where some ARM context
 420          * get saved. The rest is placed on the stack, and restored
 421          * from there before resuming.
 422          */
 423         if (save_state)
 424                 omap34xx_save_context(omap3_arm_context);
 425         if (save_state == 1 || save_state == 3)
 426                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 427         else
 428                 omap34xx_do_sram_idle(save_state);
 429
 430         /* Restore normal SDRC POWER settings */
 431         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 432             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 433              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 434             core_next_state == PWRDM_POWER_OFF)
 435                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 436
 437         /* CORE */
 438         if (core_next_state < PWRDM_POWER_ON) {
 439                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 440                 if (core_prev_state == PWRDM_POWER_OFF) {
 441                         omap3_core_restore_context();
 442                         omap3_cm_restore_context();
 443                         omap3_sram_restore_context();
 444                         omap2_sms_restore_context();
 445                 }
 446                 omap_uart_resume_idle(0);
 447                 omap_uart_resume_idle(1);
 448                 if (core_next_state == PWRDM_POWER_OFF)
 449                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 450                                                OMAP3430_GR_MOD,
 451                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 452                 pwrdm_post_transition(core_pwrdm);
 453         }
 454         omap3_intc_resume_idle();
 455
 456         /* PER */
 457         if (per_next_state < PWRDM_POWER_ON) {
 458                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 459                 omap2_gpio_resume_after_idle();
 460                 if (per_prev_state == PWRDM_POWER_OFF)
 461                         omap3_per_restore_context();
 462                 omap_uart_resume_idle(2);
 463                 omap_uart_resume_idle(3);
 464                 pwrdm_post_transition(per_pwrdm);
 465         }
 466
 467         if (!is_suspending())
 468                 console_unlock();
 469
 470 console_still_active:
 471         /* Disable IO-PAD and IO-CHAIN wakeup */
 472         if (omap3_has_io_wakeup() &&
 473             (per_next_state < PWRDM_POWER_ON ||
 474              core_next_state < PWRDM_POWER_ON)) {
 475                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 476                                              PM_WKEN);
 477                 if (omap3_has_io_chain_ctrl())
 478                         omap3_disable_io_chain();
 479         }
 480
 481         if (mpu_next_state < PWRDM_POWER_ON)
 482                 pwrdm_post_transition(mpu_pwrdm);
 483 }
 484
 485 static void omap3_pm_idle(void)
 486 {
 487         local_irq_disable();
 488         local_fiq_disable();
 489
 490         if (omap_irq_pending() || need_resched())
 491                 goto out;
 492
 493         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 494         trace_cpu_idle(1, smp_processor_id());
 495
 496         omap_sram_idle();
 497
 498         trace_power_end(smp_processor_id());
 499         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 500
 501 out:
 502         local_fiq_enable();
 503         local_irq_enable();
 504 }
 505
 506 #ifdef CONFIG_SUSPEND
 507 static int omap3_pm_suspend(void)
 508 {
 509         struct power_state *pwrst;
 510         int state, ret = 0;
 511
 512         /* Read current next_pwrsts */
 513         list_for_each_entry(pwrst, &pwrst_list, node)
 514                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 515         /* Set ones wanted by suspend */
 516         list_for_each_entry(pwrst, &pwrst_list, node) {
 517                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 518                         goto restore;
 519                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 520                         goto restore;
 521         }
 522
 523         omap_uart_prepare_suspend();
 524         omap3_intc_suspend();
 525
 526         omap_sram_idle();
 527
 528 restore:
 529         /* Restore next_pwrsts */
 530         list_for_each_entry(pwrst, &pwrst_list, node) {
 531                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 532                 if (state > pwrst->next_state) {
 533                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 534                                "target state %d\n",
 535                                pwrst->pwrdm->name, pwrst->next_state);
 536                         ret = -1;
 537                 }
 538                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 539         }
 540         if (ret)
 541                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 542         else
 543                 printk(KERN_INFO "Successfully put all powerdomains "
 544                        "to target state\n");
 545
 546         return ret;
 547 }
 548
 549 static int omap3_pm_enter(suspend_state_t unused)
 550 {
 551         int ret = 0;
 552
 553         switch (suspend_state) {
 554         case PM_SUSPEND_STANDBY:
 555         case PM_SUSPEND_MEM:
 556                 ret = omap3_pm_suspend();
 557                 break;
 558         default:
 559                 ret = -EINVAL;
 560         }
 561
 562         return ret;
 563 }
 564
 565 /* Hooks to enable / disable UART interrupts during suspend */
 566 static int omap3_pm_begin(suspend_state_t state)
 567 {
 568         disable_hlt();
 569         suspend_state = state;
 570         omap_uart_enable_irqs(0);
 571         return 0;
 572 }
 573
 574 static void omap3_pm_end(void)
 575 {
 576         suspend_state = PM_SUSPEND_ON;
 577         omap_uart_enable_irqs(1);
 578         enable_hlt();
 579         return;
 580 }
 581
 582 static const struct platform_suspend_ops omap_pm_ops = {
 583         .begin          = omap3_pm_begin,
 584         .end            = omap3_pm_end,
 585         .enter          = omap3_pm_enter,
 586         .valid          = suspend_valid_only_mem,
 587 };
 588 #endif /* CONFIG_SUSPEND */
 589
 590
 591 /**
 592  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 593  *                   retention
 594  *
 595  * In cases where IVA2 is activated by bootcode, it may prevent
 596  * full-chip retention or off-mode because it is not idle.  This
 597  * function forces the IVA2 into idle state so it can go
 598  * into retention/off and thus allow full-chip retention/off.
 599  *
 600  **/
 601 static void __init omap3_iva_idle(void)
 602 {
 603         /* ensure IVA2 clock is disabled */
 604         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 605
 606         /* if no clock activity, nothing else to do */
 607         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 608               OMAP3430_CLKACTIVITY_IVA2_MASK))
 609                 return;
 610
 611         /* Reset IVA2 */
 612         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 613                           OMAP3430_RST2_IVA2_MASK |
 614                           OMAP3430_RST3_IVA2_MASK,
 615                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 616
 617         /* Enable IVA2 clock */
 618         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 619                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 620
 621         /* Set IVA2 boot mode to 'idle' */
 622         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 623                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 624
 625         /* Un-reset IVA2 */
 626         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 627
 628         /* Disable IVA2 clock */
 629         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 630
 631         /* Reset IVA2 */
 632         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 633                           OMAP3430_RST2_IVA2_MASK |
 634                           OMAP3430_RST3_IVA2_MASK,
 635                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 636 }
 637
 638 static void __init omap3_d2d_idle(void)
 639 {
 640         u16 mask, padconf;
 641
 642         /* In a stand alone OMAP3430 where there is not a stacked
 643          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 644          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 645          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 646         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 647         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 648         padconf |= mask;
 649         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 650
 651         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 652         padconf |= mask;
 653         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 654
 655         /* reset modem */
 656         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 657                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 658                           CORE_MOD, OMAP2_RM_RSTCTRL);
 659         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 660 }
 661
 662 static void __init prcm_setup_regs(void)
 663 {
 664         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 665                                         OMAP3630_EN_UART4_MASK : 0;
 666         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 667                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 668
 669         /* XXX This should be handled by hwmod code or SCM init code */
 670         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 671
 672         /*
 673          * Enable control of expternal oscillator through
 674          * sys_clkreq. In the long run clock framework should
 675          * take care of this.
 676          */
 677         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 678                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 679                              OMAP3430_GR_MOD,
 680                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 681
 682         /* setup wakup source */
 683         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 684                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 685                           WKUP_MOD, PM_WKEN);
 686         /* No need to write EN_IO, that is always enabled */
 687         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 688                           OMAP3430_GRPSEL_GPT1_MASK |
 689                           OMAP3430_GRPSEL_GPT12_MASK,
 690                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 691         /* For some reason IO doesn't generate wakeup event even if
 692          * it is selected to mpu wakeup goup */
 693         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 694                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 695
 696         /* Enable PM_WKEN to support DSS LPR */
 697         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 698                                 OMAP3430_DSS_MOD, PM_WKEN);
 699
 700         /* Enable wakeups in PER */
 701         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 702                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 703                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 704                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 705                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 706                           OMAP3430_EN_MCBSP4_MASK,
 707                           OMAP3430_PER_MOD, PM_WKEN);
 708         /* and allow them to wake up MPU */
 709         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 710                           OMAP3430_GRPSEL_GPIO2_MASK |
 711                           OMAP3430_GRPSEL_GPIO3_MASK |
 712                           OMAP3430_GRPSEL_GPIO4_MASK |
 713                           OMAP3430_GRPSEL_GPIO5_MASK |
 714                           OMAP3430_GRPSEL_GPIO6_MASK |
 715                           OMAP3430_GRPSEL_UART3_MASK |
 716                           OMAP3430_GRPSEL_MCBSP2_MASK |
 717                           OMAP3430_GRPSEL_MCBSP3_MASK |
 718                           OMAP3430_GRPSEL_MCBSP4_MASK,
 719                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 720
 721         /* Don't attach IVA interrupts */
 722         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 723         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 724         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 725         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 726
 727         /* Clear any pending 'reset' flags */
 728         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 729         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 730         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 731         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 732         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 733         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 734         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 735
 736         /* Clear any pending PRCM interrupts */
 737         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 738
 739         omap3_iva_idle();
 740         omap3_d2d_idle();
 741 }
 742
 743 void omap3_pm_off_mode_enable(int enable)
 744 {
 745         struct power_state *pwrst;
 746         u32 state;
 747
 748         if (enable)
 749                 state = PWRDM_POWER_OFF;
 750         else
 751                 state = PWRDM_POWER_RET;
 752
 753         list_for_each_entry(pwrst, &pwrst_list, node) {
 754                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 755                                 pwrst->pwrdm == core_pwrdm &&
 756                                 state == PWRDM_POWER_OFF) {
 757                         pwrst->next_state = PWRDM_POWER_RET;
 758                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 759                                 __func__);
 760                 } else {
 761                         pwrst->next_state = state;
 762                 }
 763                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 764         }
 765 }
 766
 767 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 768 {
 769         struct power_state *pwrst;
 770
 771         list_for_each_entry(pwrst, &pwrst_list, node) {
 772                 if (pwrst->pwrdm == pwrdm)
 773                         return pwrst->next_state;
 774         }
 775         return -EINVAL;
 776 }
 777
 778 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 779 {
 780         struct power_state *pwrst;
 781
 782         list_for_each_entry(pwrst, &pwrst_list, node) {
 783                 if (pwrst->pwrdm == pwrdm) {
 784                         pwrst->next_state = state;
 785                         return 0;
 786                 }
 787         }
 788         return -EINVAL;
 789 }
 790
 791 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 792 {
 793         struct power_state *pwrst;
 794
 795         if (!pwrdm->pwrsts)
 796                 return 0;
 797
 798         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 799         if (!pwrst)
 800                 return -ENOMEM;
 801         pwrst->pwrdm = pwrdm;
 802         pwrst->next_state = PWRDM_POWER_RET;
 803         list_add(&pwrst->node, &pwrst_list);
 804
 805         if (pwrdm_has_hdwr_sar(pwrdm))
 806                 pwrdm_enable_hdwr_sar(pwrdm);
 807
 808         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 809 }
 810
 811 /*
 812  * Enable hw supervised mode for all clockdomains if it's
 813  * supported. Initiate sleep transition for other clockdomains, if
 814  * they are not used
 815  */
 816 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 817 {
 818         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 819                 clkdm_allow_idle(clkdm);
 820         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 821                  atomic_read(&clkdm->usecount) == 0)
 822                 clkdm_sleep(clkdm);
 823         return 0;
 824 }
 825
 826 /*
 827  * Push functions to SRAM
 828  *
 829  * The minimum set of functions is pushed to SRAM for execution:
 830  * - omap3_do_wfi for erratum i581 WA,
 831  * - save_secure_ram_context for security extensions.
 832  */
 833 void omap_push_sram_idle(void)
 834 {
 835         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 836
 837         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 838                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 839                                 save_secure_ram_context_sz);
 840 }
 841
 842 static void __init pm_errata_configure(void)
 843 {
 844         if (cpu_is_omap3630()) {
 845                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 846                 /* Enable the l2 cache toggling in sleep logic */
 847                 enable_omap3630_toggle_l2_on_restore();
 848                 if (omap_rev() < OMAP3630_REV_ES1_2)
 849                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 850         }
 851 }
 852
 853 static int __init omap3_pm_init(void)
 854 {
 855         struct power_state *pwrst, *tmp;
 856         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 857         int ret;
 858
 859         if (!cpu_is_omap34xx())
 860                 return -ENODEV;
 861
 862         if (!omap3_has_io_chain_ctrl())
 863                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 864
 865         pm_errata_configure();
 866
 867         /* XXX prcm_setup_regs needs to be before enabling hw
 868          * supervised mode for powerdomains */
 869         prcm_setup_regs();
 870
 871         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 872                           (irq_handler_t)prcm_interrupt_handler,
 873                           IRQF_DISABLED, "prcm", NULL);
 874         if (ret) {
 875                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 876                        INT_34XX_PRCM_MPU_IRQ);
 877                 goto err1;
 878         }
 879
 880         ret = pwrdm_for_each(pwrdms_setup, NULL);
 881         if (ret) {
 882                 printk(KERN_ERR "Failed to setup powerdomains\n");
 883                 goto err2;
 884         }
 885
 886         (void) clkdm_for_each(clkdms_setup, NULL);
 887
 888         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 889         if (mpu_pwrdm == NULL) {
 890                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 891                 goto err2;
 892         }
 893
 894         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 895         per_pwrdm = pwrdm_lookup("per_pwrdm");
 896         core_pwrdm = pwrdm_lookup("core_pwrdm");
 897
 898         neon_clkdm = clkdm_lookup("neon_clkdm");
 899         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 900         per_clkdm = clkdm_lookup("per_clkdm");
 901         core_clkdm = clkdm_lookup("core_clkdm");
 902
 903 #ifdef CONFIG_SUSPEND
 904         suspend_set_ops(&omap_pm_ops);
 905 #endif /* CONFIG_SUSPEND */
 906
 907         pm_idle = omap3_pm_idle;
 908         omap3_idle_init();
 909
 910         /*
 911          * RTA is disabled during initialization as per erratum i608
 912          * it is safer to disable RTA by the bootloader, but we would like
 913          * to be doubly sure here and prevent any mishaps.
 914          */
 915         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 916                 omap3630_ctrl_disable_rta();
 917
 918         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 919         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 920                 omap3_secure_ram_storage =
 921                         kmalloc(0x803F, GFP_KERNEL);
 922                 if (!omap3_secure_ram_storage)
 923                         printk(KERN_ERR "Memory allocation failed when"
 924                                         "allocating for secure sram context\n");
 925
 926                 local_irq_disable();
 927                 local_fiq_disable();
 928
 929                 omap_dma_global_context_save();
 930                 omap3_save_secure_ram_context();
 931                 omap_dma_global_context_restore();
 932
 933                 local_irq_enable();
 934                 local_fiq_enable();
 935         }
 936
 937         omap3_save_scratchpad_contents();
 938 err1:
 939         return ret;
 940 err2:
 941         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 942         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 943                 list_del(&pwrst->node);
 944                 kfree(pwrst);
 945         }
 946         return ret;
 947 }
 948
 949 late_initcall(omap3_pm_init);