arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 #ifdef CONFIG_SUSPEND
  55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  56 static inline bool is_suspending(void)
  57 {
  58         return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
  59 }
  60 #else
  61 static inline bool is_suspending(void)
  62 {
  63         return false;
  64 }
  65 #endif
  66
  67 /* pm34xx errata defined in pm.h */
  68 u16 pm34xx_errata;
  69
  70 struct power_state {
  71         struct powerdomain *pwrdm;
  72         u32 next_state;
  73 #ifdef CONFIG_SUSPEND
  74         u32 saved_state;
  75 #endif
  76         struct list_head node;
  77 };
  78
  79 static LIST_HEAD(pwrst_list);
  80
  81 static int (*_omap_save_secure_sram)(u32 *addr);
  82 void (*omap3_do_wfi_sram)(void);
  83
  84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  85 static struct powerdomain *core_pwrdm, *per_pwrdm;
  86 static struct powerdomain *cam_pwrdm;
  87
  88 static inline void omap3_per_save_context(void)
  89 {
  90         omap_gpio_save_context();
  91 }
  92
  93 static inline void omap3_per_restore_context(void)
  94 {
  95         omap_gpio_restore_context();
  96 }
  97
  98 static void omap3_enable_io_chain(void)
  99 {
 100         int timeout = 0;
 101
 102         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 103                                    PM_WKEN);
 104         /* Do a readback to assure write has been done */
 105         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 106
 107         while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 108                  OMAP3430_ST_IO_CHAIN_MASK)) {
 109                 timeout++;
 110                 if (timeout > 1000) {
 111                         pr_err("Wake up daisy chain activation failed.\n");
 112                         return;
 113                 }
 114                 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 115                                            WKUP_MOD, PM_WKEN);
 116         }
 117 }
 118
 119 static void omap3_disable_io_chain(void)
 120 {
 121         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 122                                      PM_WKEN);
 123 }
 124
 125 static void omap3_core_save_context(void)
 126 {
 127         omap3_ctrl_save_padconf();
 128
 129         /*
 130          * Force write last pad into memory, as this can fail in some
 131          * cases according to errata 1.157, 1.185
 132          */
 133         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 134                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 135
 136         /* Save the Interrupt controller context */
 137         omap_intc_save_context();
 138         /* Save the GPMC context */
 139         omap3_gpmc_save_context();
 140         /* Save the system control module context, padconf already save above*/
 141         omap3_control_save_context();
 142         omap_dma_global_context_save();
 143 }
 144
 145 static void omap3_core_restore_context(void)
 146 {
 147         /* Restore the control module context, padconf restored by h/w */
 148         omap3_control_restore_context();
 149         /* Restore the GPMC context */
 150         omap3_gpmc_restore_context();
 151         /* Restore the interrupt controller context */
 152         omap_intc_restore_context();
 153         omap_dma_global_context_restore();
 154 }
 155
 156 /*
 157  * FIXME: This function should be called before entering off-mode after
 158  * OMAP3 secure services have been accessed. Currently it is only called
 159  * once during boot sequence, but this works as we are not using secure
 160  * services.
 161  */
 162 static void omap3_save_secure_ram_context(void)
 163 {
 164         u32 ret;
 165         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 166
 167         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 168                 /*
 169                  * MPU next state must be set to POWER_ON temporarily,
 170                  * otherwise the WFI executed inside the ROM code
 171                  * will hang the system.
 172                  */
 173                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 174                 ret = _omap_save_secure_sram((u32 *)
 175                                 __pa(omap3_secure_ram_storage));
 176                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 177                 /* Following is for error tracking, it should not happen */
 178                 if (ret) {
 179                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 180                                 ret);
 181                         while (1)
 182                                 ;
 183                 }
 184         }
 185 }
 186
 187 /*
 188  * PRCM Interrupt Handler Helper Function
 189  *
 190  * The purpose of this function is to clear any wake-up events latched
 191  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 192  * may occur whilst attempting to clear a PM_WKST_x register and thus
 193  * set another bit in this register. A while loop is used to ensure
 194  * that any peripheral wake-up events occurring while attempting to
 195  * clear the PM_WKST_x are detected and cleared.
 196  */
 197 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 198 {
 199         u32 wkst, fclk, iclk, clken;
 200         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 201         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 202         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 203         u16 grpsel_off = (regs == 3) ?
 204                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 205         int c = 0;
 206
 207         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 208         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 209         if (wkst) {
 210                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 211                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 212                 while (wkst) {
 213                         clken = wkst;
 214                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 215                         /*
 216                          * For USBHOST, we don't know whether HOST1 or
 217                          * HOST2 woke us up, so enable both f-clocks
 218                          */
 219                         if (module == OMAP3430ES2_USBHOST_MOD)
 220                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 221                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 222                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 223                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 224                         c++;
 225                 }
 226                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 227                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 228         }
 229
 230         return c;
 231 }
 232
 233 static int _prcm_int_handle_wakeup(void)
 234 {
 235         int c;
 236
 237         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 238         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 239         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 240         if (omap_rev() > OMAP3430_REV_ES1_0) {
 241                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 242                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 243         }
 244
 245         return c;
 246 }
 247
 248 /*
 249  * PRCM Interrupt Handler
 250  *
 251  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 252  * interrupts from the PRCM for the MPU. These bits must be cleared in
 253  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 254  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 255  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 256  * register indicates that a wake-up event is pending for the MPU and
 257  * this bit can only be cleared if the all the wake-up events latched
 258  * in the various PM_WKST_x registers have been cleared. The interrupt
 259  * handler is implemented using a do-while loop so that if a wake-up
 260  * event occurred during the processing of the prcm interrupt handler
 261  * (setting a bit in the corresponding PM_WKST_x register and thus
 262  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 263  * this would be handled.
 264  */
 265 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 266 {
 267         u32 irqenable_mpu, irqstatus_mpu;
 268         int c = 0;
 269
 270         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 271                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 272         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 273                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 274         irqstatus_mpu &= irqenable_mpu;
 275
 276         do {
 277                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 278                                      OMAP3430_IO_ST_MASK)) {
 279                         c = _prcm_int_handle_wakeup();
 280
 281                         /*
 282                          * Is the MPU PRCM interrupt handler racing with the
 283                          * IVA2 PRCM interrupt handler ?
 284                          */
 285                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 286                              "but no wakeup sources are marked\n");
 287                 } else {
 288                         /* XXX we need to expand our PRCM interrupt handler */
 289                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 290                              "no code to handle it (%08x)\n", irqstatus_mpu);
 291                 }
 292
 293                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 294                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 295
 296                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 297                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 298                 irqstatus_mpu &= irqenable_mpu;
 299
 300         } while (irqstatus_mpu);
 301
 302         return IRQ_HANDLED;
 303 }
 304
 305 static void omap34xx_save_context(u32 *save)
 306 {
 307         u32 val;
 308
 309         /* Read Auxiliary Control Register */
 310         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 311         *save++ = 1;
 312         *save++ = val;
 313
 314         /* Read L2 AUX ctrl register */
 315         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 316         *save++ = 1;
 317         *save++ = val;
 318 }
 319
 320 static int omap34xx_do_sram_idle(unsigned long save_state)
 321 {
 322         omap34xx_cpu_suspend(save_state);
 323         return 0;
 324 }
 325
 326 void omap_sram_idle(void)
 327 {
 328         /* Variable to tell what needs to be saved and restored
 329          * in omap_sram_idle*/
 330         /* save_state = 0 => Nothing to save and restored */
 331         /* save_state = 1 => Only L1 and logic lost */
 332         /* save_state = 2 => Only L2 lost */
 333         /* save_state = 3 => L1, L2 and logic lost */
 334         int save_state = 0;
 335         int mpu_next_state = PWRDM_POWER_ON;
 336         int per_next_state = PWRDM_POWER_ON;
 337         int core_next_state = PWRDM_POWER_ON;
 338         int per_going_off;
 339         int core_prev_state, per_prev_state;
 340         u32 sdrc_pwr = 0;
 341
 342         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 343         switch (mpu_next_state) {
 344         case PWRDM_POWER_ON:
 345         case PWRDM_POWER_RET:
 346                 /* No need to save context */
 347                 save_state = 0;
 348                 break;
 349         case PWRDM_POWER_OFF:
 350                 save_state = 3;
 351                 break;
 352         default:
 353                 /* Invalid state */
 354                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 355                 return;
 356         }
 357
 358         /* NEON control */
 359         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 360                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 361
 362         /* Enable IO-PAD and IO-CHAIN wakeups */
 363         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 364         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 365         if (omap3_has_io_wakeup() &&
 366             (per_next_state < PWRDM_POWER_ON ||
 367              core_next_state < PWRDM_POWER_ON)) {
 368                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 369                 if (omap3_has_io_chain_ctrl())
 370                         omap3_enable_io_chain();
 371         }
 372
 373         /* Block console output in case it is on one of the OMAP UARTs */
 374         if (!is_suspending())
 375                 if (per_next_state < PWRDM_POWER_ON ||
 376                     core_next_state < PWRDM_POWER_ON)
 377                         if (!console_trylock())
 378                                 goto console_still_active;
 379
 380         if (mpu_next_state < PWRDM_POWER_ON)
 381                 pwrdm_pre_transition(mpu_pwrdm);
 382
 383         /* PER */
 384         if (per_next_state < PWRDM_POWER_ON) {
 385                 pwrdm_pre_transition(per_pwrdm);
 386                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 387                 omap_uart_prepare_idle(2);
 388                 omap_uart_prepare_idle(3);
 389                 omap2_gpio_prepare_for_idle(per_going_off);
 390                 if (per_next_state == PWRDM_POWER_OFF)
 391                                 omap3_per_save_context();
 392         }
 393
 394         /* CORE */
 395         if (core_next_state < PWRDM_POWER_ON) {
 396                 omap_uart_prepare_idle(0);
 397                 omap_uart_prepare_idle(1);
 398                 pwrdm_pre_transition(core_pwrdm);
 399                 if (core_next_state == PWRDM_POWER_OFF) {
 400                         omap3_core_save_context();
 401                         omap3_cm_save_context();
 402                 }
 403         }
 404
 405         omap3_intc_prepare_idle();
 406
 407         /*
 408          * On EMU/HS devices ROM code restores a SRDC value
 409          * from scratchpad which has automatic self refresh on timeout
 410          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 411          * Hence store/restore the SDRC_POWER register here.
 412          */
 413         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 414             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 415              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 416             core_next_state == PWRDM_POWER_OFF)
 417                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 418
 419         /*
 420          * omap3_arm_context is the location where some ARM context
 421          * get saved. The rest is placed on the stack, and restored
 422          * from there before resuming.
 423          */
 424         if (save_state)
 425                 omap34xx_save_context(omap3_arm_context);
 426         if (save_state == 1 || save_state == 3)
 427                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 428         else
 429                 omap34xx_do_sram_idle(save_state);
 430
 431         /* Restore normal SDRC POWER settings */
 432         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 433             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 434              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 435             core_next_state == PWRDM_POWER_OFF)
 436                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 437
 438         /* CORE */
 439         if (core_next_state < PWRDM_POWER_ON) {
 440                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 441                 if (core_prev_state == PWRDM_POWER_OFF) {
 442                         omap3_core_restore_context();
 443                         omap3_cm_restore_context();
 444                         omap3_sram_restore_context();
 445                         omap2_sms_restore_context();
 446                 }
 447                 omap_uart_resume_idle(0);
 448                 omap_uart_resume_idle(1);
 449                 if (core_next_state == PWRDM_POWER_OFF)
 450                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 451                                                OMAP3430_GR_MOD,
 452                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 453                 pwrdm_post_transition(core_pwrdm);
 454         }
 455         omap3_intc_resume_idle();
 456
 457         /* PER */
 458         if (per_next_state < PWRDM_POWER_ON) {
 459                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 460                 omap2_gpio_resume_after_idle();
 461                 if (per_prev_state == PWRDM_POWER_OFF)
 462                         omap3_per_restore_context();
 463                 omap_uart_resume_idle(2);
 464                 omap_uart_resume_idle(3);
 465                 pwrdm_post_transition(per_pwrdm);
 466         }
 467
 468         if (!is_suspending())
 469                 console_unlock();
 470
 471 console_still_active:
 472         /* Disable IO-PAD and IO-CHAIN wakeup */
 473         if (omap3_has_io_wakeup() &&
 474             (per_next_state < PWRDM_POWER_ON ||
 475              core_next_state < PWRDM_POWER_ON)) {
 476                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 477                                              PM_WKEN);
 478                 if (omap3_has_io_chain_ctrl())
 479                         omap3_disable_io_chain();
 480         }
 481
 482         if (mpu_next_state < PWRDM_POWER_ON)
 483                 pwrdm_post_transition(mpu_pwrdm);
 484
 485         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 486 }
 487
 488 static void omap3_pm_idle(void)
 489 {
 490         local_irq_disable();
 491         local_fiq_disable();
 492
 493         if (omap_irq_pending() || need_resched())
 494                 goto out;
 495
 496         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 497         trace_cpu_idle(1, smp_processor_id());
 498
 499         omap_sram_idle();
 500
 501         trace_power_end(smp_processor_id());
 502         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 503
 504 out:
 505         local_fiq_enable();
 506         local_irq_enable();
 507 }
 508
 509 #ifdef CONFIG_SUSPEND
 510 static int omap3_pm_suspend(void)
 511 {
 512         struct power_state *pwrst;
 513         int state, ret = 0;
 514
 515         /* Read current next_pwrsts */
 516         list_for_each_entry(pwrst, &pwrst_list, node)
 517                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 518         /* Set ones wanted by suspend */
 519         list_for_each_entry(pwrst, &pwrst_list, node) {
 520                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 521                         goto restore;
 522                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 523                         goto restore;
 524         }
 525
 526         omap_uart_prepare_suspend();
 527         omap3_intc_suspend();
 528
 529         omap_sram_idle();
 530
 531 restore:
 532         /* Restore next_pwrsts */
 533         list_for_each_entry(pwrst, &pwrst_list, node) {
 534                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 535                 if (state > pwrst->next_state) {
 536                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 537                                "target state %d\n",
 538                                pwrst->pwrdm->name, pwrst->next_state);
 539                         ret = -1;
 540                 }
 541                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 542         }
 543         if (ret)
 544                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 545         else
 546                 printk(KERN_INFO "Successfully put all powerdomains "
 547                        "to target state\n");
 548
 549         return ret;
 550 }
 551
 552 static int omap3_pm_enter(suspend_state_t unused)
 553 {
 554         int ret = 0;
 555
 556         switch (suspend_state) {
 557         case PM_SUSPEND_STANDBY:
 558         case PM_SUSPEND_MEM:
 559                 ret = omap3_pm_suspend();
 560                 break;
 561         default:
 562                 ret = -EINVAL;
 563         }
 564
 565         return ret;
 566 }
 567
 568 /* Hooks to enable / disable UART interrupts during suspend */
 569 static int omap3_pm_begin(suspend_state_t state)
 570 {
 571         disable_hlt();
 572         suspend_state = state;
 573         omap_uart_enable_irqs(0);
 574         return 0;
 575 }
 576
 577 static void omap3_pm_end(void)
 578 {
 579         suspend_state = PM_SUSPEND_ON;
 580         omap_uart_enable_irqs(1);
 581         enable_hlt();
 582         return;
 583 }
 584
 585 static const struct platform_suspend_ops omap_pm_ops = {
 586         .begin          = omap3_pm_begin,
 587         .end            = omap3_pm_end,
 588         .enter          = omap3_pm_enter,
 589         .valid          = suspend_valid_only_mem,
 590 };
 591 #endif /* CONFIG_SUSPEND */
 592
 593
 594 /**
 595  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 596  *                   retention
 597  *
 598  * In cases where IVA2 is activated by bootcode, it may prevent
 599  * full-chip retention or off-mode because it is not idle.  This
 600  * function forces the IVA2 into idle state so it can go
 601  * into retention/off and thus allow full-chip retention/off.
 602  *
 603  **/
 604 static void __init omap3_iva_idle(void)
 605 {
 606         /* ensure IVA2 clock is disabled */
 607         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 608
 609         /* if no clock activity, nothing else to do */
 610         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 611               OMAP3430_CLKACTIVITY_IVA2_MASK))
 612                 return;
 613
 614         /* Reset IVA2 */
 615         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 616                           OMAP3430_RST2_IVA2_MASK |
 617                           OMAP3430_RST3_IVA2_MASK,
 618                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 619
 620         /* Enable IVA2 clock */
 621         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 622                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 623
 624         /* Set IVA2 boot mode to 'idle' */
 625         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 626                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 627
 628         /* Un-reset IVA2 */
 629         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 630
 631         /* Disable IVA2 clock */
 632         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 633
 634         /* Reset IVA2 */
 635         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 636                           OMAP3430_RST2_IVA2_MASK |
 637                           OMAP3430_RST3_IVA2_MASK,
 638                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 639 }
 640
 641 static void __init omap3_d2d_idle(void)
 642 {
 643         u16 mask, padconf;
 644
 645         /* In a stand alone OMAP3430 where there is not a stacked
 646          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 647          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 648          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 649         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 650         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 651         padconf |= mask;
 652         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 653
 654         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 655         padconf |= mask;
 656         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 657
 658         /* reset modem */
 659         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 660                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 661                           CORE_MOD, OMAP2_RM_RSTCTRL);
 662         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 663 }
 664
 665 static void __init prcm_setup_regs(void)
 666 {
 667         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 668                                         OMAP3630_EN_UART4_MASK : 0;
 669         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 670                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 671
 672         /* XXX This should be handled by hwmod code or SCM init code */
 673         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 674
 675         /*
 676          * Enable control of expternal oscillator through
 677          * sys_clkreq. In the long run clock framework should
 678          * take care of this.
 679          */
 680         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 681                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 682                              OMAP3430_GR_MOD,
 683                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 684
 685         /* setup wakup source */
 686         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 687                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 688                           WKUP_MOD, PM_WKEN);
 689         /* No need to write EN_IO, that is always enabled */
 690         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 691                           OMAP3430_GRPSEL_GPT1_MASK |
 692                           OMAP3430_GRPSEL_GPT12_MASK,
 693                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 694         /* For some reason IO doesn't generate wakeup event even if
 695          * it is selected to mpu wakeup goup */
 696         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 697                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 698
 699         /* Enable PM_WKEN to support DSS LPR */
 700         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 701                                 OMAP3430_DSS_MOD, PM_WKEN);
 702
 703         /* Enable wakeups in PER */
 704         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 705                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 706                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 707                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 708                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 709                           OMAP3430_EN_MCBSP4_MASK,
 710                           OMAP3430_PER_MOD, PM_WKEN);
 711         /* and allow them to wake up MPU */
 712         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 713                           OMAP3430_GRPSEL_GPIO2_MASK |
 714                           OMAP3430_GRPSEL_GPIO3_MASK |
 715                           OMAP3430_GRPSEL_GPIO4_MASK |
 716                           OMAP3430_GRPSEL_GPIO5_MASK |
 717                           OMAP3430_GRPSEL_GPIO6_MASK |
 718                           OMAP3430_GRPSEL_UART3_MASK |
 719                           OMAP3430_GRPSEL_MCBSP2_MASK |
 720                           OMAP3430_GRPSEL_MCBSP3_MASK |
 721                           OMAP3430_GRPSEL_MCBSP4_MASK,
 722                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 723
 724         /* Don't attach IVA interrupts */
 725         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 726         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 727         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 728         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 729
 730         /* Clear any pending 'reset' flags */
 731         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 732         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 733         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 734         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 735         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 736         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 737         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 738
 739         /* Clear any pending PRCM interrupts */
 740         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 741
 742         omap3_iva_idle();
 743         omap3_d2d_idle();
 744 }
 745
 746 void omap3_pm_off_mode_enable(int enable)
 747 {
 748         struct power_state *pwrst;
 749         u32 state;
 750
 751         if (enable)
 752                 state = PWRDM_POWER_OFF;
 753         else
 754                 state = PWRDM_POWER_RET;
 755
 756         list_for_each_entry(pwrst, &pwrst_list, node) {
 757                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 758                                 pwrst->pwrdm == core_pwrdm &&
 759                                 state == PWRDM_POWER_OFF) {
 760                         pwrst->next_state = PWRDM_POWER_RET;
 761                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 762                                 __func__);
 763                 } else {
 764                         pwrst->next_state = state;
 765                 }
 766                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 767         }
 768 }
 769
 770 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 771 {
 772         struct power_state *pwrst;
 773
 774         list_for_each_entry(pwrst, &pwrst_list, node) {
 775                 if (pwrst->pwrdm == pwrdm)
 776                         return pwrst->next_state;
 777         }
 778         return -EINVAL;
 779 }
 780
 781 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 782 {
 783         struct power_state *pwrst;
 784
 785         list_for_each_entry(pwrst, &pwrst_list, node) {
 786                 if (pwrst->pwrdm == pwrdm) {
 787                         pwrst->next_state = state;
 788                         return 0;
 789                 }
 790         }
 791         return -EINVAL;
 792 }
 793
 794 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 795 {
 796         struct power_state *pwrst;
 797
 798         if (!pwrdm->pwrsts)
 799                 return 0;
 800
 801         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 802         if (!pwrst)
 803                 return -ENOMEM;
 804         pwrst->pwrdm = pwrdm;
 805         pwrst->next_state = PWRDM_POWER_RET;
 806         list_add(&pwrst->node, &pwrst_list);
 807
 808         if (pwrdm_has_hdwr_sar(pwrdm))
 809                 pwrdm_enable_hdwr_sar(pwrdm);
 810
 811         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 812 }
 813
 814 /*
 815  * Enable hw supervised mode for all clockdomains if it's
 816  * supported. Initiate sleep transition for other clockdomains, if
 817  * they are not used
 818  */
 819 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 820 {
 821         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 822                 clkdm_allow_idle(clkdm);
 823         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 824                  atomic_read(&clkdm->usecount) == 0)
 825                 clkdm_sleep(clkdm);
 826         return 0;
 827 }
 828
 829 /*
 830  * Push functions to SRAM
 831  *
 832  * The minimum set of functions is pushed to SRAM for execution:
 833  * - omap3_do_wfi for erratum i581 WA,
 834  * - save_secure_ram_context for security extensions.
 835  */
 836 void omap_push_sram_idle(void)
 837 {
 838         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 839
 840         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 841                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 842                                 save_secure_ram_context_sz);
 843 }
 844
 845 static void __init pm_errata_configure(void)
 846 {
 847         if (cpu_is_omap3630()) {
 848                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 849                 /* Enable the l2 cache toggling in sleep logic */
 850                 enable_omap3630_toggle_l2_on_restore();
 851                 if (omap_rev() < OMAP3630_REV_ES1_2)
 852                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 853         }
 854 }
 855
 856 static int __init omap3_pm_init(void)
 857 {
 858         struct power_state *pwrst, *tmp;
 859         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 860         int ret;
 861
 862         if (!cpu_is_omap34xx())
 863                 return -ENODEV;
 864
 865         if (!omap3_has_io_chain_ctrl())
 866                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 867
 868         pm_errata_configure();
 869
 870         /* XXX prcm_setup_regs needs to be before enabling hw
 871          * supervised mode for powerdomains */
 872         prcm_setup_regs();
 873
 874         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 875                           (irq_handler_t)prcm_interrupt_handler,
 876                           IRQF_DISABLED, "prcm", NULL);
 877         if (ret) {
 878                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 879                        INT_34XX_PRCM_MPU_IRQ);
 880                 goto err1;
 881         }
 882
 883         ret = pwrdm_for_each(pwrdms_setup, NULL);
 884         if (ret) {
 885                 printk(KERN_ERR "Failed to setup powerdomains\n");
 886                 goto err2;
 887         }
 888
 889         (void) clkdm_for_each(clkdms_setup, NULL);
 890
 891         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 892         if (mpu_pwrdm == NULL) {
 893                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 894                 goto err2;
 895         }
 896
 897         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 898         per_pwrdm = pwrdm_lookup("per_pwrdm");
 899         core_pwrdm = pwrdm_lookup("core_pwrdm");
 900         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 901
 902         neon_clkdm = clkdm_lookup("neon_clkdm");
 903         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 904         per_clkdm = clkdm_lookup("per_clkdm");
 905         core_clkdm = clkdm_lookup("core_clkdm");
 906
 907 #ifdef CONFIG_SUSPEND
 908         suspend_set_ops(&omap_pm_ops);
 909 #endif /* CONFIG_SUSPEND */
 910
 911         pm_idle = omap3_pm_idle;
 912         omap3_idle_init();
 913
 914         /*
 915          * RTA is disabled during initialization as per erratum i608
 916          * it is safer to disable RTA by the bootloader, but we would like
 917          * to be doubly sure here and prevent any mishaps.
 918          */
 919         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 920                 omap3630_ctrl_disable_rta();
 921
 922         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 923         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 924                 omap3_secure_ram_storage =
 925                         kmalloc(0x803F, GFP_KERNEL);
 926                 if (!omap3_secure_ram_storage)
 927                         printk(KERN_ERR "Memory allocation failed when"
 928                                         "allocating for secure sram context\n");
 929
 930                 local_irq_disable();
 931                 local_fiq_disable();
 932
 933                 omap_dma_global_context_save();
 934                 omap3_save_secure_ram_context();
 935                 omap_dma_global_context_restore();
 936
 937                 local_irq_enable();
 938                 local_fiq_enable();
 939         }
 940
 941         omap3_save_scratchpad_contents();
 942 err1:
 943         return ret;
 944 err2:
 945         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 946         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 947                 list_del(&pwrst->node);
 948                 kfree(pwrst);
 949         }
 950         return ret;
 951 }
 952
 953 late_initcall(omap3_pm_init);