2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
32 #include <trace/events/power.h>
34 #include <asm/suspend.h>
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/serial.h>
40 #include <plat/sdrc.h>
41 #include <plat/prcm.h>
42 #include <plat/gpmc.h>
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
49 #include "prm2xxx_3xxx.h"
55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
56 static inline bool is_suspending(void)
58 return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
61 static inline bool is_suspending(void)
67 /* pm34xx errata defined in pm.h */
71 struct powerdomain *pwrdm;
76 struct list_head node;
79 static LIST_HEAD(pwrst_list);
81 static int (*_omap_save_secure_sram)(u32 *addr);
82 void (*omap3_do_wfi_sram)(void);
84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
85 static struct powerdomain *core_pwrdm, *per_pwrdm;
86 static struct powerdomain *cam_pwrdm;
88 static inline void omap3_per_save_context(void)
90 omap_gpio_save_context();
93 static inline void omap3_per_restore_context(void)
95 omap_gpio_restore_context();
98 static void omap3_enable_io_chain(void)
102 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
104 /* Do a readback to assure write has been done */
105 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
107 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
108 OMAP3430_ST_IO_CHAIN_MASK)) {
110 if (timeout > 1000) {
111 pr_err("Wake up daisy chain activation failed.\n");
114 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
119 static void omap3_disable_io_chain(void)
121 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
125 static void omap3_core_save_context(void)
127 omap3_ctrl_save_padconf();
130 * Force write last pad into memory, as this can fail in some
131 * cases according to errata 1.157, 1.185
133 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
134 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
136 /* Save the Interrupt controller context */
137 omap_intc_save_context();
138 /* Save the GPMC context */
139 omap3_gpmc_save_context();
140 /* Save the system control module context, padconf already save above*/
141 omap3_control_save_context();
142 omap_dma_global_context_save();
145 static void omap3_core_restore_context(void)
147 /* Restore the control module context, padconf restored by h/w */
148 omap3_control_restore_context();
149 /* Restore the GPMC context */
150 omap3_gpmc_restore_context();
151 /* Restore the interrupt controller context */
152 omap_intc_restore_context();
153 omap_dma_global_context_restore();
157 * FIXME: This function should be called before entering off-mode after
158 * OMAP3 secure services have been accessed. Currently it is only called
159 * once during boot sequence, but this works as we are not using secure
162 static void omap3_save_secure_ram_context(void)
165 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
167 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
169 * MPU next state must be set to POWER_ON temporarily,
170 * otherwise the WFI executed inside the ROM code
171 * will hang the system.
173 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
174 ret = _omap_save_secure_sram((u32 *)
175 __pa(omap3_secure_ram_storage));
176 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
177 /* Following is for error tracking, it should not happen */
179 printk(KERN_ERR "save_secure_sram() returns %08x\n",
188 * PRCM Interrupt Handler Helper Function
190 * The purpose of this function is to clear any wake-up events latched
191 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
192 * may occur whilst attempting to clear a PM_WKST_x register and thus
193 * set another bit in this register. A while loop is used to ensure
194 * that any peripheral wake-up events occurring while attempting to
195 * clear the PM_WKST_x are detected and cleared.
197 static int prcm_clear_mod_irqs(s16 module, u8 regs)
199 u32 wkst, fclk, iclk, clken;
200 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
201 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
202 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
203 u16 grpsel_off = (regs == 3) ?
204 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
207 wkst = omap2_prm_read_mod_reg(module, wkst_off);
208 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
210 iclk = omap2_cm_read_mod_reg(module, iclk_off);
211 fclk = omap2_cm_read_mod_reg(module, fclk_off);
214 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
216 * For USBHOST, we don't know whether HOST1 or
217 * HOST2 woke us up, so enable both f-clocks
219 if (module == OMAP3430ES2_USBHOST_MOD)
220 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
221 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
222 omap2_prm_write_mod_reg(wkst, module, wkst_off);
223 wkst = omap2_prm_read_mod_reg(module, wkst_off);
226 omap2_cm_write_mod_reg(iclk, module, iclk_off);
227 omap2_cm_write_mod_reg(fclk, module, fclk_off);
233 static int _prcm_int_handle_wakeup(void)
237 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
238 c += prcm_clear_mod_irqs(CORE_MOD, 1);
239 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
240 if (omap_rev() > OMAP3430_REV_ES1_0) {
241 c += prcm_clear_mod_irqs(CORE_MOD, 3);
242 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
249 * PRCM Interrupt Handler
251 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
252 * interrupts from the PRCM for the MPU. These bits must be cleared in
253 * order to clear the PRCM interrupt. The PRCM interrupt handler is
254 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
255 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
256 * register indicates that a wake-up event is pending for the MPU and
257 * this bit can only be cleared if the all the wake-up events latched
258 * in the various PM_WKST_x registers have been cleared. The interrupt
259 * handler is implemented using a do-while loop so that if a wake-up
260 * event occurred during the processing of the prcm interrupt handler
261 * (setting a bit in the corresponding PM_WKST_x register and thus
262 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
263 * this would be handled.
265 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
267 u32 irqenable_mpu, irqstatus_mpu;
270 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
271 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
272 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
273 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
274 irqstatus_mpu &= irqenable_mpu;
277 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
278 OMAP3430_IO_ST_MASK)) {
279 c = _prcm_int_handle_wakeup();
282 * Is the MPU PRCM interrupt handler racing with the
283 * IVA2 PRCM interrupt handler ?
285 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
286 "but no wakeup sources are marked\n");
288 /* XXX we need to expand our PRCM interrupt handler */
289 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
290 "no code to handle it (%08x)\n", irqstatus_mpu);
293 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
294 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
296 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
297 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
298 irqstatus_mpu &= irqenable_mpu;
300 } while (irqstatus_mpu);
305 static void omap34xx_save_context(u32 *save)
309 /* Read Auxiliary Control Register */
310 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
314 /* Read L2 AUX ctrl register */
315 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
320 static int omap34xx_do_sram_idle(unsigned long save_state)
322 omap34xx_cpu_suspend(save_state);
326 void omap_sram_idle(void)
328 /* Variable to tell what needs to be saved and restored
329 * in omap_sram_idle*/
330 /* save_state = 0 => Nothing to save and restored */
331 /* save_state = 1 => Only L1 and logic lost */
332 /* save_state = 2 => Only L2 lost */
333 /* save_state = 3 => L1, L2 and logic lost */
335 int mpu_next_state = PWRDM_POWER_ON;
336 int per_next_state = PWRDM_POWER_ON;
337 int core_next_state = PWRDM_POWER_ON;
339 int core_prev_state, per_prev_state;
342 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
343 switch (mpu_next_state) {
345 case PWRDM_POWER_RET:
346 /* No need to save context */
349 case PWRDM_POWER_OFF:
354 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
359 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
360 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
362 /* Enable IO-PAD and IO-CHAIN wakeups */
363 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
364 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
365 if (omap3_has_io_wakeup() &&
366 (per_next_state < PWRDM_POWER_ON ||
367 core_next_state < PWRDM_POWER_ON)) {
368 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
369 if (omap3_has_io_chain_ctrl())
370 omap3_enable_io_chain();
373 /* Block console output in case it is on one of the OMAP UARTs */
374 if (!is_suspending())
375 if (per_next_state < PWRDM_POWER_ON ||
376 core_next_state < PWRDM_POWER_ON)
377 if (!console_trylock())
378 goto console_still_active;
380 pwrdm_pre_transition();
383 if (per_next_state < PWRDM_POWER_ON) {
384 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
385 omap_uart_prepare_idle(2);
386 omap_uart_prepare_idle(3);
387 omap2_gpio_prepare_for_idle(per_going_off);
388 if (per_next_state == PWRDM_POWER_OFF)
389 omap3_per_save_context();
393 if (core_next_state < PWRDM_POWER_ON) {
394 omap_uart_prepare_idle(0);
395 omap_uart_prepare_idle(1);
396 if (core_next_state == PWRDM_POWER_OFF) {
397 omap3_core_save_context();
398 omap3_cm_save_context();
402 omap3_intc_prepare_idle();
405 * On EMU/HS devices ROM code restores a SRDC value
406 * from scratchpad which has automatic self refresh on timeout
407 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
408 * Hence store/restore the SDRC_POWER register here.
410 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
411 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
412 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
413 core_next_state == PWRDM_POWER_OFF)
414 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
417 * omap3_arm_context is the location where some ARM context
418 * get saved. The rest is placed on the stack, and restored
419 * from there before resuming.
422 omap34xx_save_context(omap3_arm_context);
423 if (save_state == 1 || save_state == 3)
424 cpu_suspend(save_state, omap34xx_do_sram_idle);
426 omap34xx_do_sram_idle(save_state);
428 /* Restore normal SDRC POWER settings */
429 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
430 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
431 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
432 core_next_state == PWRDM_POWER_OFF)
433 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
436 if (core_next_state < PWRDM_POWER_ON) {
437 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
438 if (core_prev_state == PWRDM_POWER_OFF) {
439 omap3_core_restore_context();
440 omap3_cm_restore_context();
441 omap3_sram_restore_context();
442 omap2_sms_restore_context();
444 omap_uart_resume_idle(0);
445 omap_uart_resume_idle(1);
446 if (core_next_state == PWRDM_POWER_OFF)
447 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
449 OMAP3_PRM_VOLTCTRL_OFFSET);
451 omap3_intc_resume_idle();
453 pwrdm_post_transition();
456 if (per_next_state < PWRDM_POWER_ON) {
457 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
458 omap2_gpio_resume_after_idle();
459 if (per_prev_state == PWRDM_POWER_OFF)
460 omap3_per_restore_context();
461 omap_uart_resume_idle(2);
462 omap_uart_resume_idle(3);
465 if (!is_suspending())
468 console_still_active:
469 /* Disable IO-PAD and IO-CHAIN wakeup */
470 if (omap3_has_io_wakeup() &&
471 (per_next_state < PWRDM_POWER_ON ||
472 core_next_state < PWRDM_POWER_ON)) {
473 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
475 if (omap3_has_io_chain_ctrl())
476 omap3_disable_io_chain();
479 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
482 static void omap3_pm_idle(void)
487 if (omap_irq_pending() || need_resched())
490 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
491 trace_cpu_idle(1, smp_processor_id());
495 trace_power_end(smp_processor_id());
496 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
503 #ifdef CONFIG_SUSPEND
504 static int omap3_pm_suspend(void)
506 struct power_state *pwrst;
509 /* Read current next_pwrsts */
510 list_for_each_entry(pwrst, &pwrst_list, node)
511 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
512 /* Set ones wanted by suspend */
513 list_for_each_entry(pwrst, &pwrst_list, node) {
514 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
516 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
520 omap_uart_prepare_suspend();
521 omap3_intc_suspend();
526 /* Restore next_pwrsts */
527 list_for_each_entry(pwrst, &pwrst_list, node) {
528 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
529 if (state > pwrst->next_state) {
530 printk(KERN_INFO "Powerdomain (%s) didn't enter "
532 pwrst->pwrdm->name, pwrst->next_state);
535 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
538 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
540 printk(KERN_INFO "Successfully put all powerdomains "
541 "to target state\n");
546 static int omap3_pm_enter(suspend_state_t unused)
550 switch (suspend_state) {
551 case PM_SUSPEND_STANDBY:
553 ret = omap3_pm_suspend();
562 /* Hooks to enable / disable UART interrupts during suspend */
563 static int omap3_pm_begin(suspend_state_t state)
566 suspend_state = state;
567 omap_uart_enable_irqs(0);
571 static void omap3_pm_end(void)
573 suspend_state = PM_SUSPEND_ON;
574 omap_uart_enable_irqs(1);
579 static const struct platform_suspend_ops omap_pm_ops = {
580 .begin = omap3_pm_begin,
582 .enter = omap3_pm_enter,
583 .valid = suspend_valid_only_mem,
585 #endif /* CONFIG_SUSPEND */
589 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
592 * In cases where IVA2 is activated by bootcode, it may prevent
593 * full-chip retention or off-mode because it is not idle. This
594 * function forces the IVA2 into idle state so it can go
595 * into retention/off and thus allow full-chip retention/off.
598 static void __init omap3_iva_idle(void)
600 /* ensure IVA2 clock is disabled */
601 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
603 /* if no clock activity, nothing else to do */
604 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
605 OMAP3430_CLKACTIVITY_IVA2_MASK))
609 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
610 OMAP3430_RST2_IVA2_MASK |
611 OMAP3430_RST3_IVA2_MASK,
612 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
614 /* Enable IVA2 clock */
615 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
616 OMAP3430_IVA2_MOD, CM_FCLKEN);
618 /* Set IVA2 boot mode to 'idle' */
619 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
620 OMAP343X_CONTROL_IVA2_BOOTMOD);
623 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
625 /* Disable IVA2 clock */
626 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
629 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
630 OMAP3430_RST2_IVA2_MASK |
631 OMAP3430_RST3_IVA2_MASK,
632 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
635 static void __init omap3_d2d_idle(void)
639 /* In a stand alone OMAP3430 where there is not a stacked
640 * modem for the D2D Idle Ack and D2D MStandby must be pulled
641 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
642 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
643 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
644 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
646 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
648 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
650 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
653 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
654 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
655 CORE_MOD, OMAP2_RM_RSTCTRL);
656 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
659 static void __init prcm_setup_regs(void)
661 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
662 OMAP3630_EN_UART4_MASK : 0;
663 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
664 OMAP3630_GRPSEL_UART4_MASK : 0;
666 /* XXX This should be handled by hwmod code or SCM init code */
667 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
670 * Enable control of expternal oscillator through
671 * sys_clkreq. In the long run clock framework should
674 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
675 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
677 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
679 /* setup wakup source */
680 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
681 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
683 /* No need to write EN_IO, that is always enabled */
684 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
685 OMAP3430_GRPSEL_GPT1_MASK |
686 OMAP3430_GRPSEL_GPT12_MASK,
687 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
688 /* For some reason IO doesn't generate wakeup event even if
689 * it is selected to mpu wakeup goup */
690 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
691 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
693 /* Enable PM_WKEN to support DSS LPR */
694 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
695 OMAP3430_DSS_MOD, PM_WKEN);
697 /* Enable wakeups in PER */
698 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
699 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
700 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
701 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
702 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
703 OMAP3430_EN_MCBSP4_MASK,
704 OMAP3430_PER_MOD, PM_WKEN);
705 /* and allow them to wake up MPU */
706 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
707 OMAP3430_GRPSEL_GPIO2_MASK |
708 OMAP3430_GRPSEL_GPIO3_MASK |
709 OMAP3430_GRPSEL_GPIO4_MASK |
710 OMAP3430_GRPSEL_GPIO5_MASK |
711 OMAP3430_GRPSEL_GPIO6_MASK |
712 OMAP3430_GRPSEL_UART3_MASK |
713 OMAP3430_GRPSEL_MCBSP2_MASK |
714 OMAP3430_GRPSEL_MCBSP3_MASK |
715 OMAP3430_GRPSEL_MCBSP4_MASK,
716 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
718 /* Don't attach IVA interrupts */
719 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
720 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
721 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
722 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
724 /* Clear any pending 'reset' flags */
725 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
726 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
727 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
728 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
729 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
730 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
731 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
733 /* Clear any pending PRCM interrupts */
734 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
740 void omap3_pm_off_mode_enable(int enable)
742 struct power_state *pwrst;
746 state = PWRDM_POWER_OFF;
748 state = PWRDM_POWER_RET;
750 list_for_each_entry(pwrst, &pwrst_list, node) {
751 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
752 pwrst->pwrdm == core_pwrdm &&
753 state == PWRDM_POWER_OFF) {
754 pwrst->next_state = PWRDM_POWER_RET;
755 pr_warn("%s: Core OFF disabled due to errata i583\n",
758 pwrst->next_state = state;
760 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
764 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
766 struct power_state *pwrst;
768 list_for_each_entry(pwrst, &pwrst_list, node) {
769 if (pwrst->pwrdm == pwrdm)
770 return pwrst->next_state;
775 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
777 struct power_state *pwrst;
779 list_for_each_entry(pwrst, &pwrst_list, node) {
780 if (pwrst->pwrdm == pwrdm) {
781 pwrst->next_state = state;
788 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
790 struct power_state *pwrst;
795 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
798 pwrst->pwrdm = pwrdm;
799 pwrst->next_state = PWRDM_POWER_RET;
800 list_add(&pwrst->node, &pwrst_list);
802 if (pwrdm_has_hdwr_sar(pwrdm))
803 pwrdm_enable_hdwr_sar(pwrdm);
805 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
809 * Enable hw supervised mode for all clockdomains if it's
810 * supported. Initiate sleep transition for other clockdomains, if
813 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
815 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
816 clkdm_allow_idle(clkdm);
817 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
818 atomic_read(&clkdm->usecount) == 0)
824 * Push functions to SRAM
826 * The minimum set of functions is pushed to SRAM for execution:
827 * - omap3_do_wfi for erratum i581 WA,
828 * - save_secure_ram_context for security extensions.
830 void omap_push_sram_idle(void)
832 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
834 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
835 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
836 save_secure_ram_context_sz);
839 static void __init pm_errata_configure(void)
841 if (cpu_is_omap3630()) {
842 pm34xx_errata |= PM_RTA_ERRATUM_i608;
843 /* Enable the l2 cache toggling in sleep logic */
844 enable_omap3630_toggle_l2_on_restore();
845 if (omap_rev() < OMAP3630_REV_ES1_2)
846 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
850 static int __init omap3_pm_init(void)
852 struct power_state *pwrst, *tmp;
853 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
856 if (!cpu_is_omap34xx())
859 if (!omap3_has_io_chain_ctrl())
860 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
862 pm_errata_configure();
864 /* XXX prcm_setup_regs needs to be before enabling hw
865 * supervised mode for powerdomains */
868 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
869 (irq_handler_t)prcm_interrupt_handler,
870 IRQF_DISABLED, "prcm", NULL);
872 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
873 INT_34XX_PRCM_MPU_IRQ);
877 ret = pwrdm_for_each(pwrdms_setup, NULL);
879 printk(KERN_ERR "Failed to setup powerdomains\n");
883 (void) clkdm_for_each(clkdms_setup, NULL);
885 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
886 if (mpu_pwrdm == NULL) {
887 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
891 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
892 per_pwrdm = pwrdm_lookup("per_pwrdm");
893 core_pwrdm = pwrdm_lookup("core_pwrdm");
894 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
896 neon_clkdm = clkdm_lookup("neon_clkdm");
897 mpu_clkdm = clkdm_lookup("mpu_clkdm");
898 per_clkdm = clkdm_lookup("per_clkdm");
899 core_clkdm = clkdm_lookup("core_clkdm");
901 #ifdef CONFIG_SUSPEND
902 suspend_set_ops(&omap_pm_ops);
903 #endif /* CONFIG_SUSPEND */
905 pm_idle = omap3_pm_idle;
909 * RTA is disabled during initialization as per erratum i608
910 * it is safer to disable RTA by the bootloader, but we would like
911 * to be doubly sure here and prevent any mishaps.
913 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
914 omap3630_ctrl_disable_rta();
916 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
917 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
918 omap3_secure_ram_storage =
919 kmalloc(0x803F, GFP_KERNEL);
920 if (!omap3_secure_ram_storage)
921 printk(KERN_ERR "Memory allocation failed when"
922 "allocating for secure sram context\n");
927 omap_dma_global_context_save();
928 omap3_save_secure_ram_context();
929 omap_dma_global_context_restore();
935 omap3_save_scratchpad_contents();
939 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
940 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
941 list_del(&pwrst->node);
947 late_initcall(omap3_pm_init);