arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 #ifdef CONFIG_SUSPEND
  55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  56 static inline bool is_suspending(void)
  57 {
  58         return (suspend_state != PM_SUSPEND_ON);
  59 }
  60 #else
  61 static inline bool is_suspending(void)
  62 {
  63         return false;
  64 }
  65 #endif
  66
  67 /* pm34xx errata defined in pm.h */
  68 u16 pm34xx_errata;
  69
  70 struct power_state {
  71         struct powerdomain *pwrdm;
  72         u32 next_state;
  73 #ifdef CONFIG_SUSPEND
  74         u32 saved_state;
  75 #endif
  76         struct list_head node;
  77 };
  78
  79 static LIST_HEAD(pwrst_list);
  80
  81 static int (*_omap_save_secure_sram)(u32 *addr);
  82 void (*omap3_do_wfi_sram)(void);
  83
  84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  85 static struct powerdomain *core_pwrdm, *per_pwrdm;
  86 static struct powerdomain *cam_pwrdm;
  87
  88 static inline void omap3_per_save_context(void)
  89 {
  90         omap_gpio_save_context();
  91 }
  92
  93 static inline void omap3_per_restore_context(void)
  94 {
  95         omap_gpio_restore_context();
  96 }
  97
  98 static void omap3_enable_io_chain(void)
  99 {
 100         int timeout = 0;
 101
 102         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 103                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 104                                      PM_WKEN);
 105                 /* Do a readback to assure write has been done */
 106                 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 107
 108                 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 109                          OMAP3430_ST_IO_CHAIN_MASK)) {
 110                         timeout++;
 111                         if (timeout > 1000) {
 112                                 printk(KERN_ERR "Wake up daisy chain "
 113                                        "activation failed.\n");
 114                                 return;
 115                         }
 116                         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 117                                              WKUP_MOD, PM_WKEN);
 118                 }
 119         }
 120 }
 121
 122 static void omap3_disable_io_chain(void)
 123 {
 124         if (omap_rev() >= OMAP3430_REV_ES3_1)
 125                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 126                                        PM_WKEN);
 127 }
 128
 129 static void omap3_core_save_context(void)
 130 {
 131         omap3_ctrl_save_padconf();
 132
 133         /*
 134          * Force write last pad into memory, as this can fail in some
 135          * cases according to errata 1.157, 1.185
 136          */
 137         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 138                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 139
 140         /* Save the Interrupt controller context */
 141         omap_intc_save_context();
 142         /* Save the GPMC context */
 143         omap3_gpmc_save_context();
 144         /* Save the system control module context, padconf already save above*/
 145         omap3_control_save_context();
 146         omap_dma_global_context_save();
 147 }
 148
 149 static void omap3_core_restore_context(void)
 150 {
 151         /* Restore the control module context, padconf restored by h/w */
 152         omap3_control_restore_context();
 153         /* Restore the GPMC context */
 154         omap3_gpmc_restore_context();
 155         /* Restore the interrupt controller context */
 156         omap_intc_restore_context();
 157         omap_dma_global_context_restore();
 158 }
 159
 160 /*
 161  * FIXME: This function should be called before entering off-mode after
 162  * OMAP3 secure services have been accessed. Currently it is only called
 163  * once during boot sequence, but this works as we are not using secure
 164  * services.
 165  */
 166 static void omap3_save_secure_ram_context(void)
 167 {
 168         u32 ret;
 169         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 170
 171         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 172                 /*
 173                  * MPU next state must be set to POWER_ON temporarily,
 174                  * otherwise the WFI executed inside the ROM code
 175                  * will hang the system.
 176                  */
 177                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 178                 ret = _omap_save_secure_sram((u32 *)
 179                                 __pa(omap3_secure_ram_storage));
 180                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 181                 /* Following is for error tracking, it should not happen */
 182                 if (ret) {
 183                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 184                                 ret);
 185                         while (1)
 186                                 ;
 187                 }
 188         }
 189 }
 190
 191 /*
 192  * PRCM Interrupt Handler Helper Function
 193  *
 194  * The purpose of this function is to clear any wake-up events latched
 195  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 196  * may occur whilst attempting to clear a PM_WKST_x register and thus
 197  * set another bit in this register. A while loop is used to ensure
 198  * that any peripheral wake-up events occurring while attempting to
 199  * clear the PM_WKST_x are detected and cleared.
 200  */
 201 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 202 {
 203         u32 wkst, fclk, iclk, clken;
 204         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 205         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 206         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 207         u16 grpsel_off = (regs == 3) ?
 208                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 209         int c = 0;
 210
 211         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 212         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 213         if (wkst) {
 214                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 215                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 216                 while (wkst) {
 217                         clken = wkst;
 218                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 219                         /*
 220                          * For USBHOST, we don't know whether HOST1 or
 221                          * HOST2 woke us up, so enable both f-clocks
 222                          */
 223                         if (module == OMAP3430ES2_USBHOST_MOD)
 224                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 225                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 226                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 227                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 228                         c++;
 229                 }
 230                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 231                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 232         }
 233
 234         return c;
 235 }
 236
 237 static int _prcm_int_handle_wakeup(void)
 238 {
 239         int c;
 240
 241         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 242         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 243         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 244         if (omap_rev() > OMAP3430_REV_ES1_0) {
 245                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 246                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 247         }
 248
 249         return c;
 250 }
 251
 252 /*
 253  * PRCM Interrupt Handler
 254  *
 255  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 256  * interrupts from the PRCM for the MPU. These bits must be cleared in
 257  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 258  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 259  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 260  * register indicates that a wake-up event is pending for the MPU and
 261  * this bit can only be cleared if the all the wake-up events latched
 262  * in the various PM_WKST_x registers have been cleared. The interrupt
 263  * handler is implemented using a do-while loop so that if a wake-up
 264  * event occurred during the processing of the prcm interrupt handler
 265  * (setting a bit in the corresponding PM_WKST_x register and thus
 266  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 267  * this would be handled.
 268  */
 269 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 270 {
 271         u32 irqenable_mpu, irqstatus_mpu;
 272         int c = 0;
 273
 274         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 275                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 276         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 277                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 278         irqstatus_mpu &= irqenable_mpu;
 279
 280         do {
 281                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 282                                      OMAP3430_IO_ST_MASK)) {
 283                         c = _prcm_int_handle_wakeup();
 284
 285                         /*
 286                          * Is the MPU PRCM interrupt handler racing with the
 287                          * IVA2 PRCM interrupt handler ?
 288                          */
 289                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 290                              "but no wakeup sources are marked\n");
 291                 } else {
 292                         /* XXX we need to expand our PRCM interrupt handler */
 293                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 294                              "no code to handle it (%08x)\n", irqstatus_mpu);
 295                 }
 296
 297                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 298                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 299
 300                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 301                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 302                 irqstatus_mpu &= irqenable_mpu;
 303
 304         } while (irqstatus_mpu);
 305
 306         return IRQ_HANDLED;
 307 }
 308
 309 static void omap34xx_save_context(u32 *save)
 310 {
 311         u32 val;
 312
 313         /* Read Auxiliary Control Register */
 314         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 315         *save++ = 1;
 316         *save++ = val;
 317
 318         /* Read L2 AUX ctrl register */
 319         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 320         *save++ = 1;
 321         *save++ = val;
 322 }
 323
 324 static int omap34xx_do_sram_idle(unsigned long save_state)
 325 {
 326         omap34xx_cpu_suspend(save_state);
 327         return 0;
 328 }
 329
 330 void omap_sram_idle(void)
 331 {
 332         /* Variable to tell what needs to be saved and restored
 333          * in omap_sram_idle*/
 334         /* save_state = 0 => Nothing to save and restored */
 335         /* save_state = 1 => Only L1 and logic lost */
 336         /* save_state = 2 => Only L2 lost */
 337         /* save_state = 3 => L1, L2 and logic lost */
 338         int save_state = 0;
 339         int mpu_next_state = PWRDM_POWER_ON;
 340         int per_next_state = PWRDM_POWER_ON;
 341         int core_next_state = PWRDM_POWER_ON;
 342         int per_going_off;
 343         int core_prev_state, per_prev_state;
 344         u32 sdrc_pwr = 0;
 345
 346         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 347         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 348         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 349         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 350
 351         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 352         switch (mpu_next_state) {
 353         case PWRDM_POWER_ON:
 354         case PWRDM_POWER_RET:
 355                 /* No need to save context */
 356                 save_state = 0;
 357                 break;
 358         case PWRDM_POWER_OFF:
 359                 save_state = 3;
 360                 break;
 361         default:
 362                 /* Invalid state */
 363                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 364                 return;
 365         }
 366         pwrdm_pre_transition();
 367
 368         /* NEON control */
 369         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 370                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 371
 372         /* Enable IO-PAD and IO-CHAIN wakeups */
 373         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 374         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 375         if (omap3_has_io_wakeup() &&
 376             (per_next_state < PWRDM_POWER_ON ||
 377              core_next_state < PWRDM_POWER_ON)) {
 378                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 379                 omap3_enable_io_chain();
 380         }
 381
 382         /* Block console output in case it is on one of the OMAP UARTs */
 383         if (!is_suspending())
 384                 if (per_next_state < PWRDM_POWER_ON ||
 385                     core_next_state < PWRDM_POWER_ON)
 386                         if (!console_trylock())
 387                                 goto console_still_active;
 388
 389         /* PER */
 390         if (per_next_state < PWRDM_POWER_ON) {
 391                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 392                 omap_uart_prepare_idle(2);
 393                 omap_uart_prepare_idle(3);
 394                 omap2_gpio_prepare_for_idle(per_going_off);
 395                 if (per_next_state == PWRDM_POWER_OFF)
 396                                 omap3_per_save_context();
 397         }
 398
 399         /* CORE */
 400         if (core_next_state < PWRDM_POWER_ON) {
 401                 omap_uart_prepare_idle(0);
 402                 omap_uart_prepare_idle(1);
 403                 if (core_next_state == PWRDM_POWER_OFF) {
 404                         omap3_core_save_context();
 405                         omap3_cm_save_context();
 406                 }
 407         }
 408
 409         omap3_intc_prepare_idle();
 410
 411         /*
 412         * On EMU/HS devices ROM code restores a SRDC value
 413         * from scratchpad which has automatic self refresh on timeout
 414         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 415         * Hence store/restore the SDRC_POWER register here.
 416         */
 417         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 418             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 419             core_next_state == PWRDM_POWER_OFF)
 420                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 421
 422         /*
 423          * omap3_arm_context is the location where some ARM context
 424          * get saved. The rest is placed on the stack, and restored
 425          * from there before resuming.
 426          */
 427         if (save_state)
 428                 omap34xx_save_context(omap3_arm_context);
 429         if (save_state == 1 || save_state == 3)
 430                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 431         else
 432                 omap34xx_do_sram_idle(save_state);
 433
 434         /* Restore normal SDRC POWER settings */
 435         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 436             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 437             core_next_state == PWRDM_POWER_OFF)
 438                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 439
 440         /* CORE */
 441         if (core_next_state < PWRDM_POWER_ON) {
 442                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 443                 if (core_prev_state == PWRDM_POWER_OFF) {
 444                         omap3_core_restore_context();
 445                         omap3_cm_restore_context();
 446                         omap3_sram_restore_context();
 447                         omap2_sms_restore_context();
 448                 }
 449                 omap_uart_resume_idle(0);
 450                 omap_uart_resume_idle(1);
 451                 if (core_next_state == PWRDM_POWER_OFF)
 452                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 453                                                OMAP3430_GR_MOD,
 454                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 455         }
 456         omap3_intc_resume_idle();
 457
 458         /* PER */
 459         if (per_next_state < PWRDM_POWER_ON) {
 460                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 461                 omap2_gpio_resume_after_idle();
 462                 if (per_prev_state == PWRDM_POWER_OFF)
 463                         omap3_per_restore_context();
 464                 omap_uart_resume_idle(2);
 465                 omap_uart_resume_idle(3);
 466         }
 467
 468         if (!is_suspending())
 469                 console_unlock();
 470
 471 console_still_active:
 472         /* Disable IO-PAD and IO-CHAIN wakeup */
 473         if (omap3_has_io_wakeup() &&
 474             (per_next_state < PWRDM_POWER_ON ||
 475              core_next_state < PWRDM_POWER_ON)) {
 476                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 477                                              PM_WKEN);
 478                 omap3_disable_io_chain();
 479         }
 480
 481         pwrdm_post_transition();
 482
 483         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 484 }
 485
 486 int omap3_can_sleep(void)
 487 {
 488         if (!sleep_while_idle)
 489                 return 0;
 490         if (!omap_uart_can_sleep())
 491                 return 0;
 492         return 1;
 493 }
 494
 495 static void omap3_pm_idle(void)
 496 {
 497         local_irq_disable();
 498         local_fiq_disable();
 499
 500         if (!omap3_can_sleep())
 501                 goto out;
 502
 503         if (omap_irq_pending() || need_resched())
 504                 goto out;
 505
 506         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 507         trace_cpu_idle(1, smp_processor_id());
 508
 509         omap_sram_idle();
 510
 511         trace_power_end(smp_processor_id());
 512         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 513
 514 out:
 515         local_fiq_enable();
 516         local_irq_enable();
 517 }
 518
 519 #ifdef CONFIG_SUSPEND
 520 static int omap3_pm_suspend(void)
 521 {
 522         struct power_state *pwrst;
 523         int state, ret = 0;
 524
 525         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 526                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 527                                          wakeup_timer_milliseconds);
 528
 529         /* Read current next_pwrsts */
 530         list_for_each_entry(pwrst, &pwrst_list, node)
 531                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 532         /* Set ones wanted by suspend */
 533         list_for_each_entry(pwrst, &pwrst_list, node) {
 534                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 535                         goto restore;
 536                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 537                         goto restore;
 538         }
 539
 540         omap_uart_prepare_suspend();
 541         omap3_intc_suspend();
 542
 543         omap_sram_idle();
 544
 545 restore:
 546         /* Restore next_pwrsts */
 547         list_for_each_entry(pwrst, &pwrst_list, node) {
 548                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 549                 if (state > pwrst->next_state) {
 550                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 551                                "target state %d\n",
 552                                pwrst->pwrdm->name, pwrst->next_state);
 553                         ret = -1;
 554                 }
 555                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 556         }
 557         if (ret)
 558                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 559         else
 560                 printk(KERN_INFO "Successfully put all powerdomains "
 561                        "to target state\n");
 562
 563         return ret;
 564 }
 565
 566 static int omap3_pm_enter(suspend_state_t unused)
 567 {
 568         int ret = 0;
 569
 570         switch (suspend_state) {
 571         case PM_SUSPEND_STANDBY:
 572         case PM_SUSPEND_MEM:
 573                 ret = omap3_pm_suspend();
 574                 break;
 575         default:
 576                 ret = -EINVAL;
 577         }
 578
 579         return ret;
 580 }
 581
 582 /* Hooks to enable / disable UART interrupts during suspend */
 583 static int omap3_pm_begin(suspend_state_t state)
 584 {
 585         disable_hlt();
 586         suspend_state = state;
 587         omap_uart_enable_irqs(0);
 588         return 0;
 589 }
 590
 591 static void omap3_pm_end(void)
 592 {
 593         suspend_state = PM_SUSPEND_ON;
 594         omap_uart_enable_irqs(1);
 595         enable_hlt();
 596         return;
 597 }
 598
 599 static const struct platform_suspend_ops omap_pm_ops = {
 600         .begin          = omap3_pm_begin,
 601         .end            = omap3_pm_end,
 602         .enter          = omap3_pm_enter,
 603         .valid          = suspend_valid_only_mem,
 604 };
 605 #endif /* CONFIG_SUSPEND */
 606
 607
 608 /**
 609  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 610  *                   retention
 611  *
 612  * In cases where IVA2 is activated by bootcode, it may prevent
 613  * full-chip retention or off-mode because it is not idle.  This
 614  * function forces the IVA2 into idle state so it can go
 615  * into retention/off and thus allow full-chip retention/off.
 616  *
 617  **/
 618 static void __init omap3_iva_idle(void)
 619 {
 620         /* ensure IVA2 clock is disabled */
 621         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 622
 623         /* if no clock activity, nothing else to do */
 624         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 625               OMAP3430_CLKACTIVITY_IVA2_MASK))
 626                 return;
 627
 628         /* Reset IVA2 */
 629         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 630                           OMAP3430_RST2_IVA2_MASK |
 631                           OMAP3430_RST3_IVA2_MASK,
 632                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 633
 634         /* Enable IVA2 clock */
 635         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 636                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 637
 638         /* Set IVA2 boot mode to 'idle' */
 639         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 640                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 641
 642         /* Un-reset IVA2 */
 643         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 644
 645         /* Disable IVA2 clock */
 646         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 647
 648         /* Reset IVA2 */
 649         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 650                           OMAP3430_RST2_IVA2_MASK |
 651                           OMAP3430_RST3_IVA2_MASK,
 652                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 653 }
 654
 655 static void __init omap3_d2d_idle(void)
 656 {
 657         u16 mask, padconf;
 658
 659         /* In a stand alone OMAP3430 where there is not a stacked
 660          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 661          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 662          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 663         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 664         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 665         padconf |= mask;
 666         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 667
 668         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 669         padconf |= mask;
 670         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 671
 672         /* reset modem */
 673         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 674                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 675                           CORE_MOD, OMAP2_RM_RSTCTRL);
 676         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 677 }
 678
 679 static void __init prcm_setup_regs(void)
 680 {
 681         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 682                                         OMAP3630_EN_UART4_MASK : 0;
 683         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 684                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 685
 686         /* XXX This should be handled by hwmod code or SCM init code */
 687         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 688
 689         /*
 690          * Enable control of expternal oscillator through
 691          * sys_clkreq. In the long run clock framework should
 692          * take care of this.
 693          */
 694         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 695                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 696                              OMAP3430_GR_MOD,
 697                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 698
 699         /* setup wakup source */
 700         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 701                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 702                           WKUP_MOD, PM_WKEN);
 703         /* No need to write EN_IO, that is always enabled */
 704         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 705                           OMAP3430_GRPSEL_GPT1_MASK |
 706                           OMAP3430_GRPSEL_GPT12_MASK,
 707                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 708         /* For some reason IO doesn't generate wakeup event even if
 709          * it is selected to mpu wakeup goup */
 710         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 711                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 712
 713         /* Enable PM_WKEN to support DSS LPR */
 714         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 715                                 OMAP3430_DSS_MOD, PM_WKEN);
 716
 717         /* Enable wakeups in PER */
 718         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 719                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 720                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 721                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 722                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 723                           OMAP3430_EN_MCBSP4_MASK,
 724                           OMAP3430_PER_MOD, PM_WKEN);
 725         /* and allow them to wake up MPU */
 726         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 727                           OMAP3430_GRPSEL_GPIO2_MASK |
 728                           OMAP3430_GRPSEL_GPIO3_MASK |
 729                           OMAP3430_GRPSEL_GPIO4_MASK |
 730                           OMAP3430_GRPSEL_GPIO5_MASK |
 731                           OMAP3430_GRPSEL_GPIO6_MASK |
 732                           OMAP3430_GRPSEL_UART3_MASK |
 733                           OMAP3430_GRPSEL_MCBSP2_MASK |
 734                           OMAP3430_GRPSEL_MCBSP3_MASK |
 735                           OMAP3430_GRPSEL_MCBSP4_MASK,
 736                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 737
 738         /* Don't attach IVA interrupts */
 739         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 740         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 741         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 742         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 743
 744         /* Clear any pending 'reset' flags */
 745         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 746         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 747         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 748         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 749         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 750         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 751         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 752
 753         /* Clear any pending PRCM interrupts */
 754         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 755
 756         omap3_iva_idle();
 757         omap3_d2d_idle();
 758 }
 759
 760 void omap3_pm_off_mode_enable(int enable)
 761 {
 762         struct power_state *pwrst;
 763         u32 state;
 764
 765         if (enable)
 766                 state = PWRDM_POWER_OFF;
 767         else
 768                 state = PWRDM_POWER_RET;
 769
 770         list_for_each_entry(pwrst, &pwrst_list, node) {
 771                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 772                                 pwrst->pwrdm == core_pwrdm &&
 773                                 state == PWRDM_POWER_OFF) {
 774                         pwrst->next_state = PWRDM_POWER_RET;
 775                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 776                                 __func__);
 777                 } else {
 778                         pwrst->next_state = state;
 779                 }
 780                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 781         }
 782 }
 783
 784 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 785 {
 786         struct power_state *pwrst;
 787
 788         list_for_each_entry(pwrst, &pwrst_list, node) {
 789                 if (pwrst->pwrdm == pwrdm)
 790                         return pwrst->next_state;
 791         }
 792         return -EINVAL;
 793 }
 794
 795 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 796 {
 797         struct power_state *pwrst;
 798
 799         list_for_each_entry(pwrst, &pwrst_list, node) {
 800                 if (pwrst->pwrdm == pwrdm) {
 801                         pwrst->next_state = state;
 802                         return 0;
 803                 }
 804         }
 805         return -EINVAL;
 806 }
 807
 808 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 809 {
 810         struct power_state *pwrst;
 811
 812         if (!pwrdm->pwrsts)
 813                 return 0;
 814
 815         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 816         if (!pwrst)
 817                 return -ENOMEM;
 818         pwrst->pwrdm = pwrdm;
 819         pwrst->next_state = PWRDM_POWER_RET;
 820         list_add(&pwrst->node, &pwrst_list);
 821
 822         if (pwrdm_has_hdwr_sar(pwrdm))
 823                 pwrdm_enable_hdwr_sar(pwrdm);
 824
 825         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 826 }
 827
 828 /*
 829  * Enable hw supervised mode for all clockdomains if it's
 830  * supported. Initiate sleep transition for other clockdomains, if
 831  * they are not used
 832  */
 833 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 834 {
 835         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 836                 clkdm_allow_idle(clkdm);
 837         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 838                  atomic_read(&clkdm->usecount) == 0)
 839                 clkdm_sleep(clkdm);
 840         return 0;
 841 }
 842
 843 /*
 844  * Push functions to SRAM
 845  *
 846  * The minimum set of functions is pushed to SRAM for execution:
 847  * - omap3_do_wfi for erratum i581 WA,
 848  * - save_secure_ram_context for security extensions.
 849  */
 850 void omap_push_sram_idle(void)
 851 {
 852         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 853
 854         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 855                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 856                                 save_secure_ram_context_sz);
 857 }
 858
 859 static void __init pm_errata_configure(void)
 860 {
 861         if (cpu_is_omap3630()) {
 862                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 863                 /* Enable the l2 cache toggling in sleep logic */
 864                 enable_omap3630_toggle_l2_on_restore();
 865                 if (omap_rev() < OMAP3630_REV_ES1_2)
 866                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 867         }
 868 }
 869
 870 static int __init omap3_pm_init(void)
 871 {
 872         struct power_state *pwrst, *tmp;
 873         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 874         int ret;
 875
 876         if (!cpu_is_omap34xx())
 877                 return -ENODEV;
 878
 879         pm_errata_configure();
 880
 881         /* XXX prcm_setup_regs needs to be before enabling hw
 882          * supervised mode for powerdomains */
 883         prcm_setup_regs();
 884
 885         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 886                           (irq_handler_t)prcm_interrupt_handler,
 887                           IRQF_DISABLED, "prcm", NULL);
 888         if (ret) {
 889                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 890                        INT_34XX_PRCM_MPU_IRQ);
 891                 goto err1;
 892         }
 893
 894         ret = pwrdm_for_each(pwrdms_setup, NULL);
 895         if (ret) {
 896                 printk(KERN_ERR "Failed to setup powerdomains\n");
 897                 goto err2;
 898         }
 899
 900         (void) clkdm_for_each(clkdms_setup, NULL);
 901
 902         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 903         if (mpu_pwrdm == NULL) {
 904                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 905                 goto err2;
 906         }
 907
 908         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 909         per_pwrdm = pwrdm_lookup("per_pwrdm");
 910         core_pwrdm = pwrdm_lookup("core_pwrdm");
 911         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 912
 913         neon_clkdm = clkdm_lookup("neon_clkdm");
 914         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 915         per_clkdm = clkdm_lookup("per_clkdm");
 916         core_clkdm = clkdm_lookup("core_clkdm");
 917
 918 #ifdef CONFIG_SUSPEND
 919         suspend_set_ops(&omap_pm_ops);
 920 #endif /* CONFIG_SUSPEND */
 921
 922         pm_idle = omap3_pm_idle;
 923         omap3_idle_init();
 924
 925         /*
 926          * RTA is disabled during initialization as per erratum i608
 927          * it is safer to disable RTA by the bootloader, but we would like
 928          * to be doubly sure here and prevent any mishaps.
 929          */
 930         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 931                 omap3630_ctrl_disable_rta();
 932
 933         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 934         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 935                 omap3_secure_ram_storage =
 936                         kmalloc(0x803F, GFP_KERNEL);
 937                 if (!omap3_secure_ram_storage)
 938                         printk(KERN_ERR "Memory allocation failed when"
 939                                         "allocating for secure sram context\n");
 940
 941                 local_irq_disable();
 942                 local_fiq_disable();
 943
 944                 omap_dma_global_context_save();
 945                 omap3_save_secure_ram_context();
 946                 omap_dma_global_context_restore();
 947
 948                 local_irq_enable();
 949                 local_fiq_enable();
 950         }
 951
 952         omap3_save_scratchpad_contents();
 953 err1:
 954         return ret;
 955 err2:
 956         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 957         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 958                 list_del(&pwrst->node);
 959                 kfree(pwrst);
 960         }
 961         return ret;
 962 }
 963
 964 late_initcall(omap3_pm_init);