arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31
  32 #include <plat/sram.h>
  33 #include <plat/clockdomain.h>
  34 #include <plat/powerdomain.h>
  35 #include <plat/control.h>
  36 #include <plat/serial.h>
  37 #include <plat/sdrc.h>
  38 #include <plat/prcm.h>
  39 #include <plat/gpmc.h>
  40 #include <plat/dma.h>
  41 #include <plat/dmtimer.h>
  42
  43 #include <asm/tlbflush.h>
  44
  45 #include "cm.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52
  53 /* Scratchpad offsets */
  54 #define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
  55 #define OMAP343X_TABLE_VALUE_OFFSET        0x30
  56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
  57
  58 u32 enable_off_mode;
  59 u32 sleep_while_idle;
  60 u32 wakeup_timer_seconds;
  61 u32 wakeup_timer_milliseconds;
  62
  63 struct power_state {
  64         struct powerdomain *pwrdm;
  65         u32 next_state;
  66 #ifdef CONFIG_SUSPEND
  67         u32 saved_state;
  68 #endif
  69         struct list_head node;
  70 };
  71
  72 static LIST_HEAD(pwrst_list);
  73
  74 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  75
  76 static int (*_omap_save_secure_sram)(u32 *addr);
  77
  78 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  79 static struct powerdomain *core_pwrdm, *per_pwrdm;
  80 static struct powerdomain *cam_pwrdm;
  81
  82 static inline void omap3_per_save_context(void)
  83 {
  84         omap_gpio_save_context();
  85 }
  86
  87 static inline void omap3_per_restore_context(void)
  88 {
  89         omap_gpio_restore_context();
  90 }
  91
  92 static void omap3_enable_io_chain(void)
  93 {
  94         int timeout = 0;
  95
  96         if (omap_rev() >= OMAP3430_REV_ES3_1) {
  97                 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
  98                 /* Do a readback to assure write has been done */
  99                 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 100
 101                 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
 102                          OMAP3430_ST_IO_CHAIN)) {
 103                         timeout++;
 104                         if (timeout > 1000) {
 105                                 printk(KERN_ERR "Wake up daisy chain "
 106                                        "activation failed.\n");
 107                                 return;
 108                         }
 109                         prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
 110                                              WKUP_MOD, PM_WKST);
 111                 }
 112         }
 113 }
 114
 115 static void omap3_disable_io_chain(void)
 116 {
 117         if (omap_rev() >= OMAP3430_REV_ES3_1)
 118                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
 119 }
 120
 121 static void omap3_core_save_context(void)
 122 {
 123         u32 control_padconf_off;
 124
 125         /* Save the padconf registers */
 126         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 127         control_padconf_off |= START_PADCONF_SAVE;
 128         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 129         /* wait for the save to complete */
 130         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 131                         & PADCONF_SAVE_DONE))
 132                 udelay(1);
 133
 134         /*
 135          * Force write last pad into memory, as this can fail in some
 136          * cases according to erratas 1.157, 1.185
 137          */
 138         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 139                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 140
 141         /* Save the Interrupt controller context */
 142         omap_intc_save_context();
 143         /* Save the GPMC context */
 144         omap3_gpmc_save_context();
 145         /* Save the system control module context, padconf already save above*/
 146         omap3_control_save_context();
 147         omap_dma_global_context_save();
 148 }
 149
 150 static void omap3_core_restore_context(void)
 151 {
 152         /* Restore the control module context, padconf restored by h/w */
 153         omap3_control_restore_context();
 154         /* Restore the GPMC context */
 155         omap3_gpmc_restore_context();
 156         /* Restore the interrupt controller context */
 157         omap_intc_restore_context();
 158         omap_dma_global_context_restore();
 159 }
 160
 161 /*
 162  * FIXME: This function should be called before entering off-mode after
 163  * OMAP3 secure services have been accessed. Currently it is only called
 164  * once during boot sequence, but this works as we are not using secure
 165  * services.
 166  */
 167 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 168 {
 169         u32 ret;
 170
 171         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 172                 /*
 173                  * MPU next state must be set to POWER_ON temporarily,
 174                  * otherwise the WFI executed inside the ROM code
 175                  * will hang the system.
 176                  */
 177                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 178                 ret = _omap_save_secure_sram((u32 *)
 179                                 __pa(omap3_secure_ram_storage));
 180                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 181                 /* Following is for error tracking, it should not happen */
 182                 if (ret) {
 183                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 184                                 ret);
 185                         while (1)
 186                                 ;
 187                 }
 188         }
 189 }
 190
 191 /*
 192  * PRCM Interrupt Handler Helper Function
 193  *
 194  * The purpose of this function is to clear any wake-up events latched
 195  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 196  * may occur whilst attempting to clear a PM_WKST_x register and thus
 197  * set another bit in this register. A while loop is used to ensure
 198  * that any peripheral wake-up events occurring while attempting to
 199  * clear the PM_WKST_x are detected and cleared.
 200  */
 201 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 202 {
 203         u32 wkst, fclk, iclk, clken;
 204         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 205         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 206         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 207         u16 grpsel_off = (regs == 3) ?
 208                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 209         int c = 0;
 210
 211         wkst = prm_read_mod_reg(module, wkst_off);
 212         wkst &= prm_read_mod_reg(module, grpsel_off);
 213         if (wkst) {
 214                 iclk = cm_read_mod_reg(module, iclk_off);
 215                 fclk = cm_read_mod_reg(module, fclk_off);
 216                 while (wkst) {
 217                         clken = wkst;
 218                         cm_set_mod_reg_bits(clken, module, iclk_off);
 219                         /*
 220                          * For USBHOST, we don't know whether HOST1 or
 221                          * HOST2 woke us up, so enable both f-clocks
 222                          */
 223                         if (module == OMAP3430ES2_USBHOST_MOD)
 224                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 225                         cm_set_mod_reg_bits(clken, module, fclk_off);
 226                         prm_write_mod_reg(wkst, module, wkst_off);
 227                         wkst = prm_read_mod_reg(module, wkst_off);
 228                         c++;
 229                 }
 230                 cm_write_mod_reg(iclk, module, iclk_off);
 231                 cm_write_mod_reg(fclk, module, fclk_off);
 232         }
 233
 234         return c;
 235 }
 236
 237 static int _prcm_int_handle_wakeup(void)
 238 {
 239         int c;
 240
 241         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 242         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 243         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 244         if (omap_rev() > OMAP3430_REV_ES1_0) {
 245                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 246                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 247         }
 248
 249         return c;
 250 }
 251
 252 /*
 253  * PRCM Interrupt Handler
 254  *
 255  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 256  * interrupts from the PRCM for the MPU. These bits must be cleared in
 257  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 258  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 259  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 260  * register indicates that a wake-up event is pending for the MPU and
 261  * this bit can only be cleared if the all the wake-up events latched
 262  * in the various PM_WKST_x registers have been cleared. The interrupt
 263  * handler is implemented using a do-while loop so that if a wake-up
 264  * event occurred during the processing of the prcm interrupt handler
 265  * (setting a bit in the corresponding PM_WKST_x register and thus
 266  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 267  * this would be handled.
 268  */
 269 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 270 {
 271         u32 irqenable_mpu, irqstatus_mpu;
 272         int c = 0;
 273
 274         irqenable_mpu = prm_read_mod_reg(OCP_MOD,
 275                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 276         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 277                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 278         irqstatus_mpu &= irqenable_mpu;
 279
 280         do {
 281                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 282                         c = _prcm_int_handle_wakeup();
 283
 284                         /*
 285                          * Is the MPU PRCM interrupt handler racing with the
 286                          * IVA2 PRCM interrupt handler ?
 287                          */
 288                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 289                              "but no wakeup sources are marked\n");
 290                 } else {
 291                         /* XXX we need to expand our PRCM interrupt handler */
 292                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 293                              "no code to handle it (%08x)\n", irqstatus_mpu);
 294                 }
 295
 296                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 297                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 298
 299                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 300                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 301                 irqstatus_mpu &= irqenable_mpu;
 302
 303         } while (irqstatus_mpu);
 304
 305         return IRQ_HANDLED;
 306 }
 307
 308 static void restore_control_register(u32 val)
 309 {
 310         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 311 }
 312
 313 /* Function to restore the table entry that was modified for enabling MMU */
 314 static void restore_table_entry(void)
 315 {
 316         u32 *scratchpad_address;
 317         u32 previous_value, control_reg_value;
 318         u32 *address;
 319
 320         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 321
 322         /* Get address of entry that was modified */
 323         address = (u32 *)__raw_readl(scratchpad_address +
 324                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 325         /* Get the previous value which needs to be restored */
 326         previous_value = __raw_readl(scratchpad_address +
 327                                      OMAP343X_TABLE_VALUE_OFFSET);
 328         address = __va(address);
 329         *address = previous_value;
 330         flush_tlb_all();
 331         control_reg_value = __raw_readl(scratchpad_address
 332                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 333         /* This will enable caches and prediction */
 334         restore_control_register(control_reg_value);
 335 }
 336
 337 void omap_sram_idle(void)
 338 {
 339         /* Variable to tell what needs to be saved and restored
 340          * in omap_sram_idle*/
 341         /* save_state = 0 => Nothing to save and restored */
 342         /* save_state = 1 => Only L1 and logic lost */
 343         /* save_state = 2 => Only L2 lost */
 344         /* save_state = 3 => L1, L2 and logic lost */
 345         int save_state = 0;
 346         int mpu_next_state = PWRDM_POWER_ON;
 347         int per_next_state = PWRDM_POWER_ON;
 348         int core_next_state = PWRDM_POWER_ON;
 349         int core_prev_state, per_prev_state;
 350         u32 sdrc_pwr = 0;
 351         int per_state_modified = 0;
 352
 353         if (!_omap_sram_idle)
 354                 return;
 355
 356         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 357         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 358         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 359         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 360
 361         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 362         switch (mpu_next_state) {
 363         case PWRDM_POWER_ON:
 364         case PWRDM_POWER_RET:
 365                 /* No need to save context */
 366                 save_state = 0;
 367                 break;
 368         case PWRDM_POWER_OFF:
 369                 save_state = 3;
 370                 break;
 371         default:
 372                 /* Invalid state */
 373                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 374                 return;
 375         }
 376         pwrdm_pre_transition();
 377
 378         /* NEON control */
 379         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 380                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 381
 382         /* Enable IO-PAD and IO-CHAIN wakeups */
 383         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 384         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 385         if (per_next_state < PWRDM_POWER_ON ||
 386                         core_next_state < PWRDM_POWER_ON) {
 387                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 388                 omap3_enable_io_chain();
 389         }
 390
 391         /* PER */
 392         if (per_next_state < PWRDM_POWER_ON) {
 393                 omap_uart_prepare_idle(2);
 394                 omap2_gpio_prepare_for_idle(per_next_state);
 395                 if (per_next_state == PWRDM_POWER_OFF) {
 396                         if (core_next_state == PWRDM_POWER_ON) {
 397                                 per_next_state = PWRDM_POWER_RET;
 398                                 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
 399                                 per_state_modified = 1;
 400                         } else
 401                                 omap3_per_save_context();
 402                 }
 403         }
 404
 405         if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
 406                 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 407
 408         /* CORE */
 409         if (core_next_state < PWRDM_POWER_ON) {
 410                 omap_uart_prepare_idle(0);
 411                 omap_uart_prepare_idle(1);
 412                 if (core_next_state == PWRDM_POWER_OFF) {
 413                         omap3_core_save_context();
 414                         omap3_prcm_save_context();
 415                 }
 416         }
 417
 418         omap3_intc_prepare_idle();
 419
 420         /*
 421         * On EMU/HS devices ROM code restores a SRDC value
 422         * from scratchpad which has automatic self refresh on timeout
 423         * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
 424         * Hence store/restore the SDRC_POWER register here.
 425         */
 426         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 427             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 428             core_next_state == PWRDM_POWER_OFF)
 429                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 430
 431         /*
 432          * omap3_arm_context is the location where ARM registers
 433          * get saved. The restore path then reads from this
 434          * location and restores them back.
 435          */
 436         _omap_sram_idle(omap3_arm_context, save_state);
 437         cpu_init();
 438
 439         /* Restore normal SDRC POWER settings */
 440         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 441             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 442             core_next_state == PWRDM_POWER_OFF)
 443                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 444
 445         /* Restore table entry modified during MMU restoration */
 446         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 447                 restore_table_entry();
 448
 449         /* CORE */
 450         if (core_next_state < PWRDM_POWER_ON) {
 451                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 452                 if (core_prev_state == PWRDM_POWER_OFF) {
 453                         omap3_core_restore_context();
 454                         omap3_prcm_restore_context();
 455                         omap3_sram_restore_context();
 456                         omap2_sms_restore_context();
 457                 }
 458                 omap_uart_resume_idle(0);
 459                 omap_uart_resume_idle(1);
 460                 if (core_next_state == PWRDM_POWER_OFF)
 461                         prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
 462                                                OMAP3430_GR_MOD,
 463                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 464         }
 465         omap3_intc_resume_idle();
 466
 467         /* PER */
 468         if (per_next_state < PWRDM_POWER_ON) {
 469                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 470                 omap2_gpio_resume_after_idle();
 471                 if (per_prev_state == PWRDM_POWER_OFF)
 472                         omap3_per_restore_context();
 473                 omap_uart_resume_idle(2);
 474                 if (per_state_modified)
 475                         pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
 476         }
 477
 478         /* Disable IO-PAD and IO-CHAIN wakeup */
 479         if (per_next_state < PWRDM_POWER_ON ||
 480                         core_next_state < PWRDM_POWER_ON) {
 481                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 482                 omap3_disable_io_chain();
 483         }
 484
 485         pwrdm_post_transition();
 486
 487         omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 488 }
 489
 490 int omap3_can_sleep(void)
 491 {
 492         if (!sleep_while_idle)
 493                 return 0;
 494         if (!omap_uart_can_sleep())
 495                 return 0;
 496         return 1;
 497 }
 498
 499 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 500  * RET are supported. Function is assuming that clkdm doesn't have
 501  * hw_sup mode enabled. */
 502 int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 503 {
 504         u32 cur_state;
 505         int sleep_switch = 0;
 506         int ret = 0;
 507
 508         if (pwrdm == NULL || IS_ERR(pwrdm))
 509                 return -EINVAL;
 510
 511         while (!(pwrdm->pwrsts & (1 << state))) {
 512                 if (state == PWRDM_POWER_OFF)
 513                         return ret;
 514                 state--;
 515         }
 516
 517         cur_state = pwrdm_read_next_pwrst(pwrdm);
 518         if (cur_state == state)
 519                 return ret;
 520
 521         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 522                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 523                 sleep_switch = 1;
 524                 pwrdm_wait_transition(pwrdm);
 525         }
 526
 527         ret = pwrdm_set_next_pwrst(pwrdm, state);
 528         if (ret) {
 529                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 530                        pwrdm->name);
 531                 goto err;
 532         }
 533
 534         if (sleep_switch) {
 535                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 536                 pwrdm_wait_transition(pwrdm);
 537                 pwrdm_state_switch(pwrdm);
 538         }
 539
 540 err:
 541         return ret;
 542 }
 543
 544 static void omap3_pm_idle(void)
 545 {
 546         local_irq_disable();
 547         local_fiq_disable();
 548
 549         if (!omap3_can_sleep())
 550                 goto out;
 551
 552         if (omap_irq_pending() || need_resched())
 553                 goto out;
 554
 555         omap_sram_idle();
 556
 557 out:
 558         local_fiq_enable();
 559         local_irq_enable();
 560 }
 561
 562 #ifdef CONFIG_SUSPEND
 563 static suspend_state_t suspend_state;
 564
 565 static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
 566 {
 567         u32 tick_rate, cycles;
 568
 569         if (!seconds && !milliseconds)
 570                 return;
 571
 572         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
 573         cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
 574         omap_dm_timer_stop(gptimer_wakeup);
 575         omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
 576
 577         pr_info("PM: Resume timer in %u.%03u secs"
 578                 " (%d ticks at %d ticks/sec.)\n",
 579                 seconds, milliseconds, cycles, tick_rate);
 580 }
 581
 582 static int omap3_pm_prepare(void)
 583 {
 584         disable_hlt();
 585         return 0;
 586 }
 587
 588 static int omap3_pm_suspend(void)
 589 {
 590         struct power_state *pwrst;
 591         int state, ret = 0;
 592
 593         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 594                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 595                                          wakeup_timer_milliseconds);
 596
 597         /* Read current next_pwrsts */
 598         list_for_each_entry(pwrst, &pwrst_list, node)
 599                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 600         /* Set ones wanted by suspend */
 601         list_for_each_entry(pwrst, &pwrst_list, node) {
 602                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 603                         goto restore;
 604                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 605                         goto restore;
 606         }
 607
 608         omap_uart_prepare_suspend();
 609         omap3_intc_suspend();
 610
 611         omap_sram_idle();
 612
 613 restore:
 614         /* Restore next_pwrsts */
 615         list_for_each_entry(pwrst, &pwrst_list, node) {
 616                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 617                 if (state > pwrst->next_state) {
 618                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 619                                "target state %d\n",
 620                                pwrst->pwrdm->name, pwrst->next_state);
 621                         ret = -1;
 622                 }
 623                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 624         }
 625         if (ret)
 626                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 627         else
 628                 printk(KERN_INFO "Successfully put all powerdomains "
 629                        "to target state\n");
 630
 631         return ret;
 632 }
 633
 634 static int omap3_pm_enter(suspend_state_t unused)
 635 {
 636         int ret = 0;
 637
 638         switch (suspend_state) {
 639         case PM_SUSPEND_STANDBY:
 640         case PM_SUSPEND_MEM:
 641                 ret = omap3_pm_suspend();
 642                 break;
 643         default:
 644                 ret = -EINVAL;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void omap3_pm_finish(void)
 651 {
 652         enable_hlt();
 653 }
 654
 655 /* Hooks to enable / disable UART interrupts during suspend */
 656 static int omap3_pm_begin(suspend_state_t state)
 657 {
 658         suspend_state = state;
 659         omap_uart_enable_irqs(0);
 660         return 0;
 661 }
 662
 663 static void omap3_pm_end(void)
 664 {
 665         suspend_state = PM_SUSPEND_ON;
 666         omap_uart_enable_irqs(1);
 667         return;
 668 }
 669
 670 static struct platform_suspend_ops omap_pm_ops = {
 671         .begin          = omap3_pm_begin,
 672         .end            = omap3_pm_end,
 673         .prepare        = omap3_pm_prepare,
 674         .enter          = omap3_pm_enter,
 675         .finish         = omap3_pm_finish,
 676         .valid          = suspend_valid_only_mem,
 677 };
 678 #endif /* CONFIG_SUSPEND */
 679
 680
 681 /**
 682  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 683  *                   retention
 684  *
 685  * In cases where IVA2 is activated by bootcode, it may prevent
 686  * full-chip retention or off-mode because it is not idle.  This
 687  * function forces the IVA2 into idle state so it can go
 688  * into retention/off and thus allow full-chip retention/off.
 689  *
 690  **/
 691 static void __init omap3_iva_idle(void)
 692 {
 693         /* ensure IVA2 clock is disabled */
 694         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 695
 696         /* if no clock activity, nothing else to do */
 697         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 698               OMAP3430_CLKACTIVITY_IVA2_MASK))
 699                 return;
 700
 701         /* Reset IVA2 */
 702         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 703                           OMAP3430_RST2_IVA2 |
 704                           OMAP3430_RST3_IVA2,
 705                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 706
 707         /* Enable IVA2 clock */
 708         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 709                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 710
 711         /* Set IVA2 boot mode to 'idle' */
 712         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 713                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 714
 715         /* Un-reset IVA2 */
 716         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 717
 718         /* Disable IVA2 clock */
 719         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 720
 721         /* Reset IVA2 */
 722         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 723                           OMAP3430_RST2_IVA2 |
 724                           OMAP3430_RST3_IVA2,
 725                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 726 }
 727
 728 static void __init omap3_d2d_idle(void)
 729 {
 730         u16 mask, padconf;
 731
 732         /* In a stand alone OMAP3430 where there is not a stacked
 733          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 734          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 735          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 736         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 737         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 738         padconf |= mask;
 739         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 740
 741         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 742         padconf |= mask;
 743         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 744
 745         /* reset modem */
 746         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 747                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 748                           CORE_MOD, OMAP2_RM_RSTCTRL);
 749         prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 750 }
 751
 752 static void __init prcm_setup_regs(void)
 753 {
 754         /* XXX Reset all wkdeps. This should be done when initializing
 755          * powerdomains */
 756         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 757         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 758         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 759         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 760         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 761         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 762         if (omap_rev() > OMAP3430_REV_ES1_0) {
 763                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 764                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 765         } else
 766                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 767
 768         /*
 769          * Enable interface clock autoidle for all modules.
 770          * Note that in the long run this should be done by clockfw
 771          */
 772         cm_write_mod_reg(
 773                 OMAP3430_AUTO_MODEM |
 774                 OMAP3430ES2_AUTO_MMC3 |
 775                 OMAP3430ES2_AUTO_ICR |
 776                 OMAP3430_AUTO_AES2 |
 777                 OMAP3430_AUTO_SHA12 |
 778                 OMAP3430_AUTO_DES2 |
 779                 OMAP3430_AUTO_MMC2 |
 780                 OMAP3430_AUTO_MMC1 |
 781                 OMAP3430_AUTO_MSPRO |
 782                 OMAP3430_AUTO_HDQ |
 783                 OMAP3430_AUTO_MCSPI4 |
 784                 OMAP3430_AUTO_MCSPI3 |
 785                 OMAP3430_AUTO_MCSPI2 |
 786                 OMAP3430_AUTO_MCSPI1 |
 787                 OMAP3430_AUTO_I2C3 |
 788                 OMAP3430_AUTO_I2C2 |
 789                 OMAP3430_AUTO_I2C1 |
 790                 OMAP3430_AUTO_UART2 |
 791                 OMAP3430_AUTO_UART1 |
 792                 OMAP3430_AUTO_GPT11 |
 793                 OMAP3430_AUTO_GPT10 |
 794                 OMAP3430_AUTO_MCBSP5 |
 795                 OMAP3430_AUTO_MCBSP1 |
 796                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 797                 OMAP3430_AUTO_MAILBOXES |
 798                 OMAP3430_AUTO_OMAPCTRL |
 799                 OMAP3430ES1_AUTO_FSHOSTUSB |
 800                 OMAP3430_AUTO_HSOTGUSB |
 801                 OMAP3430_AUTO_SAD2D |
 802                 OMAP3430_AUTO_SSI,
 803                 CORE_MOD, CM_AUTOIDLE1);
 804
 805         cm_write_mod_reg(
 806                 OMAP3430_AUTO_PKA |
 807                 OMAP3430_AUTO_AES1 |
 808                 OMAP3430_AUTO_RNG |
 809                 OMAP3430_AUTO_SHA11 |
 810                 OMAP3430_AUTO_DES1,
 811                 CORE_MOD, CM_AUTOIDLE2);
 812
 813         if (omap_rev() > OMAP3430_REV_ES1_0) {
 814                 cm_write_mod_reg(
 815                         OMAP3430_AUTO_MAD2D |
 816                         OMAP3430ES2_AUTO_USBTLL,
 817                         CORE_MOD, CM_AUTOIDLE3);
 818         }
 819
 820         cm_write_mod_reg(
 821                 OMAP3430_AUTO_WDT2 |
 822                 OMAP3430_AUTO_WDT1 |
 823                 OMAP3430_AUTO_GPIO1 |
 824                 OMAP3430_AUTO_32KSYNC |
 825                 OMAP3430_AUTO_GPT12 |
 826                 OMAP3430_AUTO_GPT1 ,
 827                 WKUP_MOD, CM_AUTOIDLE);
 828
 829         cm_write_mod_reg(
 830                 OMAP3430_AUTO_DSS,
 831                 OMAP3430_DSS_MOD,
 832                 CM_AUTOIDLE);
 833
 834         cm_write_mod_reg(
 835                 OMAP3430_AUTO_CAM,
 836                 OMAP3430_CAM_MOD,
 837                 CM_AUTOIDLE);
 838
 839         cm_write_mod_reg(
 840                 OMAP3430_AUTO_GPIO6 |
 841                 OMAP3430_AUTO_GPIO5 |
 842                 OMAP3430_AUTO_GPIO4 |
 843                 OMAP3430_AUTO_GPIO3 |
 844                 OMAP3430_AUTO_GPIO2 |
 845                 OMAP3430_AUTO_WDT3 |
 846                 OMAP3430_AUTO_UART3 |
 847                 OMAP3430_AUTO_GPT9 |
 848                 OMAP3430_AUTO_GPT8 |
 849                 OMAP3430_AUTO_GPT7 |
 850                 OMAP3430_AUTO_GPT6 |
 851                 OMAP3430_AUTO_GPT5 |
 852                 OMAP3430_AUTO_GPT4 |
 853                 OMAP3430_AUTO_GPT3 |
 854                 OMAP3430_AUTO_GPT2 |
 855                 OMAP3430_AUTO_MCBSP4 |
 856                 OMAP3430_AUTO_MCBSP3 |
 857                 OMAP3430_AUTO_MCBSP2,
 858                 OMAP3430_PER_MOD,
 859                 CM_AUTOIDLE);
 860
 861         if (omap_rev() > OMAP3430_REV_ES1_0) {
 862                 cm_write_mod_reg(
 863                         OMAP3430ES2_AUTO_USBHOST,
 864                         OMAP3430ES2_USBHOST_MOD,
 865                         CM_AUTOIDLE);
 866         }
 867
 868         omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG);
 869
 870         /*
 871          * Set all plls to autoidle. This is needed until autoidle is
 872          * enabled by clockfw
 873          */
 874         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 875                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 876         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 877                          MPU_MOD,
 878                          CM_AUTOIDLE2);
 879         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 880                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 881                          PLL_MOD,
 882                          CM_AUTOIDLE);
 883         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 884                          PLL_MOD,
 885                          CM_AUTOIDLE2);
 886
 887         /*
 888          * Enable control of expternal oscillator through
 889          * sys_clkreq. In the long run clock framework should
 890          * take care of this.
 891          */
 892         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 893                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 894                              OMAP3430_GR_MOD,
 895                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 896
 897         /* setup wakup source */
 898         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 899                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 900                           WKUP_MOD, PM_WKEN);
 901         /* No need to write EN_IO, that is always enabled */
 902         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 903                           OMAP3430_EN_GPT12,
 904                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 905         /* For some reason IO doesn't generate wakeup event even if
 906          * it is selected to mpu wakeup goup */
 907         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 908                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 909
 910         /* Enable PM_WKEN to support DSS LPR */
 911         prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,
 912                                 OMAP3430_DSS_MOD, PM_WKEN);
 913
 914         /* Enable wakeups in PER */
 915         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 916                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 917                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 |
 918                           OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
 919                           OMAP3430_EN_MCBSP4,
 920                           OMAP3430_PER_MOD, PM_WKEN);
 921         /* and allow them to wake up MPU */
 922         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 923                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 924                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 |
 925                           OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
 926                           OMAP3430_EN_MCBSP4,
 927                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 928
 929         /* Don't attach IVA interrupts */
 930         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 931         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 932         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 933         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 934
 935         /* Clear any pending 'reset' flags */
 936         prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 937         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 938         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 939         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 940         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 941         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 942         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 943
 944         /* Clear any pending PRCM interrupts */
 945         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 946
 947         omap3_iva_idle();
 948         omap3_d2d_idle();
 949 }
 950
 951 void omap3_pm_off_mode_enable(int enable)
 952 {
 953         struct power_state *pwrst;
 954         u32 state;
 955
 956         if (enable)
 957                 state = PWRDM_POWER_OFF;
 958         else
 959                 state = PWRDM_POWER_RET;
 960
 961 #ifdef CONFIG_CPU_IDLE
 962         omap3_cpuidle_update_states();
 963 #endif
 964
 965         list_for_each_entry(pwrst, &pwrst_list, node) {
 966                 pwrst->next_state = state;
 967                 set_pwrdm_state(pwrst->pwrdm, state);
 968         }
 969 }
 970
 971 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 972 {
 973         struct power_state *pwrst;
 974
 975         list_for_each_entry(pwrst, &pwrst_list, node) {
 976                 if (pwrst->pwrdm == pwrdm)
 977                         return pwrst->next_state;
 978         }
 979         return -EINVAL;
 980 }
 981
 982 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 983 {
 984         struct power_state *pwrst;
 985
 986         list_for_each_entry(pwrst, &pwrst_list, node) {
 987                 if (pwrst->pwrdm == pwrdm) {
 988                         pwrst->next_state = state;
 989                         return 0;
 990                 }
 991         }
 992         return -EINVAL;
 993 }
 994
 995 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 996 {
 997         struct power_state *pwrst;
 998
 999         if (!pwrdm->pwrsts)
1000                 return 0;
1001
1002         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
1003         if (!pwrst)
1004                 return -ENOMEM;
1005         pwrst->pwrdm = pwrdm;
1006         pwrst->next_state = PWRDM_POWER_RET;
1007         list_add(&pwrst->node, &pwrst_list);
1008
1009         if (pwrdm_has_hdwr_sar(pwrdm))
1010                 pwrdm_enable_hdwr_sar(pwrdm);
1011
1012         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
1013 }
1014
1015 /*
1016  * Enable hw supervised mode for all clockdomains if it's
1017  * supported. Initiate sleep transition for other clockdomains, if
1018  * they are not used
1019  */
1020 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
1021 {
1022         clkdm_clear_all_wkdeps(clkdm);
1023         clkdm_clear_all_sleepdeps(clkdm);
1024
1025         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1026                 omap2_clkdm_allow_idle(clkdm);
1027         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1028                  atomic_read(&clkdm->usecount) == 0)
1029                 omap2_clkdm_sleep(clkdm);
1030         return 0;
1031 }
1032
1033 void omap_push_sram_idle(void)
1034 {
1035         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1036                                         omap34xx_cpu_suspend_sz);
1037         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1038                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1039                                 save_secure_ram_context_sz);
1040 }
1041
1042 static int __init omap3_pm_init(void)
1043 {
1044         struct power_state *pwrst, *tmp;
1045         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
1046         int ret;
1047
1048         if (!cpu_is_omap34xx())
1049                 return -ENODEV;
1050
1051         printk(KERN_ERR "Power Management for TI OMAP3.\n");
1052
1053         /* XXX prcm_setup_regs needs to be before enabling hw
1054          * supervised mode for powerdomains */
1055         prcm_setup_regs();
1056
1057         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1058                           (irq_handler_t)prcm_interrupt_handler,
1059                           IRQF_DISABLED, "prcm", NULL);
1060         if (ret) {
1061                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1062                        INT_34XX_PRCM_MPU_IRQ);
1063                 goto err1;
1064         }
1065
1066         ret = pwrdm_for_each(pwrdms_setup, NULL);
1067         if (ret) {
1068                 printk(KERN_ERR "Failed to setup powerdomains\n");
1069                 goto err2;
1070         }
1071
1072         (void) clkdm_for_each(clkdms_setup, NULL);
1073
1074         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1075         if (mpu_pwrdm == NULL) {
1076                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1077                 goto err2;
1078         }
1079
1080         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1081         per_pwrdm = pwrdm_lookup("per_pwrdm");
1082         core_pwrdm = pwrdm_lookup("core_pwrdm");
1083         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1084
1085         neon_clkdm = clkdm_lookup("neon_clkdm");
1086         mpu_clkdm = clkdm_lookup("mpu_clkdm");
1087         per_clkdm = clkdm_lookup("per_clkdm");
1088         core_clkdm = clkdm_lookup("core_clkdm");
1089
1090         omap_push_sram_idle();
1091 #ifdef CONFIG_SUSPEND
1092         suspend_set_ops(&omap_pm_ops);
1093 #endif /* CONFIG_SUSPEND */
1094
1095         pm_idle = omap3_pm_idle;
1096         omap3_idle_init();
1097
1098         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1099         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1100                 omap3_secure_ram_storage =
1101                         kmalloc(0x803F, GFP_KERNEL);
1102                 if (!omap3_secure_ram_storage)
1103                         printk(KERN_ERR "Memory allocation failed when"
1104                                         "allocating for secure sram context\n");
1105
1106                 local_irq_disable();
1107                 local_fiq_disable();
1108
1109                 omap_dma_global_context_save();
1110                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1111                 omap_dma_global_context_restore();
1112
1113                 local_irq_enable();
1114                 local_fiq_enable();
1115         }
1116
1117         omap3_save_scratchpad_contents();
1118 err1:
1119         return ret;
1120 err2:
1121         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1122         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1123                 list_del(&pwrst->node);
1124                 kfree(pwrst);
1125         }
1126         return ret;
1127 }
1128
1129 late_initcall(omap3_pm_init);