arch/arm/mach-omap2/opp3xxx_data.c

   1 /*
   2  * OMAP3 OPP table definitions.
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Nishanth Menon
   6  *      Kevin Hilman
   7  * Copyright (C) 2010-2011 Nokia Corporation.
   8  *      Eduardo Valentin
   9  *      Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  16  * kind, whether express or implied; without even the implied warranty
  17  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20 #include <linux/module.h>
  21
  22 #include <plat/cpu.h>
  23
  24 #include "control.h"
  25 #include "omap_opp_data.h"
  26 #include "pm.h"
  27
  28 /* 34xx */
  29
  30 /* VDD1 */
  31
  32 #define OMAP3430_VDD_MPU_OPP1_UV                975000
  33 #define OMAP3430_VDD_MPU_OPP2_UV                1075000
  34 #define OMAP3430_VDD_MPU_OPP3_UV                1200000
  35 #define OMAP3430_VDD_MPU_OPP4_UV                1270000
  36 #define OMAP3430_VDD_MPU_OPP5_UV                1350000
  37
  38 struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
  39         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
  40         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
  41         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
  42         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
  43         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
  44         VOLT_DATA_DEFINE(0, 0, 0, 0),
  45 };
  46
  47 /* VDD2 */
  48
  49 #define OMAP3430_VDD_CORE_OPP1_UV               975000
  50 #define OMAP3430_VDD_CORE_OPP2_UV               1050000
  51 #define OMAP3430_VDD_CORE_OPP3_UV               1150000
  52
  53 struct omap_volt_data omap34xx_vddcore_volt_data[] = {
  54         VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
  55         VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
  56         VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
  57         VOLT_DATA_DEFINE(0, 0, 0, 0),
  58 };
  59
  60 /* 36xx */
  61
  62 /* VDD1 */
  63
  64 #define OMAP3630_VDD_MPU_OPP50_UV               1012500
  65 #define OMAP3630_VDD_MPU_OPP100_UV              1200000
  66 #define OMAP3630_VDD_MPU_OPP120_UV              1325000
  67 #define OMAP3630_VDD_MPU_OPP1G_UV               1375000
  68
  69 struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
  70         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
  71         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
  72         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
  73         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
  74         VOLT_DATA_DEFINE(0, 0, 0, 0),
  75 };
  76
  77 /* VDD2 */
  78
  79 #define OMAP3630_VDD_CORE_OPP50_UV              1000000
  80 #define OMAP3630_VDD_CORE_OPP100_UV             1200000
  81
  82 struct omap_volt_data omap36xx_vddcore_volt_data[] = {
  83         VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
  84         VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
  85         VOLT_DATA_DEFINE(0, 0, 0, 0),
  86 };
  87
  88 /* OPP data */
  89
  90 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
  91         /* MPU OPP1 */
  92         OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
  93         /* MPU OPP2 */
  94         OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
  95         /* MPU OPP3 */
  96         OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
  97         /* MPU OPP4 */
  98         OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
  99         /* MPU OPP5 */
 100         OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
 101
 102         /*
 103          * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
 104          * almost the same than the one at 83MHz thus providing very little
 105          * gain for the power point of view. In term of energy it will even
 106          * increase the consumption due to the very negative performance
 107          * impact that frequency will do to the MPU and the whole system in
 108          * general.
 109          */
 110         OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
 111         /* L3 OPP2 */
 112         OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
 113         /* L3 OPP3 */
 114         OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
 115
 116         /* DSP OPP1 */
 117         OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
 118         /* DSP OPP2 */
 119         OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
 120         /* DSP OPP3 */
 121         OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
 122         /* DSP OPP4 */
 123         OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
 124         /* DSP OPP5 */
 125         OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
 126 };
 127
 128 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
 129         /* MPU OPP1 - OPP50 */
 130         OPP_INITIALIZER("mpu", true,  300000000, OMAP3630_VDD_MPU_OPP50_UV),
 131         /* MPU OPP2 - OPP100 */
 132         OPP_INITIALIZER("mpu", true,  600000000, OMAP3630_VDD_MPU_OPP100_UV),
 133         /* MPU OPP3 - OPP-Turbo */
 134         OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
 135         /* MPU OPP4 - OPP-SB */
 136         OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
 137
 138         /* L3 OPP1 - OPP50 */
 139         OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
 140         /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
 141         OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
 142
 143         /* DSP OPP1 - OPP50 */
 144         OPP_INITIALIZER("iva", true,  260000000, OMAP3630_VDD_MPU_OPP50_UV),
 145         /* DSP OPP2 - OPP100 */
 146         OPP_INITIALIZER("iva", true,  520000000, OMAP3630_VDD_MPU_OPP100_UV),
 147         /* DSP OPP3 - OPP-Turbo */
 148         OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
 149         /* DSP OPP4 - OPP-SB */
 150         OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
 151 };
 152
 153 /**
 154  * omap3_opp_init() - initialize omap3 opp table
 155  */
 156 int __init omap3_opp_init(void)
 157 {
 158         int r = -ENODEV;
 159
 160         if (!cpu_is_omap34xx())
 161                 return r;
 162
 163         if (cpu_is_omap3630())
 164                 r = omap_init_opp_table(omap36xx_opp_def_list,
 165                         ARRAY_SIZE(omap36xx_opp_def_list));
 166         else
 167                 r = omap_init_opp_table(omap34xx_opp_def_list,
 168                         ARRAY_SIZE(omap34xx_opp_def_list));
 169
 170         return r;
 171 }
 172 device_initcall(omap3_opp_init);