arch/arm/mach-omap2/omap_phy_internal.c

   1 /*
   2   * This file configures the internal USB PHY in OMAP4430. Used
   3   * with TWL6030 transceiver and MUSB on OMAP4430.
   4   *
   5   * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
   6   * This program is free software; you can redistribute it and/or modify
   7   * it under the terms of the GNU General Public License as published by
   8   * the Free Software Foundation; either version 2 of the License, or
   9   * (at your option) any later version.
  10   *
  11   * Author: Hema HK <hemahk@ti.com>
  12   *
  13   * This program is distributed in the hope that it will be useful,
  14   * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   * GNU General Public License for more details.
  17   *
  18   * You should have received a copy of the GNU General Public License
  19   * along with this program; if not, write to the Free Software
  20   * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21   *
  22   */
  23
  24 #include <linux/types.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/err.h>
  29 #include <linux/usb.h>
  30
  31 #include <plat/usb.h>
  32 #include "control.h"
  33
  34 /* OMAP control module register for UTMI PHY */
  35 #define CONTROL_DEV_CONF                0x300
  36 #define PHY_PD                          0x1
  37
  38 #define USBOTGHS_CONTROL                0x33c
  39 #define AVALID                          BIT(0)
  40 #define BVALID                          BIT(1)
  41 #define VBUSVALID                       BIT(2)
  42 #define SESSEND                         BIT(3)
  43 #define IDDIG                           BIT(4)
  44
  45 static struct clk *phyclk, *clk48m, *clk32k;
  46 static void __iomem *ctrl_base;
  47 static int usbotghs_control;
  48
  49 int omap4430_phy_init(struct device *dev)
  50 {
  51         ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
  52         if (!ctrl_base) {
  53                 pr_err("control module ioremap failed\n");
  54                 return -ENOMEM;
  55         }
  56         /* Power down the phy */
  57         __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
  58
  59         if (!dev)
  60                 return 0;
  61
  62         phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
  63         if (IS_ERR(phyclk)) {
  64                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
  65                 iounmap(ctrl_base);
  66                 return PTR_ERR(phyclk);
  67         }
  68
  69         clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
  70         if (IS_ERR(clk48m)) {
  71                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
  72                 clk_put(phyclk);
  73                 iounmap(ctrl_base);
  74                 return PTR_ERR(clk48m);
  75         }
  76
  77         clk32k = clk_get(dev, "usb_phy_cm_clk32k");
  78         if (IS_ERR(clk32k)) {
  79                 dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
  80                 clk_put(phyclk);
  81                 clk_put(clk48m);
  82                 iounmap(ctrl_base);
  83                 return PTR_ERR(clk32k);
  84         }
  85         return 0;
  86 }
  87
  88 int omap4430_phy_set_clk(struct device *dev, int on)
  89 {
  90         static int state;
  91
  92         if (on && !state) {
  93                 /* Enable the phy clocks */
  94                 clk_enable(phyclk);
  95                 clk_enable(clk48m);
  96                 clk_enable(clk32k);
  97                 state = 1;
  98         } else if (state) {
  99                 /* Disable the phy clocks */
 100                 clk_disable(phyclk);
 101                 clk_disable(clk48m);
 102                 clk_disable(clk32k);
 103                 state = 0;
 104         }
 105         return 0;
 106 }
 107
 108 int omap4430_phy_power(struct device *dev, int ID, int on)
 109 {
 110         if (on) {
 111                 if (ID)
 112                         /* enable VBUS valid, IDDIG groung */
 113                         __raw_writel(AVALID | VBUSVALID, ctrl_base +
 114                                                         USBOTGHS_CONTROL);
 115                 else
 116                         /*
 117                          * Enable VBUS Valid, AValid and IDDIG
 118                          * high impedance
 119                          */
 120                         __raw_writel(IDDIG | AVALID | VBUSVALID,
 121                                                 ctrl_base + USBOTGHS_CONTROL);
 122         } else {
 123                 /* Enable session END and IDIG to high impedance. */
 124                 __raw_writel(SESSEND | IDDIG, ctrl_base +
 125                                         USBOTGHS_CONTROL);
 126         }
 127         return 0;
 128 }
 129
 130 int omap4430_phy_suspend(struct device *dev, int suspend)
 131 {
 132         if (suspend) {
 133                 /* Disable the clocks */
 134                 omap4430_phy_set_clk(dev, 0);
 135                 /* Power down the phy */
 136                 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 137
 138                 /* save the context */
 139                 usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
 140         } else {
 141                 /* Enable the internel phy clcoks */
 142                 omap4430_phy_set_clk(dev, 1);
 143                 /* power on the phy */
 144                 if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
 145                         __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 146                         mdelay(200);
 147                 }
 148
 149                 /* restore the context */
 150                 __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
 151         }
 152
 153         return 0;
 154 }
 155
 156 int omap4430_phy_exit(struct device *dev)
 157 {
 158         if (ctrl_base)
 159                 iounmap(ctrl_base);
 160         if (phyclk)
 161                 clk_put(phyclk);
 162         if (clk48m)
 163                 clk_put(clk48m);
 164         if (clk32k)
 165                 clk_put(clk32k);
 166
 167         return 0;
 168 }
 169
 170 void am35x_musb_reset(void)
 171 {
 172         u32     regval;
 173
 174         /* Reset the musb interface */
 175         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 176
 177         regval |= AM35XX_USBOTGSS_SW_RST;
 178         omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
 179
 180         regval &= ~AM35XX_USBOTGSS_SW_RST;
 181         omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
 182
 183         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 184 }
 185
 186 void am35x_musb_phy_power(u8 on)
 187 {
 188         unsigned long timeout = jiffies + msecs_to_jiffies(100);
 189         u32 devconf2;
 190
 191         if (on) {
 192                 /*
 193                  * Start the on-chip PHY and its PLL.
 194                  */
 195                 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 196
 197                 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
 198                 devconf2 |= CONF2_PHY_PLLON;
 199
 200                 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 201
 202                 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
 203                 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
 204                                 & CONF2_PHYCLKGD)) {
 205                         cpu_relax();
 206
 207                         if (time_after(jiffies, timeout)) {
 208                                 pr_err(KERN_ERR "musb PHY clock good timed out\n");
 209                                 break;
 210                         }
 211                 }
 212         } else {
 213                 /*
 214                  * Power down the on-chip PHY.
 215                  */
 216                 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 217
 218                 devconf2 &= ~CONF2_PHY_PLLON;
 219                 devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
 220                 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 221         }
 222 }
 223
 224 void am35x_musb_clear_irq(void)
 225 {
 226         u32 regval;
 227
 228         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 229         regval |= AM35XX_USBOTGSS_INT_CLR;
 230         omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
 231         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 232 }
 233
 234 void am35x_set_mode(u8 musb_mode)
 235 {
 236         u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 237
 238         devconf2 &= ~CONF2_OTGMODE;
 239         switch (musb_mode) {
 240 #ifdef  CONFIG_USB_MUSB_HDRC_HCD
 241         case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
 242                 devconf2 |= CONF2_FORCE_HOST;
 243                 break;
 244 #endif
 245 #ifdef  CONFIG_USB_GADGET_MUSB_HDRC
 246         case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
 247                 devconf2 |= CONF2_FORCE_DEVICE;
 248                 break;
 249 #endif
 250 #ifdef  CONFIG_USB_MUSB_OTG
 251         case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
 252                 devconf2 |= CONF2_NO_OVERRIDE;
 253                 break;
 254 #endif
 255         default:
 256                 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
 257         }
 258
 259         omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 260 }