arch/arm/mach-omap2/omap_phy_internal.c

   1 /*
   2   * This file configures the internal USB PHY in OMAP4430. Used
   3   * with TWL6030 transceiver and MUSB on OMAP4430.
   4   *
   5   * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
   6   * This program is free software; you can redistribute it and/or modify
   7   * it under the terms of the GNU General Public License as published by
   8   * the Free Software Foundation; either version 2 of the License, or
   9   * (at your option) any later version.
  10   *
  11   * Author: Hema HK <hemahk@ti.com>
  12   *
  13   * This program is distributed in the hope that it will be useful,
  14   * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   * GNU General Public License for more details.
  17   *
  18   * You should have received a copy of the GNU General Public License
  19   * along with this program; if not, write to the Free Software
  20   * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21   *
  22   */
  23
  24 #include <linux/types.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/err.h>
  29 #include <linux/usb.h>
  30
  31 #include <plat/usb.h>
  32 #include "control.h"
  33
  34 /* OMAP control module register for UTMI PHY */
  35 #define CONTROL_DEV_CONF                0x300
  36 #define PHY_PD                          0x1
  37
  38 #define USBOTGHS_CONTROL                0x33c
  39 #define AVALID                          BIT(0)
  40 #define BVALID                          BIT(1)
  41 #define VBUSVALID                       BIT(2)
  42 #define SESSEND                         BIT(3)
  43 #define IDDIG                           BIT(4)
  44
  45 static struct clk *phyclk, *clk48m, *clk32k;
  46 static void __iomem *ctrl_base;
  47
  48 int omap4430_phy_init(struct device *dev)
  49 {
  50         ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
  51         if (!ctrl_base) {
  52                 dev_err(dev, "control module ioremap failed\n");
  53                 return -ENOMEM;
  54         }
  55         /* Power down the phy */
  56         __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
  57         phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
  58
  59         if (IS_ERR(phyclk)) {
  60                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
  61                 iounmap(ctrl_base);
  62                 return PTR_ERR(phyclk);
  63         }
  64
  65         clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
  66         if (IS_ERR(clk48m)) {
  67                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
  68                 clk_put(phyclk);
  69                 iounmap(ctrl_base);
  70                 return PTR_ERR(clk48m);
  71         }
  72
  73         clk32k = clk_get(dev, "usb_phy_cm_clk32k");
  74         if (IS_ERR(clk32k)) {
  75                 dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
  76                 clk_put(phyclk);
  77                 clk_put(clk48m);
  78                 iounmap(ctrl_base);
  79                 return PTR_ERR(clk32k);
  80         }
  81         return 0;
  82 }
  83
  84 int omap4430_phy_set_clk(struct device *dev, int on)
  85 {
  86         static int state;
  87
  88         if (on && !state) {
  89                 /* Enable the phy clocks */
  90                 clk_enable(phyclk);
  91                 clk_enable(clk48m);
  92                 clk_enable(clk32k);
  93                 state = 1;
  94         } else if (state) {
  95                 /* Disable the phy clocks */
  96                 clk_disable(phyclk);
  97                 clk_disable(clk48m);
  98                 clk_disable(clk32k);
  99                 state = 0;
 100         }
 101         return 0;
 102 }
 103
 104 int omap4430_phy_power(struct device *dev, int ID, int on)
 105 {
 106         if (on) {
 107                 /* enabled the clocks */
 108                 omap4430_phy_set_clk(dev, 1);
 109                 /* power on the phy */
 110                 if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
 111                         __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 112                         mdelay(200);
 113                 }
 114                 if (ID)
 115                         /* enable VBUS valid, IDDIG groung */
 116                         __raw_writel(AVALID | VBUSVALID, ctrl_base +
 117                                                         USBOTGHS_CONTROL);
 118                 else
 119                         /*
 120                          * Enable VBUS Valid, AValid and IDDIG
 121                          * high impedence
 122                          */
 123                         __raw_writel(IDDIG | AVALID | VBUSVALID,
 124                                                 ctrl_base + USBOTGHS_CONTROL);
 125         } else {
 126                 /* Enable session END and IDIG to high impedence. */
 127                 __raw_writel(SESSEND | IDDIG, ctrl_base +
 128                                         USBOTGHS_CONTROL);
 129                 /* Disable the clocks */
 130                 omap4430_phy_set_clk(dev, 0);
 131                 /* Power down the phy */
 132                 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 133         }
 134
 135         return 0;
 136 }
 137
 138 int omap4430_phy_exit(struct device *dev)
 139 {
 140         if (ctrl_base)
 141                 iounmap(ctrl_base);
 142         if (phyclk)
 143                 clk_put(phyclk);
 144         if (clk48m)
 145                 clk_put(clk48m);
 146         if (clk32k)
 147                 clk_put(clk32k);
 148
 149         return 0;
 150 }
 151
 152 void am35x_musb_reset(void)
 153 {
 154         u32     regval;
 155
 156         /* Reset the musb interface */
 157         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 158
 159         regval |= AM35XX_USBOTGSS_SW_RST;
 160         omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
 161
 162         regval &= ~AM35XX_USBOTGSS_SW_RST;
 163         omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
 164
 165         regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 166 }
 167
 168 void am35x_musb_phy_power(u8 on)
 169 {
 170         unsigned long timeout = jiffies + msecs_to_jiffies(100);
 171         u32 devconf2;
 172
 173         if (on) {
 174                 /*
 175                  * Start the on-chip PHY and its PLL.
 176                  */
 177                 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 178
 179                 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
 180                 devconf2 |= CONF2_PHY_PLLON;
 181
 182                 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 183
 184                 pr_info(KERN_INFO "Waiting for PHY clock good...\n");
 185                 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
 186                                 & CONF2_PHYCLKGD)) {
 187                         cpu_relax();
 188
 189                         if (time_after(jiffies, timeout)) {
 190                                 pr_err(KERN_ERR "musb PHY clock good timed out\n");
 191                                 break;
 192                         }
 193                 }
 194         } else {
 195                 /*
 196                  * Power down the on-chip PHY.
 197                  */
 198                 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 199
 200                 devconf2 &= ~CONF2_PHY_PLLON;
 201                 devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
 202                 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 203         }
 204 }
 205
 206 void am35x_musb_clear_irq(void)
 207 {
 208         u32 regval;
 209
 210         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 211         regval |= AM35XX_USBOTGSS_INT_CLR;
 212         omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
 213         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 214 }
 215
 216 void am35x_musb_set_mode(u8 musb_mode)
 217 {
 218         u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 219
 220         devconf2 &= ~CONF2_OTGMODE;
 221         switch (musb_mode) {
 222 #ifdef  CONFIG_USB_MUSB_HDRC_HCD
 223         case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
 224                 devconf2 |= CONF2_FORCE_HOST;
 225                 break;
 226 #endif
 227 #ifdef  CONFIG_USB_GADGET_MUSB_HDRC
 228         case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
 229                 devconf2 |= CONF2_FORCE_DEVICE;
 230                 break;
 231 #endif
 232 #ifdef  CONFIG_USB_MUSB_OTG
 233         case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
 234                 devconf2 |= CONF2_NO_OVERRIDE;
 235                 break;
 236 #endif
 237         default:
 238                 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
 239         }
 240
 241         omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 242 }