arch/arm/mach-omap2/omap_hwmod_81xx_data.c

   1 /*
   2  * DM81xx hwmod data.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
   5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/platform_data/gpio-omap.h>
  19 #include <linux/platform_data/hsmmc-omap.h>
  20 #include <linux/platform_data/spi-omap2-mcspi.h>
  21 #include <plat/dmtimer.h>
  22
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm81xx.h"
  25 #include "ti81xx.h"
  26 #include "wd_timer.h"
  27
  28 /*
  29  * DM816X hardware modules integration data
  30  *
  31  * Note: This is incomplete and at present, not generated from h/w database.
  32  */
  33
  34 /*
  35  * The alwon .clkctrl_offs field is offset from the CM_ALWON, that's
  36  * TRM 18.7.17 CM_ALWON device register values minus 0x1400.
  37  */
  38 #define DM816X_DM_ALWON_BASE            0x1400
  39 #define DM816X_CM_ALWON_MCASP0_CLKCTRL  (0x1540 - DM816X_DM_ALWON_BASE)
  40 #define DM816X_CM_ALWON_MCASP1_CLKCTRL  (0x1544 - DM816X_DM_ALWON_BASE)
  41 #define DM816X_CM_ALWON_MCASP2_CLKCTRL  (0x1548 - DM816X_DM_ALWON_BASE)
  42 #define DM816X_CM_ALWON_MCBSP_CLKCTRL   (0x154c - DM816X_DM_ALWON_BASE)
  43 #define DM816X_CM_ALWON_UART_0_CLKCTRL  (0x1550 - DM816X_DM_ALWON_BASE)
  44 #define DM816X_CM_ALWON_UART_1_CLKCTRL  (0x1554 - DM816X_DM_ALWON_BASE)
  45 #define DM816X_CM_ALWON_UART_2_CLKCTRL  (0x1558 - DM816X_DM_ALWON_BASE)
  46 #define DM816X_CM_ALWON_GPIO_0_CLKCTRL  (0x155c - DM816X_DM_ALWON_BASE)
  47 #define DM816X_CM_ALWON_GPIO_1_CLKCTRL  (0x1560 - DM816X_DM_ALWON_BASE)
  48 #define DM816X_CM_ALWON_I2C_0_CLKCTRL   (0x1564 - DM816X_DM_ALWON_BASE)
  49 #define DM816X_CM_ALWON_I2C_1_CLKCTRL   (0x1568 - DM816X_DM_ALWON_BASE)
  50 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
  51 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
  52 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
  53 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
  54 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
  55 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
  56 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
  57 #define DM816X_CM_ALWON_WDTIMER_CLKCTRL (0x158c - DM816X_DM_ALWON_BASE)
  58 #define DM816X_CM_ALWON_SPI_CLKCTRL     (0x1590 - DM816X_DM_ALWON_BASE)
  59 #define DM816X_CM_ALWON_MAILBOX_CLKCTRL (0x1594 - DM816X_DM_ALWON_BASE)
  60 #define DM816X_CM_ALWON_SPINBOX_CLKCTRL (0x1598 - DM816X_DM_ALWON_BASE)
  61 #define DM816X_CM_ALWON_MMUDATA_CLKCTRL (0x159c - DM816X_DM_ALWON_BASE)
  62 #define DM816X_CM_ALWON_MMUCFG_CLKCTRL  (0x15a8 - DM816X_DM_ALWON_BASE)
  63 #define DM816X_CM_ALWON_SDIO_CLKCTRL    (0x15b0 - DM816X_DM_ALWON_BASE)
  64 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL  (0x15b4 - DM816X_DM_ALWON_BASE)
  65 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL  (0x15b8 - DM816X_DM_ALWON_BASE)
  66 #define DM816X_CM_ALWON_CONTRL_CLKCTRL  (0x15c4 - DM816X_DM_ALWON_BASE)
  67 #define DM816X_CM_ALWON_GPMC_CLKCTRL    (0x15d0 - DM816X_DM_ALWON_BASE)
  68 #define DM816X_CM_ALWON_ETHERNET_0_CLKCTRL (0x15d4 - DM816X_DM_ALWON_BASE)
  69 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
  70 #define DM816X_CM_ALWON_MPU_CLKCTRL     (0x15dc - DM816X_DM_ALWON_BASE)
  71 #define DM816X_CM_ALWON_L3_CLKCTRL      (0x15e4 - DM816X_DM_ALWON_BASE)
  72 #define DM816X_CM_ALWON_L4HS_CLKCTRL    (0x15e8 - DM816X_DM_ALWON_BASE)
  73 #define DM816X_CM_ALWON_L4LS_CLKCTRL    (0x15ec - DM816X_DM_ALWON_BASE)
  74 #define DM816X_CM_ALWON_RTC_CLKCTRL     (0x15f0 - DM816X_DM_ALWON_BASE)
  75 #define DM816X_CM_ALWON_TPCC_CLKCTRL    (0x15f4 - DM816X_DM_ALWON_BASE)
  76 #define DM816X_CM_ALWON_TPTC0_CLKCTRL   (0x15f8 - DM816X_DM_ALWON_BASE)
  77 #define DM816X_CM_ALWON_TPTC1_CLKCTRL   (0x15fc - DM816X_DM_ALWON_BASE)
  78 #define DM816X_CM_ALWON_TPTC2_CLKCTRL   (0x1600 - DM816X_DM_ALWON_BASE)
  79 #define DM816X_CM_ALWON_TPTC3_CLKCTRL   (0x1604 - DM816X_DM_ALWON_BASE)
  80 #define DM816X_CM_ALWON_SR_0_CLKCTRL    (0x1608 - DM816X_DM_ALWON_BASE)
  81 #define DM816X_CM_ALWON_SR_1_CLKCTRL    (0x160c - DM816X_DM_ALWON_BASE)
  82
  83 /*
  84  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
  85  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
  86  */
  87 #define DM816X_CM_DEFAULT_OFFSET        0x500
  88 #define DM816X_CM_DEFAULT_USB_CLKCTRL   (0x558 - DM816X_CM_DEFAULT_OFFSET)
  89
  90 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
  91 static struct omap_hwmod dm816x_alwon_l3_slow_hwmod = {
  92         .name           = "alwon_l3_slow",
  93         .clkdm_name     = "alwon_l3s_clkdm",
  94         .class          = &l3_hwmod_class,
  95         .flags          = HWMOD_NO_IDLEST,
  96 };
  97
  98 static struct omap_hwmod dm816x_default_l3_slow_hwmod = {
  99         .name           = "default_l3_slow",
 100         .clkdm_name     = "default_l3_slow_clkdm",
 101         .class          = &l3_hwmod_class,
 102         .flags          = HWMOD_NO_IDLEST,
 103 };
 104
 105 static struct omap_hwmod dm816x_alwon_l3_med_hwmod = {
 106         .name           = "l3_med",
 107         .clkdm_name     = "alwon_l3_med_clkdm",
 108         .class          = &l3_hwmod_class,
 109         .flags          = HWMOD_NO_IDLEST,
 110 };
 111
 112 static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = {
 113         .name           = "l3_fast",
 114         .clkdm_name     = "alwon_l3_fast_clkdm",
 115         .class          = &l3_hwmod_class,
 116         .flags          = HWMOD_NO_IDLEST,
 117 };
 118
 119 /*
 120  * L4 standard peripherals, see TRM table 1-12 for devices using this.
 121  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 122  */
 123 static struct omap_hwmod dm816x_l4_ls_hwmod = {
 124         .name           = "l4_ls",
 125         .clkdm_name     = "alwon_l3s_clkdm",
 126         .class          = &l4_hwmod_class,
 127 };
 128
 129 /*
 130  * L4 high-speed peripherals. For devices using this, please see the TRM
 131  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 132  * table 1-73 for devices using 250MHz SYSCLK5 clock.
 133  */
 134 static struct omap_hwmod dm816x_l4_hs_hwmod = {
 135         .name           = "l4_hs",
 136         .clkdm_name     = "alwon_l3_med_clkdm",
 137         .class          = &l4_hwmod_class,
 138 };
 139
 140 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
 141 static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_ls = {
 142         .master = &dm816x_alwon_l3_slow_hwmod,
 143         .slave  = &dm816x_l4_ls_hwmod,
 144         .user   = OCP_USER_MPU,
 145 };
 146
 147 /* L3 med -> L4 fast peripheral interface running at 250MHz */
 148 static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_hs = {
 149         .master = &dm816x_alwon_l3_med_hwmod,
 150         .slave  = &dm816x_l4_hs_hwmod,
 151         .user   = OCP_USER_MPU,
 152 };
 153
 154 /* MPU */
 155 static struct omap_hwmod dm816x_mpu_hwmod = {
 156         .name           = "mpu",
 157         .clkdm_name     = "alwon_mpu_clkdm",
 158         .class          = &mpu_hwmod_class,
 159         .flags          = HWMOD_INIT_NO_IDLE,
 160         .main_clk       = "mpu_ck",
 161         .prcm           = {
 162                 .omap4 = {
 163                         .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
 164                         .modulemode = MODULEMODE_SWCTRL,
 165                 },
 166         },
 167 };
 168
 169 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
 170         .master         = &dm816x_mpu_hwmod,
 171         .slave          = &dm816x_alwon_l3_slow_hwmod,
 172         .user           = OCP_USER_MPU,
 173 };
 174
 175 /* L3 med peripheral interface running at 250MHz */
 176 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
 177         .master = &dm816x_mpu_hwmod,
 178         .slave  = &dm816x_alwon_l3_med_hwmod,
 179         .user   = OCP_USER_MPU,
 180 };
 181
 182 /* UART common */
 183 static struct omap_hwmod_class_sysconfig uart_sysc = {
 184         .rev_offs       = 0x50,
 185         .sysc_offs      = 0x54,
 186         .syss_offs      = 0x58,
 187         .sysc_flags     = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 188                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 189                                 SYSS_HAS_RESET_STATUS,
 190         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 191                                 MSTANDBY_SMART_WKUP,
 192         .sysc_fields    = &omap_hwmod_sysc_type1,
 193 };
 194
 195 static struct omap_hwmod_class uart_class = {
 196         .name = "uart",
 197         .sysc = &uart_sysc,
 198 };
 199
 200 static struct omap_hwmod dm816x_uart1_hwmod = {
 201         .name           = "uart1",
 202         .clkdm_name     = "alwon_l3s_clkdm",
 203         .main_clk       = "sysclk10_ck",
 204         .prcm           = {
 205                 .omap4 = {
 206                         .clkctrl_offs = DM816X_CM_ALWON_UART_0_CLKCTRL,
 207                         .modulemode = MODULEMODE_SWCTRL,
 208                 },
 209         },
 210         .class          = &uart_class,
 211         .flags          = DEBUG_TI81XXUART1_FLAGS,
 212 };
 213
 214 static struct omap_hwmod_ocp_if dm816x_l4_ls__uart1 = {
 215         .master         = &dm816x_l4_ls_hwmod,
 216         .slave          = &dm816x_uart1_hwmod,
 217         .clk            = "sysclk6_ck",
 218         .user           = OCP_USER_MPU,
 219 };
 220
 221 static struct omap_hwmod dm816x_uart2_hwmod = {
 222         .name           = "uart2",
 223         .clkdm_name     = "alwon_l3s_clkdm",
 224         .main_clk       = "sysclk10_ck",
 225         .prcm           = {
 226                 .omap4 = {
 227                         .clkctrl_offs = DM816X_CM_ALWON_UART_1_CLKCTRL,
 228                         .modulemode = MODULEMODE_SWCTRL,
 229                 },
 230         },
 231         .class          = &uart_class,
 232         .flags          = DEBUG_TI81XXUART2_FLAGS,
 233 };
 234
 235 static struct omap_hwmod_ocp_if dm816x_l4_ls__uart2 = {
 236         .master         = &dm816x_l4_ls_hwmod,
 237         .slave          = &dm816x_uart2_hwmod,
 238         .clk            = "sysclk6_ck",
 239         .user           = OCP_USER_MPU,
 240 };
 241
 242 static struct omap_hwmod dm816x_uart3_hwmod = {
 243         .name           = "uart3",
 244         .clkdm_name     = "alwon_l3s_clkdm",
 245         .main_clk       = "sysclk10_ck",
 246         .prcm           = {
 247                 .omap4 = {
 248                         .clkctrl_offs = DM816X_CM_ALWON_UART_2_CLKCTRL,
 249                         .modulemode = MODULEMODE_SWCTRL,
 250                 },
 251         },
 252         .class          = &uart_class,
 253         .flags          = DEBUG_TI81XXUART3_FLAGS,
 254 };
 255
 256 static struct omap_hwmod_ocp_if dm816x_l4_ls__uart3 = {
 257         .master         = &dm816x_l4_ls_hwmod,
 258         .slave          = &dm816x_uart3_hwmod,
 259         .clk            = "sysclk6_ck",
 260         .user           = OCP_USER_MPU,
 261 };
 262
 263 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
 264         .rev_offs       = 0x0,
 265         .sysc_offs      = 0x10,
 266         .syss_offs      = 0x14,
 267         .sysc_flags     = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 268                                 SYSS_HAS_RESET_STATUS,
 269         .sysc_fields    = &omap_hwmod_sysc_type1,
 270 };
 271
 272 static struct omap_hwmod_class wd_timer_class = {
 273         .name           = "wd_timer",
 274         .sysc           = &wd_timer_sysc,
 275         .pre_shutdown   = &omap2_wd_timer_disable,
 276         .reset          = &omap2_wd_timer_reset,
 277 };
 278
 279 static struct omap_hwmod dm816x_wd_timer_hwmod = {
 280         .name           = "wd_timer",
 281         .clkdm_name     = "alwon_l3s_clkdm",
 282         .main_clk       = "sysclk18_ck",
 283         .flags          = HWMOD_NO_IDLEST,
 284         .prcm           = {
 285                 .omap4 = {
 286                         .clkctrl_offs = DM816X_CM_ALWON_WDTIMER_CLKCTRL,
 287                         .modulemode = MODULEMODE_SWCTRL,
 288                 },
 289         },
 290         .class          = &wd_timer_class,
 291 };
 292
 293 static struct omap_hwmod_ocp_if dm816x_l4_ls__wd_timer1 = {
 294         .master         = &dm816x_l4_ls_hwmod,
 295         .slave          = &dm816x_wd_timer_hwmod,
 296         .clk            = "sysclk6_ck",
 297         .user           = OCP_USER_MPU,
 298 };
 299
 300 /* I2C common */
 301 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x10,
 304         .syss_offs      = 0x90,
 305         .sysc_flags     = SYSC_HAS_SIDLEMODE |
 306                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 307                                 SYSC_HAS_AUTOIDLE,
 308         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 309         .sysc_fields    = &omap_hwmod_sysc_type1,
 310 };
 311
 312 static struct omap_hwmod_class i2c_class = {
 313         .name = "i2c",
 314         .sysc = &i2c_sysc,
 315 };
 316
 317 static struct omap_hwmod dm81xx_i2c1_hwmod = {
 318         .name           = "i2c1",
 319         .clkdm_name     = "alwon_l3s_clkdm",
 320         .main_clk       = "sysclk10_ck",
 321         .prcm           = {
 322                 .omap4 = {
 323                         .clkctrl_offs = DM816X_CM_ALWON_I2C_0_CLKCTRL,
 324                         .modulemode = MODULEMODE_SWCTRL,
 325                 },
 326         },
 327         .class          = &i2c_class,
 328 };
 329
 330 static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c1 = {
 331         .master         = &dm816x_l4_ls_hwmod,
 332         .slave          = &dm81xx_i2c1_hwmod,
 333         .clk            = "sysclk6_ck",
 334         .user           = OCP_USER_MPU,
 335 };
 336
 337 static struct omap_hwmod dm816x_i2c2_hwmod = {
 338         .name           = "i2c2",
 339         .clkdm_name     = "alwon_l3s_clkdm",
 340         .main_clk       = "sysclk10_ck",
 341         .prcm           = {
 342                 .omap4 = {
 343                         .clkctrl_offs = DM816X_CM_ALWON_I2C_1_CLKCTRL,
 344                         .modulemode = MODULEMODE_SWCTRL,
 345                 },
 346         },
 347         .class          = &i2c_class,
 348 };
 349
 350 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
 351         .rev_offs       = 0x0000,
 352         .sysc_offs      = 0x0010,
 353         .syss_offs      = 0x0014,
 354         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 355                                 SYSC_HAS_SOFTRESET |
 356                                 SYSS_HAS_RESET_STATUS,
 357         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 358         .sysc_fields    = &omap_hwmod_sysc_type1,
 359 };
 360
 361 static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c2 = {
 362         .master         = &dm816x_l4_ls_hwmod,
 363         .slave          = &dm816x_i2c2_hwmod,
 364         .clk            = "sysclk6_ck",
 365         .user           = OCP_USER_MPU,
 366 };
 367
 368 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
 369         .name = "elm",
 370         .sysc = &dm81xx_elm_sysc,
 371 };
 372
 373 static struct omap_hwmod dm81xx_elm_hwmod = {
 374         .name           = "elm",
 375         .clkdm_name     = "alwon_l3s_clkdm",
 376         .class          = &dm81xx_elm_hwmod_class,
 377         .main_clk       = "sysclk6_ck",
 378 };
 379
 380 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
 381         .master         = &dm816x_l4_ls_hwmod,
 382         .slave          = &dm81xx_elm_hwmod,
 383         .user           = OCP_USER_MPU,
 384 };
 385
 386 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 387         .rev_offs       = 0x0000,
 388         .sysc_offs      = 0x0010,
 389         .syss_offs      = 0x0114,
 390         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 391                                 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 392                                 SYSS_HAS_RESET_STATUS,
 393         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 394                                 SIDLE_SMART_WKUP,
 395         .sysc_fields    = &omap_hwmod_sysc_type1,
 396 };
 397
 398 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
 399         .name   = "gpio",
 400         .sysc   = &dm81xx_gpio_sysc,
 401         .rev    = 2,
 402 };
 403
 404 static struct omap_gpio_dev_attr gpio_dev_attr = {
 405         .bank_width     = 32,
 406         .dbck_flag      = true,
 407 };
 408
 409 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 410         { .role = "dbclk", .clk = "sysclk18_ck" },
 411 };
 412
 413 static struct omap_hwmod dm81xx_gpio1_hwmod = {
 414         .name           = "gpio1",
 415         .clkdm_name     = "alwon_l3s_clkdm",
 416         .class          = &dm81xx_gpio_hwmod_class,
 417         .main_clk       = "sysclk6_ck",
 418         .prcm = {
 419                 .omap4 = {
 420                         .clkctrl_offs = DM816X_CM_ALWON_GPIO_0_CLKCTRL,
 421                         .modulemode = MODULEMODE_SWCTRL,
 422                 },
 423         },
 424         .opt_clks       = gpio1_opt_clks,
 425         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 426         .dev_attr       = &gpio_dev_attr,
 427 };
 428
 429 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
 430         .master         = &dm816x_l4_ls_hwmod,
 431         .slave          = &dm81xx_gpio1_hwmod,
 432         .user           = OCP_USER_MPU,
 433 };
 434
 435 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 436         { .role = "dbclk", .clk = "sysclk18_ck" },
 437 };
 438
 439 static struct omap_hwmod dm81xx_gpio2_hwmod = {
 440         .name           = "gpio2",
 441         .clkdm_name     = "alwon_l3s_clkdm",
 442         .class          = &dm81xx_gpio_hwmod_class,
 443         .main_clk       = "sysclk6_ck",
 444         .prcm = {
 445                 .omap4 = {
 446                         .clkctrl_offs = DM816X_CM_ALWON_GPIO_1_CLKCTRL,
 447                         .modulemode = MODULEMODE_SWCTRL,
 448                 },
 449         },
 450         .opt_clks       = gpio2_opt_clks,
 451         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 452         .dev_attr       = &gpio_dev_attr,
 453 };
 454
 455 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
 456         .master         = &dm816x_l4_ls_hwmod,
 457         .slave          = &dm81xx_gpio2_hwmod,
 458         .user           = OCP_USER_MPU,
 459 };
 460
 461 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
 462         .rev_offs       = 0x0,
 463         .sysc_offs      = 0x10,
 464         .syss_offs      = 0x14,
 465         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 466                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 467         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 468         .sysc_fields    = &omap_hwmod_sysc_type1,
 469 };
 470
 471 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
 472         .name   = "gpmc",
 473         .sysc   = &dm81xx_gpmc_sysc,
 474 };
 475
 476 static struct omap_hwmod dm81xx_gpmc_hwmod = {
 477         .name           = "gpmc",
 478         .clkdm_name     = "alwon_l3s_clkdm",
 479         .class          = &dm81xx_gpmc_hwmod_class,
 480         .main_clk       = "sysclk6_ck",
 481         .prcm = {
 482                 .omap4 = {
 483                         .clkctrl_offs = DM816X_CM_ALWON_GPMC_CLKCTRL,
 484                         .modulemode = MODULEMODE_SWCTRL,
 485                 },
 486         },
 487 };
 488
 489 struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
 490         .master         = &dm816x_alwon_l3_slow_hwmod,
 491         .slave          = &dm81xx_gpmc_hwmod,
 492         .user           = OCP_USER_MPU,
 493 };
 494
 495 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
 496         .rev_offs       = 0x0,
 497         .sysc_offs      = 0x10,
 498         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 499                                 SYSC_HAS_SOFTRESET,
 500         .idlemodes      = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
 501         .sysc_fields    = &omap_hwmod_sysc_type2,
 502 };
 503
 504 static struct omap_hwmod_class dm81xx_usbotg_class = {
 505         .name = "usbotg",
 506         .sysc = &dm81xx_usbhsotg_sysc,
 507 };
 508
 509 static struct omap_hwmod dm81xx_usbss_hwmod = {
 510         .name           = "usb_otg_hs",
 511         .clkdm_name     = "default_l3_slow_clkdm",
 512         .main_clk       = "sysclk6_ck",
 513         .prcm           = {
 514                 .omap4 = {
 515                         .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL,
 516                         .modulemode = MODULEMODE_SWCTRL,
 517                 },
 518         },
 519         .class          = &dm81xx_usbotg_class,
 520 };
 521
 522 static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
 523         .master         = &dm816x_default_l3_slow_hwmod,
 524         .slave          = &dm81xx_usbss_hwmod,
 525         .clk            = "sysclk6_ck",
 526         .user           = OCP_USER_MPU,
 527 };
 528
 529 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
 530         .rev_offs       = 0x0000,
 531         .sysc_offs      = 0x0010,
 532         .syss_offs      = 0x0014,
 533         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 534         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 535                                 SIDLE_SMART_WKUP,
 536         .sysc_fields    = &omap_hwmod_sysc_type2,
 537 };
 538
 539 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
 540         .name = "timer",
 541         .sysc = &dm816x_timer_sysc,
 542 };
 543
 544 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 545         .timer_capability       = OMAP_TIMER_ALWON,
 546 };
 547
 548 static struct omap_hwmod dm816x_timer1_hwmod = {
 549         .name           = "timer1",
 550         .clkdm_name     = "alwon_l3s_clkdm",
 551         .main_clk       = "timer1_fck",
 552         .prcm           = {
 553                 .omap4 = {
 554                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
 555                         .modulemode = MODULEMODE_SWCTRL,
 556                 },
 557         },
 558         .dev_attr       = &capability_alwon_dev_attr,
 559         .class          = &dm816x_timer_hwmod_class,
 560 };
 561
 562 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 563         .master         = &dm816x_l4_ls_hwmod,
 564         .slave          = &dm816x_timer1_hwmod,
 565         .clk            = "sysclk6_ck",
 566         .user           = OCP_USER_MPU,
 567 };
 568
 569 static struct omap_hwmod dm816x_timer2_hwmod = {
 570         .name           = "timer2",
 571         .clkdm_name     = "alwon_l3s_clkdm",
 572         .main_clk       = "timer2_fck",
 573         .prcm           = {
 574                 .omap4 = {
 575                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
 576                         .modulemode = MODULEMODE_SWCTRL,
 577                 },
 578         },
 579         .dev_attr       = &capability_alwon_dev_attr,
 580         .class          = &dm816x_timer_hwmod_class,
 581 };
 582
 583 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
 584         .master         = &dm816x_l4_ls_hwmod,
 585         .slave          = &dm816x_timer2_hwmod,
 586         .clk            = "sysclk6_ck",
 587         .user           = OCP_USER_MPU,
 588 };
 589
 590 static struct omap_hwmod dm816x_timer3_hwmod = {
 591         .name           = "timer3",
 592         .clkdm_name     = "alwon_l3s_clkdm",
 593         .main_clk       = "timer3_fck",
 594         .prcm           = {
 595                 .omap4 = {
 596                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
 597                         .modulemode = MODULEMODE_SWCTRL,
 598                 },
 599         },
 600         .dev_attr       = &capability_alwon_dev_attr,
 601         .class          = &dm816x_timer_hwmod_class,
 602 };
 603
 604 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
 605         .master         = &dm816x_l4_ls_hwmod,
 606         .slave          = &dm816x_timer3_hwmod,
 607         .clk            = "sysclk6_ck",
 608         .user           = OCP_USER_MPU,
 609 };
 610
 611 static struct omap_hwmod dm816x_timer4_hwmod = {
 612         .name           = "timer4",
 613         .clkdm_name     = "alwon_l3s_clkdm",
 614         .main_clk       = "timer4_fck",
 615         .prcm           = {
 616                 .omap4 = {
 617                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
 618                         .modulemode = MODULEMODE_SWCTRL,
 619                 },
 620         },
 621         .dev_attr       = &capability_alwon_dev_attr,
 622         .class          = &dm816x_timer_hwmod_class,
 623 };
 624
 625 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
 626         .master         = &dm816x_l4_ls_hwmod,
 627         .slave          = &dm816x_timer4_hwmod,
 628         .clk            = "sysclk6_ck",
 629         .user           = OCP_USER_MPU,
 630 };
 631
 632 static struct omap_hwmod dm816x_timer5_hwmod = {
 633         .name           = "timer5",
 634         .clkdm_name     = "alwon_l3s_clkdm",
 635         .main_clk       = "timer5_fck",
 636         .prcm           = {
 637                 .omap4 = {
 638                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
 639                         .modulemode = MODULEMODE_SWCTRL,
 640                 },
 641         },
 642         .dev_attr       = &capability_alwon_dev_attr,
 643         .class          = &dm816x_timer_hwmod_class,
 644 };
 645
 646 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
 647         .master         = &dm816x_l4_ls_hwmod,
 648         .slave          = &dm816x_timer5_hwmod,
 649         .clk            = "sysclk6_ck",
 650         .user           = OCP_USER_MPU,
 651 };
 652
 653 static struct omap_hwmod dm816x_timer6_hwmod = {
 654         .name           = "timer6",
 655         .clkdm_name     = "alwon_l3s_clkdm",
 656         .main_clk       = "timer6_fck",
 657         .prcm           = {
 658                 .omap4 = {
 659                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
 660                         .modulemode = MODULEMODE_SWCTRL,
 661                 },
 662         },
 663         .dev_attr       = &capability_alwon_dev_attr,
 664         .class          = &dm816x_timer_hwmod_class,
 665 };
 666
 667 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
 668         .master         = &dm816x_l4_ls_hwmod,
 669         .slave          = &dm816x_timer6_hwmod,
 670         .clk            = "sysclk6_ck",
 671         .user           = OCP_USER_MPU,
 672 };
 673
 674 static struct omap_hwmod dm816x_timer7_hwmod = {
 675         .name           = "timer7",
 676         .clkdm_name     = "alwon_l3s_clkdm",
 677         .main_clk       = "timer7_fck",
 678         .prcm           = {
 679                 .omap4 = {
 680                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
 681                         .modulemode = MODULEMODE_SWCTRL,
 682                 },
 683         },
 684         .dev_attr       = &capability_alwon_dev_attr,
 685         .class          = &dm816x_timer_hwmod_class,
 686 };
 687
 688 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
 689         .master         = &dm816x_l4_ls_hwmod,
 690         .slave          = &dm816x_timer7_hwmod,
 691         .clk            = "sysclk6_ck",
 692         .user           = OCP_USER_MPU,
 693 };
 694
 695 /* EMAC Ethernet */
 696 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
 697         .rev_offs       = 0x0,
 698         .sysc_offs      = 0x4,
 699         .sysc_flags     = SYSC_HAS_SOFTRESET,
 700         .sysc_fields    = &omap_hwmod_sysc_type2,
 701 };
 702
 703 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
 704         .name           = "emac",
 705         .sysc           = &dm816x_emac_sysc,
 706 };
 707
 708 /*
 709  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 710  * driver probed before EMAC0, we let MDIO do the clock idling.
 711  */
 712 static struct omap_hwmod dm816x_emac0_hwmod = {
 713         .name           = "emac0",
 714         .clkdm_name     = "alwon_ethernet_clkdm",
 715         .class          = &dm816x_emac_hwmod_class,
 716 };
 717
 718 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac0 = {
 719         .master         = &dm816x_l4_hs_hwmod,
 720         .slave          = &dm816x_emac0_hwmod,
 721         .clk            = "sysclk5_ck",
 722         .user           = OCP_USER_MPU,
 723 };
 724
 725 static struct omap_hwmod_class dm816x_mdio_hwmod_class = {
 726         .name           = "davinci_mdio",
 727         .sysc           = &dm816x_emac_sysc,
 728 };
 729
 730 struct omap_hwmod dm816x_emac0_mdio_hwmod = {
 731         .name           = "davinci_mdio",
 732         .class          = &dm816x_mdio_hwmod_class,
 733         .clkdm_name     = "alwon_ethernet_clkdm",
 734         .main_clk       = "sysclk24_ck",
 735         .flags          = HWMOD_NO_IDLEST,
 736         /*
 737          * REVISIT: This should be moved to the emac0_hwmod
 738          * once we have a better way to handle device slaves.
 739          */
 740         .prcm           = {
 741                 .omap4 = {
 742                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_0_CLKCTRL,
 743                         .modulemode = MODULEMODE_SWCTRL,
 744                 },
 745         },
 746 };
 747
 748 struct omap_hwmod_ocp_if dm816x_emac0__mdio = {
 749         .master         = &dm816x_l4_hs_hwmod,
 750         .slave          = &dm816x_emac0_mdio_hwmod,
 751         .user           = OCP_USER_MPU,
 752 };
 753
 754 static struct omap_hwmod dm816x_emac1_hwmod = {
 755         .name           = "emac1",
 756         .clkdm_name     = "alwon_ethernet_clkdm",
 757         .main_clk       = "sysclk24_ck",
 758         .flags          = HWMOD_NO_IDLEST,
 759         .prcm           = {
 760                 .omap4 = {
 761                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
 762                         .modulemode = MODULEMODE_SWCTRL,
 763                 },
 764         },
 765         .class          = &dm816x_emac_hwmod_class,
 766 };
 767
 768 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
 769         .master         = &dm816x_l4_hs_hwmod,
 770         .slave          = &dm816x_emac1_hwmod,
 771         .clk            = "sysclk5_ck",
 772         .user           = OCP_USER_MPU,
 773 };
 774
 775 static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
 776         .rev_offs       = 0x0,
 777         .sysc_offs      = 0x110,
 778         .syss_offs      = 0x114,
 779         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 780                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 781                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 782         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 783         .sysc_fields    = &omap_hwmod_sysc_type1,
 784 };
 785
 786 static struct omap_hwmod_class dm816x_mmc_class = {
 787         .name = "mmc",
 788         .sysc = &dm816x_mmc_sysc,
 789 };
 790
 791 static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = {
 792         { .role = "dbck", .clk = "sysclk18_ck", },
 793 };
 794
 795 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
 796         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 797 };
 798
 799 static struct omap_hwmod dm816x_mmc1_hwmod = {
 800         .name           = "mmc1",
 801         .clkdm_name     = "alwon_l3s_clkdm",
 802         .opt_clks       = dm816x_mmc1_opt_clks,
 803         .opt_clks_cnt   = ARRAY_SIZE(dm816x_mmc1_opt_clks),
 804         .main_clk       = "sysclk10_ck",
 805         .prcm           = {
 806                 .omap4 = {
 807                         .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
 808                         .modulemode = MODULEMODE_SWCTRL,
 809                 },
 810         },
 811         .dev_attr       = &mmc1_dev_attr,
 812         .class          = &dm816x_mmc_class,
 813 };
 814
 815 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
 816         .master         = &dm816x_l4_ls_hwmod,
 817         .slave          = &dm816x_mmc1_hwmod,
 818         .clk            = "sysclk6_ck",
 819         .user           = OCP_USER_MPU,
 820         .flags          = OMAP_FIREWALL_L4
 821 };
 822
 823 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
 824         .rev_offs       = 0x0,
 825         .sysc_offs      = 0x110,
 826         .syss_offs      = 0x114,
 827         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 828                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 829                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 830         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 831         .sysc_fields    = &omap_hwmod_sysc_type1,
 832 };
 833
 834 static struct omap_hwmod_class dm816x_mcspi_class = {
 835         .name = "mcspi",
 836         .sysc = &dm816x_mcspi_sysc,
 837         .rev = OMAP3_MCSPI_REV,
 838 };
 839
 840 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
 841         .num_chipselect = 4,
 842 };
 843
 844 static struct omap_hwmod dm816x_mcspi1_hwmod = {
 845         .name           = "mcspi1",
 846         .clkdm_name     = "alwon_l3s_clkdm",
 847         .main_clk       = "sysclk10_ck",
 848         .prcm           = {
 849                 .omap4 = {
 850                         .clkctrl_offs = DM816X_CM_ALWON_SPI_CLKCTRL,
 851                         .modulemode = MODULEMODE_SWCTRL,
 852                 },
 853         },
 854         .class          = &dm816x_mcspi_class,
 855         .dev_attr       = &dm816x_mcspi1_dev_attr,
 856 };
 857
 858 static struct omap_hwmod_ocp_if dm816x_l4_ls__mcspi1 = {
 859         .master         = &dm816x_l4_ls_hwmod,
 860         .slave          = &dm816x_mcspi1_hwmod,
 861         .clk            = "sysclk6_ck",
 862         .user           = OCP_USER_MPU,
 863 };
 864
 865 static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = {
 866         .rev_offs       = 0x000,
 867         .sysc_offs      = 0x010,
 868         .syss_offs      = 0x014,
 869         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 870                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
 871         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 872         .sysc_fields    = &omap_hwmod_sysc_type1,
 873 };
 874
 875 static struct omap_hwmod_class dm816x_mailbox_hwmod_class = {
 876         .name = "mailbox",
 877         .sysc = &dm816x_mailbox_sysc,
 878 };
 879
 880 static struct omap_hwmod dm816x_mailbox_hwmod = {
 881         .name           = "mailbox",
 882         .clkdm_name     = "alwon_l3s_clkdm",
 883         .class          = &dm816x_mailbox_hwmod_class,
 884         .main_clk       = "sysclk6_ck",
 885         .prcm           = {
 886                 .omap4 = {
 887                         .clkctrl_offs = DM816X_CM_ALWON_MAILBOX_CLKCTRL,
 888                         .modulemode = MODULEMODE_SWCTRL,
 889                 },
 890         },
 891 };
 892
 893 static struct omap_hwmod_ocp_if dm816x_l4_ls__mailbox = {
 894         .master         = &dm816x_l4_ls_hwmod,
 895         .slave          = &dm816x_mailbox_hwmod,
 896         .user           = OCP_USER_MPU,
 897 };
 898
 899 static struct omap_hwmod_class dm816x_tpcc_hwmod_class = {
 900         .name           = "tpcc",
 901 };
 902
 903 struct omap_hwmod dm816x_tpcc_hwmod = {
 904         .name           = "tpcc",
 905         .class          = &dm816x_tpcc_hwmod_class,
 906         .clkdm_name     = "alwon_l3s_clkdm",
 907         .main_clk       = "sysclk4_ck",
 908         .prcm           = {
 909                 .omap4  = {
 910                         .clkctrl_offs   = DM816X_CM_ALWON_TPCC_CLKCTRL,
 911                         .modulemode     = MODULEMODE_SWCTRL,
 912                 },
 913         },
 914 };
 915
 916 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tpcc = {
 917         .master         = &dm816x_alwon_l3_fast_hwmod,
 918         .slave          = &dm816x_tpcc_hwmod,
 919         .clk            = "sysclk4_ck",
 920         .user           = OCP_USER_MPU,
 921 };
 922
 923 static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = {
 924         {
 925                 .pa_start       = 0x49800000,
 926                 .pa_end         = 0x49800000 + SZ_8K - 1,
 927                 .flags          = ADDR_TYPE_RT,
 928         },
 929         { },
 930 };
 931
 932 static struct omap_hwmod_class dm816x_tptc0_hwmod_class = {
 933         .name           = "tptc0",
 934 };
 935
 936 struct omap_hwmod dm816x_tptc0_hwmod = {
 937         .name           = "tptc0",
 938         .class          = &dm816x_tptc0_hwmod_class,
 939         .clkdm_name     = "alwon_l3s_clkdm",
 940         .main_clk       = "sysclk4_ck",
 941         .prcm           = {
 942                 .omap4  = {
 943                         .clkctrl_offs   = DM816X_CM_ALWON_TPTC0_CLKCTRL,
 944                         .modulemode     = MODULEMODE_SWCTRL,
 945                 },
 946         },
 947 };
 948
 949 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc0 = {
 950         .master         = &dm816x_alwon_l3_fast_hwmod,
 951         .slave          = &dm816x_tptc0_hwmod,
 952         .clk            = "sysclk4_ck",
 953         .addr           = dm816x_tptc0_addr_space,
 954         .user           = OCP_USER_MPU,
 955 };
 956
 957 struct omap_hwmod_ocp_if dm816x_tptc0__alwon_l3_fast = {
 958         .master         = &dm816x_tptc0_hwmod,
 959         .slave          = &dm816x_alwon_l3_fast_hwmod,
 960         .clk            = "sysclk4_ck",
 961         .addr           = dm816x_tptc0_addr_space,
 962         .user           = OCP_USER_MPU,
 963 };
 964
 965 static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = {
 966         {
 967                 .pa_start       = 0x49900000,
 968                 .pa_end         = 0x49900000 + SZ_8K - 1,
 969                 .flags          = ADDR_TYPE_RT,
 970         },
 971         { },
 972 };
 973
 974 static struct omap_hwmod_class dm816x_tptc1_hwmod_class = {
 975         .name           = "tptc1",
 976 };
 977
 978 struct omap_hwmod dm816x_tptc1_hwmod = {
 979         .name           = "tptc1",
 980         .class          = &dm816x_tptc1_hwmod_class,
 981         .clkdm_name     = "alwon_l3s_clkdm",
 982         .main_clk       = "sysclk4_ck",
 983         .prcm           = {
 984                 .omap4  = {
 985                         .clkctrl_offs   = DM816X_CM_ALWON_TPTC1_CLKCTRL,
 986                         .modulemode     = MODULEMODE_SWCTRL,
 987                 },
 988         },
 989 };
 990
 991 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc1 = {
 992         .master         = &dm816x_alwon_l3_fast_hwmod,
 993         .slave          = &dm816x_tptc1_hwmod,
 994         .clk            = "sysclk4_ck",
 995         .addr           = dm816x_tptc1_addr_space,
 996         .user           = OCP_USER_MPU,
 997 };
 998
 999 struct omap_hwmod_ocp_if dm816x_tptc1__alwon_l3_fast = {
1000         .master         = &dm816x_tptc1_hwmod,
1001         .slave          = &dm816x_alwon_l3_fast_hwmod,
1002         .clk            = "sysclk4_ck",
1003         .addr           = dm816x_tptc1_addr_space,
1004         .user           = OCP_USER_MPU,
1005 };
1006
1007 static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = {
1008         {
1009                 .pa_start       = 0x49a00000,
1010                 .pa_end         = 0x49a00000 + SZ_8K - 1,
1011                 .flags          = ADDR_TYPE_RT,
1012         },
1013         { },
1014 };
1015
1016 static struct omap_hwmod_class dm816x_tptc2_hwmod_class = {
1017         .name           = "tptc2",
1018 };
1019
1020 struct omap_hwmod dm816x_tptc2_hwmod = {
1021         .name           = "tptc2",
1022         .class          = &dm816x_tptc2_hwmod_class,
1023         .clkdm_name     = "alwon_l3s_clkdm",
1024         .main_clk       = "sysclk4_ck",
1025         .prcm           = {
1026                 .omap4  = {
1027                         .clkctrl_offs   = DM816X_CM_ALWON_TPTC2_CLKCTRL,
1028                         .modulemode     = MODULEMODE_SWCTRL,
1029                 },
1030         },
1031 };
1032
1033 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc2 = {
1034         .master         = &dm816x_alwon_l3_fast_hwmod,
1035         .slave          = &dm816x_tptc2_hwmod,
1036         .clk            = "sysclk4_ck",
1037         .addr           = dm816x_tptc2_addr_space,
1038         .user           = OCP_USER_MPU,
1039 };
1040
1041 struct omap_hwmod_ocp_if dm816x_tptc2__alwon_l3_fast = {
1042         .master         = &dm816x_tptc2_hwmod,
1043         .slave          = &dm816x_alwon_l3_fast_hwmod,
1044         .clk            = "sysclk4_ck",
1045         .addr           = dm816x_tptc2_addr_space,
1046         .user           = OCP_USER_MPU,
1047 };
1048
1049 static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = {
1050         {
1051                 .pa_start       = 0x49b00000,
1052                 .pa_end         = 0x49b00000 + SZ_8K - 1,
1053                 .flags          = ADDR_TYPE_RT,
1054         },
1055         { },
1056 };
1057
1058 static struct omap_hwmod_class dm816x_tptc3_hwmod_class = {
1059         .name           = "tptc3",
1060 };
1061
1062 struct omap_hwmod dm816x_tptc3_hwmod = {
1063         .name           = "tptc3",
1064         .class          = &dm816x_tptc3_hwmod_class,
1065         .clkdm_name     = "alwon_l3s_clkdm",
1066         .main_clk       = "sysclk4_ck",
1067         .prcm           = {
1068                 .omap4  = {
1069                         .clkctrl_offs   = DM816X_CM_ALWON_TPTC3_CLKCTRL,
1070                         .modulemode     = MODULEMODE_SWCTRL,
1071                 },
1072         },
1073 };
1074
1075 struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc3 = {
1076         .master         = &dm816x_alwon_l3_fast_hwmod,
1077         .slave          = &dm816x_tptc3_hwmod,
1078         .clk            = "sysclk4_ck",
1079         .addr           = dm816x_tptc3_addr_space,
1080         .user           = OCP_USER_MPU,
1081 };
1082
1083 struct omap_hwmod_ocp_if dm816x_tptc3__alwon_l3_fast = {
1084         .master         = &dm816x_tptc3_hwmod,
1085         .slave          = &dm816x_alwon_l3_fast_hwmod,
1086         .clk            = "sysclk4_ck",
1087         .addr           = dm816x_tptc3_addr_space,
1088         .user           = OCP_USER_MPU,
1089 };
1090
1091 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1092         &dm816x_mpu__alwon_l3_slow,
1093         &dm816x_mpu__alwon_l3_med,
1094         &dm816x_alwon_l3_slow__l4_ls,
1095         &dm816x_alwon_l3_slow__l4_hs,
1096         &dm816x_l4_ls__uart1,
1097         &dm816x_l4_ls__uart2,
1098         &dm816x_l4_ls__uart3,
1099         &dm816x_l4_ls__wd_timer1,
1100         &dm816x_l4_ls__i2c1,
1101         &dm816x_l4_ls__i2c2,
1102         &dm81xx_l4_ls__gpio1,
1103         &dm81xx_l4_ls__gpio2,
1104         &dm81xx_l4_ls__elm,
1105         &dm816x_l4_ls__mmc1,
1106         &dm816x_l4_ls__timer1,
1107         &dm816x_l4_ls__timer2,
1108         &dm816x_l4_ls__timer3,
1109         &dm816x_l4_ls__timer4,
1110         &dm816x_l4_ls__timer5,
1111         &dm816x_l4_ls__timer6,
1112         &dm816x_l4_ls__timer7,
1113         &dm816x_l4_ls__mcspi1,
1114         &dm816x_l4_ls__mailbox,
1115         &dm816x_l4_hs__emac0,
1116         &dm816x_emac0__mdio,
1117         &dm816x_l4_hs__emac1,
1118         &dm816x_alwon_l3_fast__tpcc,
1119         &dm816x_alwon_l3_fast__tptc0,
1120         &dm816x_alwon_l3_fast__tptc1,
1121         &dm816x_alwon_l3_fast__tptc2,
1122         &dm816x_alwon_l3_fast__tptc3,
1123         &dm816x_tptc0__alwon_l3_fast,
1124         &dm816x_tptc1__alwon_l3_fast,
1125         &dm816x_tptc2__alwon_l3_fast,
1126         &dm816x_tptc3__alwon_l3_fast,
1127         &dm81xx_alwon_l3_slow__gpmc,
1128         &dm81xx_default_l3_slow__usbss,
1129         NULL,
1130 };
1131
1132 int __init ti81xx_hwmod_init(void)
1133 {
1134         omap_hwmod_init();
1135         return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1136 }