arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/i2c.h>
  32
  33 #include "omap_hwmod_common_data.h"
  34
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /* Backward references (IPs with Bus Master capability) */
  48 static struct omap_hwmod omap44xx_aess_hwmod;
  49 static struct omap_hwmod omap44xx_dma_system_hwmod;
  50 static struct omap_hwmod omap44xx_dmm_hwmod;
  51 static struct omap_hwmod omap44xx_dsp_hwmod;
  52 static struct omap_hwmod omap44xx_dss_hwmod;
  53 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  54 static struct omap_hwmod omap44xx_hsi_hwmod;
  55 static struct omap_hwmod omap44xx_ipu_hwmod;
  56 static struct omap_hwmod omap44xx_iss_hwmod;
  57 static struct omap_hwmod omap44xx_iva_hwmod;
  58 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  60 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  62 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  63 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  64 static struct omap_hwmod omap44xx_l4_per_hwmod;
  65 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  66 static struct omap_hwmod omap44xx_mmc1_hwmod;
  67 static struct omap_hwmod omap44xx_mmc2_hwmod;
  68 static struct omap_hwmod omap44xx_mpu_hwmod;
  69 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  70 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  71
  72 /*
  73  * Interconnects omap_hwmod structures
  74  * hwmods that compose the global OMAP interconnect
  75  */
  76
  77 /*
  78  * 'dmm' class
  79  * instance(s): dmm
  80  */
  81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  82         .name   = "dmm",
  83 };
  84
  85 /* dmm */
  86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  88         { .irq = -1 }
  89 };
  90
  91 /* l3_main_1 -> dmm */
  92 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  93         .master         = &omap44xx_l3_main_1_hwmod,
  94         .slave          = &omap44xx_dmm_hwmod,
  95         .clk            = "l3_div_ck",
  96         .user           = OCP_USER_SDMA,
  97 };
  98
  99 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 100         {
 101                 .pa_start       = 0x4e000000,
 102                 .pa_end         = 0x4e0007ff,
 103                 .flags          = ADDR_TYPE_RT
 104         },
 105         { }
 106 };
 107
 108 /* mpu -> dmm */
 109 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 110         .master         = &omap44xx_mpu_hwmod,
 111         .slave          = &omap44xx_dmm_hwmod,
 112         .clk            = "l3_div_ck",
 113         .addr           = omap44xx_dmm_addrs,
 114         .user           = OCP_USER_MPU,
 115 };
 116
 117 /* dmm slave ports */
 118 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 119         &omap44xx_l3_main_1__dmm,
 120         &omap44xx_mpu__dmm,
 121 };
 122
 123 static struct omap_hwmod omap44xx_dmm_hwmod = {
 124         .name           = "dmm",
 125         .class          = &omap44xx_dmm_hwmod_class,
 126         .clkdm_name     = "l3_emif_clkdm",
 127         .prcm = {
 128                 .omap4 = {
 129                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 130                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 131                 },
 132         },
 133         .slaves         = omap44xx_dmm_slaves,
 134         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 135         .mpu_irqs       = omap44xx_dmm_irqs,
 136         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 137 };
 138
 139 /*
 140  * 'emif_fw' class
 141  * instance(s): emif_fw
 142  */
 143 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 144         .name   = "emif_fw",
 145 };
 146
 147 /* emif_fw */
 148 /* dmm -> emif_fw */
 149 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 150         .master         = &omap44xx_dmm_hwmod,
 151         .slave          = &omap44xx_emif_fw_hwmod,
 152         .clk            = "l3_div_ck",
 153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 154 };
 155
 156 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 157         {
 158                 .pa_start       = 0x4a20c000,
 159                 .pa_end         = 0x4a20c0ff,
 160                 .flags          = ADDR_TYPE_RT
 161         },
 162         { }
 163 };
 164
 165 /* l4_cfg -> emif_fw */
 166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 167         .master         = &omap44xx_l4_cfg_hwmod,
 168         .slave          = &omap44xx_emif_fw_hwmod,
 169         .clk            = "l4_div_ck",
 170         .addr           = omap44xx_emif_fw_addrs,
 171         .user           = OCP_USER_MPU,
 172 };
 173
 174 /* emif_fw slave ports */
 175 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 176         &omap44xx_dmm__emif_fw,
 177         &omap44xx_l4_cfg__emif_fw,
 178 };
 179
 180 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 181         .name           = "emif_fw",
 182         .class          = &omap44xx_emif_fw_hwmod_class,
 183         .clkdm_name     = "l3_emif_clkdm",
 184         .prcm = {
 185                 .omap4 = {
 186                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 187                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 188                 },
 189         },
 190         .slaves         = omap44xx_emif_fw_slaves,
 191         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 193 };
 194
 195 /*
 196  * 'l3' class
 197  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 198  */
 199 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 200         .name   = "l3",
 201 };
 202
 203 /* l3_instr */
 204 /* iva -> l3_instr */
 205 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 206         .master         = &omap44xx_iva_hwmod,
 207         .slave          = &omap44xx_l3_instr_hwmod,
 208         .clk            = "l3_div_ck",
 209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 210 };
 211
 212 /* l3_main_3 -> l3_instr */
 213 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 214         .master         = &omap44xx_l3_main_3_hwmod,
 215         .slave          = &omap44xx_l3_instr_hwmod,
 216         .clk            = "l3_div_ck",
 217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 218 };
 219
 220 /* l3_instr slave ports */
 221 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 222         &omap44xx_iva__l3_instr,
 223         &omap44xx_l3_main_3__l3_instr,
 224 };
 225
 226 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 227         .name           = "l3_instr",
 228         .class          = &omap44xx_l3_hwmod_class,
 229         .clkdm_name     = "l3_instr_clkdm",
 230         .prcm = {
 231                 .omap4 = {
 232                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 233                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 234                         .modulemode   = MODULEMODE_HWCTRL,
 235                 },
 236         },
 237         .slaves         = omap44xx_l3_instr_slaves,
 238         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 240 };
 241
 242 /* l3_main_1 */
 243 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 244         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 245         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 246         { .irq = -1 }
 247 };
 248
 249 /* dsp -> l3_main_1 */
 250 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 251         .master         = &omap44xx_dsp_hwmod,
 252         .slave          = &omap44xx_l3_main_1_hwmod,
 253         .clk            = "l3_div_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 /* dss -> l3_main_1 */
 258 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 259         .master         = &omap44xx_dss_hwmod,
 260         .slave          = &omap44xx_l3_main_1_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* l3_main_2 -> l3_main_1 */
 266 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 267         .master         = &omap44xx_l3_main_2_hwmod,
 268         .slave          = &omap44xx_l3_main_1_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* l4_cfg -> l3_main_1 */
 274 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 275         .master         = &omap44xx_l4_cfg_hwmod,
 276         .slave          = &omap44xx_l3_main_1_hwmod,
 277         .clk            = "l4_div_ck",
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* mmc1 -> l3_main_1 */
 282 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 283         .master         = &omap44xx_mmc1_hwmod,
 284         .slave          = &omap44xx_l3_main_1_hwmod,
 285         .clk            = "l3_div_ck",
 286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 287 };
 288
 289 /* mmc2 -> l3_main_1 */
 290 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 291         .master         = &omap44xx_mmc2_hwmod,
 292         .slave          = &omap44xx_l3_main_1_hwmod,
 293         .clk            = "l3_div_ck",
 294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 295 };
 296
 297 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 298         {
 299                 .pa_start       = 0x44000000,
 300                 .pa_end         = 0x44000fff,
 301                 .flags          = ADDR_TYPE_RT
 302         },
 303         { }
 304 };
 305
 306 /* mpu -> l3_main_1 */
 307 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 308         .master         = &omap44xx_mpu_hwmod,
 309         .slave          = &omap44xx_l3_main_1_hwmod,
 310         .clk            = "l3_div_ck",
 311         .addr           = omap44xx_l3_main_1_addrs,
 312         .user           = OCP_USER_MPU,
 313 };
 314
 315 /* l3_main_1 slave ports */
 316 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 317         &omap44xx_dsp__l3_main_1,
 318         &omap44xx_dss__l3_main_1,
 319         &omap44xx_l3_main_2__l3_main_1,
 320         &omap44xx_l4_cfg__l3_main_1,
 321         &omap44xx_mmc1__l3_main_1,
 322         &omap44xx_mmc2__l3_main_1,
 323         &omap44xx_mpu__l3_main_1,
 324 };
 325
 326 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 327         .name           = "l3_main_1",
 328         .class          = &omap44xx_l3_hwmod_class,
 329         .clkdm_name     = "l3_1_clkdm",
 330         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 331         .prcm = {
 332                 .omap4 = {
 333                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 334                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 335                 },
 336         },
 337         .slaves         = omap44xx_l3_main_1_slaves,
 338         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 340 };
 341
 342 /* l3_main_2 */
 343 /* dma_system -> l3_main_2 */
 344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 345         .master         = &omap44xx_dma_system_hwmod,
 346         .slave          = &omap44xx_l3_main_2_hwmod,
 347         .clk            = "l3_div_ck",
 348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 349 };
 350
 351 /* hsi -> l3_main_2 */
 352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 353         .master         = &omap44xx_hsi_hwmod,
 354         .slave          = &omap44xx_l3_main_2_hwmod,
 355         .clk            = "l3_div_ck",
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* ipu -> l3_main_2 */
 360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 361         .master         = &omap44xx_ipu_hwmod,
 362         .slave          = &omap44xx_l3_main_2_hwmod,
 363         .clk            = "l3_div_ck",
 364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 365 };
 366
 367 /* iss -> l3_main_2 */
 368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 369         .master         = &omap44xx_iss_hwmod,
 370         .slave          = &omap44xx_l3_main_2_hwmod,
 371         .clk            = "l3_div_ck",
 372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 373 };
 374
 375 /* iva -> l3_main_2 */
 376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 377         .master         = &omap44xx_iva_hwmod,
 378         .slave          = &omap44xx_l3_main_2_hwmod,
 379         .clk            = "l3_div_ck",
 380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 381 };
 382
 383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 384         {
 385                 .pa_start       = 0x44800000,
 386                 .pa_end         = 0x44801fff,
 387                 .flags          = ADDR_TYPE_RT
 388         },
 389         { }
 390 };
 391
 392 /* l3_main_1 -> l3_main_2 */
 393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 394         .master         = &omap44xx_l3_main_1_hwmod,
 395         .slave          = &omap44xx_l3_main_2_hwmod,
 396         .clk            = "l3_div_ck",
 397         .addr           = omap44xx_l3_main_2_addrs,
 398         .user           = OCP_USER_MPU,
 399 };
 400
 401 /* l4_cfg -> l3_main_2 */
 402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 403         .master         = &omap44xx_l4_cfg_hwmod,
 404         .slave          = &omap44xx_l3_main_2_hwmod,
 405         .clk            = "l4_div_ck",
 406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 407 };
 408
 409 /* usb_otg_hs -> l3_main_2 */
 410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 411         .master         = &omap44xx_usb_otg_hs_hwmod,
 412         .slave          = &omap44xx_l3_main_2_hwmod,
 413         .clk            = "l3_div_ck",
 414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 415 };
 416
 417 /* l3_main_2 slave ports */
 418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 419         &omap44xx_dma_system__l3_main_2,
 420         &omap44xx_hsi__l3_main_2,
 421         &omap44xx_ipu__l3_main_2,
 422         &omap44xx_iss__l3_main_2,
 423         &omap44xx_iva__l3_main_2,
 424         &omap44xx_l3_main_1__l3_main_2,
 425         &omap44xx_l4_cfg__l3_main_2,
 426         &omap44xx_usb_otg_hs__l3_main_2,
 427 };
 428
 429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 430         .name           = "l3_main_2",
 431         .class          = &omap44xx_l3_hwmod_class,
 432         .clkdm_name     = "l3_2_clkdm",
 433         .prcm = {
 434                 .omap4 = {
 435                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 436                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 437                 },
 438         },
 439         .slaves         = omap44xx_l3_main_2_slaves,
 440         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 441         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 442 };
 443
 444 /* l3_main_3 */
 445 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 446         {
 447                 .pa_start       = 0x45000000,
 448                 .pa_end         = 0x45000fff,
 449                 .flags          = ADDR_TYPE_RT
 450         },
 451         { }
 452 };
 453
 454 /* l3_main_1 -> l3_main_3 */
 455 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 456         .master         = &omap44xx_l3_main_1_hwmod,
 457         .slave          = &omap44xx_l3_main_3_hwmod,
 458         .clk            = "l3_div_ck",
 459         .addr           = omap44xx_l3_main_3_addrs,
 460         .user           = OCP_USER_MPU,
 461 };
 462
 463 /* l3_main_2 -> l3_main_3 */
 464 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 465         .master         = &omap44xx_l3_main_2_hwmod,
 466         .slave          = &omap44xx_l3_main_3_hwmod,
 467         .clk            = "l3_div_ck",
 468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 469 };
 470
 471 /* l4_cfg -> l3_main_3 */
 472 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 473         .master         = &omap44xx_l4_cfg_hwmod,
 474         .slave          = &omap44xx_l3_main_3_hwmod,
 475         .clk            = "l4_div_ck",
 476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 477 };
 478
 479 /* l3_main_3 slave ports */
 480 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 481         &omap44xx_l3_main_1__l3_main_3,
 482         &omap44xx_l3_main_2__l3_main_3,
 483         &omap44xx_l4_cfg__l3_main_3,
 484 };
 485
 486 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 487         .name           = "l3_main_3",
 488         .class          = &omap44xx_l3_hwmod_class,
 489         .clkdm_name     = "l3_instr_clkdm",
 490         .prcm = {
 491                 .omap4 = {
 492                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 493                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 494                         .modulemode   = MODULEMODE_HWCTRL,
 495                 },
 496         },
 497         .slaves         = omap44xx_l3_main_3_slaves,
 498         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 499         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 500 };
 501
 502 /*
 503  * 'l4' class
 504  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 505  */
 506 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 507         .name   = "l4",
 508 };
 509
 510 /* l4_abe */
 511 /* aess -> l4_abe */
 512 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 513         .master         = &omap44xx_aess_hwmod,
 514         .slave          = &omap44xx_l4_abe_hwmod,
 515         .clk            = "ocp_abe_iclk",
 516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 517 };
 518
 519 /* dsp -> l4_abe */
 520 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 521         .master         = &omap44xx_dsp_hwmod,
 522         .slave          = &omap44xx_l4_abe_hwmod,
 523         .clk            = "ocp_abe_iclk",
 524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 525 };
 526
 527 /* l3_main_1 -> l4_abe */
 528 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 529         .master         = &omap44xx_l3_main_1_hwmod,
 530         .slave          = &omap44xx_l4_abe_hwmod,
 531         .clk            = "l3_div_ck",
 532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 533 };
 534
 535 /* mpu -> l4_abe */
 536 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 537         .master         = &omap44xx_mpu_hwmod,
 538         .slave          = &omap44xx_l4_abe_hwmod,
 539         .clk            = "ocp_abe_iclk",
 540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 541 };
 542
 543 /* l4_abe slave ports */
 544 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 545         &omap44xx_aess__l4_abe,
 546         &omap44xx_dsp__l4_abe,
 547         &omap44xx_l3_main_1__l4_abe,
 548         &omap44xx_mpu__l4_abe,
 549 };
 550
 551 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 552         .name           = "l4_abe",
 553         .class          = &omap44xx_l4_hwmod_class,
 554         .clkdm_name     = "abe_clkdm",
 555         .prcm = {
 556                 .omap4 = {
 557                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 558                 },
 559         },
 560         .slaves         = omap44xx_l4_abe_slaves,
 561         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 562         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 563 };
 564
 565 /* l4_cfg */
 566 /* l3_main_1 -> l4_cfg */
 567 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 568         .master         = &omap44xx_l3_main_1_hwmod,
 569         .slave          = &omap44xx_l4_cfg_hwmod,
 570         .clk            = "l3_div_ck",
 571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 572 };
 573
 574 /* l4_cfg slave ports */
 575 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 576         &omap44xx_l3_main_1__l4_cfg,
 577 };
 578
 579 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 580         .name           = "l4_cfg",
 581         .class          = &omap44xx_l4_hwmod_class,
 582         .clkdm_name     = "l4_cfg_clkdm",
 583         .prcm = {
 584                 .omap4 = {
 585                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 586                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 587                 },
 588         },
 589         .slaves         = omap44xx_l4_cfg_slaves,
 590         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 591         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 592 };
 593
 594 /* l4_per */
 595 /* l3_main_2 -> l4_per */
 596 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 597         .master         = &omap44xx_l3_main_2_hwmod,
 598         .slave          = &omap44xx_l4_per_hwmod,
 599         .clk            = "l3_div_ck",
 600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 601 };
 602
 603 /* l4_per slave ports */
 604 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 605         &omap44xx_l3_main_2__l4_per,
 606 };
 607
 608 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 609         .name           = "l4_per",
 610         .class          = &omap44xx_l4_hwmod_class,
 611         .clkdm_name     = "l4_per_clkdm",
 612         .prcm = {
 613                 .omap4 = {
 614                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 615                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 616                 },
 617         },
 618         .slaves         = omap44xx_l4_per_slaves,
 619         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 620         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 621 };
 622
 623 /* l4_wkup */
 624 /* l4_cfg -> l4_wkup */
 625 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 626         .master         = &omap44xx_l4_cfg_hwmod,
 627         .slave          = &omap44xx_l4_wkup_hwmod,
 628         .clk            = "l4_div_ck",
 629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 630 };
 631
 632 /* l4_wkup slave ports */
 633 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 634         &omap44xx_l4_cfg__l4_wkup,
 635 };
 636
 637 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 638         .name           = "l4_wkup",
 639         .class          = &omap44xx_l4_hwmod_class,
 640         .clkdm_name     = "l4_wkup_clkdm",
 641         .prcm = {
 642                 .omap4 = {
 643                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 644                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 645                 },
 646         },
 647         .slaves         = omap44xx_l4_wkup_slaves,
 648         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 649         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 650 };
 651
 652 /*
 653  * 'mpu_bus' class
 654  * instance(s): mpu_private
 655  */
 656 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 657         .name   = "mpu_bus",
 658 };
 659
 660 /* mpu_private */
 661 /* mpu -> mpu_private */
 662 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 663         .master         = &omap44xx_mpu_hwmod,
 664         .slave          = &omap44xx_mpu_private_hwmod,
 665         .clk            = "l3_div_ck",
 666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 667 };
 668
 669 /* mpu_private slave ports */
 670 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 671         &omap44xx_mpu__mpu_private,
 672 };
 673
 674 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 675         .name           = "mpu_private",
 676         .class          = &omap44xx_mpu_bus_hwmod_class,
 677         .clkdm_name     = "mpuss_clkdm",
 678         .slaves         = omap44xx_mpu_private_slaves,
 679         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 680         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 681 };
 682
 683 /*
 684  * Modules omap_hwmod structures
 685  *
 686  * The following IPs are excluded for the moment because:
 687  * - They do not need an explicit SW control using omap_hwmod API.
 688  * - They still need to be validated with the driver
 689  *   properly adapted to omap_hwmod / omap_device
 690  *
 691  *  c2c
 692  *  c2c_target_fw
 693  *  cm_core
 694  *  cm_core_aon
 695  *  ctrl_module_core
 696  *  ctrl_module_pad_core
 697  *  ctrl_module_pad_wkup
 698  *  ctrl_module_wkup
 699  *  debugss
 700  *  efuse_ctrl_cust
 701  *  efuse_ctrl_std
 702  *  elm
 703  *  emif1
 704  *  emif2
 705  *  fdif
 706  *  gpmc
 707  *  gpu
 708  *  hdq1w
 709  *  mcasp
 710  *  mpu_c0
 711  *  mpu_c1
 712  *  ocmc_ram
 713  *  ocp2scp_usb_phy
 714  *  ocp_wp_noc
 715  *  prcm_mpu
 716  *  prm
 717  *  scrm
 718  *  sl2if
 719  *  slimbus1
 720  *  slimbus2
 721  *  usb_host_fs
 722  *  usb_host_hs
 723  *  usb_phy_cm
 724  *  usb_tll_hs
 725  *  usim
 726  */
 727
 728 /*
 729  * 'aess' class
 730  * audio engine sub system
 731  */
 732
 733 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 734         .rev_offs       = 0x0000,
 735         .sysc_offs      = 0x0010,
 736         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 737         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 738                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 739                            MSTANDBY_SMART_WKUP),
 740         .sysc_fields    = &omap_hwmod_sysc_type2,
 741 };
 742
 743 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 744         .name   = "aess",
 745         .sysc   = &omap44xx_aess_sysc,
 746 };
 747
 748 /* aess */
 749 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 750         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 751         { .irq = -1 }
 752 };
 753
 754 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 755         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 756         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 757         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 758         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 759         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 760         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 761         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 762         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 763         { .dma_req = -1 }
 764 };
 765
 766 /* aess master ports */
 767 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 768         &omap44xx_aess__l4_abe,
 769 };
 770
 771 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 772         {
 773                 .pa_start       = 0x401f1000,
 774                 .pa_end         = 0x401f13ff,
 775                 .flags          = ADDR_TYPE_RT
 776         },
 777         { }
 778 };
 779
 780 /* l4_abe -> aess */
 781 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 782         .master         = &omap44xx_l4_abe_hwmod,
 783         .slave          = &omap44xx_aess_hwmod,
 784         .clk            = "ocp_abe_iclk",
 785         .addr           = omap44xx_aess_addrs,
 786         .user           = OCP_USER_MPU,
 787 };
 788
 789 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 790         {
 791                 .pa_start       = 0x490f1000,
 792                 .pa_end         = 0x490f13ff,
 793                 .flags          = ADDR_TYPE_RT
 794         },
 795         { }
 796 };
 797
 798 /* l4_abe -> aess (dma) */
 799 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 800         .master         = &omap44xx_l4_abe_hwmod,
 801         .slave          = &omap44xx_aess_hwmod,
 802         .clk            = "ocp_abe_iclk",
 803         .addr           = omap44xx_aess_dma_addrs,
 804         .user           = OCP_USER_SDMA,
 805 };
 806
 807 /* aess slave ports */
 808 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 809         &omap44xx_l4_abe__aess,
 810         &omap44xx_l4_abe__aess_dma,
 811 };
 812
 813 static struct omap_hwmod omap44xx_aess_hwmod = {
 814         .name           = "aess",
 815         .class          = &omap44xx_aess_hwmod_class,
 816         .clkdm_name     = "abe_clkdm",
 817         .mpu_irqs       = omap44xx_aess_irqs,
 818         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 819         .main_clk       = "aess_fck",
 820         .prcm = {
 821                 .omap4 = {
 822                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 823                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 824                         .modulemode   = MODULEMODE_SWCTRL,
 825                 },
 826         },
 827         .slaves         = omap44xx_aess_slaves,
 828         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 829         .masters        = omap44xx_aess_masters,
 830         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 831         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 832 };
 833
 834 /*
 835  * 'bandgap' class
 836  * bangap reference for ldo regulators
 837  */
 838
 839 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 840         .name   = "bandgap",
 841 };
 842
 843 /* bandgap */
 844 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 845         { .role = "fclk", .clk = "bandgap_fclk" },
 846 };
 847
 848 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 849         .name           = "bandgap",
 850         .class          = &omap44xx_bandgap_hwmod_class,
 851         .clkdm_name     = "l4_wkup_clkdm",
 852         .prcm = {
 853                 .omap4 = {
 854                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 855                 },
 856         },
 857         .opt_clks       = bandgap_opt_clks,
 858         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 860 };
 861
 862 /*
 863  * 'counter' class
 864  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 865  */
 866
 867 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 868         .rev_offs       = 0x0000,
 869         .sysc_offs      = 0x0004,
 870         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 872                            SIDLE_SMART_WKUP),
 873         .sysc_fields    = &omap_hwmod_sysc_type1,
 874 };
 875
 876 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 877         .name   = "counter",
 878         .sysc   = &omap44xx_counter_sysc,
 879 };
 880
 881 /* counter_32k */
 882 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 883 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 884         {
 885                 .pa_start       = 0x4a304000,
 886                 .pa_end         = 0x4a30401f,
 887                 .flags          = ADDR_TYPE_RT
 888         },
 889         { }
 890 };
 891
 892 /* l4_wkup -> counter_32k */
 893 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 894         .master         = &omap44xx_l4_wkup_hwmod,
 895         .slave          = &omap44xx_counter_32k_hwmod,
 896         .clk            = "l4_wkup_clk_mux_ck",
 897         .addr           = omap44xx_counter_32k_addrs,
 898         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 899 };
 900
 901 /* counter_32k slave ports */
 902 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 903         &omap44xx_l4_wkup__counter_32k,
 904 };
 905
 906 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 907         .name           = "counter_32k",
 908         .class          = &omap44xx_counter_hwmod_class,
 909         .clkdm_name     = "l4_wkup_clkdm",
 910         .flags          = HWMOD_SWSUP_SIDLE,
 911         .main_clk       = "sys_32k_ck",
 912         .prcm = {
 913                 .omap4 = {
 914                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 915                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 916                 },
 917         },
 918         .slaves         = omap44xx_counter_32k_slaves,
 919         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 920         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 921 };
 922
 923 /*
 924  * 'dma' class
 925  * dma controller for data exchange between memory to memory (i.e. internal or
 926  * external memory) and gp peripherals to memory or memory to gp peripherals
 927  */
 928
 929 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 930         .rev_offs       = 0x0000,
 931         .sysc_offs      = 0x002c,
 932         .syss_offs      = 0x0028,
 933         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 934                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 935                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 936                            SYSS_HAS_RESET_STATUS),
 937         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 938                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 939         .sysc_fields    = &omap_hwmod_sysc_type1,
 940 };
 941
 942 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 943         .name   = "dma",
 944         .sysc   = &omap44xx_dma_sysc,
 945 };
 946
 947 /* dma dev_attr */
 948 static struct omap_dma_dev_attr dma_dev_attr = {
 949         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 950                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 951         .lch_count      = 32,
 952 };
 953
 954 /* dma_system */
 955 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 956         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 957         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 958         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 959         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 960         { .irq = -1 }
 961 };
 962
 963 /* dma_system master ports */
 964 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 965         &omap44xx_dma_system__l3_main_2,
 966 };
 967
 968 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 969         {
 970                 .pa_start       = 0x4a056000,
 971                 .pa_end         = 0x4a056fff,
 972                 .flags          = ADDR_TYPE_RT
 973         },
 974         { }
 975 };
 976
 977 /* l4_cfg -> dma_system */
 978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 979         .master         = &omap44xx_l4_cfg_hwmod,
 980         .slave          = &omap44xx_dma_system_hwmod,
 981         .clk            = "l4_div_ck",
 982         .addr           = omap44xx_dma_system_addrs,
 983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 984 };
 985
 986 /* dma_system slave ports */
 987 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 988         &omap44xx_l4_cfg__dma_system,
 989 };
 990
 991 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 992         .name           = "dma_system",
 993         .class          = &omap44xx_dma_hwmod_class,
 994         .clkdm_name     = "l3_dma_clkdm",
 995         .mpu_irqs       = omap44xx_dma_system_irqs,
 996         .main_clk       = "l3_div_ck",
 997         .prcm = {
 998                 .omap4 = {
 999                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
1000                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
1001                 },
1002         },
1003         .dev_attr       = &dma_dev_attr,
1004         .slaves         = omap44xx_dma_system_slaves,
1005         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1006         .masters        = omap44xx_dma_system_masters,
1007         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1008         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1009 };
1010
1011 /*
1012  * 'dmic' class
1013  * digital microphone controller
1014  */
1015
1016 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1017         .rev_offs       = 0x0000,
1018         .sysc_offs      = 0x0010,
1019         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1020                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1021         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1022                            SIDLE_SMART_WKUP),
1023         .sysc_fields    = &omap_hwmod_sysc_type2,
1024 };
1025
1026 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1027         .name   = "dmic",
1028         .sysc   = &omap44xx_dmic_sysc,
1029 };
1030
1031 /* dmic */
1032 static struct omap_hwmod omap44xx_dmic_hwmod;
1033 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1034         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1035         { .irq = -1 }
1036 };
1037
1038 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1039         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1040         { .dma_req = -1 }
1041 };
1042
1043 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1044         {
1045                 .pa_start       = 0x4012e000,
1046                 .pa_end         = 0x4012e07f,
1047                 .flags          = ADDR_TYPE_RT
1048         },
1049         { }
1050 };
1051
1052 /* l4_abe -> dmic */
1053 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1054         .master         = &omap44xx_l4_abe_hwmod,
1055         .slave          = &omap44xx_dmic_hwmod,
1056         .clk            = "ocp_abe_iclk",
1057         .addr           = omap44xx_dmic_addrs,
1058         .user           = OCP_USER_MPU,
1059 };
1060
1061 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1062         {
1063                 .pa_start       = 0x4902e000,
1064                 .pa_end         = 0x4902e07f,
1065                 .flags          = ADDR_TYPE_RT
1066         },
1067         { }
1068 };
1069
1070 /* l4_abe -> dmic (dma) */
1071 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1072         .master         = &omap44xx_l4_abe_hwmod,
1073         .slave          = &omap44xx_dmic_hwmod,
1074         .clk            = "ocp_abe_iclk",
1075         .addr           = omap44xx_dmic_dma_addrs,
1076         .user           = OCP_USER_SDMA,
1077 };
1078
1079 /* dmic slave ports */
1080 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1081         &omap44xx_l4_abe__dmic,
1082         &omap44xx_l4_abe__dmic_dma,
1083 };
1084
1085 static struct omap_hwmod omap44xx_dmic_hwmod = {
1086         .name           = "dmic",
1087         .class          = &omap44xx_dmic_hwmod_class,
1088         .clkdm_name     = "abe_clkdm",
1089         .mpu_irqs       = omap44xx_dmic_irqs,
1090         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1091         .main_clk       = "dmic_fck",
1092         .prcm = {
1093                 .omap4 = {
1094                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1095                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1096                         .modulemode   = MODULEMODE_SWCTRL,
1097                 },
1098         },
1099         .slaves         = omap44xx_dmic_slaves,
1100         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1101         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1102 };
1103
1104 /*
1105  * 'dsp' class
1106  * dsp sub-system
1107  */
1108
1109 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1110         .name   = "dsp",
1111 };
1112
1113 /* dsp */
1114 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1115         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1116         { .irq = -1 }
1117 };
1118
1119 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1120         { .name = "mmu_cache", .rst_shift = 1 },
1121 };
1122
1123 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1124         { .name = "dsp", .rst_shift = 0 },
1125 };
1126
1127 /* dsp -> iva */
1128 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1129         .master         = &omap44xx_dsp_hwmod,
1130         .slave          = &omap44xx_iva_hwmod,
1131         .clk            = "dpll_iva_m5x2_ck",
1132 };
1133
1134 /* dsp master ports */
1135 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1136         &omap44xx_dsp__l3_main_1,
1137         &omap44xx_dsp__l4_abe,
1138         &omap44xx_dsp__iva,
1139 };
1140
1141 /* l4_cfg -> dsp */
1142 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1143         .master         = &omap44xx_l4_cfg_hwmod,
1144         .slave          = &omap44xx_dsp_hwmod,
1145         .clk            = "l4_div_ck",
1146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1147 };
1148
1149 /* dsp slave ports */
1150 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1151         &omap44xx_l4_cfg__dsp,
1152 };
1153
1154 /* Pseudo hwmod for reset control purpose only */
1155 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1156         .name           = "dsp_c0",
1157         .class          = &omap44xx_dsp_hwmod_class,
1158         .clkdm_name     = "tesla_clkdm",
1159         .flags          = HWMOD_INIT_NO_RESET,
1160         .rst_lines      = omap44xx_dsp_c0_resets,
1161         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1162         .prcm = {
1163                 .omap4 = {
1164                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1165                 },
1166         },
1167         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1168 };
1169
1170 static struct omap_hwmod omap44xx_dsp_hwmod = {
1171         .name           = "dsp",
1172         .class          = &omap44xx_dsp_hwmod_class,
1173         .clkdm_name     = "tesla_clkdm",
1174         .mpu_irqs       = omap44xx_dsp_irqs,
1175         .rst_lines      = omap44xx_dsp_resets,
1176         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1177         .main_clk       = "dsp_fck",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1181                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1182                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1183                         .modulemode   = MODULEMODE_HWCTRL,
1184                 },
1185         },
1186         .slaves         = omap44xx_dsp_slaves,
1187         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1188         .masters        = omap44xx_dsp_masters,
1189         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1191 };
1192
1193 /*
1194  * 'dss' class
1195  * display sub-system
1196  */
1197
1198 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1199         .rev_offs       = 0x0000,
1200         .syss_offs      = 0x0014,
1201         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1202 };
1203
1204 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1205         .name   = "dss",
1206         .sysc   = &omap44xx_dss_sysc,
1207 };
1208
1209 /* dss */
1210 /* dss master ports */
1211 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1212         &omap44xx_dss__l3_main_1,
1213 };
1214
1215 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1216         {
1217                 .pa_start       = 0x58000000,
1218                 .pa_end         = 0x5800007f,
1219                 .flags          = ADDR_TYPE_RT
1220         },
1221         { }
1222 };
1223
1224 /* l3_main_2 -> dss */
1225 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1226         .master         = &omap44xx_l3_main_2_hwmod,
1227         .slave          = &omap44xx_dss_hwmod,
1228         .clk            = "dss_fck",
1229         .addr           = omap44xx_dss_dma_addrs,
1230         .user           = OCP_USER_SDMA,
1231 };
1232
1233 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1234         {
1235                 .pa_start       = 0x48040000,
1236                 .pa_end         = 0x4804007f,
1237                 .flags          = ADDR_TYPE_RT
1238         },
1239         { }
1240 };
1241
1242 /* l4_per -> dss */
1243 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1244         .master         = &omap44xx_l4_per_hwmod,
1245         .slave          = &omap44xx_dss_hwmod,
1246         .clk            = "l4_div_ck",
1247         .addr           = omap44xx_dss_addrs,
1248         .user           = OCP_USER_MPU,
1249 };
1250
1251 /* dss slave ports */
1252 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1253         &omap44xx_l3_main_2__dss,
1254         &omap44xx_l4_per__dss,
1255 };
1256
1257 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1258         { .role = "sys_clk", .clk = "dss_sys_clk" },
1259         { .role = "tv_clk", .clk = "dss_tv_clk" },
1260         { .role = "dss_clk", .clk = "dss_dss_clk" },
1261         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1262 };
1263
1264 static struct omap_hwmod omap44xx_dss_hwmod = {
1265         .name           = "dss_core",
1266         .class          = &omap44xx_dss_hwmod_class,
1267         .clkdm_name     = "l3_dss_clkdm",
1268         .main_clk       = "dss_dss_clk",
1269         .prcm = {
1270                 .omap4 = {
1271                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1272                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1273                 },
1274         },
1275         .opt_clks       = dss_opt_clks,
1276         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1277         .slaves         = omap44xx_dss_slaves,
1278         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1279         .masters        = omap44xx_dss_masters,
1280         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1281         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1282 };
1283
1284 /*
1285  * 'dispc' class
1286  * display controller
1287  */
1288
1289 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1290         .rev_offs       = 0x0000,
1291         .sysc_offs      = 0x0010,
1292         .syss_offs      = 0x0014,
1293         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1294                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1295                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1296                            SYSS_HAS_RESET_STATUS),
1297         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1298                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1299         .sysc_fields    = &omap_hwmod_sysc_type1,
1300 };
1301
1302 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1303         .name   = "dispc",
1304         .sysc   = &omap44xx_dispc_sysc,
1305 };
1306
1307 /* dss_dispc */
1308 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1309 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1310         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1311         { .irq = -1 }
1312 };
1313
1314 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1315         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1316         { .dma_req = -1 }
1317 };
1318
1319 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1320         {
1321                 .pa_start       = 0x58001000,
1322                 .pa_end         = 0x58001fff,
1323                 .flags          = ADDR_TYPE_RT
1324         },
1325         { }
1326 };
1327
1328 /* l3_main_2 -> dss_dispc */
1329 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1330         .master         = &omap44xx_l3_main_2_hwmod,
1331         .slave          = &omap44xx_dss_dispc_hwmod,
1332         .clk            = "dss_fck",
1333         .addr           = omap44xx_dss_dispc_dma_addrs,
1334         .user           = OCP_USER_SDMA,
1335 };
1336
1337 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1338         {
1339                 .pa_start       = 0x48041000,
1340                 .pa_end         = 0x48041fff,
1341                 .flags          = ADDR_TYPE_RT
1342         },
1343         { }
1344 };
1345
1346 /* l4_per -> dss_dispc */
1347 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1348         .master         = &omap44xx_l4_per_hwmod,
1349         .slave          = &omap44xx_dss_dispc_hwmod,
1350         .clk            = "l4_div_ck",
1351         .addr           = omap44xx_dss_dispc_addrs,
1352         .user           = OCP_USER_MPU,
1353 };
1354
1355 /* dss_dispc slave ports */
1356 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1357         &omap44xx_l3_main_2__dss_dispc,
1358         &omap44xx_l4_per__dss_dispc,
1359 };
1360
1361 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1362         { .role = "sys_clk", .clk = "dss_sys_clk" },
1363         { .role = "tv_clk", .clk = "dss_tv_clk" },
1364         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1365 };
1366
1367 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1368         .name           = "dss_dispc",
1369         .class          = &omap44xx_dispc_hwmod_class,
1370         .clkdm_name     = "l3_dss_clkdm",
1371         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1372         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1373         .main_clk       = "dss_dss_clk",
1374         .prcm = {
1375                 .omap4 = {
1376                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1377                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1378                 },
1379         },
1380         .opt_clks       = dss_dispc_opt_clks,
1381         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1382         .slaves         = omap44xx_dss_dispc_slaves,
1383         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1384         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1385 };
1386
1387 /*
1388  * 'dsi' class
1389  * display serial interface controller
1390  */
1391
1392 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1393         .rev_offs       = 0x0000,
1394         .sysc_offs      = 0x0010,
1395         .syss_offs      = 0x0014,
1396         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1397                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1398                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1399         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1400         .sysc_fields    = &omap_hwmod_sysc_type1,
1401 };
1402
1403 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1404         .name   = "dsi",
1405         .sysc   = &omap44xx_dsi_sysc,
1406 };
1407
1408 /* dss_dsi1 */
1409 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1410 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1411         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1412         { .irq = -1 }
1413 };
1414
1415 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1416         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1417         { .dma_req = -1 }
1418 };
1419
1420 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1421         {
1422                 .pa_start       = 0x58004000,
1423                 .pa_end         = 0x580041ff,
1424                 .flags          = ADDR_TYPE_RT
1425         },
1426         { }
1427 };
1428
1429 /* l3_main_2 -> dss_dsi1 */
1430 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1431         .master         = &omap44xx_l3_main_2_hwmod,
1432         .slave          = &omap44xx_dss_dsi1_hwmod,
1433         .clk            = "dss_fck",
1434         .addr           = omap44xx_dss_dsi1_dma_addrs,
1435         .user           = OCP_USER_SDMA,
1436 };
1437
1438 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1439         {
1440                 .pa_start       = 0x48044000,
1441                 .pa_end         = 0x480441ff,
1442                 .flags          = ADDR_TYPE_RT
1443         },
1444         { }
1445 };
1446
1447 /* l4_per -> dss_dsi1 */
1448 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1449         .master         = &omap44xx_l4_per_hwmod,
1450         .slave          = &omap44xx_dss_dsi1_hwmod,
1451         .clk            = "l4_div_ck",
1452         .addr           = omap44xx_dss_dsi1_addrs,
1453         .user           = OCP_USER_MPU,
1454 };
1455
1456 /* dss_dsi1 slave ports */
1457 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1458         &omap44xx_l3_main_2__dss_dsi1,
1459         &omap44xx_l4_per__dss_dsi1,
1460 };
1461
1462 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1463         { .role = "sys_clk", .clk = "dss_sys_clk" },
1464 };
1465
1466 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1467         .name           = "dss_dsi1",
1468         .class          = &omap44xx_dsi_hwmod_class,
1469         .clkdm_name     = "l3_dss_clkdm",
1470         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1471         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1472         .main_clk       = "dss_dss_clk",
1473         .prcm = {
1474                 .omap4 = {
1475                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1476                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1477                 },
1478         },
1479         .opt_clks       = dss_dsi1_opt_clks,
1480         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1481         .slaves         = omap44xx_dss_dsi1_slaves,
1482         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1483         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1484 };
1485
1486 /* dss_dsi2 */
1487 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1488 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1489         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1490         { .irq = -1 }
1491 };
1492
1493 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1494         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1495         { .dma_req = -1 }
1496 };
1497
1498 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1499         {
1500                 .pa_start       = 0x58005000,
1501                 .pa_end         = 0x580051ff,
1502                 .flags          = ADDR_TYPE_RT
1503         },
1504         { }
1505 };
1506
1507 /* l3_main_2 -> dss_dsi2 */
1508 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1509         .master         = &omap44xx_l3_main_2_hwmod,
1510         .slave          = &omap44xx_dss_dsi2_hwmod,
1511         .clk            = "dss_fck",
1512         .addr           = omap44xx_dss_dsi2_dma_addrs,
1513         .user           = OCP_USER_SDMA,
1514 };
1515
1516 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1517         {
1518                 .pa_start       = 0x48045000,
1519                 .pa_end         = 0x480451ff,
1520                 .flags          = ADDR_TYPE_RT
1521         },
1522         { }
1523 };
1524
1525 /* l4_per -> dss_dsi2 */
1526 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1527         .master         = &omap44xx_l4_per_hwmod,
1528         .slave          = &omap44xx_dss_dsi2_hwmod,
1529         .clk            = "l4_div_ck",
1530         .addr           = omap44xx_dss_dsi2_addrs,
1531         .user           = OCP_USER_MPU,
1532 };
1533
1534 /* dss_dsi2 slave ports */
1535 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1536         &omap44xx_l3_main_2__dss_dsi2,
1537         &omap44xx_l4_per__dss_dsi2,
1538 };
1539
1540 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1541         { .role = "sys_clk", .clk = "dss_sys_clk" },
1542 };
1543
1544 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1545         .name           = "dss_dsi2",
1546         .class          = &omap44xx_dsi_hwmod_class,
1547         .clkdm_name     = "l3_dss_clkdm",
1548         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1549         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1550         .main_clk       = "dss_dss_clk",
1551         .prcm = {
1552                 .omap4 = {
1553                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1554                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1555                 },
1556         },
1557         .opt_clks       = dss_dsi2_opt_clks,
1558         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1559         .slaves         = omap44xx_dss_dsi2_slaves,
1560         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1561         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1562 };
1563
1564 /*
1565  * 'hdmi' class
1566  * hdmi controller
1567  */
1568
1569 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1570         .rev_offs       = 0x0000,
1571         .sysc_offs      = 0x0010,
1572         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1573                            SYSC_HAS_SOFTRESET),
1574         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1575                            SIDLE_SMART_WKUP),
1576         .sysc_fields    = &omap_hwmod_sysc_type2,
1577 };
1578
1579 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1580         .name   = "hdmi",
1581         .sysc   = &omap44xx_hdmi_sysc,
1582 };
1583
1584 /* dss_hdmi */
1585 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1586 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1587         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1588         { .irq = -1 }
1589 };
1590
1591 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1592         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1593         { .dma_req = -1 }
1594 };
1595
1596 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1597         {
1598                 .pa_start       = 0x58006000,
1599                 .pa_end         = 0x58006fff,
1600                 .flags          = ADDR_TYPE_RT
1601         },
1602         { }
1603 };
1604
1605 /* l3_main_2 -> dss_hdmi */
1606 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1607         .master         = &omap44xx_l3_main_2_hwmod,
1608         .slave          = &omap44xx_dss_hdmi_hwmod,
1609         .clk            = "dss_fck",
1610         .addr           = omap44xx_dss_hdmi_dma_addrs,
1611         .user           = OCP_USER_SDMA,
1612 };
1613
1614 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1615         {
1616                 .pa_start       = 0x48046000,
1617                 .pa_end         = 0x48046fff,
1618                 .flags          = ADDR_TYPE_RT
1619         },
1620         { }
1621 };
1622
1623 /* l4_per -> dss_hdmi */
1624 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1625         .master         = &omap44xx_l4_per_hwmod,
1626         .slave          = &omap44xx_dss_hdmi_hwmod,
1627         .clk            = "l4_div_ck",
1628         .addr           = omap44xx_dss_hdmi_addrs,
1629         .user           = OCP_USER_MPU,
1630 };
1631
1632 /* dss_hdmi slave ports */
1633 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1634         &omap44xx_l3_main_2__dss_hdmi,
1635         &omap44xx_l4_per__dss_hdmi,
1636 };
1637
1638 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1639         { .role = "sys_clk", .clk = "dss_sys_clk" },
1640 };
1641
1642 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1643         .name           = "dss_hdmi",
1644         .class          = &omap44xx_hdmi_hwmod_class,
1645         .clkdm_name     = "l3_dss_clkdm",
1646         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1647         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1648         .main_clk       = "dss_dss_clk",
1649         .prcm = {
1650                 .omap4 = {
1651                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1652                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1653                 },
1654         },
1655         .opt_clks       = dss_hdmi_opt_clks,
1656         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1657         .slaves         = omap44xx_dss_hdmi_slaves,
1658         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1660 };
1661
1662 /*
1663  * 'rfbi' class
1664  * remote frame buffer interface
1665  */
1666
1667 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1668         .rev_offs       = 0x0000,
1669         .sysc_offs      = 0x0010,
1670         .syss_offs      = 0x0014,
1671         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1672                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1673         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1674         .sysc_fields    = &omap_hwmod_sysc_type1,
1675 };
1676
1677 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1678         .name   = "rfbi",
1679         .sysc   = &omap44xx_rfbi_sysc,
1680 };
1681
1682 /* dss_rfbi */
1683 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1684 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1685         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1686         { .dma_req = -1 }
1687 };
1688
1689 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1690         {
1691                 .pa_start       = 0x58002000,
1692                 .pa_end         = 0x580020ff,
1693                 .flags          = ADDR_TYPE_RT
1694         },
1695         { }
1696 };
1697
1698 /* l3_main_2 -> dss_rfbi */
1699 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1700         .master         = &omap44xx_l3_main_2_hwmod,
1701         .slave          = &omap44xx_dss_rfbi_hwmod,
1702         .clk            = "dss_fck",
1703         .addr           = omap44xx_dss_rfbi_dma_addrs,
1704         .user           = OCP_USER_SDMA,
1705 };
1706
1707 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1708         {
1709                 .pa_start       = 0x48042000,
1710                 .pa_end         = 0x480420ff,
1711                 .flags          = ADDR_TYPE_RT
1712         },
1713         { }
1714 };
1715
1716 /* l4_per -> dss_rfbi */
1717 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1718         .master         = &omap44xx_l4_per_hwmod,
1719         .slave          = &omap44xx_dss_rfbi_hwmod,
1720         .clk            = "l4_div_ck",
1721         .addr           = omap44xx_dss_rfbi_addrs,
1722         .user           = OCP_USER_MPU,
1723 };
1724
1725 /* dss_rfbi slave ports */
1726 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1727         &omap44xx_l3_main_2__dss_rfbi,
1728         &omap44xx_l4_per__dss_rfbi,
1729 };
1730
1731 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1732         { .role = "ick", .clk = "dss_fck" },
1733 };
1734
1735 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1736         .name           = "dss_rfbi",
1737         .class          = &omap44xx_rfbi_hwmod_class,
1738         .clkdm_name     = "l3_dss_clkdm",
1739         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1740         .main_clk       = "dss_dss_clk",
1741         .prcm = {
1742                 .omap4 = {
1743                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1744                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1745                 },
1746         },
1747         .opt_clks       = dss_rfbi_opt_clks,
1748         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1749         .slaves         = omap44xx_dss_rfbi_slaves,
1750         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1751         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1752 };
1753
1754 /*
1755  * 'venc' class
1756  * video encoder
1757  */
1758
1759 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1760         .name   = "venc",
1761 };
1762
1763 /* dss_venc */
1764 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1765 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1766         {
1767                 .pa_start       = 0x58003000,
1768                 .pa_end         = 0x580030ff,
1769                 .flags          = ADDR_TYPE_RT
1770         },
1771         { }
1772 };
1773
1774 /* l3_main_2 -> dss_venc */
1775 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1776         .master         = &omap44xx_l3_main_2_hwmod,
1777         .slave          = &omap44xx_dss_venc_hwmod,
1778         .clk            = "dss_fck",
1779         .addr           = omap44xx_dss_venc_dma_addrs,
1780         .user           = OCP_USER_SDMA,
1781 };
1782
1783 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1784         {
1785                 .pa_start       = 0x48043000,
1786                 .pa_end         = 0x480430ff,
1787                 .flags          = ADDR_TYPE_RT
1788         },
1789         { }
1790 };
1791
1792 /* l4_per -> dss_venc */
1793 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1794         .master         = &omap44xx_l4_per_hwmod,
1795         .slave          = &omap44xx_dss_venc_hwmod,
1796         .clk            = "l4_div_ck",
1797         .addr           = omap44xx_dss_venc_addrs,
1798         .user           = OCP_USER_MPU,
1799 };
1800
1801 /* dss_venc slave ports */
1802 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1803         &omap44xx_l3_main_2__dss_venc,
1804         &omap44xx_l4_per__dss_venc,
1805 };
1806
1807 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1808         .name           = "dss_venc",
1809         .class          = &omap44xx_venc_hwmod_class,
1810         .clkdm_name     = "l3_dss_clkdm",
1811         .main_clk       = "dss_dss_clk",
1812         .prcm = {
1813                 .omap4 = {
1814                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1815                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1816                 },
1817         },
1818         .slaves         = omap44xx_dss_venc_slaves,
1819         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1820         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1821 };
1822
1823 /*
1824  * 'gpio' class
1825  * general purpose io module
1826  */
1827
1828 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1829         .rev_offs       = 0x0000,
1830         .sysc_offs      = 0x0010,
1831         .syss_offs      = 0x0114,
1832         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1833                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1834                            SYSS_HAS_RESET_STATUS),
1835         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1836                            SIDLE_SMART_WKUP),
1837         .sysc_fields    = &omap_hwmod_sysc_type1,
1838 };
1839
1840 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1841         .name   = "gpio",
1842         .sysc   = &omap44xx_gpio_sysc,
1843         .rev    = 2,
1844 };
1845
1846 /* gpio dev_attr */
1847 static struct omap_gpio_dev_attr gpio_dev_attr = {
1848         .bank_width     = 32,
1849         .dbck_flag      = true,
1850 };
1851
1852 /* gpio1 */
1853 static struct omap_hwmod omap44xx_gpio1_hwmod;
1854 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1855         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1856         { .irq = -1 }
1857 };
1858
1859 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1860         {
1861                 .pa_start       = 0x4a310000,
1862                 .pa_end         = 0x4a3101ff,
1863                 .flags          = ADDR_TYPE_RT
1864         },
1865         { }
1866 };
1867
1868 /* l4_wkup -> gpio1 */
1869 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1870         .master         = &omap44xx_l4_wkup_hwmod,
1871         .slave          = &omap44xx_gpio1_hwmod,
1872         .clk            = "l4_wkup_clk_mux_ck",
1873         .addr           = omap44xx_gpio1_addrs,
1874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1875 };
1876
1877 /* gpio1 slave ports */
1878 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1879         &omap44xx_l4_wkup__gpio1,
1880 };
1881
1882 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1883         { .role = "dbclk", .clk = "gpio1_dbclk" },
1884 };
1885
1886 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1887         .name           = "gpio1",
1888         .class          = &omap44xx_gpio_hwmod_class,
1889         .clkdm_name     = "l4_wkup_clkdm",
1890         .mpu_irqs       = omap44xx_gpio1_irqs,
1891         .main_clk       = "gpio1_ick",
1892         .prcm = {
1893                 .omap4 = {
1894                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1895                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1896                         .modulemode   = MODULEMODE_HWCTRL,
1897                 },
1898         },
1899         .opt_clks       = gpio1_opt_clks,
1900         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1901         .dev_attr       = &gpio_dev_attr,
1902         .slaves         = omap44xx_gpio1_slaves,
1903         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1904         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1905 };
1906
1907 /* gpio2 */
1908 static struct omap_hwmod omap44xx_gpio2_hwmod;
1909 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1910         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1911         { .irq = -1 }
1912 };
1913
1914 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1915         {
1916                 .pa_start       = 0x48055000,
1917                 .pa_end         = 0x480551ff,
1918                 .flags          = ADDR_TYPE_RT
1919         },
1920         { }
1921 };
1922
1923 /* l4_per -> gpio2 */
1924 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1925         .master         = &omap44xx_l4_per_hwmod,
1926         .slave          = &omap44xx_gpio2_hwmod,
1927         .clk            = "l4_div_ck",
1928         .addr           = omap44xx_gpio2_addrs,
1929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1930 };
1931
1932 /* gpio2 slave ports */
1933 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1934         &omap44xx_l4_per__gpio2,
1935 };
1936
1937 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1938         { .role = "dbclk", .clk = "gpio2_dbclk" },
1939 };
1940
1941 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1942         .name           = "gpio2",
1943         .class          = &omap44xx_gpio_hwmod_class,
1944         .clkdm_name     = "l4_per_clkdm",
1945         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1946         .mpu_irqs       = omap44xx_gpio2_irqs,
1947         .main_clk       = "gpio2_ick",
1948         .prcm = {
1949                 .omap4 = {
1950                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1951                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1952                         .modulemode   = MODULEMODE_HWCTRL,
1953                 },
1954         },
1955         .opt_clks       = gpio2_opt_clks,
1956         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1957         .dev_attr       = &gpio_dev_attr,
1958         .slaves         = omap44xx_gpio2_slaves,
1959         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1961 };
1962
1963 /* gpio3 */
1964 static struct omap_hwmod omap44xx_gpio3_hwmod;
1965 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1966         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1967         { .irq = -1 }
1968 };
1969
1970 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1971         {
1972                 .pa_start       = 0x48057000,
1973                 .pa_end         = 0x480571ff,
1974                 .flags          = ADDR_TYPE_RT
1975         },
1976         { }
1977 };
1978
1979 /* l4_per -> gpio3 */
1980 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1981         .master         = &omap44xx_l4_per_hwmod,
1982         .slave          = &omap44xx_gpio3_hwmod,
1983         .clk            = "l4_div_ck",
1984         .addr           = omap44xx_gpio3_addrs,
1985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1986 };
1987
1988 /* gpio3 slave ports */
1989 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1990         &omap44xx_l4_per__gpio3,
1991 };
1992
1993 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1994         { .role = "dbclk", .clk = "gpio3_dbclk" },
1995 };
1996
1997 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1998         .name           = "gpio3",
1999         .class          = &omap44xx_gpio_hwmod_class,
2000         .clkdm_name     = "l4_per_clkdm",
2001         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2002         .mpu_irqs       = omap44xx_gpio3_irqs,
2003         .main_clk       = "gpio3_ick",
2004         .prcm = {
2005                 .omap4 = {
2006                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
2007                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
2008                         .modulemode   = MODULEMODE_HWCTRL,
2009                 },
2010         },
2011         .opt_clks       = gpio3_opt_clks,
2012         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2013         .dev_attr       = &gpio_dev_attr,
2014         .slaves         = omap44xx_gpio3_slaves,
2015         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
2016         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2017 };
2018
2019 /* gpio4 */
2020 static struct omap_hwmod omap44xx_gpio4_hwmod;
2021 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
2022         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2023         { .irq = -1 }
2024 };
2025
2026 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2027         {
2028                 .pa_start       = 0x48059000,
2029                 .pa_end         = 0x480591ff,
2030                 .flags          = ADDR_TYPE_RT
2031         },
2032         { }
2033 };
2034
2035 /* l4_per -> gpio4 */
2036 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2037         .master         = &omap44xx_l4_per_hwmod,
2038         .slave          = &omap44xx_gpio4_hwmod,
2039         .clk            = "l4_div_ck",
2040         .addr           = omap44xx_gpio4_addrs,
2041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2042 };
2043
2044 /* gpio4 slave ports */
2045 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2046         &omap44xx_l4_per__gpio4,
2047 };
2048
2049 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2050         { .role = "dbclk", .clk = "gpio4_dbclk" },
2051 };
2052
2053 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2054         .name           = "gpio4",
2055         .class          = &omap44xx_gpio_hwmod_class,
2056         .clkdm_name     = "l4_per_clkdm",
2057         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2058         .mpu_irqs       = omap44xx_gpio4_irqs,
2059         .main_clk       = "gpio4_ick",
2060         .prcm = {
2061                 .omap4 = {
2062                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2063                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2064                         .modulemode   = MODULEMODE_HWCTRL,
2065                 },
2066         },
2067         .opt_clks       = gpio4_opt_clks,
2068         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2069         .dev_attr       = &gpio_dev_attr,
2070         .slaves         = omap44xx_gpio4_slaves,
2071         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2072         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2073 };
2074
2075 /* gpio5 */
2076 static struct omap_hwmod omap44xx_gpio5_hwmod;
2077 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2078         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2079         { .irq = -1 }
2080 };
2081
2082 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2083         {
2084                 .pa_start       = 0x4805b000,
2085                 .pa_end         = 0x4805b1ff,
2086                 .flags          = ADDR_TYPE_RT
2087         },
2088         { }
2089 };
2090
2091 /* l4_per -> gpio5 */
2092 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2093         .master         = &omap44xx_l4_per_hwmod,
2094         .slave          = &omap44xx_gpio5_hwmod,
2095         .clk            = "l4_div_ck",
2096         .addr           = omap44xx_gpio5_addrs,
2097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2098 };
2099
2100 /* gpio5 slave ports */
2101 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2102         &omap44xx_l4_per__gpio5,
2103 };
2104
2105 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2106         { .role = "dbclk", .clk = "gpio5_dbclk" },
2107 };
2108
2109 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2110         .name           = "gpio5",
2111         .class          = &omap44xx_gpio_hwmod_class,
2112         .clkdm_name     = "l4_per_clkdm",
2113         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2114         .mpu_irqs       = omap44xx_gpio5_irqs,
2115         .main_clk       = "gpio5_ick",
2116         .prcm = {
2117                 .omap4 = {
2118                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2119                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2120                         .modulemode   = MODULEMODE_HWCTRL,
2121                 },
2122         },
2123         .opt_clks       = gpio5_opt_clks,
2124         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2125         .dev_attr       = &gpio_dev_attr,
2126         .slaves         = omap44xx_gpio5_slaves,
2127         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2128         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2129 };
2130
2131 /* gpio6 */
2132 static struct omap_hwmod omap44xx_gpio6_hwmod;
2133 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2134         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2135         { .irq = -1 }
2136 };
2137
2138 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2139         {
2140                 .pa_start       = 0x4805d000,
2141                 .pa_end         = 0x4805d1ff,
2142                 .flags          = ADDR_TYPE_RT
2143         },
2144         { }
2145 };
2146
2147 /* l4_per -> gpio6 */
2148 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2149         .master         = &omap44xx_l4_per_hwmod,
2150         .slave          = &omap44xx_gpio6_hwmod,
2151         .clk            = "l4_div_ck",
2152         .addr           = omap44xx_gpio6_addrs,
2153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2154 };
2155
2156 /* gpio6 slave ports */
2157 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2158         &omap44xx_l4_per__gpio6,
2159 };
2160
2161 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2162         { .role = "dbclk", .clk = "gpio6_dbclk" },
2163 };
2164
2165 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2166         .name           = "gpio6",
2167         .class          = &omap44xx_gpio_hwmod_class,
2168         .clkdm_name     = "l4_per_clkdm",
2169         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2170         .mpu_irqs       = omap44xx_gpio6_irqs,
2171         .main_clk       = "gpio6_ick",
2172         .prcm = {
2173                 .omap4 = {
2174                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2175                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2176                         .modulemode   = MODULEMODE_HWCTRL,
2177                 },
2178         },
2179         .opt_clks       = gpio6_opt_clks,
2180         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2181         .dev_attr       = &gpio_dev_attr,
2182         .slaves         = omap44xx_gpio6_slaves,
2183         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2184         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2185 };
2186
2187 /*
2188  * 'hsi' class
2189  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2190  * serial if)
2191  */
2192
2193 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2194         .rev_offs       = 0x0000,
2195         .sysc_offs      = 0x0010,
2196         .syss_offs      = 0x0014,
2197         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2198                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2199                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2200         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2201                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2202                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2203         .sysc_fields    = &omap_hwmod_sysc_type1,
2204 };
2205
2206 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2207         .name   = "hsi",
2208         .sysc   = &omap44xx_hsi_sysc,
2209 };
2210
2211 /* hsi */
2212 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2213         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2214         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2215         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2216         { .irq = -1 }
2217 };
2218
2219 /* hsi master ports */
2220 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2221         &omap44xx_hsi__l3_main_2,
2222 };
2223
2224 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2225         {
2226                 .pa_start       = 0x4a058000,
2227                 .pa_end         = 0x4a05bfff,
2228                 .flags          = ADDR_TYPE_RT
2229         },
2230         { }
2231 };
2232
2233 /* l4_cfg -> hsi */
2234 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2235         .master         = &omap44xx_l4_cfg_hwmod,
2236         .slave          = &omap44xx_hsi_hwmod,
2237         .clk            = "l4_div_ck",
2238         .addr           = omap44xx_hsi_addrs,
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* hsi slave ports */
2243 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2244         &omap44xx_l4_cfg__hsi,
2245 };
2246
2247 static struct omap_hwmod omap44xx_hsi_hwmod = {
2248         .name           = "hsi",
2249         .class          = &omap44xx_hsi_hwmod_class,
2250         .clkdm_name     = "l3_init_clkdm",
2251         .mpu_irqs       = omap44xx_hsi_irqs,
2252         .main_clk       = "hsi_fck",
2253         .prcm = {
2254                 .omap4 = {
2255                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2256                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2257                         .modulemode   = MODULEMODE_HWCTRL,
2258                 },
2259         },
2260         .slaves         = omap44xx_hsi_slaves,
2261         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2262         .masters        = omap44xx_hsi_masters,
2263         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2264         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2265 };
2266
2267 /*
2268  * 'i2c' class
2269  * multimaster high-speed i2c controller
2270  */
2271
2272 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2273         .sysc_offs      = 0x0010,
2274         .syss_offs      = 0x0090,
2275         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2276                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2277                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2278         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2279                            SIDLE_SMART_WKUP),
2280         .sysc_fields    = &omap_hwmod_sysc_type1,
2281 };
2282
2283 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2284         .name   = "i2c",
2285         .sysc   = &omap44xx_i2c_sysc,
2286         .rev    = OMAP_I2C_IP_VERSION_2,
2287         .reset  = &omap_i2c_reset,
2288 };
2289
2290 static struct omap_i2c_dev_attr i2c_dev_attr = {
2291         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2292 };
2293
2294 /* i2c1 */
2295 static struct omap_hwmod omap44xx_i2c1_hwmod;
2296 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2297         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2298         { .irq = -1 }
2299 };
2300
2301 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2302         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2303         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2304         { .dma_req = -1 }
2305 };
2306
2307 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2308         {
2309                 .pa_start       = 0x48070000,
2310                 .pa_end         = 0x480700ff,
2311                 .flags          = ADDR_TYPE_RT
2312         },
2313         { }
2314 };
2315
2316 /* l4_per -> i2c1 */
2317 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2318         .master         = &omap44xx_l4_per_hwmod,
2319         .slave          = &omap44xx_i2c1_hwmod,
2320         .clk            = "l4_div_ck",
2321         .addr           = omap44xx_i2c1_addrs,
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 /* i2c1 slave ports */
2326 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2327         &omap44xx_l4_per__i2c1,
2328 };
2329
2330 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2331         .name           = "i2c1",
2332         .class          = &omap44xx_i2c_hwmod_class,
2333         .clkdm_name     = "l4_per_clkdm",
2334         .flags          = HWMOD_16BIT_REG,
2335         .mpu_irqs       = omap44xx_i2c1_irqs,
2336         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2337         .main_clk       = "i2c1_fck",
2338         .prcm = {
2339                 .omap4 = {
2340                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2341                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2342                         .modulemode   = MODULEMODE_SWCTRL,
2343                 },
2344         },
2345         .slaves         = omap44xx_i2c1_slaves,
2346         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2347         .dev_attr       = &i2c_dev_attr,
2348         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2349 };
2350
2351 /* i2c2 */
2352 static struct omap_hwmod omap44xx_i2c2_hwmod;
2353 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2354         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2355         { .irq = -1 }
2356 };
2357
2358 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2359         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2360         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2361         { .dma_req = -1 }
2362 };
2363
2364 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2365         {
2366                 .pa_start       = 0x48072000,
2367                 .pa_end         = 0x480720ff,
2368                 .flags          = ADDR_TYPE_RT
2369         },
2370         { }
2371 };
2372
2373 /* l4_per -> i2c2 */
2374 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2375         .master         = &omap44xx_l4_per_hwmod,
2376         .slave          = &omap44xx_i2c2_hwmod,
2377         .clk            = "l4_div_ck",
2378         .addr           = omap44xx_i2c2_addrs,
2379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2381
2382 /* i2c2 slave ports */
2383 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2384         &omap44xx_l4_per__i2c2,
2385 };
2386
2387 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2388         .name           = "i2c2",
2389         .class          = &omap44xx_i2c_hwmod_class,
2390         .clkdm_name     = "l4_per_clkdm",
2391         .flags          = HWMOD_16BIT_REG,
2392         .mpu_irqs       = omap44xx_i2c2_irqs,
2393         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2394         .main_clk       = "i2c2_fck",
2395         .prcm = {
2396                 .omap4 = {
2397                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2398                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2399                         .modulemode   = MODULEMODE_SWCTRL,
2400                 },
2401         },
2402         .slaves         = omap44xx_i2c2_slaves,
2403         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2404         .dev_attr       = &i2c_dev_attr,
2405         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2406 };
2407
2408 /* i2c3 */
2409 static struct omap_hwmod omap44xx_i2c3_hwmod;
2410 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2411         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2412         { .irq = -1 }
2413 };
2414
2415 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2416         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2417         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2418         { .dma_req = -1 }
2419 };
2420
2421 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2422         {
2423                 .pa_start       = 0x48060000,
2424                 .pa_end         = 0x480600ff,
2425                 .flags          = ADDR_TYPE_RT
2426         },
2427         { }
2428 };
2429
2430 /* l4_per -> i2c3 */
2431 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2432         .master         = &omap44xx_l4_per_hwmod,
2433         .slave          = &omap44xx_i2c3_hwmod,
2434         .clk            = "l4_div_ck",
2435         .addr           = omap44xx_i2c3_addrs,
2436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2438
2439 /* i2c3 slave ports */
2440 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2441         &omap44xx_l4_per__i2c3,
2442 };
2443
2444 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2445         .name           = "i2c3",
2446         .class          = &omap44xx_i2c_hwmod_class,
2447         .clkdm_name     = "l4_per_clkdm",
2448         .flags          = HWMOD_16BIT_REG,
2449         .mpu_irqs       = omap44xx_i2c3_irqs,
2450         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2451         .main_clk       = "i2c3_fck",
2452         .prcm = {
2453                 .omap4 = {
2454                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2455                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2456                         .modulemode   = MODULEMODE_SWCTRL,
2457                 },
2458         },
2459         .slaves         = omap44xx_i2c3_slaves,
2460         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2461         .dev_attr       = &i2c_dev_attr,
2462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2463 };
2464
2465 /* i2c4 */
2466 static struct omap_hwmod omap44xx_i2c4_hwmod;
2467 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2468         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2469         { .irq = -1 }
2470 };
2471
2472 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2473         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2474         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2475         { .dma_req = -1 }
2476 };
2477
2478 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2479         {
2480                 .pa_start       = 0x48350000,
2481                 .pa_end         = 0x483500ff,
2482                 .flags          = ADDR_TYPE_RT
2483         },
2484         { }
2485 };
2486
2487 /* l4_per -> i2c4 */
2488 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2489         .master         = &omap44xx_l4_per_hwmod,
2490         .slave          = &omap44xx_i2c4_hwmod,
2491         .clk            = "l4_div_ck",
2492         .addr           = omap44xx_i2c4_addrs,
2493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2495
2496 /* i2c4 slave ports */
2497 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2498         &omap44xx_l4_per__i2c4,
2499 };
2500
2501 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2502         .name           = "i2c4",
2503         .class          = &omap44xx_i2c_hwmod_class,
2504         .clkdm_name     = "l4_per_clkdm",
2505         .flags          = HWMOD_16BIT_REG,
2506         .mpu_irqs       = omap44xx_i2c4_irqs,
2507         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2508         .main_clk       = "i2c4_fck",
2509         .prcm = {
2510                 .omap4 = {
2511                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2512                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2513                         .modulemode   = MODULEMODE_SWCTRL,
2514                 },
2515         },
2516         .slaves         = omap44xx_i2c4_slaves,
2517         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2518         .dev_attr       = &i2c_dev_attr,
2519         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2520 };
2521
2522 /*
2523  * 'ipu' class
2524  * imaging processor unit
2525  */
2526
2527 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2528         .name   = "ipu",
2529 };
2530
2531 /* ipu */
2532 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2533         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2534         { .irq = -1 }
2535 };
2536
2537 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2538         { .name = "cpu0", .rst_shift = 0 },
2539 };
2540
2541 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2542         { .name = "cpu1", .rst_shift = 1 },
2543 };
2544
2545 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2546         { .name = "mmu_cache", .rst_shift = 2 },
2547 };
2548
2549 /* ipu master ports */
2550 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2551         &omap44xx_ipu__l3_main_2,
2552 };
2553
2554 /* l3_main_2 -> ipu */
2555 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2556         .master         = &omap44xx_l3_main_2_hwmod,
2557         .slave          = &omap44xx_ipu_hwmod,
2558         .clk            = "l3_div_ck",
2559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2560 };
2561
2562 /* ipu slave ports */
2563 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2564         &omap44xx_l3_main_2__ipu,
2565 };
2566
2567 /* Pseudo hwmod for reset control purpose only */
2568 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2569         .name           = "ipu_c0",
2570         .class          = &omap44xx_ipu_hwmod_class,
2571         .clkdm_name     = "ducati_clkdm",
2572         .flags          = HWMOD_INIT_NO_RESET,
2573         .rst_lines      = omap44xx_ipu_c0_resets,
2574         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2575         .prcm = {
2576                 .omap4 = {
2577                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2578                 },
2579         },
2580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2581 };
2582
2583 /* Pseudo hwmod for reset control purpose only */
2584 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2585         .name           = "ipu_c1",
2586         .class          = &omap44xx_ipu_hwmod_class,
2587         .clkdm_name     = "ducati_clkdm",
2588         .flags          = HWMOD_INIT_NO_RESET,
2589         .rst_lines      = omap44xx_ipu_c1_resets,
2590         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2591         .prcm = {
2592                 .omap4 = {
2593                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2594                 },
2595         },
2596         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2597 };
2598
2599 static struct omap_hwmod omap44xx_ipu_hwmod = {
2600         .name           = "ipu",
2601         .class          = &omap44xx_ipu_hwmod_class,
2602         .clkdm_name     = "ducati_clkdm",
2603         .mpu_irqs       = omap44xx_ipu_irqs,
2604         .rst_lines      = omap44xx_ipu_resets,
2605         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2606         .main_clk       = "ipu_fck",
2607         .prcm = {
2608                 .omap4 = {
2609                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2610                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2611                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2612                         .modulemode   = MODULEMODE_HWCTRL,
2613                 },
2614         },
2615         .slaves         = omap44xx_ipu_slaves,
2616         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2617         .masters        = omap44xx_ipu_masters,
2618         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2619         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2620 };
2621
2622 /*
2623  * 'iss' class
2624  * external images sensor pixel data processor
2625  */
2626
2627 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2628         .rev_offs       = 0x0000,
2629         .sysc_offs      = 0x0010,
2630         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2631                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2632         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2633                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2634                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2635         .sysc_fields    = &omap_hwmod_sysc_type2,
2636 };
2637
2638 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2639         .name   = "iss",
2640         .sysc   = &omap44xx_iss_sysc,
2641 };
2642
2643 /* iss */
2644 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2645         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2646         { .irq = -1 }
2647 };
2648
2649 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2650         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2651         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2652         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2653         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2654         { .dma_req = -1 }
2655 };
2656
2657 /* iss master ports */
2658 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2659         &omap44xx_iss__l3_main_2,
2660 };
2661
2662 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2663         {
2664                 .pa_start       = 0x52000000,
2665                 .pa_end         = 0x520000ff,
2666                 .flags          = ADDR_TYPE_RT
2667         },
2668         { }
2669 };
2670
2671 /* l3_main_2 -> iss */
2672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2673         .master         = &omap44xx_l3_main_2_hwmod,
2674         .slave          = &omap44xx_iss_hwmod,
2675         .clk            = "l3_div_ck",
2676         .addr           = omap44xx_iss_addrs,
2677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2679
2680 /* iss slave ports */
2681 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2682         &omap44xx_l3_main_2__iss,
2683 };
2684
2685 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2686         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2687 };
2688
2689 static struct omap_hwmod omap44xx_iss_hwmod = {
2690         .name           = "iss",
2691         .class          = &omap44xx_iss_hwmod_class,
2692         .clkdm_name     = "iss_clkdm",
2693         .mpu_irqs       = omap44xx_iss_irqs,
2694         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2695         .main_clk       = "iss_fck",
2696         .prcm = {
2697                 .omap4 = {
2698                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2699                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2700                         .modulemode   = MODULEMODE_SWCTRL,
2701                 },
2702         },
2703         .opt_clks       = iss_opt_clks,
2704         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2705         .slaves         = omap44xx_iss_slaves,
2706         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2707         .masters        = omap44xx_iss_masters,
2708         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2710 };
2711
2712 /*
2713  * 'iva' class
2714  * multi-standard video encoder/decoder hardware accelerator
2715  */
2716
2717 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2718         .name   = "iva",
2719 };
2720
2721 /* iva */
2722 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2723         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2724         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2725         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2726         { .irq = -1 }
2727 };
2728
2729 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2730         { .name = "logic", .rst_shift = 2 },
2731 };
2732
2733 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2734         { .name = "seq0", .rst_shift = 0 },
2735 };
2736
2737 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2738         { .name = "seq1", .rst_shift = 1 },
2739 };
2740
2741 /* iva master ports */
2742 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2743         &omap44xx_iva__l3_main_2,
2744         &omap44xx_iva__l3_instr,
2745 };
2746
2747 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2748         {
2749                 .pa_start       = 0x5a000000,
2750                 .pa_end         = 0x5a07ffff,
2751                 .flags          = ADDR_TYPE_RT
2752         },
2753         { }
2754 };
2755
2756 /* l3_main_2 -> iva */
2757 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2758         .master         = &omap44xx_l3_main_2_hwmod,
2759         .slave          = &omap44xx_iva_hwmod,
2760         .clk            = "l3_div_ck",
2761         .addr           = omap44xx_iva_addrs,
2762         .user           = OCP_USER_MPU,
2763 };
2764
2765 /* iva slave ports */
2766 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2767         &omap44xx_dsp__iva,
2768         &omap44xx_l3_main_2__iva,
2769 };
2770
2771 /* Pseudo hwmod for reset control purpose only */
2772 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2773         .name           = "iva_seq0",
2774         .class          = &omap44xx_iva_hwmod_class,
2775         .clkdm_name     = "ivahd_clkdm",
2776         .flags          = HWMOD_INIT_NO_RESET,
2777         .rst_lines      = omap44xx_iva_seq0_resets,
2778         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2779         .prcm = {
2780                 .omap4 = {
2781                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2782                 },
2783         },
2784         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2785 };
2786
2787 /* Pseudo hwmod for reset control purpose only */
2788 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2789         .name           = "iva_seq1",
2790         .class          = &omap44xx_iva_hwmod_class,
2791         .clkdm_name     = "ivahd_clkdm",
2792         .flags          = HWMOD_INIT_NO_RESET,
2793         .rst_lines      = omap44xx_iva_seq1_resets,
2794         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2795         .prcm = {
2796                 .omap4 = {
2797                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2798                 },
2799         },
2800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2801 };
2802
2803 static struct omap_hwmod omap44xx_iva_hwmod = {
2804         .name           = "iva",
2805         .class          = &omap44xx_iva_hwmod_class,
2806         .clkdm_name     = "ivahd_clkdm",
2807         .mpu_irqs       = omap44xx_iva_irqs,
2808         .rst_lines      = omap44xx_iva_resets,
2809         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2810         .main_clk       = "iva_fck",
2811         .prcm = {
2812                 .omap4 = {
2813                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2814                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2815                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2816                         .modulemode   = MODULEMODE_HWCTRL,
2817                 },
2818         },
2819         .slaves         = omap44xx_iva_slaves,
2820         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2821         .masters        = omap44xx_iva_masters,
2822         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2823         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2824 };
2825
2826 /*
2827  * 'kbd' class
2828  * keyboard controller
2829  */
2830
2831 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2832         .rev_offs       = 0x0000,
2833         .sysc_offs      = 0x0010,
2834         .syss_offs      = 0x0014,
2835         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2836                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2837                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2838                            SYSS_HAS_RESET_STATUS),
2839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2840         .sysc_fields    = &omap_hwmod_sysc_type1,
2841 };
2842
2843 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2844         .name   = "kbd",
2845         .sysc   = &omap44xx_kbd_sysc,
2846 };
2847
2848 /* kbd */
2849 static struct omap_hwmod omap44xx_kbd_hwmod;
2850 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2851         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2852         { .irq = -1 }
2853 };
2854
2855 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2856         {
2857                 .pa_start       = 0x4a31c000,
2858                 .pa_end         = 0x4a31c07f,
2859                 .flags          = ADDR_TYPE_RT
2860         },
2861         { }
2862 };
2863
2864 /* l4_wkup -> kbd */
2865 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2866         .master         = &omap44xx_l4_wkup_hwmod,
2867         .slave          = &omap44xx_kbd_hwmod,
2868         .clk            = "l4_wkup_clk_mux_ck",
2869         .addr           = omap44xx_kbd_addrs,
2870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2871 };
2872
2873 /* kbd slave ports */
2874 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2875         &omap44xx_l4_wkup__kbd,
2876 };
2877
2878 static struct omap_hwmod omap44xx_kbd_hwmod = {
2879         .name           = "kbd",
2880         .class          = &omap44xx_kbd_hwmod_class,
2881         .clkdm_name     = "l4_wkup_clkdm",
2882         .mpu_irqs       = omap44xx_kbd_irqs,
2883         .main_clk       = "kbd_fck",
2884         .prcm = {
2885                 .omap4 = {
2886                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2887                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2888                         .modulemode   = MODULEMODE_SWCTRL,
2889                 },
2890         },
2891         .slaves         = omap44xx_kbd_slaves,
2892         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2893         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2894 };
2895
2896 /*
2897  * 'mailbox' class
2898  * mailbox module allowing communication between the on-chip processors using a
2899  * queued mailbox-interrupt mechanism.
2900  */
2901
2902 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2903         .rev_offs       = 0x0000,
2904         .sysc_offs      = 0x0010,
2905         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2906                            SYSC_HAS_SOFTRESET),
2907         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2908         .sysc_fields    = &omap_hwmod_sysc_type2,
2909 };
2910
2911 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2912         .name   = "mailbox",
2913         .sysc   = &omap44xx_mailbox_sysc,
2914 };
2915
2916 /* mailbox */
2917 static struct omap_hwmod omap44xx_mailbox_hwmod;
2918 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2919         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2920         { .irq = -1 }
2921 };
2922
2923 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2924         {
2925                 .pa_start       = 0x4a0f4000,
2926                 .pa_end         = 0x4a0f41ff,
2927                 .flags          = ADDR_TYPE_RT
2928         },
2929         { }
2930 };
2931
2932 /* l4_cfg -> mailbox */
2933 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2934         .master         = &omap44xx_l4_cfg_hwmod,
2935         .slave          = &omap44xx_mailbox_hwmod,
2936         .clk            = "l4_div_ck",
2937         .addr           = omap44xx_mailbox_addrs,
2938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2939 };
2940
2941 /* mailbox slave ports */
2942 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2943         &omap44xx_l4_cfg__mailbox,
2944 };
2945
2946 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2947         .name           = "mailbox",
2948         .class          = &omap44xx_mailbox_hwmod_class,
2949         .clkdm_name     = "l4_cfg_clkdm",
2950         .mpu_irqs       = omap44xx_mailbox_irqs,
2951         .prcm = {
2952                 .omap4 = {
2953                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2954                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2955                 },
2956         },
2957         .slaves         = omap44xx_mailbox_slaves,
2958         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2960 };
2961
2962 /*
2963  * 'mcbsp' class
2964  * multi channel buffered serial port controller
2965  */
2966
2967 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2968         .sysc_offs      = 0x008c,
2969         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2970                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2972         .sysc_fields    = &omap_hwmod_sysc_type1,
2973 };
2974
2975 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2976         .name   = "mcbsp",
2977         .sysc   = &omap44xx_mcbsp_sysc,
2978         .rev    = MCBSP_CONFIG_TYPE4,
2979 };
2980
2981 /* mcbsp1 */
2982 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2983 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2984         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2985         { .irq = -1 }
2986 };
2987
2988 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2989         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2990         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2991         { .dma_req = -1 }
2992 };
2993
2994 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2995         {
2996                 .name           = "mpu",
2997                 .pa_start       = 0x40122000,
2998                 .pa_end         = 0x401220ff,
2999                 .flags          = ADDR_TYPE_RT
3000         },
3001         { }
3002 };
3003
3004 /* l4_abe -> mcbsp1 */
3005 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3006         .master         = &omap44xx_l4_abe_hwmod,
3007         .slave          = &omap44xx_mcbsp1_hwmod,
3008         .clk            = "ocp_abe_iclk",
3009         .addr           = omap44xx_mcbsp1_addrs,
3010         .user           = OCP_USER_MPU,
3011 };
3012
3013 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
3014         {
3015                 .name           = "dma",
3016                 .pa_start       = 0x49022000,
3017                 .pa_end         = 0x490220ff,
3018                 .flags          = ADDR_TYPE_RT
3019         },
3020         { }
3021 };
3022
3023 /* l4_abe -> mcbsp1 (dma) */
3024 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
3025         .master         = &omap44xx_l4_abe_hwmod,
3026         .slave          = &omap44xx_mcbsp1_hwmod,
3027         .clk            = "ocp_abe_iclk",
3028         .addr           = omap44xx_mcbsp1_dma_addrs,
3029         .user           = OCP_USER_SDMA,
3030 };
3031
3032 /* mcbsp1 slave ports */
3033 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
3034         &omap44xx_l4_abe__mcbsp1,
3035         &omap44xx_l4_abe__mcbsp1_dma,
3036 };
3037
3038 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3039         .name           = "mcbsp1",
3040         .class          = &omap44xx_mcbsp_hwmod_class,
3041         .clkdm_name     = "abe_clkdm",
3042         .mpu_irqs       = omap44xx_mcbsp1_irqs,
3043         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
3044         .main_clk       = "mcbsp1_fck",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3048                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3049                         .modulemode   = MODULEMODE_SWCTRL,
3050                 },
3051         },
3052         .slaves         = omap44xx_mcbsp1_slaves,
3053         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3054         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3055 };
3056
3057 /* mcbsp2 */
3058 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3059 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3060         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3061         { .irq = -1 }
3062 };
3063
3064 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3065         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3066         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3067         { .dma_req = -1 }
3068 };
3069
3070 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3071         {
3072                 .name           = "mpu",
3073                 .pa_start       = 0x40124000,
3074                 .pa_end         = 0x401240ff,
3075                 .flags          = ADDR_TYPE_RT
3076         },
3077         { }
3078 };
3079
3080 /* l4_abe -> mcbsp2 */
3081 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3082         .master         = &omap44xx_l4_abe_hwmod,
3083         .slave          = &omap44xx_mcbsp2_hwmod,
3084         .clk            = "ocp_abe_iclk",
3085         .addr           = omap44xx_mcbsp2_addrs,
3086         .user           = OCP_USER_MPU,
3087 };
3088
3089 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3090         {
3091                 .name           = "dma",
3092                 .pa_start       = 0x49024000,
3093                 .pa_end         = 0x490240ff,
3094                 .flags          = ADDR_TYPE_RT
3095         },
3096         { }
3097 };
3098
3099 /* l4_abe -> mcbsp2 (dma) */
3100 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3101         .master         = &omap44xx_l4_abe_hwmod,
3102         .slave          = &omap44xx_mcbsp2_hwmod,
3103         .clk            = "ocp_abe_iclk",
3104         .addr           = omap44xx_mcbsp2_dma_addrs,
3105         .user           = OCP_USER_SDMA,
3106 };
3107
3108 /* mcbsp2 slave ports */
3109 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3110         &omap44xx_l4_abe__mcbsp2,
3111         &omap44xx_l4_abe__mcbsp2_dma,
3112 };
3113
3114 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3115         .name           = "mcbsp2",
3116         .class          = &omap44xx_mcbsp_hwmod_class,
3117         .clkdm_name     = "abe_clkdm",
3118         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3119         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3120         .main_clk       = "mcbsp2_fck",
3121         .prcm = {
3122                 .omap4 = {
3123                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3124                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3125                         .modulemode   = MODULEMODE_SWCTRL,
3126                 },
3127         },
3128         .slaves         = omap44xx_mcbsp2_slaves,
3129         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3130         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3131 };
3132
3133 /* mcbsp3 */
3134 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3135 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3136         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3137         { .irq = -1 }
3138 };
3139
3140 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3141         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3142         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3143         { .dma_req = -1 }
3144 };
3145
3146 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3147         {
3148                 .name           = "mpu",
3149                 .pa_start       = 0x40126000,
3150                 .pa_end         = 0x401260ff,
3151                 .flags          = ADDR_TYPE_RT
3152         },
3153         { }
3154 };
3155
3156 /* l4_abe -> mcbsp3 */
3157 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3158         .master         = &omap44xx_l4_abe_hwmod,
3159         .slave          = &omap44xx_mcbsp3_hwmod,
3160         .clk            = "ocp_abe_iclk",
3161         .addr           = omap44xx_mcbsp3_addrs,
3162         .user           = OCP_USER_MPU,
3163 };
3164
3165 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3166         {
3167                 .name           = "dma",
3168                 .pa_start       = 0x49026000,
3169                 .pa_end         = 0x490260ff,
3170                 .flags          = ADDR_TYPE_RT
3171         },
3172         { }
3173 };
3174
3175 /* l4_abe -> mcbsp3 (dma) */
3176 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3177         .master         = &omap44xx_l4_abe_hwmod,
3178         .slave          = &omap44xx_mcbsp3_hwmod,
3179         .clk            = "ocp_abe_iclk",
3180         .addr           = omap44xx_mcbsp3_dma_addrs,
3181         .user           = OCP_USER_SDMA,
3182 };
3183
3184 /* mcbsp3 slave ports */
3185 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3186         &omap44xx_l4_abe__mcbsp3,
3187         &omap44xx_l4_abe__mcbsp3_dma,
3188 };
3189
3190 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3191         .name           = "mcbsp3",
3192         .class          = &omap44xx_mcbsp_hwmod_class,
3193         .clkdm_name     = "abe_clkdm",
3194         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3195         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3196         .main_clk       = "mcbsp3_fck",
3197         .prcm = {
3198                 .omap4 = {
3199                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3200                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3201                         .modulemode   = MODULEMODE_SWCTRL,
3202                 },
3203         },
3204         .slaves         = omap44xx_mcbsp3_slaves,
3205         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3206         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3207 };
3208
3209 /* mcbsp4 */
3210 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3211 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3212         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3213         { .irq = -1 }
3214 };
3215
3216 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3217         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3218         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3219         { .dma_req = -1 }
3220 };
3221
3222 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3223         {
3224                 .pa_start       = 0x48096000,
3225                 .pa_end         = 0x480960ff,
3226                 .flags          = ADDR_TYPE_RT
3227         },
3228         { }
3229 };
3230
3231 /* l4_per -> mcbsp4 */
3232 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3233         .master         = &omap44xx_l4_per_hwmod,
3234         .slave          = &omap44xx_mcbsp4_hwmod,
3235         .clk            = "l4_div_ck",
3236         .addr           = omap44xx_mcbsp4_addrs,
3237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3238 };
3239
3240 /* mcbsp4 slave ports */
3241 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3242         &omap44xx_l4_per__mcbsp4,
3243 };
3244
3245 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3246         .name           = "mcbsp4",
3247         .class          = &omap44xx_mcbsp_hwmod_class,
3248         .clkdm_name     = "l4_per_clkdm",
3249         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3250         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3251         .main_clk       = "mcbsp4_fck",
3252         .prcm = {
3253                 .omap4 = {
3254                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3255                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3256                         .modulemode   = MODULEMODE_SWCTRL,
3257                 },
3258         },
3259         .slaves         = omap44xx_mcbsp4_slaves,
3260         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3261         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3262 };
3263
3264 /*
3265  * 'mcpdm' class
3266  * multi channel pdm controller (proprietary interface with phoenix power
3267  * ic)
3268  */
3269
3270 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3271         .rev_offs       = 0x0000,
3272         .sysc_offs      = 0x0010,
3273         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3274                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3275         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3276                            SIDLE_SMART_WKUP),
3277         .sysc_fields    = &omap_hwmod_sysc_type2,
3278 };
3279
3280 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3281         .name   = "mcpdm",
3282         .sysc   = &omap44xx_mcpdm_sysc,
3283 };
3284
3285 /* mcpdm */
3286 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3287 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3288         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3289         { .irq = -1 }
3290 };
3291
3292 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3293         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3294         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3295         { .dma_req = -1 }
3296 };
3297
3298 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3299         {
3300                 .pa_start       = 0x40132000,
3301                 .pa_end         = 0x4013207f,
3302                 .flags          = ADDR_TYPE_RT
3303         },
3304         { }
3305 };
3306
3307 /* l4_abe -> mcpdm */
3308 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3309         .master         = &omap44xx_l4_abe_hwmod,
3310         .slave          = &omap44xx_mcpdm_hwmod,
3311         .clk            = "ocp_abe_iclk",
3312         .addr           = omap44xx_mcpdm_addrs,
3313         .user           = OCP_USER_MPU,
3314 };
3315
3316 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3317         {
3318                 .pa_start       = 0x49032000,
3319                 .pa_end         = 0x4903207f,
3320                 .flags          = ADDR_TYPE_RT
3321         },
3322         { }
3323 };
3324
3325 /* l4_abe -> mcpdm (dma) */
3326 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3327         .master         = &omap44xx_l4_abe_hwmod,
3328         .slave          = &omap44xx_mcpdm_hwmod,
3329         .clk            = "ocp_abe_iclk",
3330         .addr           = omap44xx_mcpdm_dma_addrs,
3331         .user           = OCP_USER_SDMA,
3332 };
3333
3334 /* mcpdm slave ports */
3335 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3336         &omap44xx_l4_abe__mcpdm,
3337         &omap44xx_l4_abe__mcpdm_dma,
3338 };
3339
3340 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3341         .name           = "mcpdm",
3342         .class          = &omap44xx_mcpdm_hwmod_class,
3343         .clkdm_name     = "abe_clkdm",
3344         .mpu_irqs       = omap44xx_mcpdm_irqs,
3345         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3346         .main_clk       = "mcpdm_fck",
3347         .prcm = {
3348                 .omap4 = {
3349                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3350                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3351                         .modulemode   = MODULEMODE_SWCTRL,
3352                 },
3353         },
3354         .slaves         = omap44xx_mcpdm_slaves,
3355         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3356         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3357 };
3358
3359 /*
3360  * 'mcspi' class
3361  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3362  * bus
3363  */
3364
3365 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3366         .rev_offs       = 0x0000,
3367         .sysc_offs      = 0x0010,
3368         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3369                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3370         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3371                            SIDLE_SMART_WKUP),
3372         .sysc_fields    = &omap_hwmod_sysc_type2,
3373 };
3374
3375 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3376         .name   = "mcspi",
3377         .sysc   = &omap44xx_mcspi_sysc,
3378         .rev    = OMAP4_MCSPI_REV,
3379 };
3380
3381 /* mcspi1 */
3382 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3383 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3384         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3385         { .irq = -1 }
3386 };
3387
3388 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3389         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3390         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3391         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3392         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3393         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3394         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3395         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3396         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3397         { .dma_req = -1 }
3398 };
3399
3400 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3401         {
3402                 .pa_start       = 0x48098000,
3403                 .pa_end         = 0x480981ff,
3404                 .flags          = ADDR_TYPE_RT
3405         },
3406         { }
3407 };
3408
3409 /* l4_per -> mcspi1 */
3410 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3411         .master         = &omap44xx_l4_per_hwmod,
3412         .slave          = &omap44xx_mcspi1_hwmod,
3413         .clk            = "l4_div_ck",
3414         .addr           = omap44xx_mcspi1_addrs,
3415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 /* mcspi1 slave ports */
3419 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3420         &omap44xx_l4_per__mcspi1,
3421 };
3422
3423 /* mcspi1 dev_attr */
3424 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3425         .num_chipselect = 4,
3426 };
3427
3428 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3429         .name           = "mcspi1",
3430         .class          = &omap44xx_mcspi_hwmod_class,
3431         .clkdm_name     = "l4_per_clkdm",
3432         .mpu_irqs       = omap44xx_mcspi1_irqs,
3433         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3434         .main_clk       = "mcspi1_fck",
3435         .prcm = {
3436                 .omap4 = {
3437                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3438                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3439                         .modulemode   = MODULEMODE_SWCTRL,
3440                 },
3441         },
3442         .dev_attr       = &mcspi1_dev_attr,
3443         .slaves         = omap44xx_mcspi1_slaves,
3444         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3445         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3446 };
3447
3448 /* mcspi2 */
3449 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3450 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3451         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3452         { .irq = -1 }
3453 };
3454
3455 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3456         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3457         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3458         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3459         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3460         { .dma_req = -1 }
3461 };
3462
3463 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3464         {
3465                 .pa_start       = 0x4809a000,
3466                 .pa_end         = 0x4809a1ff,
3467                 .flags          = ADDR_TYPE_RT
3468         },
3469         { }
3470 };
3471
3472 /* l4_per -> mcspi2 */
3473 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3474         .master         = &omap44xx_l4_per_hwmod,
3475         .slave          = &omap44xx_mcspi2_hwmod,
3476         .clk            = "l4_div_ck",
3477         .addr           = omap44xx_mcspi2_addrs,
3478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3479 };
3480
3481 /* mcspi2 slave ports */
3482 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3483         &omap44xx_l4_per__mcspi2,
3484 };
3485
3486 /* mcspi2 dev_attr */
3487 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3488         .num_chipselect = 2,
3489 };
3490
3491 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3492         .name           = "mcspi2",
3493         .class          = &omap44xx_mcspi_hwmod_class,
3494         .clkdm_name     = "l4_per_clkdm",
3495         .mpu_irqs       = omap44xx_mcspi2_irqs,
3496         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3497         .main_clk       = "mcspi2_fck",
3498         .prcm = {
3499                 .omap4 = {
3500                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3501                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3502                         .modulemode   = MODULEMODE_SWCTRL,
3503                 },
3504         },
3505         .dev_attr       = &mcspi2_dev_attr,
3506         .slaves         = omap44xx_mcspi2_slaves,
3507         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3509 };
3510
3511 /* mcspi3 */
3512 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3513 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3514         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3515         { .irq = -1 }
3516 };
3517
3518 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3519         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3520         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3521         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3522         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3523         { .dma_req = -1 }
3524 };
3525
3526 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3527         {
3528                 .pa_start       = 0x480b8000,
3529                 .pa_end         = 0x480b81ff,
3530                 .flags          = ADDR_TYPE_RT
3531         },
3532         { }
3533 };
3534
3535 /* l4_per -> mcspi3 */
3536 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3537         .master         = &omap44xx_l4_per_hwmod,
3538         .slave          = &omap44xx_mcspi3_hwmod,
3539         .clk            = "l4_div_ck",
3540         .addr           = omap44xx_mcspi3_addrs,
3541         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3542 };
3543
3544 /* mcspi3 slave ports */
3545 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3546         &omap44xx_l4_per__mcspi3,
3547 };
3548
3549 /* mcspi3 dev_attr */
3550 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3551         .num_chipselect = 2,
3552 };
3553
3554 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3555         .name           = "mcspi3",
3556         .class          = &omap44xx_mcspi_hwmod_class,
3557         .clkdm_name     = "l4_per_clkdm",
3558         .mpu_irqs       = omap44xx_mcspi3_irqs,
3559         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3560         .main_clk       = "mcspi3_fck",
3561         .prcm = {
3562                 .omap4 = {
3563                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3564                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3565                         .modulemode   = MODULEMODE_SWCTRL,
3566                 },
3567         },
3568         .dev_attr       = &mcspi3_dev_attr,
3569         .slaves         = omap44xx_mcspi3_slaves,
3570         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3571         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3572 };
3573
3574 /* mcspi4 */
3575 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3576 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3577         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3578         { .irq = -1 }
3579 };
3580
3581 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3582         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3583         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3584         { .dma_req = -1 }
3585 };
3586
3587 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3588         {
3589                 .pa_start       = 0x480ba000,
3590                 .pa_end         = 0x480ba1ff,
3591                 .flags          = ADDR_TYPE_RT
3592         },
3593         { }
3594 };
3595
3596 /* l4_per -> mcspi4 */
3597 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3598         .master         = &omap44xx_l4_per_hwmod,
3599         .slave          = &omap44xx_mcspi4_hwmod,
3600         .clk            = "l4_div_ck",
3601         .addr           = omap44xx_mcspi4_addrs,
3602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3603 };
3604
3605 /* mcspi4 slave ports */
3606 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3607         &omap44xx_l4_per__mcspi4,
3608 };
3609
3610 /* mcspi4 dev_attr */
3611 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3612         .num_chipselect = 1,
3613 };
3614
3615 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3616         .name           = "mcspi4",
3617         .class          = &omap44xx_mcspi_hwmod_class,
3618         .clkdm_name     = "l4_per_clkdm",
3619         .mpu_irqs       = omap44xx_mcspi4_irqs,
3620         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3621         .main_clk       = "mcspi4_fck",
3622         .prcm = {
3623                 .omap4 = {
3624                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3625                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3626                         .modulemode   = MODULEMODE_SWCTRL,
3627                 },
3628         },
3629         .dev_attr       = &mcspi4_dev_attr,
3630         .slaves         = omap44xx_mcspi4_slaves,
3631         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3632         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3633 };
3634
3635 /*
3636  * 'mmc' class
3637  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3638  */
3639
3640 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3641         .rev_offs       = 0x0000,
3642         .sysc_offs      = 0x0010,
3643         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3644                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3645                            SYSC_HAS_SOFTRESET),
3646         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3647                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3648                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3649         .sysc_fields    = &omap_hwmod_sysc_type2,
3650 };
3651
3652 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3653         .name   = "mmc",
3654         .sysc   = &omap44xx_mmc_sysc,
3655 };
3656
3657 /* mmc1 */
3658 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3659         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3660         { .irq = -1 }
3661 };
3662
3663 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3664         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3665         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3666         { .dma_req = -1 }
3667 };
3668
3669 /* mmc1 master ports */
3670 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3671         &omap44xx_mmc1__l3_main_1,
3672 };
3673
3674 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3675         {
3676                 .pa_start       = 0x4809c000,
3677                 .pa_end         = 0x4809c3ff,
3678                 .flags          = ADDR_TYPE_RT
3679         },
3680         { }
3681 };
3682
3683 /* l4_per -> mmc1 */
3684 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3685         .master         = &omap44xx_l4_per_hwmod,
3686         .slave          = &omap44xx_mmc1_hwmod,
3687         .clk            = "l4_div_ck",
3688         .addr           = omap44xx_mmc1_addrs,
3689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3691
3692 /* mmc1 slave ports */
3693 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3694         &omap44xx_l4_per__mmc1,
3695 };
3696
3697 /* mmc1 dev_attr */
3698 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3699         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3700 };
3701
3702 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3703         .name           = "mmc1",
3704         .class          = &omap44xx_mmc_hwmod_class,
3705         .clkdm_name     = "l3_init_clkdm",
3706         .mpu_irqs       = omap44xx_mmc1_irqs,
3707         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3708         .main_clk       = "mmc1_fck",
3709         .prcm = {
3710                 .omap4 = {
3711                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3712                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3713                         .modulemode   = MODULEMODE_SWCTRL,
3714                 },
3715         },
3716         .dev_attr       = &mmc1_dev_attr,
3717         .slaves         = omap44xx_mmc1_slaves,
3718         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3719         .masters        = omap44xx_mmc1_masters,
3720         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3721         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3722 };
3723
3724 /* mmc2 */
3725 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3726         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3727         { .irq = -1 }
3728 };
3729
3730 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3731         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3732         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3733         { .dma_req = -1 }
3734 };
3735
3736 /* mmc2 master ports */
3737 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3738         &omap44xx_mmc2__l3_main_1,
3739 };
3740
3741 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3742         {
3743                 .pa_start       = 0x480b4000,
3744                 .pa_end         = 0x480b43ff,
3745                 .flags          = ADDR_TYPE_RT
3746         },
3747         { }
3748 };
3749
3750 /* l4_per -> mmc2 */
3751 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3752         .master         = &omap44xx_l4_per_hwmod,
3753         .slave          = &omap44xx_mmc2_hwmod,
3754         .clk            = "l4_div_ck",
3755         .addr           = omap44xx_mmc2_addrs,
3756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3757 };
3758
3759 /* mmc2 slave ports */
3760 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3761         &omap44xx_l4_per__mmc2,
3762 };
3763
3764 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3765         .name           = "mmc2",
3766         .class          = &omap44xx_mmc_hwmod_class,
3767         .clkdm_name     = "l3_init_clkdm",
3768         .mpu_irqs       = omap44xx_mmc2_irqs,
3769         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3770         .main_clk       = "mmc2_fck",
3771         .prcm = {
3772                 .omap4 = {
3773                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3774                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3775                         .modulemode   = MODULEMODE_SWCTRL,
3776                 },
3777         },
3778         .slaves         = omap44xx_mmc2_slaves,
3779         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3780         .masters        = omap44xx_mmc2_masters,
3781         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3783 };
3784
3785 /* mmc3 */
3786 static struct omap_hwmod omap44xx_mmc3_hwmod;
3787 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3788         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3789         { .irq = -1 }
3790 };
3791
3792 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3793         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3794         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3795         { .dma_req = -1 }
3796 };
3797
3798 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3799         {
3800                 .pa_start       = 0x480ad000,
3801                 .pa_end         = 0x480ad3ff,
3802                 .flags          = ADDR_TYPE_RT
3803         },
3804         { }
3805 };
3806
3807 /* l4_per -> mmc3 */
3808 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3809         .master         = &omap44xx_l4_per_hwmod,
3810         .slave          = &omap44xx_mmc3_hwmod,
3811         .clk            = "l4_div_ck",
3812         .addr           = omap44xx_mmc3_addrs,
3813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3814 };
3815
3816 /* mmc3 slave ports */
3817 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3818         &omap44xx_l4_per__mmc3,
3819 };
3820
3821 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3822         .name           = "mmc3",
3823         .class          = &omap44xx_mmc_hwmod_class,
3824         .clkdm_name     = "l4_per_clkdm",
3825         .mpu_irqs       = omap44xx_mmc3_irqs,
3826         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3827         .main_clk       = "mmc3_fck",
3828         .prcm = {
3829                 .omap4 = {
3830                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3831                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3832                         .modulemode   = MODULEMODE_SWCTRL,
3833                 },
3834         },
3835         .slaves         = omap44xx_mmc3_slaves,
3836         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3837         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3838 };
3839
3840 /* mmc4 */
3841 static struct omap_hwmod omap44xx_mmc4_hwmod;
3842 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3843         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3844         { .irq = -1 }
3845 };
3846
3847 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3848         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3849         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3850         { .dma_req = -1 }
3851 };
3852
3853 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3854         {
3855                 .pa_start       = 0x480d1000,
3856                 .pa_end         = 0x480d13ff,
3857                 .flags          = ADDR_TYPE_RT
3858         },
3859         { }
3860 };
3861
3862 /* l4_per -> mmc4 */
3863 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3864         .master         = &omap44xx_l4_per_hwmod,
3865         .slave          = &omap44xx_mmc4_hwmod,
3866         .clk            = "l4_div_ck",
3867         .addr           = omap44xx_mmc4_addrs,
3868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3869 };
3870
3871 /* mmc4 slave ports */
3872 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3873         &omap44xx_l4_per__mmc4,
3874 };
3875
3876 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3877         .name           = "mmc4",
3878         .class          = &omap44xx_mmc_hwmod_class,
3879         .clkdm_name     = "l4_per_clkdm",
3880         .mpu_irqs       = omap44xx_mmc4_irqs,
3881
3882         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3883         .main_clk       = "mmc4_fck",
3884         .prcm = {
3885                 .omap4 = {
3886                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3887                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3888                         .modulemode   = MODULEMODE_SWCTRL,
3889                 },
3890         },
3891         .slaves         = omap44xx_mmc4_slaves,
3892         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3893         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3894 };
3895
3896 /* mmc5 */
3897 static struct omap_hwmod omap44xx_mmc5_hwmod;
3898 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3899         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3900         { .irq = -1 }
3901 };
3902
3903 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3904         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3905         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3906         { .dma_req = -1 }
3907 };
3908
3909 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3910         {
3911                 .pa_start       = 0x480d5000,
3912                 .pa_end         = 0x480d53ff,
3913                 .flags          = ADDR_TYPE_RT
3914         },
3915         { }
3916 };
3917
3918 /* l4_per -> mmc5 */
3919 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3920         .master         = &omap44xx_l4_per_hwmod,
3921         .slave          = &omap44xx_mmc5_hwmod,
3922         .clk            = "l4_div_ck",
3923         .addr           = omap44xx_mmc5_addrs,
3924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3925 };
3926
3927 /* mmc5 slave ports */
3928 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3929         &omap44xx_l4_per__mmc5,
3930 };
3931
3932 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3933         .name           = "mmc5",
3934         .class          = &omap44xx_mmc_hwmod_class,
3935         .clkdm_name     = "l4_per_clkdm",
3936         .mpu_irqs       = omap44xx_mmc5_irqs,
3937         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3938         .main_clk       = "mmc5_fck",
3939         .prcm = {
3940                 .omap4 = {
3941                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3942                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3943                         .modulemode   = MODULEMODE_SWCTRL,
3944                 },
3945         },
3946         .slaves         = omap44xx_mmc5_slaves,
3947         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3948         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3949 };
3950
3951 /*
3952  * 'mpu' class
3953  * mpu sub-system
3954  */
3955
3956 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3957         .name   = "mpu",
3958 };
3959
3960 /* mpu */
3961 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3962         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3963         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3964         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3965         { .irq = -1 }
3966 };
3967
3968 /* mpu master ports */
3969 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3970         &omap44xx_mpu__l3_main_1,
3971         &omap44xx_mpu__l4_abe,
3972         &omap44xx_mpu__dmm,
3973 };
3974
3975 static struct omap_hwmod omap44xx_mpu_hwmod = {
3976         .name           = "mpu",
3977         .class          = &omap44xx_mpu_hwmod_class,
3978         .clkdm_name     = "mpuss_clkdm",
3979         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3980         .mpu_irqs       = omap44xx_mpu_irqs,
3981         .main_clk       = "dpll_mpu_m2_ck",
3982         .prcm = {
3983                 .omap4 = {
3984                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3985                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3986                 },
3987         },
3988         .masters        = omap44xx_mpu_masters,
3989         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3990         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3991 };
3992
3993 /*
3994  * 'smartreflex' class
3995  * smartreflex module (monitor silicon performance and outputs a measure of
3996  * performance error)
3997  */
3998
3999 /* The IP is not compliant to type1 / type2 scheme */
4000 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
4001         .sidle_shift    = 24,
4002         .enwkup_shift   = 26,
4003 };
4004
4005 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
4006         .sysc_offs      = 0x0038,
4007         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
4008         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4009                            SIDLE_SMART_WKUP),
4010         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
4011 };
4012
4013 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
4014         .name   = "smartreflex",
4015         .sysc   = &omap44xx_smartreflex_sysc,
4016         .rev    = 2,
4017 };
4018
4019 /* smartreflex_core */
4020 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
4021 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
4022         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
4023         { .irq = -1 }
4024 };
4025
4026 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4027         {
4028                 .pa_start       = 0x4a0dd000,
4029                 .pa_end         = 0x4a0dd03f,
4030                 .flags          = ADDR_TYPE_RT
4031         },
4032         { }
4033 };
4034
4035 /* l4_cfg -> smartreflex_core */
4036 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4037         .master         = &omap44xx_l4_cfg_hwmod,
4038         .slave          = &omap44xx_smartreflex_core_hwmod,
4039         .clk            = "l4_div_ck",
4040         .addr           = omap44xx_smartreflex_core_addrs,
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 /* smartreflex_core slave ports */
4045 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
4046         &omap44xx_l4_cfg__smartreflex_core,
4047 };
4048
4049 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4050         .name           = "smartreflex_core",
4051         .class          = &omap44xx_smartreflex_hwmod_class,
4052         .clkdm_name     = "l4_ao_clkdm",
4053         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
4054
4055         .main_clk       = "smartreflex_core_fck",
4056         .vdd_name       = "core",
4057         .prcm = {
4058                 .omap4 = {
4059                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4060                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4061                         .modulemode   = MODULEMODE_SWCTRL,
4062                 },
4063         },
4064         .slaves         = omap44xx_smartreflex_core_slaves,
4065         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4066         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4067 };
4068
4069 /* smartreflex_iva */
4070 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4071 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4072         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4073         { .irq = -1 }
4074 };
4075
4076 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4077         {
4078                 .pa_start       = 0x4a0db000,
4079                 .pa_end         = 0x4a0db03f,
4080                 .flags          = ADDR_TYPE_RT
4081         },
4082         { }
4083 };
4084
4085 /* l4_cfg -> smartreflex_iva */
4086 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4087         .master         = &omap44xx_l4_cfg_hwmod,
4088         .slave          = &omap44xx_smartreflex_iva_hwmod,
4089         .clk            = "l4_div_ck",
4090         .addr           = omap44xx_smartreflex_iva_addrs,
4091         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4092 };
4093
4094 /* smartreflex_iva slave ports */
4095 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4096         &omap44xx_l4_cfg__smartreflex_iva,
4097 };
4098
4099 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4100         .name           = "smartreflex_iva",
4101         .class          = &omap44xx_smartreflex_hwmod_class,
4102         .clkdm_name     = "l4_ao_clkdm",
4103         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4104         .main_clk       = "smartreflex_iva_fck",
4105         .vdd_name       = "iva",
4106         .prcm = {
4107                 .omap4 = {
4108                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4109                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4110                         .modulemode   = MODULEMODE_SWCTRL,
4111                 },
4112         },
4113         .slaves         = omap44xx_smartreflex_iva_slaves,
4114         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4115         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4116 };
4117
4118 /* smartreflex_mpu */
4119 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4120 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4121         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4122         { .irq = -1 }
4123 };
4124
4125 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4126         {
4127                 .pa_start       = 0x4a0d9000,
4128                 .pa_end         = 0x4a0d903f,
4129                 .flags          = ADDR_TYPE_RT
4130         },
4131         { }
4132 };
4133
4134 /* l4_cfg -> smartreflex_mpu */
4135 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4136         .master         = &omap44xx_l4_cfg_hwmod,
4137         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4138         .clk            = "l4_div_ck",
4139         .addr           = omap44xx_smartreflex_mpu_addrs,
4140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4141 };
4142
4143 /* smartreflex_mpu slave ports */
4144 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4145         &omap44xx_l4_cfg__smartreflex_mpu,
4146 };
4147
4148 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4149         .name           = "smartreflex_mpu",
4150         .class          = &omap44xx_smartreflex_hwmod_class,
4151         .clkdm_name     = "l4_ao_clkdm",
4152         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4153         .main_clk       = "smartreflex_mpu_fck",
4154         .vdd_name       = "mpu",
4155         .prcm = {
4156                 .omap4 = {
4157                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4158                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4159                         .modulemode   = MODULEMODE_SWCTRL,
4160                 },
4161         },
4162         .slaves         = omap44xx_smartreflex_mpu_slaves,
4163         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4164         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4165 };
4166
4167 /*
4168  * 'spinlock' class
4169  * spinlock provides hardware assistance for synchronizing the processes
4170  * running on multiple processors
4171  */
4172
4173 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4174         .rev_offs       = 0x0000,
4175         .sysc_offs      = 0x0010,
4176         .syss_offs      = 0x0014,
4177         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4178                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4179                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4180         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4181                            SIDLE_SMART_WKUP),
4182         .sysc_fields    = &omap_hwmod_sysc_type1,
4183 };
4184
4185 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4186         .name   = "spinlock",
4187         .sysc   = &omap44xx_spinlock_sysc,
4188 };
4189
4190 /* spinlock */
4191 static struct omap_hwmod omap44xx_spinlock_hwmod;
4192 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4193         {
4194                 .pa_start       = 0x4a0f6000,
4195                 .pa_end         = 0x4a0f6fff,
4196                 .flags          = ADDR_TYPE_RT
4197         },
4198         { }
4199 };
4200
4201 /* l4_cfg -> spinlock */
4202 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4203         .master         = &omap44xx_l4_cfg_hwmod,
4204         .slave          = &omap44xx_spinlock_hwmod,
4205         .clk            = "l4_div_ck",
4206         .addr           = omap44xx_spinlock_addrs,
4207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4208 };
4209
4210 /* spinlock slave ports */
4211 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4212         &omap44xx_l4_cfg__spinlock,
4213 };
4214
4215 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4216         .name           = "spinlock",
4217         .class          = &omap44xx_spinlock_hwmod_class,
4218         .clkdm_name     = "l4_cfg_clkdm",
4219         .prcm = {
4220                 .omap4 = {
4221                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4222                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4223                 },
4224         },
4225         .slaves         = omap44xx_spinlock_slaves,
4226         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4227         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4228 };
4229
4230 /*
4231  * 'timer' class
4232  * general purpose timer module with accurate 1ms tick
4233  * This class contains several variants: ['timer_1ms', 'timer']
4234  */
4235
4236 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4237         .rev_offs       = 0x0000,
4238         .sysc_offs      = 0x0010,
4239         .syss_offs      = 0x0014,
4240         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4241                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4242                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4243                            SYSS_HAS_RESET_STATUS),
4244         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4245         .sysc_fields    = &omap_hwmod_sysc_type1,
4246 };
4247
4248 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4249         .name   = "timer",
4250         .sysc   = &omap44xx_timer_1ms_sysc,
4251 };
4252
4253 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4254         .rev_offs       = 0x0000,
4255         .sysc_offs      = 0x0010,
4256         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4257                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4258         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4259                            SIDLE_SMART_WKUP),
4260         .sysc_fields    = &omap_hwmod_sysc_type2,
4261 };
4262
4263 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4264         .name   = "timer",
4265         .sysc   = &omap44xx_timer_sysc,
4266 };
4267
4268 /* timer1 */
4269 static struct omap_hwmod omap44xx_timer1_hwmod;
4270 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4271         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4272         { .irq = -1 }
4273 };
4274
4275 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4276         {
4277                 .pa_start       = 0x4a318000,
4278                 .pa_end         = 0x4a31807f,
4279                 .flags          = ADDR_TYPE_RT
4280         },
4281         { }
4282 };
4283
4284 /* l4_wkup -> timer1 */
4285 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4286         .master         = &omap44xx_l4_wkup_hwmod,
4287         .slave          = &omap44xx_timer1_hwmod,
4288         .clk            = "l4_wkup_clk_mux_ck",
4289         .addr           = omap44xx_timer1_addrs,
4290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4291 };
4292
4293 /* timer1 slave ports */
4294 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4295         &omap44xx_l4_wkup__timer1,
4296 };
4297
4298 static struct omap_hwmod omap44xx_timer1_hwmod = {
4299         .name           = "timer1",
4300         .class          = &omap44xx_timer_1ms_hwmod_class,
4301         .clkdm_name     = "l4_wkup_clkdm",
4302         .mpu_irqs       = omap44xx_timer1_irqs,
4303         .main_clk       = "timer1_fck",
4304         .prcm = {
4305                 .omap4 = {
4306                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4307                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4308                         .modulemode   = MODULEMODE_SWCTRL,
4309                 },
4310         },
4311         .slaves         = omap44xx_timer1_slaves,
4312         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4313         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4314 };
4315
4316 /* timer2 */
4317 static struct omap_hwmod omap44xx_timer2_hwmod;
4318 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4319         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4320         { .irq = -1 }
4321 };
4322
4323 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4324         {
4325                 .pa_start       = 0x48032000,
4326                 .pa_end         = 0x4803207f,
4327                 .flags          = ADDR_TYPE_RT
4328         },
4329         { }
4330 };
4331
4332 /* l4_per -> timer2 */
4333 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4334         .master         = &omap44xx_l4_per_hwmod,
4335         .slave          = &omap44xx_timer2_hwmod,
4336         .clk            = "l4_div_ck",
4337         .addr           = omap44xx_timer2_addrs,
4338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4339 };
4340
4341 /* timer2 slave ports */
4342 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4343         &omap44xx_l4_per__timer2,
4344 };
4345
4346 static struct omap_hwmod omap44xx_timer2_hwmod = {
4347         .name           = "timer2",
4348         .class          = &omap44xx_timer_1ms_hwmod_class,
4349         .clkdm_name     = "l4_per_clkdm",
4350         .mpu_irqs       = omap44xx_timer2_irqs,
4351         .main_clk       = "timer2_fck",
4352         .prcm = {
4353                 .omap4 = {
4354                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4355                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4356                         .modulemode   = MODULEMODE_SWCTRL,
4357                 },
4358         },
4359         .slaves         = omap44xx_timer2_slaves,
4360         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4361         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4362 };
4363
4364 /* timer3 */
4365 static struct omap_hwmod omap44xx_timer3_hwmod;
4366 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4367         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4368         { .irq = -1 }
4369 };
4370
4371 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4372         {
4373                 .pa_start       = 0x48034000,
4374                 .pa_end         = 0x4803407f,
4375                 .flags          = ADDR_TYPE_RT
4376         },
4377         { }
4378 };
4379
4380 /* l4_per -> timer3 */
4381 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4382         .master         = &omap44xx_l4_per_hwmod,
4383         .slave          = &omap44xx_timer3_hwmod,
4384         .clk            = "l4_div_ck",
4385         .addr           = omap44xx_timer3_addrs,
4386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4387 };
4388
4389 /* timer3 slave ports */
4390 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4391         &omap44xx_l4_per__timer3,
4392 };
4393
4394 static struct omap_hwmod omap44xx_timer3_hwmod = {
4395         .name           = "timer3",
4396         .class          = &omap44xx_timer_hwmod_class,
4397         .clkdm_name     = "l4_per_clkdm",
4398         .mpu_irqs       = omap44xx_timer3_irqs,
4399         .main_clk       = "timer3_fck",
4400         .prcm = {
4401                 .omap4 = {
4402                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4403                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4404                         .modulemode   = MODULEMODE_SWCTRL,
4405                 },
4406         },
4407         .slaves         = omap44xx_timer3_slaves,
4408         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4409         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4410 };
4411
4412 /* timer4 */
4413 static struct omap_hwmod omap44xx_timer4_hwmod;
4414 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4415         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4416         { .irq = -1 }
4417 };
4418
4419 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4420         {
4421                 .pa_start       = 0x48036000,
4422                 .pa_end         = 0x4803607f,
4423                 .flags          = ADDR_TYPE_RT
4424         },
4425         { }
4426 };
4427
4428 /* l4_per -> timer4 */
4429 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4430         .master         = &omap44xx_l4_per_hwmod,
4431         .slave          = &omap44xx_timer4_hwmod,
4432         .clk            = "l4_div_ck",
4433         .addr           = omap44xx_timer4_addrs,
4434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4435 };
4436
4437 /* timer4 slave ports */
4438 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4439         &omap44xx_l4_per__timer4,
4440 };
4441
4442 static struct omap_hwmod omap44xx_timer4_hwmod = {
4443         .name           = "timer4",
4444         .class          = &omap44xx_timer_hwmod_class,
4445         .clkdm_name     = "l4_per_clkdm",
4446         .mpu_irqs       = omap44xx_timer4_irqs,
4447         .main_clk       = "timer4_fck",
4448         .prcm = {
4449                 .omap4 = {
4450                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4451                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4452                         .modulemode   = MODULEMODE_SWCTRL,
4453                 },
4454         },
4455         .slaves         = omap44xx_timer4_slaves,
4456         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4457         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4458 };
4459
4460 /* timer5 */
4461 static struct omap_hwmod omap44xx_timer5_hwmod;
4462 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4463         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4464         { .irq = -1 }
4465 };
4466
4467 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4468         {
4469                 .pa_start       = 0x40138000,
4470                 .pa_end         = 0x4013807f,
4471                 .flags          = ADDR_TYPE_RT
4472         },
4473         { }
4474 };
4475
4476 /* l4_abe -> timer5 */
4477 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4478         .master         = &omap44xx_l4_abe_hwmod,
4479         .slave          = &omap44xx_timer5_hwmod,
4480         .clk            = "ocp_abe_iclk",
4481         .addr           = omap44xx_timer5_addrs,
4482         .user           = OCP_USER_MPU,
4483 };
4484
4485 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4486         {
4487                 .pa_start       = 0x49038000,
4488                 .pa_end         = 0x4903807f,
4489                 .flags          = ADDR_TYPE_RT
4490         },
4491         { }
4492 };
4493
4494 /* l4_abe -> timer5 (dma) */
4495 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4496         .master         = &omap44xx_l4_abe_hwmod,
4497         .slave          = &omap44xx_timer5_hwmod,
4498         .clk            = "ocp_abe_iclk",
4499         .addr           = omap44xx_timer5_dma_addrs,
4500         .user           = OCP_USER_SDMA,
4501 };
4502
4503 /* timer5 slave ports */
4504 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4505         &omap44xx_l4_abe__timer5,
4506         &omap44xx_l4_abe__timer5_dma,
4507 };
4508
4509 static struct omap_hwmod omap44xx_timer5_hwmod = {
4510         .name           = "timer5",
4511         .class          = &omap44xx_timer_hwmod_class,
4512         .clkdm_name     = "abe_clkdm",
4513         .mpu_irqs       = omap44xx_timer5_irqs,
4514         .main_clk       = "timer5_fck",
4515         .prcm = {
4516                 .omap4 = {
4517                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4518                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4519                         .modulemode   = MODULEMODE_SWCTRL,
4520                 },
4521         },
4522         .slaves         = omap44xx_timer5_slaves,
4523         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4525 };
4526
4527 /* timer6 */
4528 static struct omap_hwmod omap44xx_timer6_hwmod;
4529 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4530         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4531         { .irq = -1 }
4532 };
4533
4534 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4535         {
4536                 .pa_start       = 0x4013a000,
4537                 .pa_end         = 0x4013a07f,
4538                 .flags          = ADDR_TYPE_RT
4539         },
4540         { }
4541 };
4542
4543 /* l4_abe -> timer6 */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4545         .master         = &omap44xx_l4_abe_hwmod,
4546         .slave          = &omap44xx_timer6_hwmod,
4547         .clk            = "ocp_abe_iclk",
4548         .addr           = omap44xx_timer6_addrs,
4549         .user           = OCP_USER_MPU,
4550 };
4551
4552 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4553         {
4554                 .pa_start       = 0x4903a000,
4555                 .pa_end         = 0x4903a07f,
4556                 .flags          = ADDR_TYPE_RT
4557         },
4558         { }
4559 };
4560
4561 /* l4_abe -> timer6 (dma) */
4562 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4563         .master         = &omap44xx_l4_abe_hwmod,
4564         .slave          = &omap44xx_timer6_hwmod,
4565         .clk            = "ocp_abe_iclk",
4566         .addr           = omap44xx_timer6_dma_addrs,
4567         .user           = OCP_USER_SDMA,
4568 };
4569
4570 /* timer6 slave ports */
4571 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4572         &omap44xx_l4_abe__timer6,
4573         &omap44xx_l4_abe__timer6_dma,
4574 };
4575
4576 static struct omap_hwmod omap44xx_timer6_hwmod = {
4577         .name           = "timer6",
4578         .class          = &omap44xx_timer_hwmod_class,
4579         .clkdm_name     = "abe_clkdm",
4580         .mpu_irqs       = omap44xx_timer6_irqs,
4581
4582         .main_clk       = "timer6_fck",
4583         .prcm = {
4584                 .omap4 = {
4585                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4586                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4587                         .modulemode   = MODULEMODE_SWCTRL,
4588                 },
4589         },
4590         .slaves         = omap44xx_timer6_slaves,
4591         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4592         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4593 };
4594
4595 /* timer7 */
4596 static struct omap_hwmod omap44xx_timer7_hwmod;
4597 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4598         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4599         { .irq = -1 }
4600 };
4601
4602 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4603         {
4604                 .pa_start       = 0x4013c000,
4605                 .pa_end         = 0x4013c07f,
4606                 .flags          = ADDR_TYPE_RT
4607         },
4608         { }
4609 };
4610
4611 /* l4_abe -> timer7 */
4612 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4613         .master         = &omap44xx_l4_abe_hwmod,
4614         .slave          = &omap44xx_timer7_hwmod,
4615         .clk            = "ocp_abe_iclk",
4616         .addr           = omap44xx_timer7_addrs,
4617         .user           = OCP_USER_MPU,
4618 };
4619
4620 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4621         {
4622                 .pa_start       = 0x4903c000,
4623                 .pa_end         = 0x4903c07f,
4624                 .flags          = ADDR_TYPE_RT
4625         },
4626         { }
4627 };
4628
4629 /* l4_abe -> timer7 (dma) */
4630 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4631         .master         = &omap44xx_l4_abe_hwmod,
4632         .slave          = &omap44xx_timer7_hwmod,
4633         .clk            = "ocp_abe_iclk",
4634         .addr           = omap44xx_timer7_dma_addrs,
4635         .user           = OCP_USER_SDMA,
4636 };
4637
4638 /* timer7 slave ports */
4639 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4640         &omap44xx_l4_abe__timer7,
4641         &omap44xx_l4_abe__timer7_dma,
4642 };
4643
4644 static struct omap_hwmod omap44xx_timer7_hwmod = {
4645         .name           = "timer7",
4646         .class          = &omap44xx_timer_hwmod_class,
4647         .clkdm_name     = "abe_clkdm",
4648         .mpu_irqs       = omap44xx_timer7_irqs,
4649         .main_clk       = "timer7_fck",
4650         .prcm = {
4651                 .omap4 = {
4652                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4653                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4654                         .modulemode   = MODULEMODE_SWCTRL,
4655                 },
4656         },
4657         .slaves         = omap44xx_timer7_slaves,
4658         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4660 };
4661
4662 /* timer8 */
4663 static struct omap_hwmod omap44xx_timer8_hwmod;
4664 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4665         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4666         { .irq = -1 }
4667 };
4668
4669 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4670         {
4671                 .pa_start       = 0x4013e000,
4672                 .pa_end         = 0x4013e07f,
4673                 .flags          = ADDR_TYPE_RT
4674         },
4675         { }
4676 };
4677
4678 /* l4_abe -> timer8 */
4679 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4680         .master         = &omap44xx_l4_abe_hwmod,
4681         .slave          = &omap44xx_timer8_hwmod,
4682         .clk            = "ocp_abe_iclk",
4683         .addr           = omap44xx_timer8_addrs,
4684         .user           = OCP_USER_MPU,
4685 };
4686
4687 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4688         {
4689                 .pa_start       = 0x4903e000,
4690                 .pa_end         = 0x4903e07f,
4691                 .flags          = ADDR_TYPE_RT
4692         },
4693         { }
4694 };
4695
4696 /* l4_abe -> timer8 (dma) */
4697 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4698         .master         = &omap44xx_l4_abe_hwmod,
4699         .slave          = &omap44xx_timer8_hwmod,
4700         .clk            = "ocp_abe_iclk",
4701         .addr           = omap44xx_timer8_dma_addrs,
4702         .user           = OCP_USER_SDMA,
4703 };
4704
4705 /* timer8 slave ports */
4706 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4707         &omap44xx_l4_abe__timer8,
4708         &omap44xx_l4_abe__timer8_dma,
4709 };
4710
4711 static struct omap_hwmod omap44xx_timer8_hwmod = {
4712         .name           = "timer8",
4713         .class          = &omap44xx_timer_hwmod_class,
4714         .clkdm_name     = "abe_clkdm",
4715         .mpu_irqs       = omap44xx_timer8_irqs,
4716         .main_clk       = "timer8_fck",
4717         .prcm = {
4718                 .omap4 = {
4719                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4720                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4721                         .modulemode   = MODULEMODE_SWCTRL,
4722                 },
4723         },
4724         .slaves         = omap44xx_timer8_slaves,
4725         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4726         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4727 };
4728
4729 /* timer9 */
4730 static struct omap_hwmod omap44xx_timer9_hwmod;
4731 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4732         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4733         { .irq = -1 }
4734 };
4735
4736 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4737         {
4738                 .pa_start       = 0x4803e000,
4739                 .pa_end         = 0x4803e07f,
4740                 .flags          = ADDR_TYPE_RT
4741         },
4742         { }
4743 };
4744
4745 /* l4_per -> timer9 */
4746 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4747         .master         = &omap44xx_l4_per_hwmod,
4748         .slave          = &omap44xx_timer9_hwmod,
4749         .clk            = "l4_div_ck",
4750         .addr           = omap44xx_timer9_addrs,
4751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4752 };
4753
4754 /* timer9 slave ports */
4755 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4756         &omap44xx_l4_per__timer9,
4757 };
4758
4759 static struct omap_hwmod omap44xx_timer9_hwmod = {
4760         .name           = "timer9",
4761         .class          = &omap44xx_timer_hwmod_class,
4762         .clkdm_name     = "l4_per_clkdm",
4763         .mpu_irqs       = omap44xx_timer9_irqs,
4764         .main_clk       = "timer9_fck",
4765         .prcm = {
4766                 .omap4 = {
4767                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4768                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4769                         .modulemode   = MODULEMODE_SWCTRL,
4770                 },
4771         },
4772         .slaves         = omap44xx_timer9_slaves,
4773         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4774         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4775 };
4776
4777 /* timer10 */
4778 static struct omap_hwmod omap44xx_timer10_hwmod;
4779 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4780         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4781         { .irq = -1 }
4782 };
4783
4784 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4785         {
4786                 .pa_start       = 0x48086000,
4787                 .pa_end         = 0x4808607f,
4788                 .flags          = ADDR_TYPE_RT
4789         },
4790         { }
4791 };
4792
4793 /* l4_per -> timer10 */
4794 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4795         .master         = &omap44xx_l4_per_hwmod,
4796         .slave          = &omap44xx_timer10_hwmod,
4797         .clk            = "l4_div_ck",
4798         .addr           = omap44xx_timer10_addrs,
4799         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4800 };
4801
4802 /* timer10 slave ports */
4803 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4804         &omap44xx_l4_per__timer10,
4805 };
4806
4807 static struct omap_hwmod omap44xx_timer10_hwmod = {
4808         .name           = "timer10",
4809         .class          = &omap44xx_timer_1ms_hwmod_class,
4810         .clkdm_name     = "l4_per_clkdm",
4811         .mpu_irqs       = omap44xx_timer10_irqs,
4812         .main_clk       = "timer10_fck",
4813         .prcm = {
4814                 .omap4 = {
4815                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4816                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4817                         .modulemode   = MODULEMODE_SWCTRL,
4818                 },
4819         },
4820         .slaves         = omap44xx_timer10_slaves,
4821         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4822         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4823 };
4824
4825 /* timer11 */
4826 static struct omap_hwmod omap44xx_timer11_hwmod;
4827 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4828         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4829         { .irq = -1 }
4830 };
4831
4832 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4833         {
4834                 .pa_start       = 0x48088000,
4835                 .pa_end         = 0x4808807f,
4836                 .flags          = ADDR_TYPE_RT
4837         },
4838         { }
4839 };
4840
4841 /* l4_per -> timer11 */
4842 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4843         .master         = &omap44xx_l4_per_hwmod,
4844         .slave          = &omap44xx_timer11_hwmod,
4845         .clk            = "l4_div_ck",
4846         .addr           = omap44xx_timer11_addrs,
4847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4848 };
4849
4850 /* timer11 slave ports */
4851 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4852         &omap44xx_l4_per__timer11,
4853 };
4854
4855 static struct omap_hwmod omap44xx_timer11_hwmod = {
4856         .name           = "timer11",
4857         .class          = &omap44xx_timer_hwmod_class,
4858         .clkdm_name     = "l4_per_clkdm",
4859         .mpu_irqs       = omap44xx_timer11_irqs,
4860         .main_clk       = "timer11_fck",
4861         .prcm = {
4862                 .omap4 = {
4863                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4864                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4865                         .modulemode   = MODULEMODE_SWCTRL,
4866                 },
4867         },
4868         .slaves         = omap44xx_timer11_slaves,
4869         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4870         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4871 };
4872
4873 /*
4874  * 'uart' class
4875  * universal asynchronous receiver/transmitter (uart)
4876  */
4877
4878 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4879         .rev_offs       = 0x0050,
4880         .sysc_offs      = 0x0054,
4881         .syss_offs      = 0x0058,
4882         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4883                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4884                            SYSS_HAS_RESET_STATUS),
4885         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4886                            SIDLE_SMART_WKUP),
4887         .sysc_fields    = &omap_hwmod_sysc_type1,
4888 };
4889
4890 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4891         .name   = "uart",
4892         .sysc   = &omap44xx_uart_sysc,
4893 };
4894
4895 /* uart1 */
4896 static struct omap_hwmod omap44xx_uart1_hwmod;
4897 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4898         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4899         { .irq = -1 }
4900 };
4901
4902 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4903         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4904         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4905         { .dma_req = -1 }
4906 };
4907
4908 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4909         {
4910                 .pa_start       = 0x4806a000,
4911                 .pa_end         = 0x4806a0ff,
4912                 .flags          = ADDR_TYPE_RT
4913         },
4914         { }
4915 };
4916
4917 /* l4_per -> uart1 */
4918 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4919         .master         = &omap44xx_l4_per_hwmod,
4920         .slave          = &omap44xx_uart1_hwmod,
4921         .clk            = "l4_div_ck",
4922         .addr           = omap44xx_uart1_addrs,
4923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4924 };
4925
4926 /* uart1 slave ports */
4927 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4928         &omap44xx_l4_per__uart1,
4929 };
4930
4931 static struct omap_hwmod omap44xx_uart1_hwmod = {
4932         .name           = "uart1",
4933         .class          = &omap44xx_uart_hwmod_class,
4934         .clkdm_name     = "l4_per_clkdm",
4935         .mpu_irqs       = omap44xx_uart1_irqs,
4936         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4937         .main_clk       = "uart1_fck",
4938         .prcm = {
4939                 .omap4 = {
4940                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4941                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4942                         .modulemode   = MODULEMODE_SWCTRL,
4943                 },
4944         },
4945         .slaves         = omap44xx_uart1_slaves,
4946         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4947         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4948 };
4949
4950 /* uart2 */
4951 static struct omap_hwmod omap44xx_uart2_hwmod;
4952 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4953         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4954         { .irq = -1 }
4955 };
4956
4957 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4958         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4959         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4960         { .dma_req = -1 }
4961 };
4962
4963 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4964         {
4965                 .pa_start       = 0x4806c000,
4966                 .pa_end         = 0x4806c0ff,
4967                 .flags          = ADDR_TYPE_RT
4968         },
4969         { }
4970 };
4971
4972 /* l4_per -> uart2 */
4973 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4974         .master         = &omap44xx_l4_per_hwmod,
4975         .slave          = &omap44xx_uart2_hwmod,
4976         .clk            = "l4_div_ck",
4977         .addr           = omap44xx_uart2_addrs,
4978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4979 };
4980
4981 /* uart2 slave ports */
4982 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4983         &omap44xx_l4_per__uart2,
4984 };
4985
4986 static struct omap_hwmod omap44xx_uart2_hwmod = {
4987         .name           = "uart2",
4988         .class          = &omap44xx_uart_hwmod_class,
4989         .clkdm_name     = "l4_per_clkdm",
4990         .mpu_irqs       = omap44xx_uart2_irqs,
4991         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4992         .main_clk       = "uart2_fck",
4993         .prcm = {
4994                 .omap4 = {
4995                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4996                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4997                         .modulemode   = MODULEMODE_SWCTRL,
4998                 },
4999         },
5000         .slaves         = omap44xx_uart2_slaves,
5001         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
5002         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5003 };
5004
5005 /* uart3 */
5006 static struct omap_hwmod omap44xx_uart3_hwmod;
5007 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
5008         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
5009         { .irq = -1 }
5010 };
5011
5012 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
5013         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
5014         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
5015         { .dma_req = -1 }
5016 };
5017
5018 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5019         {
5020                 .pa_start       = 0x48020000,
5021                 .pa_end         = 0x480200ff,
5022                 .flags          = ADDR_TYPE_RT
5023         },
5024         { }
5025 };
5026
5027 /* l4_per -> uart3 */
5028 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5029         .master         = &omap44xx_l4_per_hwmod,
5030         .slave          = &omap44xx_uart3_hwmod,
5031         .clk            = "l4_div_ck",
5032         .addr           = omap44xx_uart3_addrs,
5033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5034 };
5035
5036 /* uart3 slave ports */
5037 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
5038         &omap44xx_l4_per__uart3,
5039 };
5040
5041 static struct omap_hwmod omap44xx_uart3_hwmod = {
5042         .name           = "uart3",
5043         .class          = &omap44xx_uart_hwmod_class,
5044         .clkdm_name     = "l4_per_clkdm",
5045         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5046         .mpu_irqs       = omap44xx_uart3_irqs,
5047         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
5048         .main_clk       = "uart3_fck",
5049         .prcm = {
5050                 .omap4 = {
5051                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5052                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5053                         .modulemode   = MODULEMODE_SWCTRL,
5054                 },
5055         },
5056         .slaves         = omap44xx_uart3_slaves,
5057         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
5058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5059 };
5060
5061 /* uart4 */
5062 static struct omap_hwmod omap44xx_uart4_hwmod;
5063 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5064         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5065         { .irq = -1 }
5066 };
5067
5068 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5069         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5070         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5071         { .dma_req = -1 }
5072 };
5073
5074 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5075         {
5076                 .pa_start       = 0x4806e000,
5077                 .pa_end         = 0x4806e0ff,
5078                 .flags          = ADDR_TYPE_RT
5079         },
5080         { }
5081 };
5082
5083 /* l4_per -> uart4 */
5084 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5085         .master         = &omap44xx_l4_per_hwmod,
5086         .slave          = &omap44xx_uart4_hwmod,
5087         .clk            = "l4_div_ck",
5088         .addr           = omap44xx_uart4_addrs,
5089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5090 };
5091
5092 /* uart4 slave ports */
5093 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5094         &omap44xx_l4_per__uart4,
5095 };
5096
5097 static struct omap_hwmod omap44xx_uart4_hwmod = {
5098         .name           = "uart4",
5099         .class          = &omap44xx_uart_hwmod_class,
5100         .clkdm_name     = "l4_per_clkdm",
5101         .mpu_irqs       = omap44xx_uart4_irqs,
5102         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5103         .main_clk       = "uart4_fck",
5104         .prcm = {
5105                 .omap4 = {
5106                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5107                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5108                         .modulemode   = MODULEMODE_SWCTRL,
5109                 },
5110         },
5111         .slaves         = omap44xx_uart4_slaves,
5112         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5114 };
5115
5116 /*
5117  * 'usb_otg_hs' class
5118  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5119  */
5120
5121 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5122         .rev_offs       = 0x0400,
5123         .sysc_offs      = 0x0404,
5124         .syss_offs      = 0x0408,
5125         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5126                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5127                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5128         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5129                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5130                            MSTANDBY_SMART),
5131         .sysc_fields    = &omap_hwmod_sysc_type1,
5132 };
5133
5134 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5135         .name   = "usb_otg_hs",
5136         .sysc   = &omap44xx_usb_otg_hs_sysc,
5137 };
5138
5139 /* usb_otg_hs */
5140 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5141         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5142         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5143         { .irq = -1 }
5144 };
5145
5146 /* usb_otg_hs master ports */
5147 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5148         &omap44xx_usb_otg_hs__l3_main_2,
5149 };
5150
5151 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5152         {
5153                 .pa_start       = 0x4a0ab000,
5154                 .pa_end         = 0x4a0ab003,
5155                 .flags          = ADDR_TYPE_RT
5156         },
5157         { }
5158 };
5159
5160 /* l4_cfg -> usb_otg_hs */
5161 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5162         .master         = &omap44xx_l4_cfg_hwmod,
5163         .slave          = &omap44xx_usb_otg_hs_hwmod,
5164         .clk            = "l4_div_ck",
5165         .addr           = omap44xx_usb_otg_hs_addrs,
5166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5167 };
5168
5169 /* usb_otg_hs slave ports */
5170 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5171         &omap44xx_l4_cfg__usb_otg_hs,
5172 };
5173
5174 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5175         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5176 };
5177
5178 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5179         .name           = "usb_otg_hs",
5180         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5181         .clkdm_name     = "l3_init_clkdm",
5182         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5183         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5184         .main_clk       = "usb_otg_hs_ick",
5185         .prcm = {
5186                 .omap4 = {
5187                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5188                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5189                         .modulemode   = MODULEMODE_HWCTRL,
5190                 },
5191         },
5192         .opt_clks       = usb_otg_hs_opt_clks,
5193         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5194         .slaves         = omap44xx_usb_otg_hs_slaves,
5195         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5196         .masters        = omap44xx_usb_otg_hs_masters,
5197         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5198         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5199 };
5200
5201 /*
5202  * 'wd_timer' class
5203  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5204  * overflow condition
5205  */
5206
5207 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5208         .rev_offs       = 0x0000,
5209         .sysc_offs      = 0x0010,
5210         .syss_offs      = 0x0014,
5211         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5212                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5213         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5214                            SIDLE_SMART_WKUP),
5215         .sysc_fields    = &omap_hwmod_sysc_type1,
5216 };
5217
5218 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5219         .name           = "wd_timer",
5220         .sysc           = &omap44xx_wd_timer_sysc,
5221         .pre_shutdown   = &omap2_wd_timer_disable,
5222 };
5223
5224 /* wd_timer2 */
5225 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5226 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5227         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5228         { .irq = -1 }
5229 };
5230
5231 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5232         {
5233                 .pa_start       = 0x4a314000,
5234                 .pa_end         = 0x4a31407f,
5235                 .flags          = ADDR_TYPE_RT
5236         },
5237         { }
5238 };
5239
5240 /* l4_wkup -> wd_timer2 */
5241 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5242         .master         = &omap44xx_l4_wkup_hwmod,
5243         .slave          = &omap44xx_wd_timer2_hwmod,
5244         .clk            = "l4_wkup_clk_mux_ck",
5245         .addr           = omap44xx_wd_timer2_addrs,
5246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5247 };
5248
5249 /* wd_timer2 slave ports */
5250 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5251         &omap44xx_l4_wkup__wd_timer2,
5252 };
5253
5254 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5255         .name           = "wd_timer2",
5256         .class          = &omap44xx_wd_timer_hwmod_class,
5257         .clkdm_name     = "l4_wkup_clkdm",
5258         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5259         .main_clk       = "wd_timer2_fck",
5260         .prcm = {
5261                 .omap4 = {
5262                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5263                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5264                         .modulemode   = MODULEMODE_SWCTRL,
5265                 },
5266         },
5267         .slaves         = omap44xx_wd_timer2_slaves,
5268         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5269         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5270 };
5271
5272 /* wd_timer3 */
5273 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5274 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5275         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5276         { .irq = -1 }
5277 };
5278
5279 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5280         {
5281                 .pa_start       = 0x40130000,
5282                 .pa_end         = 0x4013007f,
5283                 .flags          = ADDR_TYPE_RT
5284         },
5285         { }
5286 };
5287
5288 /* l4_abe -> wd_timer3 */
5289 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5290         .master         = &omap44xx_l4_abe_hwmod,
5291         .slave          = &omap44xx_wd_timer3_hwmod,
5292         .clk            = "ocp_abe_iclk",
5293         .addr           = omap44xx_wd_timer3_addrs,
5294         .user           = OCP_USER_MPU,
5295 };
5296
5297 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5298         {
5299                 .pa_start       = 0x49030000,
5300                 .pa_end         = 0x4903007f,
5301                 .flags          = ADDR_TYPE_RT
5302         },
5303         { }
5304 };
5305
5306 /* l4_abe -> wd_timer3 (dma) */
5307 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5308         .master         = &omap44xx_l4_abe_hwmod,
5309         .slave          = &omap44xx_wd_timer3_hwmod,
5310         .clk            = "ocp_abe_iclk",
5311         .addr           = omap44xx_wd_timer3_dma_addrs,
5312         .user           = OCP_USER_SDMA,
5313 };
5314
5315 /* wd_timer3 slave ports */
5316 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5317         &omap44xx_l4_abe__wd_timer3,
5318         &omap44xx_l4_abe__wd_timer3_dma,
5319 };
5320
5321 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5322         .name           = "wd_timer3",
5323         .class          = &omap44xx_wd_timer_hwmod_class,
5324         .clkdm_name     = "abe_clkdm",
5325         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5326         .main_clk       = "wd_timer3_fck",
5327         .prcm = {
5328                 .omap4 = {
5329                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5330                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5331                         .modulemode   = MODULEMODE_SWCTRL,
5332                 },
5333         },
5334         .slaves         = omap44xx_wd_timer3_slaves,
5335         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5336         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5337 };
5338
5339 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5340
5341         /* dmm class */
5342         &omap44xx_dmm_hwmod,
5343
5344         /* emif_fw class */
5345         &omap44xx_emif_fw_hwmod,
5346
5347         /* l3 class */
5348         &omap44xx_l3_instr_hwmod,
5349         &omap44xx_l3_main_1_hwmod,
5350         &omap44xx_l3_main_2_hwmod,
5351         &omap44xx_l3_main_3_hwmod,
5352
5353         /* l4 class */
5354         &omap44xx_l4_abe_hwmod,
5355         &omap44xx_l4_cfg_hwmod,
5356         &omap44xx_l4_per_hwmod,
5357         &omap44xx_l4_wkup_hwmod,
5358
5359         /* mpu_bus class */
5360         &omap44xx_mpu_private_hwmod,
5361
5362         /* aess class */
5363 /*      &omap44xx_aess_hwmod, */
5364
5365         /* bandgap class */
5366         &omap44xx_bandgap_hwmod,
5367
5368         /* counter class */
5369 /*      &omap44xx_counter_32k_hwmod, */
5370
5371         /* dma class */
5372         &omap44xx_dma_system_hwmod,
5373
5374         /* dmic class */
5375         &omap44xx_dmic_hwmod,
5376
5377         /* dsp class */
5378         &omap44xx_dsp_hwmod,
5379         &omap44xx_dsp_c0_hwmod,
5380
5381         /* dss class */
5382         &omap44xx_dss_hwmod,
5383         &omap44xx_dss_dispc_hwmod,
5384         &omap44xx_dss_dsi1_hwmod,
5385         &omap44xx_dss_dsi2_hwmod,
5386         &omap44xx_dss_hdmi_hwmod,
5387         &omap44xx_dss_rfbi_hwmod,
5388         &omap44xx_dss_venc_hwmod,
5389
5390         /* gpio class */
5391         &omap44xx_gpio1_hwmod,
5392         &omap44xx_gpio2_hwmod,
5393         &omap44xx_gpio3_hwmod,
5394         &omap44xx_gpio4_hwmod,
5395         &omap44xx_gpio5_hwmod,
5396         &omap44xx_gpio6_hwmod,
5397
5398         /* hsi class */
5399 /*      &omap44xx_hsi_hwmod, */
5400
5401         /* i2c class */
5402         &omap44xx_i2c1_hwmod,
5403         &omap44xx_i2c2_hwmod,
5404         &omap44xx_i2c3_hwmod,
5405         &omap44xx_i2c4_hwmod,
5406
5407         /* ipu class */
5408         &omap44xx_ipu_hwmod,
5409         &omap44xx_ipu_c0_hwmod,
5410         &omap44xx_ipu_c1_hwmod,
5411
5412         /* iss class */
5413 /*      &omap44xx_iss_hwmod, */
5414
5415         /* iva class */
5416         &omap44xx_iva_hwmod,
5417         &omap44xx_iva_seq0_hwmod,
5418         &omap44xx_iva_seq1_hwmod,
5419
5420         /* kbd class */
5421         &omap44xx_kbd_hwmod,
5422
5423         /* mailbox class */
5424         &omap44xx_mailbox_hwmod,
5425
5426         /* mcbsp class */
5427         &omap44xx_mcbsp1_hwmod,
5428         &omap44xx_mcbsp2_hwmod,
5429         &omap44xx_mcbsp3_hwmod,
5430         &omap44xx_mcbsp4_hwmod,
5431
5432         /* mcpdm class */
5433         &omap44xx_mcpdm_hwmod,
5434
5435         /* mcspi class */
5436         &omap44xx_mcspi1_hwmod,
5437         &omap44xx_mcspi2_hwmod,
5438         &omap44xx_mcspi3_hwmod,
5439         &omap44xx_mcspi4_hwmod,
5440
5441         /* mmc class */
5442         &omap44xx_mmc1_hwmod,
5443         &omap44xx_mmc2_hwmod,
5444         &omap44xx_mmc3_hwmod,
5445         &omap44xx_mmc4_hwmod,
5446         &omap44xx_mmc5_hwmod,
5447
5448         /* mpu class */
5449         &omap44xx_mpu_hwmod,
5450
5451         /* smartreflex class */
5452         &omap44xx_smartreflex_core_hwmod,
5453         &omap44xx_smartreflex_iva_hwmod,
5454         &omap44xx_smartreflex_mpu_hwmod,
5455
5456         /* spinlock class */
5457         &omap44xx_spinlock_hwmod,
5458
5459         /* timer class */
5460         &omap44xx_timer1_hwmod,
5461         &omap44xx_timer2_hwmod,
5462         &omap44xx_timer3_hwmod,
5463         &omap44xx_timer4_hwmod,
5464         &omap44xx_timer5_hwmod,
5465         &omap44xx_timer6_hwmod,
5466         &omap44xx_timer7_hwmod,
5467         &omap44xx_timer8_hwmod,
5468         &omap44xx_timer9_hwmod,
5469         &omap44xx_timer10_hwmod,
5470         &omap44xx_timer11_hwmod,
5471
5472         /* uart class */
5473         &omap44xx_uart1_hwmod,
5474         &omap44xx_uart2_hwmod,
5475         &omap44xx_uart3_hwmod,
5476         &omap44xx_uart4_hwmod,
5477
5478         /* usb_otg_hs class */
5479         &omap44xx_usb_otg_hs_hwmod,
5480
5481         /* wd_timer class */
5482         &omap44xx_wd_timer2_hwmod,
5483         &omap44xx_wd_timer3_hwmod,
5484
5485         NULL,
5486 };
5487
5488 int __init omap44xx_hwmod_init(void)
5489 {
5490         return omap_hwmod_register(omap44xx_hwmods);
5491 }
5492