arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/i2c.h>
  32
  33 #include "omap_hwmod_common_data.h"
  34
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /* Backward references (IPs with Bus Master capability) */
  48 static struct omap_hwmod omap44xx_aess_hwmod;
  49 static struct omap_hwmod omap44xx_dma_system_hwmod;
  50 static struct omap_hwmod omap44xx_dmm_hwmod;
  51 static struct omap_hwmod omap44xx_dsp_hwmod;
  52 static struct omap_hwmod omap44xx_dss_hwmod;
  53 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  54 static struct omap_hwmod omap44xx_hsi_hwmod;
  55 static struct omap_hwmod omap44xx_ipu_hwmod;
  56 static struct omap_hwmod omap44xx_iss_hwmod;
  57 static struct omap_hwmod omap44xx_iva_hwmod;
  58 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  60 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  62 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  63 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  64 static struct omap_hwmod omap44xx_l4_per_hwmod;
  65 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  66 static struct omap_hwmod omap44xx_mmc1_hwmod;
  67 static struct omap_hwmod omap44xx_mmc2_hwmod;
  68 static struct omap_hwmod omap44xx_mpu_hwmod;
  69 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  70 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  71
  72 /*
  73  * Interconnects omap_hwmod structures
  74  * hwmods that compose the global OMAP interconnect
  75  */
  76
  77 /*
  78  * 'dmm' class
  79  * instance(s): dmm
  80  */
  81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  82         .name   = "dmm",
  83 };
  84
  85 /* dmm */
  86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  88         { .irq = -1 }
  89 };
  90
  91 /* l3_main_1 -> dmm */
  92 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  93         .master         = &omap44xx_l3_main_1_hwmod,
  94         .slave          = &omap44xx_dmm_hwmod,
  95         .clk            = "l3_div_ck",
  96         .user           = OCP_USER_SDMA,
  97 };
  98
  99 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 100         {
 101                 .pa_start       = 0x4e000000,
 102                 .pa_end         = 0x4e0007ff,
 103                 .flags          = ADDR_TYPE_RT
 104         },
 105         { }
 106 };
 107
 108 /* mpu -> dmm */
 109 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 110         .master         = &omap44xx_mpu_hwmod,
 111         .slave          = &omap44xx_dmm_hwmod,
 112         .clk            = "l3_div_ck",
 113         .addr           = omap44xx_dmm_addrs,
 114         .user           = OCP_USER_MPU,
 115 };
 116
 117 /* dmm slave ports */
 118 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 119         &omap44xx_l3_main_1__dmm,
 120         &omap44xx_mpu__dmm,
 121 };
 122
 123 static struct omap_hwmod omap44xx_dmm_hwmod = {
 124         .name           = "dmm",
 125         .class          = &omap44xx_dmm_hwmod_class,
 126         .clkdm_name     = "l3_emif_clkdm",
 127         .prcm = {
 128                 .omap4 = {
 129                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 130                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 131                 },
 132         },
 133         .slaves         = omap44xx_dmm_slaves,
 134         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 135         .mpu_irqs       = omap44xx_dmm_irqs,
 136 };
 137
 138 /*
 139  * 'emif_fw' class
 140  * instance(s): emif_fw
 141  */
 142 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 143         .name   = "emif_fw",
 144 };
 145
 146 /* emif_fw */
 147 /* dmm -> emif_fw */
 148 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 149         .master         = &omap44xx_dmm_hwmod,
 150         .slave          = &omap44xx_emif_fw_hwmod,
 151         .clk            = "l3_div_ck",
 152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 153 };
 154
 155 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 156         {
 157                 .pa_start       = 0x4a20c000,
 158                 .pa_end         = 0x4a20c0ff,
 159                 .flags          = ADDR_TYPE_RT
 160         },
 161         { }
 162 };
 163
 164 /* l4_cfg -> emif_fw */
 165 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 166         .master         = &omap44xx_l4_cfg_hwmod,
 167         .slave          = &omap44xx_emif_fw_hwmod,
 168         .clk            = "l4_div_ck",
 169         .addr           = omap44xx_emif_fw_addrs,
 170         .user           = OCP_USER_MPU,
 171 };
 172
 173 /* emif_fw slave ports */
 174 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 175         &omap44xx_dmm__emif_fw,
 176         &omap44xx_l4_cfg__emif_fw,
 177 };
 178
 179 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 180         .name           = "emif_fw",
 181         .class          = &omap44xx_emif_fw_hwmod_class,
 182         .clkdm_name     = "l3_emif_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 187                 },
 188         },
 189         .slaves         = omap44xx_emif_fw_slaves,
 190         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 191 };
 192
 193 /*
 194  * 'l3' class
 195  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 196  */
 197 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 198         .name   = "l3",
 199 };
 200
 201 /* l3_instr */
 202 /* iva -> l3_instr */
 203 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 204         .master         = &omap44xx_iva_hwmod,
 205         .slave          = &omap44xx_l3_instr_hwmod,
 206         .clk            = "l3_div_ck",
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208 };
 209
 210 /* l3_main_3 -> l3_instr */
 211 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 212         .master         = &omap44xx_l3_main_3_hwmod,
 213         .slave          = &omap44xx_l3_instr_hwmod,
 214         .clk            = "l3_div_ck",
 215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 216 };
 217
 218 /* l3_instr slave ports */
 219 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 220         &omap44xx_iva__l3_instr,
 221         &omap44xx_l3_main_3__l3_instr,
 222 };
 223
 224 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 225         .name           = "l3_instr",
 226         .class          = &omap44xx_l3_hwmod_class,
 227         .clkdm_name     = "l3_instr_clkdm",
 228         .prcm = {
 229                 .omap4 = {
 230                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 231                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 232                         .modulemode   = MODULEMODE_HWCTRL,
 233                 },
 234         },
 235         .slaves         = omap44xx_l3_instr_slaves,
 236         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 237 };
 238
 239 /* l3_main_1 */
 240 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 241         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 242         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 243         { .irq = -1 }
 244 };
 245
 246 /* dsp -> l3_main_1 */
 247 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 248         .master         = &omap44xx_dsp_hwmod,
 249         .slave          = &omap44xx_l3_main_1_hwmod,
 250         .clk            = "l3_div_ck",
 251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 252 };
 253
 254 /* dss -> l3_main_1 */
 255 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 256         .master         = &omap44xx_dss_hwmod,
 257         .slave          = &omap44xx_l3_main_1_hwmod,
 258         .clk            = "l3_div_ck",
 259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 260 };
 261
 262 /* l3_main_2 -> l3_main_1 */
 263 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 264         .master         = &omap44xx_l3_main_2_hwmod,
 265         .slave          = &omap44xx_l3_main_1_hwmod,
 266         .clk            = "l3_div_ck",
 267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 268 };
 269
 270 /* l4_cfg -> l3_main_1 */
 271 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 272         .master         = &omap44xx_l4_cfg_hwmod,
 273         .slave          = &omap44xx_l3_main_1_hwmod,
 274         .clk            = "l4_div_ck",
 275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 276 };
 277
 278 /* mmc1 -> l3_main_1 */
 279 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 280         .master         = &omap44xx_mmc1_hwmod,
 281         .slave          = &omap44xx_l3_main_1_hwmod,
 282         .clk            = "l3_div_ck",
 283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 284 };
 285
 286 /* mmc2 -> l3_main_1 */
 287 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 288         .master         = &omap44xx_mmc2_hwmod,
 289         .slave          = &omap44xx_l3_main_1_hwmod,
 290         .clk            = "l3_div_ck",
 291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 292 };
 293
 294 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 295         {
 296                 .pa_start       = 0x44000000,
 297                 .pa_end         = 0x44000fff,
 298                 .flags          = ADDR_TYPE_RT
 299         },
 300         { }
 301 };
 302
 303 /* mpu -> l3_main_1 */
 304 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 305         .master         = &omap44xx_mpu_hwmod,
 306         .slave          = &omap44xx_l3_main_1_hwmod,
 307         .clk            = "l3_div_ck",
 308         .addr           = omap44xx_l3_main_1_addrs,
 309         .user           = OCP_USER_MPU,
 310 };
 311
 312 /* l3_main_1 slave ports */
 313 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 314         &omap44xx_dsp__l3_main_1,
 315         &omap44xx_dss__l3_main_1,
 316         &omap44xx_l3_main_2__l3_main_1,
 317         &omap44xx_l4_cfg__l3_main_1,
 318         &omap44xx_mmc1__l3_main_1,
 319         &omap44xx_mmc2__l3_main_1,
 320         &omap44xx_mpu__l3_main_1,
 321 };
 322
 323 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 324         .name           = "l3_main_1",
 325         .class          = &omap44xx_l3_hwmod_class,
 326         .clkdm_name     = "l3_1_clkdm",
 327         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 328         .prcm = {
 329                 .omap4 = {
 330                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 331                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 332                 },
 333         },
 334         .slaves         = omap44xx_l3_main_1_slaves,
 335         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 336 };
 337
 338 /* l3_main_2 */
 339 /* dma_system -> l3_main_2 */
 340 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 341         .master         = &omap44xx_dma_system_hwmod,
 342         .slave          = &omap44xx_l3_main_2_hwmod,
 343         .clk            = "l3_div_ck",
 344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 345 };
 346
 347 /* hsi -> l3_main_2 */
 348 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 349         .master         = &omap44xx_hsi_hwmod,
 350         .slave          = &omap44xx_l3_main_2_hwmod,
 351         .clk            = "l3_div_ck",
 352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 353 };
 354
 355 /* ipu -> l3_main_2 */
 356 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 357         .master         = &omap44xx_ipu_hwmod,
 358         .slave          = &omap44xx_l3_main_2_hwmod,
 359         .clk            = "l3_div_ck",
 360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 361 };
 362
 363 /* iss -> l3_main_2 */
 364 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 365         .master         = &omap44xx_iss_hwmod,
 366         .slave          = &omap44xx_l3_main_2_hwmod,
 367         .clk            = "l3_div_ck",
 368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 369 };
 370
 371 /* iva -> l3_main_2 */
 372 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 373         .master         = &omap44xx_iva_hwmod,
 374         .slave          = &omap44xx_l3_main_2_hwmod,
 375         .clk            = "l3_div_ck",
 376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 377 };
 378
 379 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 380         {
 381                 .pa_start       = 0x44800000,
 382                 .pa_end         = 0x44801fff,
 383                 .flags          = ADDR_TYPE_RT
 384         },
 385         { }
 386 };
 387
 388 /* l3_main_1 -> l3_main_2 */
 389 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 390         .master         = &omap44xx_l3_main_1_hwmod,
 391         .slave          = &omap44xx_l3_main_2_hwmod,
 392         .clk            = "l3_div_ck",
 393         .addr           = omap44xx_l3_main_2_addrs,
 394         .user           = OCP_USER_MPU,
 395 };
 396
 397 /* l4_cfg -> l3_main_2 */
 398 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 399         .master         = &omap44xx_l4_cfg_hwmod,
 400         .slave          = &omap44xx_l3_main_2_hwmod,
 401         .clk            = "l4_div_ck",
 402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 403 };
 404
 405 /* usb_otg_hs -> l3_main_2 */
 406 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 407         .master         = &omap44xx_usb_otg_hs_hwmod,
 408         .slave          = &omap44xx_l3_main_2_hwmod,
 409         .clk            = "l3_div_ck",
 410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 411 };
 412
 413 /* l3_main_2 slave ports */
 414 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 415         &omap44xx_dma_system__l3_main_2,
 416         &omap44xx_hsi__l3_main_2,
 417         &omap44xx_ipu__l3_main_2,
 418         &omap44xx_iss__l3_main_2,
 419         &omap44xx_iva__l3_main_2,
 420         &omap44xx_l3_main_1__l3_main_2,
 421         &omap44xx_l4_cfg__l3_main_2,
 422         &omap44xx_usb_otg_hs__l3_main_2,
 423 };
 424
 425 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 426         .name           = "l3_main_2",
 427         .class          = &omap44xx_l3_hwmod_class,
 428         .clkdm_name     = "l3_2_clkdm",
 429         .prcm = {
 430                 .omap4 = {
 431                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 432                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 433                 },
 434         },
 435         .slaves         = omap44xx_l3_main_2_slaves,
 436         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 437 };
 438
 439 /* l3_main_3 */
 440 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 441         {
 442                 .pa_start       = 0x45000000,
 443                 .pa_end         = 0x45000fff,
 444                 .flags          = ADDR_TYPE_RT
 445         },
 446         { }
 447 };
 448
 449 /* l3_main_1 -> l3_main_3 */
 450 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 451         .master         = &omap44xx_l3_main_1_hwmod,
 452         .slave          = &omap44xx_l3_main_3_hwmod,
 453         .clk            = "l3_div_ck",
 454         .addr           = omap44xx_l3_main_3_addrs,
 455         .user           = OCP_USER_MPU,
 456 };
 457
 458 /* l3_main_2 -> l3_main_3 */
 459 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 460         .master         = &omap44xx_l3_main_2_hwmod,
 461         .slave          = &omap44xx_l3_main_3_hwmod,
 462         .clk            = "l3_div_ck",
 463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 464 };
 465
 466 /* l4_cfg -> l3_main_3 */
 467 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 468         .master         = &omap44xx_l4_cfg_hwmod,
 469         .slave          = &omap44xx_l3_main_3_hwmod,
 470         .clk            = "l4_div_ck",
 471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 472 };
 473
 474 /* l3_main_3 slave ports */
 475 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 476         &omap44xx_l3_main_1__l3_main_3,
 477         &omap44xx_l3_main_2__l3_main_3,
 478         &omap44xx_l4_cfg__l3_main_3,
 479 };
 480
 481 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 482         .name           = "l3_main_3",
 483         .class          = &omap44xx_l3_hwmod_class,
 484         .clkdm_name     = "l3_instr_clkdm",
 485         .prcm = {
 486                 .omap4 = {
 487                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 488                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 489                         .modulemode   = MODULEMODE_HWCTRL,
 490                 },
 491         },
 492         .slaves         = omap44xx_l3_main_3_slaves,
 493         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 494 };
 495
 496 /*
 497  * 'l4' class
 498  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 499  */
 500 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 501         .name   = "l4",
 502 };
 503
 504 /* l4_abe */
 505 /* aess -> l4_abe */
 506 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 507         .master         = &omap44xx_aess_hwmod,
 508         .slave          = &omap44xx_l4_abe_hwmod,
 509         .clk            = "ocp_abe_iclk",
 510         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 511 };
 512
 513 /* dsp -> l4_abe */
 514 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 515         .master         = &omap44xx_dsp_hwmod,
 516         .slave          = &omap44xx_l4_abe_hwmod,
 517         .clk            = "ocp_abe_iclk",
 518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 519 };
 520
 521 /* l3_main_1 -> l4_abe */
 522 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 523         .master         = &omap44xx_l3_main_1_hwmod,
 524         .slave          = &omap44xx_l4_abe_hwmod,
 525         .clk            = "l3_div_ck",
 526         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 527 };
 528
 529 /* mpu -> l4_abe */
 530 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 531         .master         = &omap44xx_mpu_hwmod,
 532         .slave          = &omap44xx_l4_abe_hwmod,
 533         .clk            = "ocp_abe_iclk",
 534         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 535 };
 536
 537 /* l4_abe slave ports */
 538 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 539         &omap44xx_aess__l4_abe,
 540         &omap44xx_dsp__l4_abe,
 541         &omap44xx_l3_main_1__l4_abe,
 542         &omap44xx_mpu__l4_abe,
 543 };
 544
 545 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 546         .name           = "l4_abe",
 547         .class          = &omap44xx_l4_hwmod_class,
 548         .clkdm_name     = "abe_clkdm",
 549         .prcm = {
 550                 .omap4 = {
 551                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 552                 },
 553         },
 554         .slaves         = omap44xx_l4_abe_slaves,
 555         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 556 };
 557
 558 /* l4_cfg */
 559 /* l3_main_1 -> l4_cfg */
 560 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 561         .master         = &omap44xx_l3_main_1_hwmod,
 562         .slave          = &omap44xx_l4_cfg_hwmod,
 563         .clk            = "l3_div_ck",
 564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 565 };
 566
 567 /* l4_cfg slave ports */
 568 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 569         &omap44xx_l3_main_1__l4_cfg,
 570 };
 571
 572 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 573         .name           = "l4_cfg",
 574         .class          = &omap44xx_l4_hwmod_class,
 575         .clkdm_name     = "l4_cfg_clkdm",
 576         .prcm = {
 577                 .omap4 = {
 578                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 579                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 580                 },
 581         },
 582         .slaves         = omap44xx_l4_cfg_slaves,
 583         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 584 };
 585
 586 /* l4_per */
 587 /* l3_main_2 -> l4_per */
 588 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 589         .master         = &omap44xx_l3_main_2_hwmod,
 590         .slave          = &omap44xx_l4_per_hwmod,
 591         .clk            = "l3_div_ck",
 592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 593 };
 594
 595 /* l4_per slave ports */
 596 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 597         &omap44xx_l3_main_2__l4_per,
 598 };
 599
 600 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 601         .name           = "l4_per",
 602         .class          = &omap44xx_l4_hwmod_class,
 603         .clkdm_name     = "l4_per_clkdm",
 604         .prcm = {
 605                 .omap4 = {
 606                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 607                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 608                 },
 609         },
 610         .slaves         = omap44xx_l4_per_slaves,
 611         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 612 };
 613
 614 /* l4_wkup */
 615 /* l4_cfg -> l4_wkup */
 616 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 617         .master         = &omap44xx_l4_cfg_hwmod,
 618         .slave          = &omap44xx_l4_wkup_hwmod,
 619         .clk            = "l4_div_ck",
 620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 621 };
 622
 623 /* l4_wkup slave ports */
 624 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 625         &omap44xx_l4_cfg__l4_wkup,
 626 };
 627
 628 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 629         .name           = "l4_wkup",
 630         .class          = &omap44xx_l4_hwmod_class,
 631         .clkdm_name     = "l4_wkup_clkdm",
 632         .prcm = {
 633                 .omap4 = {
 634                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 635                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 636                 },
 637         },
 638         .slaves         = omap44xx_l4_wkup_slaves,
 639         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 640 };
 641
 642 /*
 643  * 'mpu_bus' class
 644  * instance(s): mpu_private
 645  */
 646 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 647         .name   = "mpu_bus",
 648 };
 649
 650 /* mpu_private */
 651 /* mpu -> mpu_private */
 652 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 653         .master         = &omap44xx_mpu_hwmod,
 654         .slave          = &omap44xx_mpu_private_hwmod,
 655         .clk            = "l3_div_ck",
 656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 657 };
 658
 659 /* mpu_private slave ports */
 660 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 661         &omap44xx_mpu__mpu_private,
 662 };
 663
 664 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 665         .name           = "mpu_private",
 666         .class          = &omap44xx_mpu_bus_hwmod_class,
 667         .clkdm_name     = "mpuss_clkdm",
 668         .slaves         = omap44xx_mpu_private_slaves,
 669         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 670 };
 671
 672 /*
 673  * Modules omap_hwmod structures
 674  *
 675  * The following IPs are excluded for the moment because:
 676  * - They do not need an explicit SW control using omap_hwmod API.
 677  * - They still need to be validated with the driver
 678  *   properly adapted to omap_hwmod / omap_device
 679  *
 680  *  c2c
 681  *  c2c_target_fw
 682  *  cm_core
 683  *  cm_core_aon
 684  *  ctrl_module_core
 685  *  ctrl_module_pad_core
 686  *  ctrl_module_pad_wkup
 687  *  ctrl_module_wkup
 688  *  debugss
 689  *  efuse_ctrl_cust
 690  *  efuse_ctrl_std
 691  *  elm
 692  *  emif1
 693  *  emif2
 694  *  fdif
 695  *  gpmc
 696  *  gpu
 697  *  hdq1w
 698  *  mcasp
 699  *  mpu_c0
 700  *  mpu_c1
 701  *  ocmc_ram
 702  *  ocp2scp_usb_phy
 703  *  ocp_wp_noc
 704  *  prcm_mpu
 705  *  prm
 706  *  scrm
 707  *  sl2if
 708  *  slimbus1
 709  *  slimbus2
 710  *  usb_host_fs
 711  *  usb_host_hs
 712  *  usb_phy_cm
 713  *  usb_tll_hs
 714  *  usim
 715  */
 716
 717 /*
 718  * 'aess' class
 719  * audio engine sub system
 720  */
 721
 722 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 723         .rev_offs       = 0x0000,
 724         .sysc_offs      = 0x0010,
 725         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 726         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 727                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 728                            MSTANDBY_SMART_WKUP),
 729         .sysc_fields    = &omap_hwmod_sysc_type2,
 730 };
 731
 732 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 733         .name   = "aess",
 734         .sysc   = &omap44xx_aess_sysc,
 735 };
 736
 737 /* aess */
 738 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 739         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 740         { .irq = -1 }
 741 };
 742
 743 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 744         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 745         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 746         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 747         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 748         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 749         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 750         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 751         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 752         { .dma_req = -1 }
 753 };
 754
 755 /* aess master ports */
 756 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 757         &omap44xx_aess__l4_abe,
 758 };
 759
 760 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 761         {
 762                 .pa_start       = 0x401f1000,
 763                 .pa_end         = 0x401f13ff,
 764                 .flags          = ADDR_TYPE_RT
 765         },
 766         { }
 767 };
 768
 769 /* l4_abe -> aess */
 770 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 771         .master         = &omap44xx_l4_abe_hwmod,
 772         .slave          = &omap44xx_aess_hwmod,
 773         .clk            = "ocp_abe_iclk",
 774         .addr           = omap44xx_aess_addrs,
 775         .user           = OCP_USER_MPU,
 776 };
 777
 778 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 779         {
 780                 .pa_start       = 0x490f1000,
 781                 .pa_end         = 0x490f13ff,
 782                 .flags          = ADDR_TYPE_RT
 783         },
 784         { }
 785 };
 786
 787 /* l4_abe -> aess (dma) */
 788 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 789         .master         = &omap44xx_l4_abe_hwmod,
 790         .slave          = &omap44xx_aess_hwmod,
 791         .clk            = "ocp_abe_iclk",
 792         .addr           = omap44xx_aess_dma_addrs,
 793         .user           = OCP_USER_SDMA,
 794 };
 795
 796 /* aess slave ports */
 797 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 798         &omap44xx_l4_abe__aess,
 799         &omap44xx_l4_abe__aess_dma,
 800 };
 801
 802 static struct omap_hwmod omap44xx_aess_hwmod = {
 803         .name           = "aess",
 804         .class          = &omap44xx_aess_hwmod_class,
 805         .clkdm_name     = "abe_clkdm",
 806         .mpu_irqs       = omap44xx_aess_irqs,
 807         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 808         .main_clk       = "aess_fck",
 809         .prcm = {
 810                 .omap4 = {
 811                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 812                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 813                         .modulemode   = MODULEMODE_SWCTRL,
 814                 },
 815         },
 816         .slaves         = omap44xx_aess_slaves,
 817         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 818         .masters        = omap44xx_aess_masters,
 819         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 820 };
 821
 822 /*
 823  * 'bandgap' class
 824  * bangap reference for ldo regulators
 825  */
 826
 827 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 828         .name   = "bandgap",
 829 };
 830
 831 /* bandgap */
 832 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 833         { .role = "fclk", .clk = "bandgap_fclk" },
 834 };
 835
 836 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 837         .name           = "bandgap",
 838         .class          = &omap44xx_bandgap_hwmod_class,
 839         .clkdm_name     = "l4_wkup_clkdm",
 840         .prcm = {
 841                 .omap4 = {
 842                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 843                 },
 844         },
 845         .opt_clks       = bandgap_opt_clks,
 846         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 847 };
 848
 849 /*
 850  * 'counter' class
 851  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 852  */
 853
 854 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 855         .rev_offs       = 0x0000,
 856         .sysc_offs      = 0x0004,
 857         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 858         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 859                            SIDLE_SMART_WKUP),
 860         .sysc_fields    = &omap_hwmod_sysc_type1,
 861 };
 862
 863 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 864         .name   = "counter",
 865         .sysc   = &omap44xx_counter_sysc,
 866 };
 867
 868 /* counter_32k */
 869 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 870 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 871         {
 872                 .pa_start       = 0x4a304000,
 873                 .pa_end         = 0x4a30401f,
 874                 .flags          = ADDR_TYPE_RT
 875         },
 876         { }
 877 };
 878
 879 /* l4_wkup -> counter_32k */
 880 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 881         .master         = &omap44xx_l4_wkup_hwmod,
 882         .slave          = &omap44xx_counter_32k_hwmod,
 883         .clk            = "l4_wkup_clk_mux_ck",
 884         .addr           = omap44xx_counter_32k_addrs,
 885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 886 };
 887
 888 /* counter_32k slave ports */
 889 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 890         &omap44xx_l4_wkup__counter_32k,
 891 };
 892
 893 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 894         .name           = "counter_32k",
 895         .class          = &omap44xx_counter_hwmod_class,
 896         .clkdm_name     = "l4_wkup_clkdm",
 897         .flags          = HWMOD_SWSUP_SIDLE,
 898         .main_clk       = "sys_32k_ck",
 899         .prcm = {
 900                 .omap4 = {
 901                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 902                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 903                 },
 904         },
 905         .slaves         = omap44xx_counter_32k_slaves,
 906         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 907 };
 908
 909 /*
 910  * 'dma' class
 911  * dma controller for data exchange between memory to memory (i.e. internal or
 912  * external memory) and gp peripherals to memory or memory to gp peripherals
 913  */
 914
 915 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 916         .rev_offs       = 0x0000,
 917         .sysc_offs      = 0x002c,
 918         .syss_offs      = 0x0028,
 919         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 920                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 921                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 922                            SYSS_HAS_RESET_STATUS),
 923         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 924                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 925         .sysc_fields    = &omap_hwmod_sysc_type1,
 926 };
 927
 928 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 929         .name   = "dma",
 930         .sysc   = &omap44xx_dma_sysc,
 931 };
 932
 933 /* dma dev_attr */
 934 static struct omap_dma_dev_attr dma_dev_attr = {
 935         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 936                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 937         .lch_count      = 32,
 938 };
 939
 940 /* dma_system */
 941 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 942         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 943         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 944         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 945         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 946         { .irq = -1 }
 947 };
 948
 949 /* dma_system master ports */
 950 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 951         &omap44xx_dma_system__l3_main_2,
 952 };
 953
 954 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 955         {
 956                 .pa_start       = 0x4a056000,
 957                 .pa_end         = 0x4a056fff,
 958                 .flags          = ADDR_TYPE_RT
 959         },
 960         { }
 961 };
 962
 963 /* l4_cfg -> dma_system */
 964 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 965         .master         = &omap44xx_l4_cfg_hwmod,
 966         .slave          = &omap44xx_dma_system_hwmod,
 967         .clk            = "l4_div_ck",
 968         .addr           = omap44xx_dma_system_addrs,
 969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 970 };
 971
 972 /* dma_system slave ports */
 973 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 974         &omap44xx_l4_cfg__dma_system,
 975 };
 976
 977 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 978         .name           = "dma_system",
 979         .class          = &omap44xx_dma_hwmod_class,
 980         .clkdm_name     = "l3_dma_clkdm",
 981         .mpu_irqs       = omap44xx_dma_system_irqs,
 982         .main_clk       = "l3_div_ck",
 983         .prcm = {
 984                 .omap4 = {
 985                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 986                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 987                 },
 988         },
 989         .dev_attr       = &dma_dev_attr,
 990         .slaves         = omap44xx_dma_system_slaves,
 991         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 992         .masters        = omap44xx_dma_system_masters,
 993         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 994 };
 995
 996 /*
 997  * 'dmic' class
 998  * digital microphone controller
 999  */
1000
1001 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1002         .rev_offs       = 0x0000,
1003         .sysc_offs      = 0x0010,
1004         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1005                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1007                            SIDLE_SMART_WKUP),
1008         .sysc_fields    = &omap_hwmod_sysc_type2,
1009 };
1010
1011 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1012         .name   = "dmic",
1013         .sysc   = &omap44xx_dmic_sysc,
1014 };
1015
1016 /* dmic */
1017 static struct omap_hwmod omap44xx_dmic_hwmod;
1018 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1019         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1020         { .irq = -1 }
1021 };
1022
1023 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1024         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1025         { .dma_req = -1 }
1026 };
1027
1028 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1029         {
1030                 .pa_start       = 0x4012e000,
1031                 .pa_end         = 0x4012e07f,
1032                 .flags          = ADDR_TYPE_RT
1033         },
1034         { }
1035 };
1036
1037 /* l4_abe -> dmic */
1038 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1039         .master         = &omap44xx_l4_abe_hwmod,
1040         .slave          = &omap44xx_dmic_hwmod,
1041         .clk            = "ocp_abe_iclk",
1042         .addr           = omap44xx_dmic_addrs,
1043         .user           = OCP_USER_MPU,
1044 };
1045
1046 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1047         {
1048                 .pa_start       = 0x4902e000,
1049                 .pa_end         = 0x4902e07f,
1050                 .flags          = ADDR_TYPE_RT
1051         },
1052         { }
1053 };
1054
1055 /* l4_abe -> dmic (dma) */
1056 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1057         .master         = &omap44xx_l4_abe_hwmod,
1058         .slave          = &omap44xx_dmic_hwmod,
1059         .clk            = "ocp_abe_iclk",
1060         .addr           = omap44xx_dmic_dma_addrs,
1061         .user           = OCP_USER_SDMA,
1062 };
1063
1064 /* dmic slave ports */
1065 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1066         &omap44xx_l4_abe__dmic,
1067         &omap44xx_l4_abe__dmic_dma,
1068 };
1069
1070 static struct omap_hwmod omap44xx_dmic_hwmod = {
1071         .name           = "dmic",
1072         .class          = &omap44xx_dmic_hwmod_class,
1073         .clkdm_name     = "abe_clkdm",
1074         .mpu_irqs       = omap44xx_dmic_irqs,
1075         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1076         .main_clk       = "dmic_fck",
1077         .prcm = {
1078                 .omap4 = {
1079                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1080                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1081                         .modulemode   = MODULEMODE_SWCTRL,
1082                 },
1083         },
1084         .slaves         = omap44xx_dmic_slaves,
1085         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1086 };
1087
1088 /*
1089  * 'dsp' class
1090  * dsp sub-system
1091  */
1092
1093 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1094         .name   = "dsp",
1095 };
1096
1097 /* dsp */
1098 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1099         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1100         { .irq = -1 }
1101 };
1102
1103 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1104         { .name = "mmu_cache", .rst_shift = 1 },
1105 };
1106
1107 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1108         { .name = "dsp", .rst_shift = 0 },
1109 };
1110
1111 /* dsp -> iva */
1112 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1113         .master         = &omap44xx_dsp_hwmod,
1114         .slave          = &omap44xx_iva_hwmod,
1115         .clk            = "dpll_iva_m5x2_ck",
1116 };
1117
1118 /* dsp master ports */
1119 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1120         &omap44xx_dsp__l3_main_1,
1121         &omap44xx_dsp__l4_abe,
1122         &omap44xx_dsp__iva,
1123 };
1124
1125 /* l4_cfg -> dsp */
1126 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1127         .master         = &omap44xx_l4_cfg_hwmod,
1128         .slave          = &omap44xx_dsp_hwmod,
1129         .clk            = "l4_div_ck",
1130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1131 };
1132
1133 /* dsp slave ports */
1134 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1135         &omap44xx_l4_cfg__dsp,
1136 };
1137
1138 /* Pseudo hwmod for reset control purpose only */
1139 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1140         .name           = "dsp_c0",
1141         .class          = &omap44xx_dsp_hwmod_class,
1142         .clkdm_name     = "tesla_clkdm",
1143         .flags          = HWMOD_INIT_NO_RESET,
1144         .rst_lines      = omap44xx_dsp_c0_resets,
1145         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1146         .prcm = {
1147                 .omap4 = {
1148                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1149                 },
1150         },
1151 };
1152
1153 static struct omap_hwmod omap44xx_dsp_hwmod = {
1154         .name           = "dsp",
1155         .class          = &omap44xx_dsp_hwmod_class,
1156         .clkdm_name     = "tesla_clkdm",
1157         .mpu_irqs       = omap44xx_dsp_irqs,
1158         .rst_lines      = omap44xx_dsp_resets,
1159         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1160         .main_clk       = "dsp_fck",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1164                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1165                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1166                         .modulemode   = MODULEMODE_HWCTRL,
1167                 },
1168         },
1169         .slaves         = omap44xx_dsp_slaves,
1170         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1171         .masters        = omap44xx_dsp_masters,
1172         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1173 };
1174
1175 /*
1176  * 'dss' class
1177  * display sub-system
1178  */
1179
1180 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1181         .rev_offs       = 0x0000,
1182         .syss_offs      = 0x0014,
1183         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1184 };
1185
1186 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1187         .name   = "dss",
1188         .sysc   = &omap44xx_dss_sysc,
1189 };
1190
1191 /* dss */
1192 /* dss master ports */
1193 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1194         &omap44xx_dss__l3_main_1,
1195 };
1196
1197 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1198         {
1199                 .pa_start       = 0x58000000,
1200                 .pa_end         = 0x5800007f,
1201                 .flags          = ADDR_TYPE_RT
1202         },
1203         { }
1204 };
1205
1206 /* l3_main_2 -> dss */
1207 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1208         .master         = &omap44xx_l3_main_2_hwmod,
1209         .slave          = &omap44xx_dss_hwmod,
1210         .clk            = "dss_fck",
1211         .addr           = omap44xx_dss_dma_addrs,
1212         .user           = OCP_USER_SDMA,
1213 };
1214
1215 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1216         {
1217                 .pa_start       = 0x48040000,
1218                 .pa_end         = 0x4804007f,
1219                 .flags          = ADDR_TYPE_RT
1220         },
1221         { }
1222 };
1223
1224 /* l4_per -> dss */
1225 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1226         .master         = &omap44xx_l4_per_hwmod,
1227         .slave          = &omap44xx_dss_hwmod,
1228         .clk            = "l4_div_ck",
1229         .addr           = omap44xx_dss_addrs,
1230         .user           = OCP_USER_MPU,
1231 };
1232
1233 /* dss slave ports */
1234 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1235         &omap44xx_l3_main_2__dss,
1236         &omap44xx_l4_per__dss,
1237 };
1238
1239 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1240         { .role = "sys_clk", .clk = "dss_sys_clk" },
1241         { .role = "tv_clk", .clk = "dss_tv_clk" },
1242         { .role = "dss_clk", .clk = "dss_dss_clk" },
1243         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_dss_hwmod = {
1247         .name           = "dss_core",
1248         .class          = &omap44xx_dss_hwmod_class,
1249         .clkdm_name     = "l3_dss_clkdm",
1250         .main_clk       = "dss_dss_clk",
1251         .prcm = {
1252                 .omap4 = {
1253                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1254                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1255                 },
1256         },
1257         .opt_clks       = dss_opt_clks,
1258         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1259         .slaves         = omap44xx_dss_slaves,
1260         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1261         .masters        = omap44xx_dss_masters,
1262         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1263 };
1264
1265 /*
1266  * 'dispc' class
1267  * display controller
1268  */
1269
1270 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1271         .rev_offs       = 0x0000,
1272         .sysc_offs      = 0x0010,
1273         .syss_offs      = 0x0014,
1274         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1275                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1276                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1277                            SYSS_HAS_RESET_STATUS),
1278         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1279                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1280         .sysc_fields    = &omap_hwmod_sysc_type1,
1281 };
1282
1283 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1284         .name   = "dispc",
1285         .sysc   = &omap44xx_dispc_sysc,
1286 };
1287
1288 /* dss_dispc */
1289 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1290 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1291         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1292         { .irq = -1 }
1293 };
1294
1295 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1296         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1297         { .dma_req = -1 }
1298 };
1299
1300 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1301         {
1302                 .pa_start       = 0x58001000,
1303                 .pa_end         = 0x58001fff,
1304                 .flags          = ADDR_TYPE_RT
1305         },
1306         { }
1307 };
1308
1309 /* l3_main_2 -> dss_dispc */
1310 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1311         .master         = &omap44xx_l3_main_2_hwmod,
1312         .slave          = &omap44xx_dss_dispc_hwmod,
1313         .clk            = "dss_fck",
1314         .addr           = omap44xx_dss_dispc_dma_addrs,
1315         .user           = OCP_USER_SDMA,
1316 };
1317
1318 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1319         {
1320                 .pa_start       = 0x48041000,
1321                 .pa_end         = 0x48041fff,
1322                 .flags          = ADDR_TYPE_RT
1323         },
1324         { }
1325 };
1326
1327 /* l4_per -> dss_dispc */
1328 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1329         .master         = &omap44xx_l4_per_hwmod,
1330         .slave          = &omap44xx_dss_dispc_hwmod,
1331         .clk            = "l4_div_ck",
1332         .addr           = omap44xx_dss_dispc_addrs,
1333         .user           = OCP_USER_MPU,
1334 };
1335
1336 /* dss_dispc slave ports */
1337 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1338         &omap44xx_l3_main_2__dss_dispc,
1339         &omap44xx_l4_per__dss_dispc,
1340 };
1341
1342 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1343         { .role = "sys_clk", .clk = "dss_sys_clk" },
1344         { .role = "tv_clk", .clk = "dss_tv_clk" },
1345         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1346 };
1347
1348 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1349         .name           = "dss_dispc",
1350         .class          = &omap44xx_dispc_hwmod_class,
1351         .clkdm_name     = "l3_dss_clkdm",
1352         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1353         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1354         .main_clk       = "dss_dss_clk",
1355         .prcm = {
1356                 .omap4 = {
1357                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1358                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1359                 },
1360         },
1361         .opt_clks       = dss_dispc_opt_clks,
1362         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1363         .slaves         = omap44xx_dss_dispc_slaves,
1364         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1365 };
1366
1367 /*
1368  * 'dsi' class
1369  * display serial interface controller
1370  */
1371
1372 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1373         .rev_offs       = 0x0000,
1374         .sysc_offs      = 0x0010,
1375         .syss_offs      = 0x0014,
1376         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1377                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1378                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1379         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1380         .sysc_fields    = &omap_hwmod_sysc_type1,
1381 };
1382
1383 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1384         .name   = "dsi",
1385         .sysc   = &omap44xx_dsi_sysc,
1386 };
1387
1388 /* dss_dsi1 */
1389 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1390 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1391         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1392         { .irq = -1 }
1393 };
1394
1395 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1396         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1397         { .dma_req = -1 }
1398 };
1399
1400 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1401         {
1402                 .pa_start       = 0x58004000,
1403                 .pa_end         = 0x580041ff,
1404                 .flags          = ADDR_TYPE_RT
1405         },
1406         { }
1407 };
1408
1409 /* l3_main_2 -> dss_dsi1 */
1410 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1411         .master         = &omap44xx_l3_main_2_hwmod,
1412         .slave          = &omap44xx_dss_dsi1_hwmod,
1413         .clk            = "dss_fck",
1414         .addr           = omap44xx_dss_dsi1_dma_addrs,
1415         .user           = OCP_USER_SDMA,
1416 };
1417
1418 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1419         {
1420                 .pa_start       = 0x48044000,
1421                 .pa_end         = 0x480441ff,
1422                 .flags          = ADDR_TYPE_RT
1423         },
1424         { }
1425 };
1426
1427 /* l4_per -> dss_dsi1 */
1428 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1429         .master         = &omap44xx_l4_per_hwmod,
1430         .slave          = &omap44xx_dss_dsi1_hwmod,
1431         .clk            = "l4_div_ck",
1432         .addr           = omap44xx_dss_dsi1_addrs,
1433         .user           = OCP_USER_MPU,
1434 };
1435
1436 /* dss_dsi1 slave ports */
1437 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1438         &omap44xx_l3_main_2__dss_dsi1,
1439         &omap44xx_l4_per__dss_dsi1,
1440 };
1441
1442 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1443         { .role = "sys_clk", .clk = "dss_sys_clk" },
1444 };
1445
1446 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1447         .name           = "dss_dsi1",
1448         .class          = &omap44xx_dsi_hwmod_class,
1449         .clkdm_name     = "l3_dss_clkdm",
1450         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1451         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1452         .main_clk       = "dss_dss_clk",
1453         .prcm = {
1454                 .omap4 = {
1455                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1456                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1457                 },
1458         },
1459         .opt_clks       = dss_dsi1_opt_clks,
1460         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1461         .slaves         = omap44xx_dss_dsi1_slaves,
1462         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1463 };
1464
1465 /* dss_dsi2 */
1466 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1467 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1468         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1469         { .irq = -1 }
1470 };
1471
1472 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1473         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1474         { .dma_req = -1 }
1475 };
1476
1477 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1478         {
1479                 .pa_start       = 0x58005000,
1480                 .pa_end         = 0x580051ff,
1481                 .flags          = ADDR_TYPE_RT
1482         },
1483         { }
1484 };
1485
1486 /* l3_main_2 -> dss_dsi2 */
1487 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1488         .master         = &omap44xx_l3_main_2_hwmod,
1489         .slave          = &omap44xx_dss_dsi2_hwmod,
1490         .clk            = "dss_fck",
1491         .addr           = omap44xx_dss_dsi2_dma_addrs,
1492         .user           = OCP_USER_SDMA,
1493 };
1494
1495 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1496         {
1497                 .pa_start       = 0x48045000,
1498                 .pa_end         = 0x480451ff,
1499                 .flags          = ADDR_TYPE_RT
1500         },
1501         { }
1502 };
1503
1504 /* l4_per -> dss_dsi2 */
1505 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1506         .master         = &omap44xx_l4_per_hwmod,
1507         .slave          = &omap44xx_dss_dsi2_hwmod,
1508         .clk            = "l4_div_ck",
1509         .addr           = omap44xx_dss_dsi2_addrs,
1510         .user           = OCP_USER_MPU,
1511 };
1512
1513 /* dss_dsi2 slave ports */
1514 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1515         &omap44xx_l3_main_2__dss_dsi2,
1516         &omap44xx_l4_per__dss_dsi2,
1517 };
1518
1519 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1520         { .role = "sys_clk", .clk = "dss_sys_clk" },
1521 };
1522
1523 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1524         .name           = "dss_dsi2",
1525         .class          = &omap44xx_dsi_hwmod_class,
1526         .clkdm_name     = "l3_dss_clkdm",
1527         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1528         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1529         .main_clk       = "dss_dss_clk",
1530         .prcm = {
1531                 .omap4 = {
1532                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1533                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1534                 },
1535         },
1536         .opt_clks       = dss_dsi2_opt_clks,
1537         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1538         .slaves         = omap44xx_dss_dsi2_slaves,
1539         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1540 };
1541
1542 /*
1543  * 'hdmi' class
1544  * hdmi controller
1545  */
1546
1547 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1548         .rev_offs       = 0x0000,
1549         .sysc_offs      = 0x0010,
1550         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1551                            SYSC_HAS_SOFTRESET),
1552         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1553                            SIDLE_SMART_WKUP),
1554         .sysc_fields    = &omap_hwmod_sysc_type2,
1555 };
1556
1557 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1558         .name   = "hdmi",
1559         .sysc   = &omap44xx_hdmi_sysc,
1560 };
1561
1562 /* dss_hdmi */
1563 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1564 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1565         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1566         { .irq = -1 }
1567 };
1568
1569 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1570         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1571         { .dma_req = -1 }
1572 };
1573
1574 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1575         {
1576                 .pa_start       = 0x58006000,
1577                 .pa_end         = 0x58006fff,
1578                 .flags          = ADDR_TYPE_RT
1579         },
1580         { }
1581 };
1582
1583 /* l3_main_2 -> dss_hdmi */
1584 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1585         .master         = &omap44xx_l3_main_2_hwmod,
1586         .slave          = &omap44xx_dss_hdmi_hwmod,
1587         .clk            = "dss_fck",
1588         .addr           = omap44xx_dss_hdmi_dma_addrs,
1589         .user           = OCP_USER_SDMA,
1590 };
1591
1592 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1593         {
1594                 .pa_start       = 0x48046000,
1595                 .pa_end         = 0x48046fff,
1596                 .flags          = ADDR_TYPE_RT
1597         },
1598         { }
1599 };
1600
1601 /* l4_per -> dss_hdmi */
1602 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1603         .master         = &omap44xx_l4_per_hwmod,
1604         .slave          = &omap44xx_dss_hdmi_hwmod,
1605         .clk            = "l4_div_ck",
1606         .addr           = omap44xx_dss_hdmi_addrs,
1607         .user           = OCP_USER_MPU,
1608 };
1609
1610 /* dss_hdmi slave ports */
1611 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1612         &omap44xx_l3_main_2__dss_hdmi,
1613         &omap44xx_l4_per__dss_hdmi,
1614 };
1615
1616 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1617         { .role = "sys_clk", .clk = "dss_sys_clk" },
1618 };
1619
1620 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1621         .name           = "dss_hdmi",
1622         .class          = &omap44xx_hdmi_hwmod_class,
1623         .clkdm_name     = "l3_dss_clkdm",
1624         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1625         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1626         .main_clk       = "dss_dss_clk",
1627         .prcm = {
1628                 .omap4 = {
1629                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1630                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1631                 },
1632         },
1633         .opt_clks       = dss_hdmi_opt_clks,
1634         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1635         .slaves         = omap44xx_dss_hdmi_slaves,
1636         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1637 };
1638
1639 /*
1640  * 'rfbi' class
1641  * remote frame buffer interface
1642  */
1643
1644 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1645         .rev_offs       = 0x0000,
1646         .sysc_offs      = 0x0010,
1647         .syss_offs      = 0x0014,
1648         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1649                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1650         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1651         .sysc_fields    = &omap_hwmod_sysc_type1,
1652 };
1653
1654 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1655         .name   = "rfbi",
1656         .sysc   = &omap44xx_rfbi_sysc,
1657 };
1658
1659 /* dss_rfbi */
1660 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1661 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1662         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1663         { .dma_req = -1 }
1664 };
1665
1666 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1667         {
1668                 .pa_start       = 0x58002000,
1669                 .pa_end         = 0x580020ff,
1670                 .flags          = ADDR_TYPE_RT
1671         },
1672         { }
1673 };
1674
1675 /* l3_main_2 -> dss_rfbi */
1676 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1677         .master         = &omap44xx_l3_main_2_hwmod,
1678         .slave          = &omap44xx_dss_rfbi_hwmod,
1679         .clk            = "dss_fck",
1680         .addr           = omap44xx_dss_rfbi_dma_addrs,
1681         .user           = OCP_USER_SDMA,
1682 };
1683
1684 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1685         {
1686                 .pa_start       = 0x48042000,
1687                 .pa_end         = 0x480420ff,
1688                 .flags          = ADDR_TYPE_RT
1689         },
1690         { }
1691 };
1692
1693 /* l4_per -> dss_rfbi */
1694 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1695         .master         = &omap44xx_l4_per_hwmod,
1696         .slave          = &omap44xx_dss_rfbi_hwmod,
1697         .clk            = "l4_div_ck",
1698         .addr           = omap44xx_dss_rfbi_addrs,
1699         .user           = OCP_USER_MPU,
1700 };
1701
1702 /* dss_rfbi slave ports */
1703 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1704         &omap44xx_l3_main_2__dss_rfbi,
1705         &omap44xx_l4_per__dss_rfbi,
1706 };
1707
1708 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1709         { .role = "ick", .clk = "dss_fck" },
1710 };
1711
1712 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1713         .name           = "dss_rfbi",
1714         .class          = &omap44xx_rfbi_hwmod_class,
1715         .clkdm_name     = "l3_dss_clkdm",
1716         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1717         .main_clk       = "dss_dss_clk",
1718         .prcm = {
1719                 .omap4 = {
1720                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1721                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1722                 },
1723         },
1724         .opt_clks       = dss_rfbi_opt_clks,
1725         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1726         .slaves         = omap44xx_dss_rfbi_slaves,
1727         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1728 };
1729
1730 /*
1731  * 'venc' class
1732  * video encoder
1733  */
1734
1735 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1736         .name   = "venc",
1737 };
1738
1739 /* dss_venc */
1740 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1741 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1742         {
1743                 .pa_start       = 0x58003000,
1744                 .pa_end         = 0x580030ff,
1745                 .flags          = ADDR_TYPE_RT
1746         },
1747         { }
1748 };
1749
1750 /* l3_main_2 -> dss_venc */
1751 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1752         .master         = &omap44xx_l3_main_2_hwmod,
1753         .slave          = &omap44xx_dss_venc_hwmod,
1754         .clk            = "dss_fck",
1755         .addr           = omap44xx_dss_venc_dma_addrs,
1756         .user           = OCP_USER_SDMA,
1757 };
1758
1759 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1760         {
1761                 .pa_start       = 0x48043000,
1762                 .pa_end         = 0x480430ff,
1763                 .flags          = ADDR_TYPE_RT
1764         },
1765         { }
1766 };
1767
1768 /* l4_per -> dss_venc */
1769 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1770         .master         = &omap44xx_l4_per_hwmod,
1771         .slave          = &omap44xx_dss_venc_hwmod,
1772         .clk            = "l4_div_ck",
1773         .addr           = omap44xx_dss_venc_addrs,
1774         .user           = OCP_USER_MPU,
1775 };
1776
1777 /* dss_venc slave ports */
1778 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1779         &omap44xx_l3_main_2__dss_venc,
1780         &omap44xx_l4_per__dss_venc,
1781 };
1782
1783 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1784         .name           = "dss_venc",
1785         .class          = &omap44xx_venc_hwmod_class,
1786         .clkdm_name     = "l3_dss_clkdm",
1787         .main_clk       = "dss_dss_clk",
1788         .prcm = {
1789                 .omap4 = {
1790                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1791                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1792                 },
1793         },
1794         .slaves         = omap44xx_dss_venc_slaves,
1795         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1796 };
1797
1798 /*
1799  * 'gpio' class
1800  * general purpose io module
1801  */
1802
1803 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1804         .rev_offs       = 0x0000,
1805         .sysc_offs      = 0x0010,
1806         .syss_offs      = 0x0114,
1807         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1808                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1809                            SYSS_HAS_RESET_STATUS),
1810         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1811                            SIDLE_SMART_WKUP),
1812         .sysc_fields    = &omap_hwmod_sysc_type1,
1813 };
1814
1815 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1816         .name   = "gpio",
1817         .sysc   = &omap44xx_gpio_sysc,
1818         .rev    = 2,
1819 };
1820
1821 /* gpio dev_attr */
1822 static struct omap_gpio_dev_attr gpio_dev_attr = {
1823         .bank_width     = 32,
1824         .dbck_flag      = true,
1825 };
1826
1827 /* gpio1 */
1828 static struct omap_hwmod omap44xx_gpio1_hwmod;
1829 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1830         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1831         { .irq = -1 }
1832 };
1833
1834 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1835         {
1836                 .pa_start       = 0x4a310000,
1837                 .pa_end         = 0x4a3101ff,
1838                 .flags          = ADDR_TYPE_RT
1839         },
1840         { }
1841 };
1842
1843 /* l4_wkup -> gpio1 */
1844 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1845         .master         = &omap44xx_l4_wkup_hwmod,
1846         .slave          = &omap44xx_gpio1_hwmod,
1847         .clk            = "l4_wkup_clk_mux_ck",
1848         .addr           = omap44xx_gpio1_addrs,
1849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1850 };
1851
1852 /* gpio1 slave ports */
1853 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1854         &omap44xx_l4_wkup__gpio1,
1855 };
1856
1857 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1858         { .role = "dbclk", .clk = "gpio1_dbclk" },
1859 };
1860
1861 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1862         .name           = "gpio1",
1863         .class          = &omap44xx_gpio_hwmod_class,
1864         .clkdm_name     = "l4_wkup_clkdm",
1865         .mpu_irqs       = omap44xx_gpio1_irqs,
1866         .main_clk       = "gpio1_ick",
1867         .prcm = {
1868                 .omap4 = {
1869                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1870                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1871                         .modulemode   = MODULEMODE_HWCTRL,
1872                 },
1873         },
1874         .opt_clks       = gpio1_opt_clks,
1875         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1876         .dev_attr       = &gpio_dev_attr,
1877         .slaves         = omap44xx_gpio1_slaves,
1878         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1879 };
1880
1881 /* gpio2 */
1882 static struct omap_hwmod omap44xx_gpio2_hwmod;
1883 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1884         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1885         { .irq = -1 }
1886 };
1887
1888 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1889         {
1890                 .pa_start       = 0x48055000,
1891                 .pa_end         = 0x480551ff,
1892                 .flags          = ADDR_TYPE_RT
1893         },
1894         { }
1895 };
1896
1897 /* l4_per -> gpio2 */
1898 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1899         .master         = &omap44xx_l4_per_hwmod,
1900         .slave          = &omap44xx_gpio2_hwmod,
1901         .clk            = "l4_div_ck",
1902         .addr           = omap44xx_gpio2_addrs,
1903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1904 };
1905
1906 /* gpio2 slave ports */
1907 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1908         &omap44xx_l4_per__gpio2,
1909 };
1910
1911 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1912         { .role = "dbclk", .clk = "gpio2_dbclk" },
1913 };
1914
1915 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1916         .name           = "gpio2",
1917         .class          = &omap44xx_gpio_hwmod_class,
1918         .clkdm_name     = "l4_per_clkdm",
1919         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1920         .mpu_irqs       = omap44xx_gpio2_irqs,
1921         .main_clk       = "gpio2_ick",
1922         .prcm = {
1923                 .omap4 = {
1924                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1925                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1926                         .modulemode   = MODULEMODE_HWCTRL,
1927                 },
1928         },
1929         .opt_clks       = gpio2_opt_clks,
1930         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1931         .dev_attr       = &gpio_dev_attr,
1932         .slaves         = omap44xx_gpio2_slaves,
1933         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1934 };
1935
1936 /* gpio3 */
1937 static struct omap_hwmod omap44xx_gpio3_hwmod;
1938 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1939         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1940         { .irq = -1 }
1941 };
1942
1943 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1944         {
1945                 .pa_start       = 0x48057000,
1946                 .pa_end         = 0x480571ff,
1947                 .flags          = ADDR_TYPE_RT
1948         },
1949         { }
1950 };
1951
1952 /* l4_per -> gpio3 */
1953 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1954         .master         = &omap44xx_l4_per_hwmod,
1955         .slave          = &omap44xx_gpio3_hwmod,
1956         .clk            = "l4_div_ck",
1957         .addr           = omap44xx_gpio3_addrs,
1958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1959 };
1960
1961 /* gpio3 slave ports */
1962 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1963         &omap44xx_l4_per__gpio3,
1964 };
1965
1966 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1967         { .role = "dbclk", .clk = "gpio3_dbclk" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1971         .name           = "gpio3",
1972         .class          = &omap44xx_gpio_hwmod_class,
1973         .clkdm_name     = "l4_per_clkdm",
1974         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1975         .mpu_irqs       = omap44xx_gpio3_irqs,
1976         .main_clk       = "gpio3_ick",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_HWCTRL,
1982                 },
1983         },
1984         .opt_clks       = gpio3_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1986         .dev_attr       = &gpio_dev_attr,
1987         .slaves         = omap44xx_gpio3_slaves,
1988         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1989 };
1990
1991 /* gpio4 */
1992 static struct omap_hwmod omap44xx_gpio4_hwmod;
1993 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1994         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1995         { .irq = -1 }
1996 };
1997
1998 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1999         {
2000                 .pa_start       = 0x48059000,
2001                 .pa_end         = 0x480591ff,
2002                 .flags          = ADDR_TYPE_RT
2003         },
2004         { }
2005 };
2006
2007 /* l4_per -> gpio4 */
2008 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2009         .master         = &omap44xx_l4_per_hwmod,
2010         .slave          = &omap44xx_gpio4_hwmod,
2011         .clk            = "l4_div_ck",
2012         .addr           = omap44xx_gpio4_addrs,
2013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2014 };
2015
2016 /* gpio4 slave ports */
2017 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2018         &omap44xx_l4_per__gpio4,
2019 };
2020
2021 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2022         { .role = "dbclk", .clk = "gpio4_dbclk" },
2023 };
2024
2025 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2026         .name           = "gpio4",
2027         .class          = &omap44xx_gpio_hwmod_class,
2028         .clkdm_name     = "l4_per_clkdm",
2029         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2030         .mpu_irqs       = omap44xx_gpio4_irqs,
2031         .main_clk       = "gpio4_ick",
2032         .prcm = {
2033                 .omap4 = {
2034                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2035                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2036                         .modulemode   = MODULEMODE_HWCTRL,
2037                 },
2038         },
2039         .opt_clks       = gpio4_opt_clks,
2040         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2041         .dev_attr       = &gpio_dev_attr,
2042         .slaves         = omap44xx_gpio4_slaves,
2043         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2044 };
2045
2046 /* gpio5 */
2047 static struct omap_hwmod omap44xx_gpio5_hwmod;
2048 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2049         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2050         { .irq = -1 }
2051 };
2052
2053 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2054         {
2055                 .pa_start       = 0x4805b000,
2056                 .pa_end         = 0x4805b1ff,
2057                 .flags          = ADDR_TYPE_RT
2058         },
2059         { }
2060 };
2061
2062 /* l4_per -> gpio5 */
2063 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2064         .master         = &omap44xx_l4_per_hwmod,
2065         .slave          = &omap44xx_gpio5_hwmod,
2066         .clk            = "l4_div_ck",
2067         .addr           = omap44xx_gpio5_addrs,
2068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2069 };
2070
2071 /* gpio5 slave ports */
2072 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2073         &omap44xx_l4_per__gpio5,
2074 };
2075
2076 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2077         { .role = "dbclk", .clk = "gpio5_dbclk" },
2078 };
2079
2080 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2081         .name           = "gpio5",
2082         .class          = &omap44xx_gpio_hwmod_class,
2083         .clkdm_name     = "l4_per_clkdm",
2084         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2085         .mpu_irqs       = omap44xx_gpio5_irqs,
2086         .main_clk       = "gpio5_ick",
2087         .prcm = {
2088                 .omap4 = {
2089                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2090                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2091                         .modulemode   = MODULEMODE_HWCTRL,
2092                 },
2093         },
2094         .opt_clks       = gpio5_opt_clks,
2095         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2096         .dev_attr       = &gpio_dev_attr,
2097         .slaves         = omap44xx_gpio5_slaves,
2098         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2099 };
2100
2101 /* gpio6 */
2102 static struct omap_hwmod omap44xx_gpio6_hwmod;
2103 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2104         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2105         { .irq = -1 }
2106 };
2107
2108 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2109         {
2110                 .pa_start       = 0x4805d000,
2111                 .pa_end         = 0x4805d1ff,
2112                 .flags          = ADDR_TYPE_RT
2113         },
2114         { }
2115 };
2116
2117 /* l4_per -> gpio6 */
2118 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2119         .master         = &omap44xx_l4_per_hwmod,
2120         .slave          = &omap44xx_gpio6_hwmod,
2121         .clk            = "l4_div_ck",
2122         .addr           = omap44xx_gpio6_addrs,
2123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2124 };
2125
2126 /* gpio6 slave ports */
2127 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2128         &omap44xx_l4_per__gpio6,
2129 };
2130
2131 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2132         { .role = "dbclk", .clk = "gpio6_dbclk" },
2133 };
2134
2135 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2136         .name           = "gpio6",
2137         .class          = &omap44xx_gpio_hwmod_class,
2138         .clkdm_name     = "l4_per_clkdm",
2139         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2140         .mpu_irqs       = omap44xx_gpio6_irqs,
2141         .main_clk       = "gpio6_ick",
2142         .prcm = {
2143                 .omap4 = {
2144                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2145                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2146                         .modulemode   = MODULEMODE_HWCTRL,
2147                 },
2148         },
2149         .opt_clks       = gpio6_opt_clks,
2150         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2151         .dev_attr       = &gpio_dev_attr,
2152         .slaves         = omap44xx_gpio6_slaves,
2153         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2154 };
2155
2156 /*
2157  * 'hsi' class
2158  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2159  * serial if)
2160  */
2161
2162 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2163         .rev_offs       = 0x0000,
2164         .sysc_offs      = 0x0010,
2165         .syss_offs      = 0x0014,
2166         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2167                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2168                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2169         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2170                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2171                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2172         .sysc_fields    = &omap_hwmod_sysc_type1,
2173 };
2174
2175 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2176         .name   = "hsi",
2177         .sysc   = &omap44xx_hsi_sysc,
2178 };
2179
2180 /* hsi */
2181 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2182         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2183         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2184         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2185         { .irq = -1 }
2186 };
2187
2188 /* hsi master ports */
2189 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2190         &omap44xx_hsi__l3_main_2,
2191 };
2192
2193 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2194         {
2195                 .pa_start       = 0x4a058000,
2196                 .pa_end         = 0x4a05bfff,
2197                 .flags          = ADDR_TYPE_RT
2198         },
2199         { }
2200 };
2201
2202 /* l4_cfg -> hsi */
2203 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2204         .master         = &omap44xx_l4_cfg_hwmod,
2205         .slave          = &omap44xx_hsi_hwmod,
2206         .clk            = "l4_div_ck",
2207         .addr           = omap44xx_hsi_addrs,
2208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2209 };
2210
2211 /* hsi slave ports */
2212 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2213         &omap44xx_l4_cfg__hsi,
2214 };
2215
2216 static struct omap_hwmod omap44xx_hsi_hwmod = {
2217         .name           = "hsi",
2218         .class          = &omap44xx_hsi_hwmod_class,
2219         .clkdm_name     = "l3_init_clkdm",
2220         .mpu_irqs       = omap44xx_hsi_irqs,
2221         .main_clk       = "hsi_fck",
2222         .prcm = {
2223                 .omap4 = {
2224                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2225                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2226                         .modulemode   = MODULEMODE_HWCTRL,
2227                 },
2228         },
2229         .slaves         = omap44xx_hsi_slaves,
2230         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2231         .masters        = omap44xx_hsi_masters,
2232         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2233 };
2234
2235 /*
2236  * 'i2c' class
2237  * multimaster high-speed i2c controller
2238  */
2239
2240 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2241         .sysc_offs      = 0x0010,
2242         .syss_offs      = 0x0090,
2243         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2244                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2245                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2246         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2247                            SIDLE_SMART_WKUP),
2248         .sysc_fields    = &omap_hwmod_sysc_type1,
2249 };
2250
2251 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2252         .name   = "i2c",
2253         .sysc   = &omap44xx_i2c_sysc,
2254         .rev    = OMAP_I2C_IP_VERSION_2,
2255         .reset  = &omap_i2c_reset,
2256 };
2257
2258 static struct omap_i2c_dev_attr i2c_dev_attr = {
2259         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2260 };
2261
2262 /* i2c1 */
2263 static struct omap_hwmod omap44xx_i2c1_hwmod;
2264 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2265         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2266         { .irq = -1 }
2267 };
2268
2269 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2270         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2271         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2272         { .dma_req = -1 }
2273 };
2274
2275 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2276         {
2277                 .pa_start       = 0x48070000,
2278                 .pa_end         = 0x480700ff,
2279                 .flags          = ADDR_TYPE_RT
2280         },
2281         { }
2282 };
2283
2284 /* l4_per -> i2c1 */
2285 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2286         .master         = &omap44xx_l4_per_hwmod,
2287         .slave          = &omap44xx_i2c1_hwmod,
2288         .clk            = "l4_div_ck",
2289         .addr           = omap44xx_i2c1_addrs,
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292
2293 /* i2c1 slave ports */
2294 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2295         &omap44xx_l4_per__i2c1,
2296 };
2297
2298 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2299         .name           = "i2c1",
2300         .class          = &omap44xx_i2c_hwmod_class,
2301         .clkdm_name     = "l4_per_clkdm",
2302         .flags          = HWMOD_16BIT_REG,
2303         .mpu_irqs       = omap44xx_i2c1_irqs,
2304         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2305         .main_clk       = "i2c1_fck",
2306         .prcm = {
2307                 .omap4 = {
2308                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2309                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2310                         .modulemode   = MODULEMODE_SWCTRL,
2311                 },
2312         },
2313         .slaves         = omap44xx_i2c1_slaves,
2314         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2315         .dev_attr       = &i2c_dev_attr,
2316 };
2317
2318 /* i2c2 */
2319 static struct omap_hwmod omap44xx_i2c2_hwmod;
2320 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2321         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2322         { .irq = -1 }
2323 };
2324
2325 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2326         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2327         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2328         { .dma_req = -1 }
2329 };
2330
2331 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2332         {
2333                 .pa_start       = 0x48072000,
2334                 .pa_end         = 0x480720ff,
2335                 .flags          = ADDR_TYPE_RT
2336         },
2337         { }
2338 };
2339
2340 /* l4_per -> i2c2 */
2341 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2342         .master         = &omap44xx_l4_per_hwmod,
2343         .slave          = &omap44xx_i2c2_hwmod,
2344         .clk            = "l4_div_ck",
2345         .addr           = omap44xx_i2c2_addrs,
2346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2347 };
2348
2349 /* i2c2 slave ports */
2350 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2351         &omap44xx_l4_per__i2c2,
2352 };
2353
2354 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2355         .name           = "i2c2",
2356         .class          = &omap44xx_i2c_hwmod_class,
2357         .clkdm_name     = "l4_per_clkdm",
2358         .flags          = HWMOD_16BIT_REG,
2359         .mpu_irqs       = omap44xx_i2c2_irqs,
2360         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2361         .main_clk       = "i2c2_fck",
2362         .prcm = {
2363                 .omap4 = {
2364                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2365                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2366                         .modulemode   = MODULEMODE_SWCTRL,
2367                 },
2368         },
2369         .slaves         = omap44xx_i2c2_slaves,
2370         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2371         .dev_attr       = &i2c_dev_attr,
2372 };
2373
2374 /* i2c3 */
2375 static struct omap_hwmod omap44xx_i2c3_hwmod;
2376 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2377         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2378         { .irq = -1 }
2379 };
2380
2381 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2382         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2383         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2384         { .dma_req = -1 }
2385 };
2386
2387 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2388         {
2389                 .pa_start       = 0x48060000,
2390                 .pa_end         = 0x480600ff,
2391                 .flags          = ADDR_TYPE_RT
2392         },
2393         { }
2394 };
2395
2396 /* l4_per -> i2c3 */
2397 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2398         .master         = &omap44xx_l4_per_hwmod,
2399         .slave          = &omap44xx_i2c3_hwmod,
2400         .clk            = "l4_div_ck",
2401         .addr           = omap44xx_i2c3_addrs,
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* i2c3 slave ports */
2406 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2407         &omap44xx_l4_per__i2c3,
2408 };
2409
2410 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2411         .name           = "i2c3",
2412         .class          = &omap44xx_i2c_hwmod_class,
2413         .clkdm_name     = "l4_per_clkdm",
2414         .flags          = HWMOD_16BIT_REG,
2415         .mpu_irqs       = omap44xx_i2c3_irqs,
2416         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2417         .main_clk       = "i2c3_fck",
2418         .prcm = {
2419                 .omap4 = {
2420                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2421                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2422                         .modulemode   = MODULEMODE_SWCTRL,
2423                 },
2424         },
2425         .slaves         = omap44xx_i2c3_slaves,
2426         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2427         .dev_attr       = &i2c_dev_attr,
2428 };
2429
2430 /* i2c4 */
2431 static struct omap_hwmod omap44xx_i2c4_hwmod;
2432 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2433         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2434         { .irq = -1 }
2435 };
2436
2437 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2438         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2439         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2440         { .dma_req = -1 }
2441 };
2442
2443 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2444         {
2445                 .pa_start       = 0x48350000,
2446                 .pa_end         = 0x483500ff,
2447                 .flags          = ADDR_TYPE_RT
2448         },
2449         { }
2450 };
2451
2452 /* l4_per -> i2c4 */
2453 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2454         .master         = &omap44xx_l4_per_hwmod,
2455         .slave          = &omap44xx_i2c4_hwmod,
2456         .clk            = "l4_div_ck",
2457         .addr           = omap44xx_i2c4_addrs,
2458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2459 };
2460
2461 /* i2c4 slave ports */
2462 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2463         &omap44xx_l4_per__i2c4,
2464 };
2465
2466 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2467         .name           = "i2c4",
2468         .class          = &omap44xx_i2c_hwmod_class,
2469         .clkdm_name     = "l4_per_clkdm",
2470         .flags          = HWMOD_16BIT_REG,
2471         .mpu_irqs       = omap44xx_i2c4_irqs,
2472         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2473         .main_clk       = "i2c4_fck",
2474         .prcm = {
2475                 .omap4 = {
2476                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2477                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2478                         .modulemode   = MODULEMODE_SWCTRL,
2479                 },
2480         },
2481         .slaves         = omap44xx_i2c4_slaves,
2482         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2483         .dev_attr       = &i2c_dev_attr,
2484 };
2485
2486 /*
2487  * 'ipu' class
2488  * imaging processor unit
2489  */
2490
2491 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2492         .name   = "ipu",
2493 };
2494
2495 /* ipu */
2496 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2497         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2498         { .irq = -1 }
2499 };
2500
2501 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2502         { .name = "cpu0", .rst_shift = 0 },
2503 };
2504
2505 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2506         { .name = "cpu1", .rst_shift = 1 },
2507 };
2508
2509 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2510         { .name = "mmu_cache", .rst_shift = 2 },
2511 };
2512
2513 /* ipu master ports */
2514 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2515         &omap44xx_ipu__l3_main_2,
2516 };
2517
2518 /* l3_main_2 -> ipu */
2519 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2520         .master         = &omap44xx_l3_main_2_hwmod,
2521         .slave          = &omap44xx_ipu_hwmod,
2522         .clk            = "l3_div_ck",
2523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2524 };
2525
2526 /* ipu slave ports */
2527 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2528         &omap44xx_l3_main_2__ipu,
2529 };
2530
2531 /* Pseudo hwmod for reset control purpose only */
2532 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2533         .name           = "ipu_c0",
2534         .class          = &omap44xx_ipu_hwmod_class,
2535         .clkdm_name     = "ducati_clkdm",
2536         .flags          = HWMOD_INIT_NO_RESET,
2537         .rst_lines      = omap44xx_ipu_c0_resets,
2538         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2539         .prcm = {
2540                 .omap4 = {
2541                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2542                 },
2543         },
2544 };
2545
2546 /* Pseudo hwmod for reset control purpose only */
2547 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2548         .name           = "ipu_c1",
2549         .class          = &omap44xx_ipu_hwmod_class,
2550         .clkdm_name     = "ducati_clkdm",
2551         .flags          = HWMOD_INIT_NO_RESET,
2552         .rst_lines      = omap44xx_ipu_c1_resets,
2553         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2554         .prcm = {
2555                 .omap4 = {
2556                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2557                 },
2558         },
2559 };
2560
2561 static struct omap_hwmod omap44xx_ipu_hwmod = {
2562         .name           = "ipu",
2563         .class          = &omap44xx_ipu_hwmod_class,
2564         .clkdm_name     = "ducati_clkdm",
2565         .mpu_irqs       = omap44xx_ipu_irqs,
2566         .rst_lines      = omap44xx_ipu_resets,
2567         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2568         .main_clk       = "ipu_fck",
2569         .prcm = {
2570                 .omap4 = {
2571                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2572                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2573                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2574                         .modulemode   = MODULEMODE_HWCTRL,
2575                 },
2576         },
2577         .slaves         = omap44xx_ipu_slaves,
2578         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2579         .masters        = omap44xx_ipu_masters,
2580         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2581 };
2582
2583 /*
2584  * 'iss' class
2585  * external images sensor pixel data processor
2586  */
2587
2588 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2589         .rev_offs       = 0x0000,
2590         .sysc_offs      = 0x0010,
2591         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2594                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2595                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2596         .sysc_fields    = &omap_hwmod_sysc_type2,
2597 };
2598
2599 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2600         .name   = "iss",
2601         .sysc   = &omap44xx_iss_sysc,
2602 };
2603
2604 /* iss */
2605 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2606         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2607         { .irq = -1 }
2608 };
2609
2610 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2611         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2612         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2613         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2614         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2615         { .dma_req = -1 }
2616 };
2617
2618 /* iss master ports */
2619 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2620         &omap44xx_iss__l3_main_2,
2621 };
2622
2623 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2624         {
2625                 .pa_start       = 0x52000000,
2626                 .pa_end         = 0x520000ff,
2627                 .flags          = ADDR_TYPE_RT
2628         },
2629         { }
2630 };
2631
2632 /* l3_main_2 -> iss */
2633 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2634         .master         = &omap44xx_l3_main_2_hwmod,
2635         .slave          = &omap44xx_iss_hwmod,
2636         .clk            = "l3_div_ck",
2637         .addr           = omap44xx_iss_addrs,
2638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2639 };
2640
2641 /* iss slave ports */
2642 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2643         &omap44xx_l3_main_2__iss,
2644 };
2645
2646 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2647         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2648 };
2649
2650 static struct omap_hwmod omap44xx_iss_hwmod = {
2651         .name           = "iss",
2652         .class          = &omap44xx_iss_hwmod_class,
2653         .clkdm_name     = "iss_clkdm",
2654         .mpu_irqs       = omap44xx_iss_irqs,
2655         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2656         .main_clk       = "iss_fck",
2657         .prcm = {
2658                 .omap4 = {
2659                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2660                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2661                         .modulemode   = MODULEMODE_SWCTRL,
2662                 },
2663         },
2664         .opt_clks       = iss_opt_clks,
2665         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2666         .slaves         = omap44xx_iss_slaves,
2667         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2668         .masters        = omap44xx_iss_masters,
2669         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2670 };
2671
2672 /*
2673  * 'iva' class
2674  * multi-standard video encoder/decoder hardware accelerator
2675  */
2676
2677 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2678         .name   = "iva",
2679 };
2680
2681 /* iva */
2682 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2683         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2684         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2685         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2686         { .irq = -1 }
2687 };
2688
2689 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2690         { .name = "logic", .rst_shift = 2 },
2691 };
2692
2693 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2694         { .name = "seq0", .rst_shift = 0 },
2695 };
2696
2697 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2698         { .name = "seq1", .rst_shift = 1 },
2699 };
2700
2701 /* iva master ports */
2702 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2703         &omap44xx_iva__l3_main_2,
2704         &omap44xx_iva__l3_instr,
2705 };
2706
2707 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2708         {
2709                 .pa_start       = 0x5a000000,
2710                 .pa_end         = 0x5a07ffff,
2711                 .flags          = ADDR_TYPE_RT
2712         },
2713         { }
2714 };
2715
2716 /* l3_main_2 -> iva */
2717 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2718         .master         = &omap44xx_l3_main_2_hwmod,
2719         .slave          = &omap44xx_iva_hwmod,
2720         .clk            = "l3_div_ck",
2721         .addr           = omap44xx_iva_addrs,
2722         .user           = OCP_USER_MPU,
2723 };
2724
2725 /* iva slave ports */
2726 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2727         &omap44xx_dsp__iva,
2728         &omap44xx_l3_main_2__iva,
2729 };
2730
2731 /* Pseudo hwmod for reset control purpose only */
2732 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2733         .name           = "iva_seq0",
2734         .class          = &omap44xx_iva_hwmod_class,
2735         .clkdm_name     = "ivahd_clkdm",
2736         .flags          = HWMOD_INIT_NO_RESET,
2737         .rst_lines      = omap44xx_iva_seq0_resets,
2738         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2739         .prcm = {
2740                 .omap4 = {
2741                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2742                 },
2743         },
2744 };
2745
2746 /* Pseudo hwmod for reset control purpose only */
2747 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2748         .name           = "iva_seq1",
2749         .class          = &omap44xx_iva_hwmod_class,
2750         .clkdm_name     = "ivahd_clkdm",
2751         .flags          = HWMOD_INIT_NO_RESET,
2752         .rst_lines      = omap44xx_iva_seq1_resets,
2753         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2754         .prcm = {
2755                 .omap4 = {
2756                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2757                 },
2758         },
2759 };
2760
2761 static struct omap_hwmod omap44xx_iva_hwmod = {
2762         .name           = "iva",
2763         .class          = &omap44xx_iva_hwmod_class,
2764         .clkdm_name     = "ivahd_clkdm",
2765         .mpu_irqs       = omap44xx_iva_irqs,
2766         .rst_lines      = omap44xx_iva_resets,
2767         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2768         .main_clk       = "iva_fck",
2769         .prcm = {
2770                 .omap4 = {
2771                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2772                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2773                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2774                         .modulemode   = MODULEMODE_HWCTRL,
2775                 },
2776         },
2777         .slaves         = omap44xx_iva_slaves,
2778         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2779         .masters        = omap44xx_iva_masters,
2780         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2781 };
2782
2783 /*
2784  * 'kbd' class
2785  * keyboard controller
2786  */
2787
2788 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2789         .rev_offs       = 0x0000,
2790         .sysc_offs      = 0x0010,
2791         .syss_offs      = 0x0014,
2792         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2793                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2794                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2795                            SYSS_HAS_RESET_STATUS),
2796         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2797         .sysc_fields    = &omap_hwmod_sysc_type1,
2798 };
2799
2800 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2801         .name   = "kbd",
2802         .sysc   = &omap44xx_kbd_sysc,
2803 };
2804
2805 /* kbd */
2806 static struct omap_hwmod omap44xx_kbd_hwmod;
2807 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2808         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2809         { .irq = -1 }
2810 };
2811
2812 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2813         {
2814                 .pa_start       = 0x4a31c000,
2815                 .pa_end         = 0x4a31c07f,
2816                 .flags          = ADDR_TYPE_RT
2817         },
2818         { }
2819 };
2820
2821 /* l4_wkup -> kbd */
2822 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2823         .master         = &omap44xx_l4_wkup_hwmod,
2824         .slave          = &omap44xx_kbd_hwmod,
2825         .clk            = "l4_wkup_clk_mux_ck",
2826         .addr           = omap44xx_kbd_addrs,
2827         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2828 };
2829
2830 /* kbd slave ports */
2831 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2832         &omap44xx_l4_wkup__kbd,
2833 };
2834
2835 static struct omap_hwmod omap44xx_kbd_hwmod = {
2836         .name           = "kbd",
2837         .class          = &omap44xx_kbd_hwmod_class,
2838         .clkdm_name     = "l4_wkup_clkdm",
2839         .mpu_irqs       = omap44xx_kbd_irqs,
2840         .main_clk       = "kbd_fck",
2841         .prcm = {
2842                 .omap4 = {
2843                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2844                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2845                         .modulemode   = MODULEMODE_SWCTRL,
2846                 },
2847         },
2848         .slaves         = omap44xx_kbd_slaves,
2849         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2850 };
2851
2852 /*
2853  * 'mailbox' class
2854  * mailbox module allowing communication between the on-chip processors using a
2855  * queued mailbox-interrupt mechanism.
2856  */
2857
2858 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2859         .rev_offs       = 0x0000,
2860         .sysc_offs      = 0x0010,
2861         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2862                            SYSC_HAS_SOFTRESET),
2863         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2864         .sysc_fields    = &omap_hwmod_sysc_type2,
2865 };
2866
2867 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2868         .name   = "mailbox",
2869         .sysc   = &omap44xx_mailbox_sysc,
2870 };
2871
2872 /* mailbox */
2873 static struct omap_hwmod omap44xx_mailbox_hwmod;
2874 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2875         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2876         { .irq = -1 }
2877 };
2878
2879 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2880         {
2881                 .pa_start       = 0x4a0f4000,
2882                 .pa_end         = 0x4a0f41ff,
2883                 .flags          = ADDR_TYPE_RT
2884         },
2885         { }
2886 };
2887
2888 /* l4_cfg -> mailbox */
2889 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2890         .master         = &omap44xx_l4_cfg_hwmod,
2891         .slave          = &omap44xx_mailbox_hwmod,
2892         .clk            = "l4_div_ck",
2893         .addr           = omap44xx_mailbox_addrs,
2894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2895 };
2896
2897 /* mailbox slave ports */
2898 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2899         &omap44xx_l4_cfg__mailbox,
2900 };
2901
2902 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2903         .name           = "mailbox",
2904         .class          = &omap44xx_mailbox_hwmod_class,
2905         .clkdm_name     = "l4_cfg_clkdm",
2906         .mpu_irqs       = omap44xx_mailbox_irqs,
2907         .prcm = {
2908                 .omap4 = {
2909                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2910                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2911                 },
2912         },
2913         .slaves         = omap44xx_mailbox_slaves,
2914         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2915 };
2916
2917 /*
2918  * 'mcbsp' class
2919  * multi channel buffered serial port controller
2920  */
2921
2922 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2923         .sysc_offs      = 0x008c,
2924         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2925                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2926         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2927         .sysc_fields    = &omap_hwmod_sysc_type1,
2928 };
2929
2930 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2931         .name   = "mcbsp",
2932         .sysc   = &omap44xx_mcbsp_sysc,
2933         .rev    = MCBSP_CONFIG_TYPE4,
2934 };
2935
2936 /* mcbsp1 */
2937 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2938 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2939         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2940         { .irq = -1 }
2941 };
2942
2943 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2944         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2945         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2946         { .dma_req = -1 }
2947 };
2948
2949 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2950         {
2951                 .name           = "mpu",
2952                 .pa_start       = 0x40122000,
2953                 .pa_end         = 0x401220ff,
2954                 .flags          = ADDR_TYPE_RT
2955         },
2956         { }
2957 };
2958
2959 /* l4_abe -> mcbsp1 */
2960 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2961         .master         = &omap44xx_l4_abe_hwmod,
2962         .slave          = &omap44xx_mcbsp1_hwmod,
2963         .clk            = "ocp_abe_iclk",
2964         .addr           = omap44xx_mcbsp1_addrs,
2965         .user           = OCP_USER_MPU,
2966 };
2967
2968 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2969         {
2970                 .name           = "dma",
2971                 .pa_start       = 0x49022000,
2972                 .pa_end         = 0x490220ff,
2973                 .flags          = ADDR_TYPE_RT
2974         },
2975         { }
2976 };
2977
2978 /* l4_abe -> mcbsp1 (dma) */
2979 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2980         .master         = &omap44xx_l4_abe_hwmod,
2981         .slave          = &omap44xx_mcbsp1_hwmod,
2982         .clk            = "ocp_abe_iclk",
2983         .addr           = omap44xx_mcbsp1_dma_addrs,
2984         .user           = OCP_USER_SDMA,
2985 };
2986
2987 /* mcbsp1 slave ports */
2988 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2989         &omap44xx_l4_abe__mcbsp1,
2990         &omap44xx_l4_abe__mcbsp1_dma,
2991 };
2992
2993 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2994         .name           = "mcbsp1",
2995         .class          = &omap44xx_mcbsp_hwmod_class,
2996         .clkdm_name     = "abe_clkdm",
2997         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2998         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2999         .main_clk       = "mcbsp1_fck",
3000         .prcm = {
3001                 .omap4 = {
3002                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3003                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3004                         .modulemode   = MODULEMODE_SWCTRL,
3005                 },
3006         },
3007         .slaves         = omap44xx_mcbsp1_slaves,
3008         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3009 };
3010
3011 /* mcbsp2 */
3012 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3013 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3014         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3015         { .irq = -1 }
3016 };
3017
3018 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3019         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3020         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3021         { .dma_req = -1 }
3022 };
3023
3024 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3025         {
3026                 .name           = "mpu",
3027                 .pa_start       = 0x40124000,
3028                 .pa_end         = 0x401240ff,
3029                 .flags          = ADDR_TYPE_RT
3030         },
3031         { }
3032 };
3033
3034 /* l4_abe -> mcbsp2 */
3035 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3036         .master         = &omap44xx_l4_abe_hwmod,
3037         .slave          = &omap44xx_mcbsp2_hwmod,
3038         .clk            = "ocp_abe_iclk",
3039         .addr           = omap44xx_mcbsp2_addrs,
3040         .user           = OCP_USER_MPU,
3041 };
3042
3043 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3044         {
3045                 .name           = "dma",
3046                 .pa_start       = 0x49024000,
3047                 .pa_end         = 0x490240ff,
3048                 .flags          = ADDR_TYPE_RT
3049         },
3050         { }
3051 };
3052
3053 /* l4_abe -> mcbsp2 (dma) */
3054 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3055         .master         = &omap44xx_l4_abe_hwmod,
3056         .slave          = &omap44xx_mcbsp2_hwmod,
3057         .clk            = "ocp_abe_iclk",
3058         .addr           = omap44xx_mcbsp2_dma_addrs,
3059         .user           = OCP_USER_SDMA,
3060 };
3061
3062 /* mcbsp2 slave ports */
3063 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3064         &omap44xx_l4_abe__mcbsp2,
3065         &omap44xx_l4_abe__mcbsp2_dma,
3066 };
3067
3068 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3069         .name           = "mcbsp2",
3070         .class          = &omap44xx_mcbsp_hwmod_class,
3071         .clkdm_name     = "abe_clkdm",
3072         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3073         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3074         .main_clk       = "mcbsp2_fck",
3075         .prcm = {
3076                 .omap4 = {
3077                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3078                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3079                         .modulemode   = MODULEMODE_SWCTRL,
3080                 },
3081         },
3082         .slaves         = omap44xx_mcbsp2_slaves,
3083         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3084 };
3085
3086 /* mcbsp3 */
3087 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3088 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3089         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3090         { .irq = -1 }
3091 };
3092
3093 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3094         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3095         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3096         { .dma_req = -1 }
3097 };
3098
3099 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3100         {
3101                 .name           = "mpu",
3102                 .pa_start       = 0x40126000,
3103                 .pa_end         = 0x401260ff,
3104                 .flags          = ADDR_TYPE_RT
3105         },
3106         { }
3107 };
3108
3109 /* l4_abe -> mcbsp3 */
3110 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3111         .master         = &omap44xx_l4_abe_hwmod,
3112         .slave          = &omap44xx_mcbsp3_hwmod,
3113         .clk            = "ocp_abe_iclk",
3114         .addr           = omap44xx_mcbsp3_addrs,
3115         .user           = OCP_USER_MPU,
3116 };
3117
3118 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3119         {
3120                 .name           = "dma",
3121                 .pa_start       = 0x49026000,
3122                 .pa_end         = 0x490260ff,
3123                 .flags          = ADDR_TYPE_RT
3124         },
3125         { }
3126 };
3127
3128 /* l4_abe -> mcbsp3 (dma) */
3129 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3130         .master         = &omap44xx_l4_abe_hwmod,
3131         .slave          = &omap44xx_mcbsp3_hwmod,
3132         .clk            = "ocp_abe_iclk",
3133         .addr           = omap44xx_mcbsp3_dma_addrs,
3134         .user           = OCP_USER_SDMA,
3135 };
3136
3137 /* mcbsp3 slave ports */
3138 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3139         &omap44xx_l4_abe__mcbsp3,
3140         &omap44xx_l4_abe__mcbsp3_dma,
3141 };
3142
3143 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3144         .name           = "mcbsp3",
3145         .class          = &omap44xx_mcbsp_hwmod_class,
3146         .clkdm_name     = "abe_clkdm",
3147         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3148         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3149         .main_clk       = "mcbsp3_fck",
3150         .prcm = {
3151                 .omap4 = {
3152                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3153                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3154                         .modulemode   = MODULEMODE_SWCTRL,
3155                 },
3156         },
3157         .slaves         = omap44xx_mcbsp3_slaves,
3158         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3159 };
3160
3161 /* mcbsp4 */
3162 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3163 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3164         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3165         { .irq = -1 }
3166 };
3167
3168 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3169         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3170         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3171         { .dma_req = -1 }
3172 };
3173
3174 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3175         {
3176                 .pa_start       = 0x48096000,
3177                 .pa_end         = 0x480960ff,
3178                 .flags          = ADDR_TYPE_RT
3179         },
3180         { }
3181 };
3182
3183 /* l4_per -> mcbsp4 */
3184 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3185         .master         = &omap44xx_l4_per_hwmod,
3186         .slave          = &omap44xx_mcbsp4_hwmod,
3187         .clk            = "l4_div_ck",
3188         .addr           = omap44xx_mcbsp4_addrs,
3189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3190 };
3191
3192 /* mcbsp4 slave ports */
3193 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3194         &omap44xx_l4_per__mcbsp4,
3195 };
3196
3197 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3198         .name           = "mcbsp4",
3199         .class          = &omap44xx_mcbsp_hwmod_class,
3200         .clkdm_name     = "l4_per_clkdm",
3201         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3202         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3203         .main_clk       = "mcbsp4_fck",
3204         .prcm = {
3205                 .omap4 = {
3206                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3207                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3208                         .modulemode   = MODULEMODE_SWCTRL,
3209                 },
3210         },
3211         .slaves         = omap44xx_mcbsp4_slaves,
3212         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3213 };
3214
3215 /*
3216  * 'mcpdm' class
3217  * multi channel pdm controller (proprietary interface with phoenix power
3218  * ic)
3219  */
3220
3221 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3222         .rev_offs       = 0x0000,
3223         .sysc_offs      = 0x0010,
3224         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3225                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3226         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3227                            SIDLE_SMART_WKUP),
3228         .sysc_fields    = &omap_hwmod_sysc_type2,
3229 };
3230
3231 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3232         .name   = "mcpdm",
3233         .sysc   = &omap44xx_mcpdm_sysc,
3234 };
3235
3236 /* mcpdm */
3237 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3238 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3239         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3240         { .irq = -1 }
3241 };
3242
3243 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3244         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3245         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3246         { .dma_req = -1 }
3247 };
3248
3249 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3250         {
3251                 .pa_start       = 0x40132000,
3252                 .pa_end         = 0x4013207f,
3253                 .flags          = ADDR_TYPE_RT
3254         },
3255         { }
3256 };
3257
3258 /* l4_abe -> mcpdm */
3259 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3260         .master         = &omap44xx_l4_abe_hwmod,
3261         .slave          = &omap44xx_mcpdm_hwmod,
3262         .clk            = "ocp_abe_iclk",
3263         .addr           = omap44xx_mcpdm_addrs,
3264         .user           = OCP_USER_MPU,
3265 };
3266
3267 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3268         {
3269                 .pa_start       = 0x49032000,
3270                 .pa_end         = 0x4903207f,
3271                 .flags          = ADDR_TYPE_RT
3272         },
3273         { }
3274 };
3275
3276 /* l4_abe -> mcpdm (dma) */
3277 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3278         .master         = &omap44xx_l4_abe_hwmod,
3279         .slave          = &omap44xx_mcpdm_hwmod,
3280         .clk            = "ocp_abe_iclk",
3281         .addr           = omap44xx_mcpdm_dma_addrs,
3282         .user           = OCP_USER_SDMA,
3283 };
3284
3285 /* mcpdm slave ports */
3286 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3287         &omap44xx_l4_abe__mcpdm,
3288         &omap44xx_l4_abe__mcpdm_dma,
3289 };
3290
3291 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3292         .name           = "mcpdm",
3293         .class          = &omap44xx_mcpdm_hwmod_class,
3294         .clkdm_name     = "abe_clkdm",
3295         .mpu_irqs       = omap44xx_mcpdm_irqs,
3296         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3297         .main_clk       = "mcpdm_fck",
3298         .prcm = {
3299                 .omap4 = {
3300                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3301                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3302                         .modulemode   = MODULEMODE_SWCTRL,
3303                 },
3304         },
3305         .slaves         = omap44xx_mcpdm_slaves,
3306         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3307 };
3308
3309 /*
3310  * 'mcspi' class
3311  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3312  * bus
3313  */
3314
3315 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3316         .rev_offs       = 0x0000,
3317         .sysc_offs      = 0x0010,
3318         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3319                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3321                            SIDLE_SMART_WKUP),
3322         .sysc_fields    = &omap_hwmod_sysc_type2,
3323 };
3324
3325 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3326         .name   = "mcspi",
3327         .sysc   = &omap44xx_mcspi_sysc,
3328         .rev    = OMAP4_MCSPI_REV,
3329 };
3330
3331 /* mcspi1 */
3332 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3333 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3334         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3335         { .irq = -1 }
3336 };
3337
3338 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3339         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3340         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3341         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3342         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3343         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3344         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3345         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3346         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3347         { .dma_req = -1 }
3348 };
3349
3350 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3351         {
3352                 .pa_start       = 0x48098000,
3353                 .pa_end         = 0x480981ff,
3354                 .flags          = ADDR_TYPE_RT
3355         },
3356         { }
3357 };
3358
3359 /* l4_per -> mcspi1 */
3360 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3361         .master         = &omap44xx_l4_per_hwmod,
3362         .slave          = &omap44xx_mcspi1_hwmod,
3363         .clk            = "l4_div_ck",
3364         .addr           = omap44xx_mcspi1_addrs,
3365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3366 };
3367
3368 /* mcspi1 slave ports */
3369 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3370         &omap44xx_l4_per__mcspi1,
3371 };
3372
3373 /* mcspi1 dev_attr */
3374 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3375         .num_chipselect = 4,
3376 };
3377
3378 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3379         .name           = "mcspi1",
3380         .class          = &omap44xx_mcspi_hwmod_class,
3381         .clkdm_name     = "l4_per_clkdm",
3382         .mpu_irqs       = omap44xx_mcspi1_irqs,
3383         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3384         .main_clk       = "mcspi1_fck",
3385         .prcm = {
3386                 .omap4 = {
3387                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3388                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3389                         .modulemode   = MODULEMODE_SWCTRL,
3390                 },
3391         },
3392         .dev_attr       = &mcspi1_dev_attr,
3393         .slaves         = omap44xx_mcspi1_slaves,
3394         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3395 };
3396
3397 /* mcspi2 */
3398 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3399 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3400         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3401         { .irq = -1 }
3402 };
3403
3404 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3405         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3406         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3407         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3408         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3409         { .dma_req = -1 }
3410 };
3411
3412 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3413         {
3414                 .pa_start       = 0x4809a000,
3415                 .pa_end         = 0x4809a1ff,
3416                 .flags          = ADDR_TYPE_RT
3417         },
3418         { }
3419 };
3420
3421 /* l4_per -> mcspi2 */
3422 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3423         .master         = &omap44xx_l4_per_hwmod,
3424         .slave          = &omap44xx_mcspi2_hwmod,
3425         .clk            = "l4_div_ck",
3426         .addr           = omap44xx_mcspi2_addrs,
3427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3428 };
3429
3430 /* mcspi2 slave ports */
3431 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3432         &omap44xx_l4_per__mcspi2,
3433 };
3434
3435 /* mcspi2 dev_attr */
3436 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3437         .num_chipselect = 2,
3438 };
3439
3440 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3441         .name           = "mcspi2",
3442         .class          = &omap44xx_mcspi_hwmod_class,
3443         .clkdm_name     = "l4_per_clkdm",
3444         .mpu_irqs       = omap44xx_mcspi2_irqs,
3445         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3446         .main_clk       = "mcspi2_fck",
3447         .prcm = {
3448                 .omap4 = {
3449                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3450                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3451                         .modulemode   = MODULEMODE_SWCTRL,
3452                 },
3453         },
3454         .dev_attr       = &mcspi2_dev_attr,
3455         .slaves         = omap44xx_mcspi2_slaves,
3456         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3457 };
3458
3459 /* mcspi3 */
3460 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3461 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3462         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3463         { .irq = -1 }
3464 };
3465
3466 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3467         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3468         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3469         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3470         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3471         { .dma_req = -1 }
3472 };
3473
3474 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3475         {
3476                 .pa_start       = 0x480b8000,
3477                 .pa_end         = 0x480b81ff,
3478                 .flags          = ADDR_TYPE_RT
3479         },
3480         { }
3481 };
3482
3483 /* l4_per -> mcspi3 */
3484 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3485         .master         = &omap44xx_l4_per_hwmod,
3486         .slave          = &omap44xx_mcspi3_hwmod,
3487         .clk            = "l4_div_ck",
3488         .addr           = omap44xx_mcspi3_addrs,
3489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3490 };
3491
3492 /* mcspi3 slave ports */
3493 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3494         &omap44xx_l4_per__mcspi3,
3495 };
3496
3497 /* mcspi3 dev_attr */
3498 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3499         .num_chipselect = 2,
3500 };
3501
3502 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3503         .name           = "mcspi3",
3504         .class          = &omap44xx_mcspi_hwmod_class,
3505         .clkdm_name     = "l4_per_clkdm",
3506         .mpu_irqs       = omap44xx_mcspi3_irqs,
3507         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3508         .main_clk       = "mcspi3_fck",
3509         .prcm = {
3510                 .omap4 = {
3511                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3512                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3513                         .modulemode   = MODULEMODE_SWCTRL,
3514                 },
3515         },
3516         .dev_attr       = &mcspi3_dev_attr,
3517         .slaves         = omap44xx_mcspi3_slaves,
3518         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3519 };
3520
3521 /* mcspi4 */
3522 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3523 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3524         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3525         { .irq = -1 }
3526 };
3527
3528 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3529         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3530         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3531         { .dma_req = -1 }
3532 };
3533
3534 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3535         {
3536                 .pa_start       = 0x480ba000,
3537                 .pa_end         = 0x480ba1ff,
3538                 .flags          = ADDR_TYPE_RT
3539         },
3540         { }
3541 };
3542
3543 /* l4_per -> mcspi4 */
3544 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3545         .master         = &omap44xx_l4_per_hwmod,
3546         .slave          = &omap44xx_mcspi4_hwmod,
3547         .clk            = "l4_div_ck",
3548         .addr           = omap44xx_mcspi4_addrs,
3549         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3550 };
3551
3552 /* mcspi4 slave ports */
3553 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3554         &omap44xx_l4_per__mcspi4,
3555 };
3556
3557 /* mcspi4 dev_attr */
3558 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3559         .num_chipselect = 1,
3560 };
3561
3562 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3563         .name           = "mcspi4",
3564         .class          = &omap44xx_mcspi_hwmod_class,
3565         .clkdm_name     = "l4_per_clkdm",
3566         .mpu_irqs       = omap44xx_mcspi4_irqs,
3567         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3568         .main_clk       = "mcspi4_fck",
3569         .prcm = {
3570                 .omap4 = {
3571                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3572                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3573                         .modulemode   = MODULEMODE_SWCTRL,
3574                 },
3575         },
3576         .dev_attr       = &mcspi4_dev_attr,
3577         .slaves         = omap44xx_mcspi4_slaves,
3578         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3579 };
3580
3581 /*
3582  * 'mmc' class
3583  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3584  */
3585
3586 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3587         .rev_offs       = 0x0000,
3588         .sysc_offs      = 0x0010,
3589         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3590                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3591                            SYSC_HAS_SOFTRESET),
3592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3593                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3594                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3595         .sysc_fields    = &omap_hwmod_sysc_type2,
3596 };
3597
3598 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3599         .name   = "mmc",
3600         .sysc   = &omap44xx_mmc_sysc,
3601 };
3602
3603 /* mmc1 */
3604 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3605         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3606         { .irq = -1 }
3607 };
3608
3609 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3610         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3611         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3612         { .dma_req = -1 }
3613 };
3614
3615 /* mmc1 master ports */
3616 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3617         &omap44xx_mmc1__l3_main_1,
3618 };
3619
3620 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3621         {
3622                 .pa_start       = 0x4809c000,
3623                 .pa_end         = 0x4809c3ff,
3624                 .flags          = ADDR_TYPE_RT
3625         },
3626         { }
3627 };
3628
3629 /* l4_per -> mmc1 */
3630 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3631         .master         = &omap44xx_l4_per_hwmod,
3632         .slave          = &omap44xx_mmc1_hwmod,
3633         .clk            = "l4_div_ck",
3634         .addr           = omap44xx_mmc1_addrs,
3635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3636 };
3637
3638 /* mmc1 slave ports */
3639 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3640         &omap44xx_l4_per__mmc1,
3641 };
3642
3643 /* mmc1 dev_attr */
3644 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3645         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3646 };
3647
3648 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3649         .name           = "mmc1",
3650         .class          = &omap44xx_mmc_hwmod_class,
3651         .clkdm_name     = "l3_init_clkdm",
3652         .mpu_irqs       = omap44xx_mmc1_irqs,
3653         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3654         .main_clk       = "mmc1_fck",
3655         .prcm = {
3656                 .omap4 = {
3657                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3658                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3659                         .modulemode   = MODULEMODE_SWCTRL,
3660                 },
3661         },
3662         .dev_attr       = &mmc1_dev_attr,
3663         .slaves         = omap44xx_mmc1_slaves,
3664         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3665         .masters        = omap44xx_mmc1_masters,
3666         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3667 };
3668
3669 /* mmc2 */
3670 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3671         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3672         { .irq = -1 }
3673 };
3674
3675 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3676         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3677         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3678         { .dma_req = -1 }
3679 };
3680
3681 /* mmc2 master ports */
3682 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3683         &omap44xx_mmc2__l3_main_1,
3684 };
3685
3686 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3687         {
3688                 .pa_start       = 0x480b4000,
3689                 .pa_end         = 0x480b43ff,
3690                 .flags          = ADDR_TYPE_RT
3691         },
3692         { }
3693 };
3694
3695 /* l4_per -> mmc2 */
3696 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3697         .master         = &omap44xx_l4_per_hwmod,
3698         .slave          = &omap44xx_mmc2_hwmod,
3699         .clk            = "l4_div_ck",
3700         .addr           = omap44xx_mmc2_addrs,
3701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3702 };
3703
3704 /* mmc2 slave ports */
3705 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3706         &omap44xx_l4_per__mmc2,
3707 };
3708
3709 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3710         .name           = "mmc2",
3711         .class          = &omap44xx_mmc_hwmod_class,
3712         .clkdm_name     = "l3_init_clkdm",
3713         .mpu_irqs       = omap44xx_mmc2_irqs,
3714         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3715         .main_clk       = "mmc2_fck",
3716         .prcm = {
3717                 .omap4 = {
3718                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3719                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3720                         .modulemode   = MODULEMODE_SWCTRL,
3721                 },
3722         },
3723         .slaves         = omap44xx_mmc2_slaves,
3724         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3725         .masters        = omap44xx_mmc2_masters,
3726         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3727 };
3728
3729 /* mmc3 */
3730 static struct omap_hwmod omap44xx_mmc3_hwmod;
3731 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3732         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3733         { .irq = -1 }
3734 };
3735
3736 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3737         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3738         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3739         { .dma_req = -1 }
3740 };
3741
3742 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3743         {
3744                 .pa_start       = 0x480ad000,
3745                 .pa_end         = 0x480ad3ff,
3746                 .flags          = ADDR_TYPE_RT
3747         },
3748         { }
3749 };
3750
3751 /* l4_per -> mmc3 */
3752 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3753         .master         = &omap44xx_l4_per_hwmod,
3754         .slave          = &omap44xx_mmc3_hwmod,
3755         .clk            = "l4_div_ck",
3756         .addr           = omap44xx_mmc3_addrs,
3757         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3758 };
3759
3760 /* mmc3 slave ports */
3761 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3762         &omap44xx_l4_per__mmc3,
3763 };
3764
3765 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3766         .name           = "mmc3",
3767         .class          = &omap44xx_mmc_hwmod_class,
3768         .clkdm_name     = "l4_per_clkdm",
3769         .mpu_irqs       = omap44xx_mmc3_irqs,
3770         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3771         .main_clk       = "mmc3_fck",
3772         .prcm = {
3773                 .omap4 = {
3774                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3775                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3776                         .modulemode   = MODULEMODE_SWCTRL,
3777                 },
3778         },
3779         .slaves         = omap44xx_mmc3_slaves,
3780         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3781 };
3782
3783 /* mmc4 */
3784 static struct omap_hwmod omap44xx_mmc4_hwmod;
3785 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3786         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3787         { .irq = -1 }
3788 };
3789
3790 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3791         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3792         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3793         { .dma_req = -1 }
3794 };
3795
3796 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3797         {
3798                 .pa_start       = 0x480d1000,
3799                 .pa_end         = 0x480d13ff,
3800                 .flags          = ADDR_TYPE_RT
3801         },
3802         { }
3803 };
3804
3805 /* l4_per -> mmc4 */
3806 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3807         .master         = &omap44xx_l4_per_hwmod,
3808         .slave          = &omap44xx_mmc4_hwmod,
3809         .clk            = "l4_div_ck",
3810         .addr           = omap44xx_mmc4_addrs,
3811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3812 };
3813
3814 /* mmc4 slave ports */
3815 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3816         &omap44xx_l4_per__mmc4,
3817 };
3818
3819 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3820         .name           = "mmc4",
3821         .class          = &omap44xx_mmc_hwmod_class,
3822         .clkdm_name     = "l4_per_clkdm",
3823         .mpu_irqs       = omap44xx_mmc4_irqs,
3824
3825         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3826         .main_clk       = "mmc4_fck",
3827         .prcm = {
3828                 .omap4 = {
3829                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3830                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3831                         .modulemode   = MODULEMODE_SWCTRL,
3832                 },
3833         },
3834         .slaves         = omap44xx_mmc4_slaves,
3835         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3836 };
3837
3838 /* mmc5 */
3839 static struct omap_hwmod omap44xx_mmc5_hwmod;
3840 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3841         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3842         { .irq = -1 }
3843 };
3844
3845 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3846         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3847         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3848         { .dma_req = -1 }
3849 };
3850
3851 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3852         {
3853                 .pa_start       = 0x480d5000,
3854                 .pa_end         = 0x480d53ff,
3855                 .flags          = ADDR_TYPE_RT
3856         },
3857         { }
3858 };
3859
3860 /* l4_per -> mmc5 */
3861 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3862         .master         = &omap44xx_l4_per_hwmod,
3863         .slave          = &omap44xx_mmc5_hwmod,
3864         .clk            = "l4_div_ck",
3865         .addr           = omap44xx_mmc5_addrs,
3866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3867 };
3868
3869 /* mmc5 slave ports */
3870 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3871         &omap44xx_l4_per__mmc5,
3872 };
3873
3874 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3875         .name           = "mmc5",
3876         .class          = &omap44xx_mmc_hwmod_class,
3877         .clkdm_name     = "l4_per_clkdm",
3878         .mpu_irqs       = omap44xx_mmc5_irqs,
3879         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3880         .main_clk       = "mmc5_fck",
3881         .prcm = {
3882                 .omap4 = {
3883                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3884                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3885                         .modulemode   = MODULEMODE_SWCTRL,
3886                 },
3887         },
3888         .slaves         = omap44xx_mmc5_slaves,
3889         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3890 };
3891
3892 /*
3893  * 'mpu' class
3894  * mpu sub-system
3895  */
3896
3897 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3898         .name   = "mpu",
3899 };
3900
3901 /* mpu */
3902 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3903         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3904         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3905         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3906         { .irq = -1 }
3907 };
3908
3909 /* mpu master ports */
3910 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3911         &omap44xx_mpu__l3_main_1,
3912         &omap44xx_mpu__l4_abe,
3913         &omap44xx_mpu__dmm,
3914 };
3915
3916 static struct omap_hwmod omap44xx_mpu_hwmod = {
3917         .name           = "mpu",
3918         .class          = &omap44xx_mpu_hwmod_class,
3919         .clkdm_name     = "mpuss_clkdm",
3920         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3921         .mpu_irqs       = omap44xx_mpu_irqs,
3922         .main_clk       = "dpll_mpu_m2_ck",
3923         .prcm = {
3924                 .omap4 = {
3925                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3926                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3927                 },
3928         },
3929         .masters        = omap44xx_mpu_masters,
3930         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3931 };
3932
3933 /*
3934  * 'smartreflex' class
3935  * smartreflex module (monitor silicon performance and outputs a measure of
3936  * performance error)
3937  */
3938
3939 /* The IP is not compliant to type1 / type2 scheme */
3940 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3941         .sidle_shift    = 24,
3942         .enwkup_shift   = 26,
3943 };
3944
3945 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3946         .sysc_offs      = 0x0038,
3947         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3948         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3949                            SIDLE_SMART_WKUP),
3950         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3951 };
3952
3953 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3954         .name   = "smartreflex",
3955         .sysc   = &omap44xx_smartreflex_sysc,
3956         .rev    = 2,
3957 };
3958
3959 /* smartreflex_core */
3960 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3961 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3962         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3963         { .irq = -1 }
3964 };
3965
3966 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3967         {
3968                 .pa_start       = 0x4a0dd000,
3969                 .pa_end         = 0x4a0dd03f,
3970                 .flags          = ADDR_TYPE_RT
3971         },
3972         { }
3973 };
3974
3975 /* l4_cfg -> smartreflex_core */
3976 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3977         .master         = &omap44xx_l4_cfg_hwmod,
3978         .slave          = &omap44xx_smartreflex_core_hwmod,
3979         .clk            = "l4_div_ck",
3980         .addr           = omap44xx_smartreflex_core_addrs,
3981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3982 };
3983
3984 /* smartreflex_core slave ports */
3985 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3986         &omap44xx_l4_cfg__smartreflex_core,
3987 };
3988
3989 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3990         .name           = "smartreflex_core",
3991         .class          = &omap44xx_smartreflex_hwmod_class,
3992         .clkdm_name     = "l4_ao_clkdm",
3993         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3994
3995         .main_clk       = "smartreflex_core_fck",
3996         .vdd_name       = "core",
3997         .prcm = {
3998                 .omap4 = {
3999                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4000                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4001                         .modulemode   = MODULEMODE_SWCTRL,
4002                 },
4003         },
4004         .slaves         = omap44xx_smartreflex_core_slaves,
4005         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4006 };
4007
4008 /* smartreflex_iva */
4009 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4010 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4011         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4012         { .irq = -1 }
4013 };
4014
4015 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4016         {
4017                 .pa_start       = 0x4a0db000,
4018                 .pa_end         = 0x4a0db03f,
4019                 .flags          = ADDR_TYPE_RT
4020         },
4021         { }
4022 };
4023
4024 /* l4_cfg -> smartreflex_iva */
4025 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4026         .master         = &omap44xx_l4_cfg_hwmod,
4027         .slave          = &omap44xx_smartreflex_iva_hwmod,
4028         .clk            = "l4_div_ck",
4029         .addr           = omap44xx_smartreflex_iva_addrs,
4030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4031 };
4032
4033 /* smartreflex_iva slave ports */
4034 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4035         &omap44xx_l4_cfg__smartreflex_iva,
4036 };
4037
4038 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4039         .name           = "smartreflex_iva",
4040         .class          = &omap44xx_smartreflex_hwmod_class,
4041         .clkdm_name     = "l4_ao_clkdm",
4042         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4043         .main_clk       = "smartreflex_iva_fck",
4044         .vdd_name       = "iva",
4045         .prcm = {
4046                 .omap4 = {
4047                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4048                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4049                         .modulemode   = MODULEMODE_SWCTRL,
4050                 },
4051         },
4052         .slaves         = omap44xx_smartreflex_iva_slaves,
4053         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4054 };
4055
4056 /* smartreflex_mpu */
4057 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4058 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4059         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4060         { .irq = -1 }
4061 };
4062
4063 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4064         {
4065                 .pa_start       = 0x4a0d9000,
4066                 .pa_end         = 0x4a0d903f,
4067                 .flags          = ADDR_TYPE_RT
4068         },
4069         { }
4070 };
4071
4072 /* l4_cfg -> smartreflex_mpu */
4073 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4074         .master         = &omap44xx_l4_cfg_hwmod,
4075         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4076         .clk            = "l4_div_ck",
4077         .addr           = omap44xx_smartreflex_mpu_addrs,
4078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4079 };
4080
4081 /* smartreflex_mpu slave ports */
4082 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4083         &omap44xx_l4_cfg__smartreflex_mpu,
4084 };
4085
4086 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4087         .name           = "smartreflex_mpu",
4088         .class          = &omap44xx_smartreflex_hwmod_class,
4089         .clkdm_name     = "l4_ao_clkdm",
4090         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4091         .main_clk       = "smartreflex_mpu_fck",
4092         .vdd_name       = "mpu",
4093         .prcm = {
4094                 .omap4 = {
4095                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4096                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4097                         .modulemode   = MODULEMODE_SWCTRL,
4098                 },
4099         },
4100         .slaves         = omap44xx_smartreflex_mpu_slaves,
4101         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4102 };
4103
4104 /*
4105  * 'spinlock' class
4106  * spinlock provides hardware assistance for synchronizing the processes
4107  * running on multiple processors
4108  */
4109
4110 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4111         .rev_offs       = 0x0000,
4112         .sysc_offs      = 0x0010,
4113         .syss_offs      = 0x0014,
4114         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4115                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4116                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4117         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4118                            SIDLE_SMART_WKUP),
4119         .sysc_fields    = &omap_hwmod_sysc_type1,
4120 };
4121
4122 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4123         .name   = "spinlock",
4124         .sysc   = &omap44xx_spinlock_sysc,
4125 };
4126
4127 /* spinlock */
4128 static struct omap_hwmod omap44xx_spinlock_hwmod;
4129 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4130         {
4131                 .pa_start       = 0x4a0f6000,
4132                 .pa_end         = 0x4a0f6fff,
4133                 .flags          = ADDR_TYPE_RT
4134         },
4135         { }
4136 };
4137
4138 /* l4_cfg -> spinlock */
4139 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4140         .master         = &omap44xx_l4_cfg_hwmod,
4141         .slave          = &omap44xx_spinlock_hwmod,
4142         .clk            = "l4_div_ck",
4143         .addr           = omap44xx_spinlock_addrs,
4144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4145 };
4146
4147 /* spinlock slave ports */
4148 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4149         &omap44xx_l4_cfg__spinlock,
4150 };
4151
4152 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4153         .name           = "spinlock",
4154         .class          = &omap44xx_spinlock_hwmod_class,
4155         .clkdm_name     = "l4_cfg_clkdm",
4156         .prcm = {
4157                 .omap4 = {
4158                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4159                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4160                 },
4161         },
4162         .slaves         = omap44xx_spinlock_slaves,
4163         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4164 };
4165
4166 /*
4167  * 'timer' class
4168  * general purpose timer module with accurate 1ms tick
4169  * This class contains several variants: ['timer_1ms', 'timer']
4170  */
4171
4172 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4173         .rev_offs       = 0x0000,
4174         .sysc_offs      = 0x0010,
4175         .syss_offs      = 0x0014,
4176         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4177                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4178                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4179                            SYSS_HAS_RESET_STATUS),
4180         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4181         .sysc_fields    = &omap_hwmod_sysc_type1,
4182 };
4183
4184 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4185         .name   = "timer",
4186         .sysc   = &omap44xx_timer_1ms_sysc,
4187 };
4188
4189 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4190         .rev_offs       = 0x0000,
4191         .sysc_offs      = 0x0010,
4192         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4193                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4194         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4195                            SIDLE_SMART_WKUP),
4196         .sysc_fields    = &omap_hwmod_sysc_type2,
4197 };
4198
4199 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4200         .name   = "timer",
4201         .sysc   = &omap44xx_timer_sysc,
4202 };
4203
4204 /* timer1 */
4205 static struct omap_hwmod omap44xx_timer1_hwmod;
4206 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4207         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4208         { .irq = -1 }
4209 };
4210
4211 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4212         {
4213                 .pa_start       = 0x4a318000,
4214                 .pa_end         = 0x4a31807f,
4215                 .flags          = ADDR_TYPE_RT
4216         },
4217         { }
4218 };
4219
4220 /* l4_wkup -> timer1 */
4221 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4222         .master         = &omap44xx_l4_wkup_hwmod,
4223         .slave          = &omap44xx_timer1_hwmod,
4224         .clk            = "l4_wkup_clk_mux_ck",
4225         .addr           = omap44xx_timer1_addrs,
4226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4227 };
4228
4229 /* timer1 slave ports */
4230 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4231         &omap44xx_l4_wkup__timer1,
4232 };
4233
4234 static struct omap_hwmod omap44xx_timer1_hwmod = {
4235         .name           = "timer1",
4236         .class          = &omap44xx_timer_1ms_hwmod_class,
4237         .clkdm_name     = "l4_wkup_clkdm",
4238         .mpu_irqs       = omap44xx_timer1_irqs,
4239         .main_clk       = "timer1_fck",
4240         .prcm = {
4241                 .omap4 = {
4242                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4243                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4244                         .modulemode   = MODULEMODE_SWCTRL,
4245                 },
4246         },
4247         .slaves         = omap44xx_timer1_slaves,
4248         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4249 };
4250
4251 /* timer2 */
4252 static struct omap_hwmod omap44xx_timer2_hwmod;
4253 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4254         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4255         { .irq = -1 }
4256 };
4257
4258 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4259         {
4260                 .pa_start       = 0x48032000,
4261                 .pa_end         = 0x4803207f,
4262                 .flags          = ADDR_TYPE_RT
4263         },
4264         { }
4265 };
4266
4267 /* l4_per -> timer2 */
4268 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4269         .master         = &omap44xx_l4_per_hwmod,
4270         .slave          = &omap44xx_timer2_hwmod,
4271         .clk            = "l4_div_ck",
4272         .addr           = omap44xx_timer2_addrs,
4273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4274 };
4275
4276 /* timer2 slave ports */
4277 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4278         &omap44xx_l4_per__timer2,
4279 };
4280
4281 static struct omap_hwmod omap44xx_timer2_hwmod = {
4282         .name           = "timer2",
4283         .class          = &omap44xx_timer_1ms_hwmod_class,
4284         .clkdm_name     = "l4_per_clkdm",
4285         .mpu_irqs       = omap44xx_timer2_irqs,
4286         .main_clk       = "timer2_fck",
4287         .prcm = {
4288                 .omap4 = {
4289                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4290                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4291                         .modulemode   = MODULEMODE_SWCTRL,
4292                 },
4293         },
4294         .slaves         = omap44xx_timer2_slaves,
4295         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4296 };
4297
4298 /* timer3 */
4299 static struct omap_hwmod omap44xx_timer3_hwmod;
4300 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4301         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4302         { .irq = -1 }
4303 };
4304
4305 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4306         {
4307                 .pa_start       = 0x48034000,
4308                 .pa_end         = 0x4803407f,
4309                 .flags          = ADDR_TYPE_RT
4310         },
4311         { }
4312 };
4313
4314 /* l4_per -> timer3 */
4315 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4316         .master         = &omap44xx_l4_per_hwmod,
4317         .slave          = &omap44xx_timer3_hwmod,
4318         .clk            = "l4_div_ck",
4319         .addr           = omap44xx_timer3_addrs,
4320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4321 };
4322
4323 /* timer3 slave ports */
4324 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4325         &omap44xx_l4_per__timer3,
4326 };
4327
4328 static struct omap_hwmod omap44xx_timer3_hwmod = {
4329         .name           = "timer3",
4330         .class          = &omap44xx_timer_hwmod_class,
4331         .clkdm_name     = "l4_per_clkdm",
4332         .mpu_irqs       = omap44xx_timer3_irqs,
4333         .main_clk       = "timer3_fck",
4334         .prcm = {
4335                 .omap4 = {
4336                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4337                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4338                         .modulemode   = MODULEMODE_SWCTRL,
4339                 },
4340         },
4341         .slaves         = omap44xx_timer3_slaves,
4342         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4343 };
4344
4345 /* timer4 */
4346 static struct omap_hwmod omap44xx_timer4_hwmod;
4347 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4348         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4349         { .irq = -1 }
4350 };
4351
4352 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4353         {
4354                 .pa_start       = 0x48036000,
4355                 .pa_end         = 0x4803607f,
4356                 .flags          = ADDR_TYPE_RT
4357         },
4358         { }
4359 };
4360
4361 /* l4_per -> timer4 */
4362 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4363         .master         = &omap44xx_l4_per_hwmod,
4364         .slave          = &omap44xx_timer4_hwmod,
4365         .clk            = "l4_div_ck",
4366         .addr           = omap44xx_timer4_addrs,
4367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4368 };
4369
4370 /* timer4 slave ports */
4371 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4372         &omap44xx_l4_per__timer4,
4373 };
4374
4375 static struct omap_hwmod omap44xx_timer4_hwmod = {
4376         .name           = "timer4",
4377         .class          = &omap44xx_timer_hwmod_class,
4378         .clkdm_name     = "l4_per_clkdm",
4379         .mpu_irqs       = omap44xx_timer4_irqs,
4380         .main_clk       = "timer4_fck",
4381         .prcm = {
4382                 .omap4 = {
4383                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4384                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4385                         .modulemode   = MODULEMODE_SWCTRL,
4386                 },
4387         },
4388         .slaves         = omap44xx_timer4_slaves,
4389         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4390 };
4391
4392 /* timer5 */
4393 static struct omap_hwmod omap44xx_timer5_hwmod;
4394 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4395         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4396         { .irq = -1 }
4397 };
4398
4399 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4400         {
4401                 .pa_start       = 0x40138000,
4402                 .pa_end         = 0x4013807f,
4403                 .flags          = ADDR_TYPE_RT
4404         },
4405         { }
4406 };
4407
4408 /* l4_abe -> timer5 */
4409 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4410         .master         = &omap44xx_l4_abe_hwmod,
4411         .slave          = &omap44xx_timer5_hwmod,
4412         .clk            = "ocp_abe_iclk",
4413         .addr           = omap44xx_timer5_addrs,
4414         .user           = OCP_USER_MPU,
4415 };
4416
4417 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4418         {
4419                 .pa_start       = 0x49038000,
4420                 .pa_end         = 0x4903807f,
4421                 .flags          = ADDR_TYPE_RT
4422         },
4423         { }
4424 };
4425
4426 /* l4_abe -> timer5 (dma) */
4427 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4428         .master         = &omap44xx_l4_abe_hwmod,
4429         .slave          = &omap44xx_timer5_hwmod,
4430         .clk            = "ocp_abe_iclk",
4431         .addr           = omap44xx_timer5_dma_addrs,
4432         .user           = OCP_USER_SDMA,
4433 };
4434
4435 /* timer5 slave ports */
4436 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4437         &omap44xx_l4_abe__timer5,
4438         &omap44xx_l4_abe__timer5_dma,
4439 };
4440
4441 static struct omap_hwmod omap44xx_timer5_hwmod = {
4442         .name           = "timer5",
4443         .class          = &omap44xx_timer_hwmod_class,
4444         .clkdm_name     = "abe_clkdm",
4445         .mpu_irqs       = omap44xx_timer5_irqs,
4446         .main_clk       = "timer5_fck",
4447         .prcm = {
4448                 .omap4 = {
4449                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4450                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4451                         .modulemode   = MODULEMODE_SWCTRL,
4452                 },
4453         },
4454         .slaves         = omap44xx_timer5_slaves,
4455         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4456 };
4457
4458 /* timer6 */
4459 static struct omap_hwmod omap44xx_timer6_hwmod;
4460 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4461         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4462         { .irq = -1 }
4463 };
4464
4465 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4466         {
4467                 .pa_start       = 0x4013a000,
4468                 .pa_end         = 0x4013a07f,
4469                 .flags          = ADDR_TYPE_RT
4470         },
4471         { }
4472 };
4473
4474 /* l4_abe -> timer6 */
4475 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4476         .master         = &omap44xx_l4_abe_hwmod,
4477         .slave          = &omap44xx_timer6_hwmod,
4478         .clk            = "ocp_abe_iclk",
4479         .addr           = omap44xx_timer6_addrs,
4480         .user           = OCP_USER_MPU,
4481 };
4482
4483 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4484         {
4485                 .pa_start       = 0x4903a000,
4486                 .pa_end         = 0x4903a07f,
4487                 .flags          = ADDR_TYPE_RT
4488         },
4489         { }
4490 };
4491
4492 /* l4_abe -> timer6 (dma) */
4493 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4494         .master         = &omap44xx_l4_abe_hwmod,
4495         .slave          = &omap44xx_timer6_hwmod,
4496         .clk            = "ocp_abe_iclk",
4497         .addr           = omap44xx_timer6_dma_addrs,
4498         .user           = OCP_USER_SDMA,
4499 };
4500
4501 /* timer6 slave ports */
4502 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4503         &omap44xx_l4_abe__timer6,
4504         &omap44xx_l4_abe__timer6_dma,
4505 };
4506
4507 static struct omap_hwmod omap44xx_timer6_hwmod = {
4508         .name           = "timer6",
4509         .class          = &omap44xx_timer_hwmod_class,
4510         .clkdm_name     = "abe_clkdm",
4511         .mpu_irqs       = omap44xx_timer6_irqs,
4512
4513         .main_clk       = "timer6_fck",
4514         .prcm = {
4515                 .omap4 = {
4516                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4517                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4518                         .modulemode   = MODULEMODE_SWCTRL,
4519                 },
4520         },
4521         .slaves         = omap44xx_timer6_slaves,
4522         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4523 };
4524
4525 /* timer7 */
4526 static struct omap_hwmod omap44xx_timer7_hwmod;
4527 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4528         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4529         { .irq = -1 }
4530 };
4531
4532 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4533         {
4534                 .pa_start       = 0x4013c000,
4535                 .pa_end         = 0x4013c07f,
4536                 .flags          = ADDR_TYPE_RT
4537         },
4538         { }
4539 };
4540
4541 /* l4_abe -> timer7 */
4542 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4543         .master         = &omap44xx_l4_abe_hwmod,
4544         .slave          = &omap44xx_timer7_hwmod,
4545         .clk            = "ocp_abe_iclk",
4546         .addr           = omap44xx_timer7_addrs,
4547         .user           = OCP_USER_MPU,
4548 };
4549
4550 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4551         {
4552                 .pa_start       = 0x4903c000,
4553                 .pa_end         = 0x4903c07f,
4554                 .flags          = ADDR_TYPE_RT
4555         },
4556         { }
4557 };
4558
4559 /* l4_abe -> timer7 (dma) */
4560 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4561         .master         = &omap44xx_l4_abe_hwmod,
4562         .slave          = &omap44xx_timer7_hwmod,
4563         .clk            = "ocp_abe_iclk",
4564         .addr           = omap44xx_timer7_dma_addrs,
4565         .user           = OCP_USER_SDMA,
4566 };
4567
4568 /* timer7 slave ports */
4569 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4570         &omap44xx_l4_abe__timer7,
4571         &omap44xx_l4_abe__timer7_dma,
4572 };
4573
4574 static struct omap_hwmod omap44xx_timer7_hwmod = {
4575         .name           = "timer7",
4576         .class          = &omap44xx_timer_hwmod_class,
4577         .clkdm_name     = "abe_clkdm",
4578         .mpu_irqs       = omap44xx_timer7_irqs,
4579         .main_clk       = "timer7_fck",
4580         .prcm = {
4581                 .omap4 = {
4582                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4583                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4584                         .modulemode   = MODULEMODE_SWCTRL,
4585                 },
4586         },
4587         .slaves         = omap44xx_timer7_slaves,
4588         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4589 };
4590
4591 /* timer8 */
4592 static struct omap_hwmod omap44xx_timer8_hwmod;
4593 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4594         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4595         { .irq = -1 }
4596 };
4597
4598 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4599         {
4600                 .pa_start       = 0x4013e000,
4601                 .pa_end         = 0x4013e07f,
4602                 .flags          = ADDR_TYPE_RT
4603         },
4604         { }
4605 };
4606
4607 /* l4_abe -> timer8 */
4608 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4609         .master         = &omap44xx_l4_abe_hwmod,
4610         .slave          = &omap44xx_timer8_hwmod,
4611         .clk            = "ocp_abe_iclk",
4612         .addr           = omap44xx_timer8_addrs,
4613         .user           = OCP_USER_MPU,
4614 };
4615
4616 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4617         {
4618                 .pa_start       = 0x4903e000,
4619                 .pa_end         = 0x4903e07f,
4620                 .flags          = ADDR_TYPE_RT
4621         },
4622         { }
4623 };
4624
4625 /* l4_abe -> timer8 (dma) */
4626 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4627         .master         = &omap44xx_l4_abe_hwmod,
4628         .slave          = &omap44xx_timer8_hwmod,
4629         .clk            = "ocp_abe_iclk",
4630         .addr           = omap44xx_timer8_dma_addrs,
4631         .user           = OCP_USER_SDMA,
4632 };
4633
4634 /* timer8 slave ports */
4635 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4636         &omap44xx_l4_abe__timer8,
4637         &omap44xx_l4_abe__timer8_dma,
4638 };
4639
4640 static struct omap_hwmod omap44xx_timer8_hwmod = {
4641         .name           = "timer8",
4642         .class          = &omap44xx_timer_hwmod_class,
4643         .clkdm_name     = "abe_clkdm",
4644         .mpu_irqs       = omap44xx_timer8_irqs,
4645         .main_clk       = "timer8_fck",
4646         .prcm = {
4647                 .omap4 = {
4648                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4649                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4650                         .modulemode   = MODULEMODE_SWCTRL,
4651                 },
4652         },
4653         .slaves         = omap44xx_timer8_slaves,
4654         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4655 };
4656
4657 /* timer9 */
4658 static struct omap_hwmod omap44xx_timer9_hwmod;
4659 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4660         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4661         { .irq = -1 }
4662 };
4663
4664 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4665         {
4666                 .pa_start       = 0x4803e000,
4667                 .pa_end         = 0x4803e07f,
4668                 .flags          = ADDR_TYPE_RT
4669         },
4670         { }
4671 };
4672
4673 /* l4_per -> timer9 */
4674 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4675         .master         = &omap44xx_l4_per_hwmod,
4676         .slave          = &omap44xx_timer9_hwmod,
4677         .clk            = "l4_div_ck",
4678         .addr           = omap44xx_timer9_addrs,
4679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4680 };
4681
4682 /* timer9 slave ports */
4683 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4684         &omap44xx_l4_per__timer9,
4685 };
4686
4687 static struct omap_hwmod omap44xx_timer9_hwmod = {
4688         .name           = "timer9",
4689         .class          = &omap44xx_timer_hwmod_class,
4690         .clkdm_name     = "l4_per_clkdm",
4691         .mpu_irqs       = omap44xx_timer9_irqs,
4692         .main_clk       = "timer9_fck",
4693         .prcm = {
4694                 .omap4 = {
4695                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4696                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4697                         .modulemode   = MODULEMODE_SWCTRL,
4698                 },
4699         },
4700         .slaves         = omap44xx_timer9_slaves,
4701         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4702 };
4703
4704 /* timer10 */
4705 static struct omap_hwmod omap44xx_timer10_hwmod;
4706 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4707         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4708         { .irq = -1 }
4709 };
4710
4711 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4712         {
4713                 .pa_start       = 0x48086000,
4714                 .pa_end         = 0x4808607f,
4715                 .flags          = ADDR_TYPE_RT
4716         },
4717         { }
4718 };
4719
4720 /* l4_per -> timer10 */
4721 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4722         .master         = &omap44xx_l4_per_hwmod,
4723         .slave          = &omap44xx_timer10_hwmod,
4724         .clk            = "l4_div_ck",
4725         .addr           = omap44xx_timer10_addrs,
4726         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4727 };
4728
4729 /* timer10 slave ports */
4730 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4731         &omap44xx_l4_per__timer10,
4732 };
4733
4734 static struct omap_hwmod omap44xx_timer10_hwmod = {
4735         .name           = "timer10",
4736         .class          = &omap44xx_timer_1ms_hwmod_class,
4737         .clkdm_name     = "l4_per_clkdm",
4738         .mpu_irqs       = omap44xx_timer10_irqs,
4739         .main_clk       = "timer10_fck",
4740         .prcm = {
4741                 .omap4 = {
4742                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4743                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4744                         .modulemode   = MODULEMODE_SWCTRL,
4745                 },
4746         },
4747         .slaves         = omap44xx_timer10_slaves,
4748         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4749 };
4750
4751 /* timer11 */
4752 static struct omap_hwmod omap44xx_timer11_hwmod;
4753 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4754         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4755         { .irq = -1 }
4756 };
4757
4758 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4759         {
4760                 .pa_start       = 0x48088000,
4761                 .pa_end         = 0x4808807f,
4762                 .flags          = ADDR_TYPE_RT
4763         },
4764         { }
4765 };
4766
4767 /* l4_per -> timer11 */
4768 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4769         .master         = &omap44xx_l4_per_hwmod,
4770         .slave          = &omap44xx_timer11_hwmod,
4771         .clk            = "l4_div_ck",
4772         .addr           = omap44xx_timer11_addrs,
4773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4774 };
4775
4776 /* timer11 slave ports */
4777 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4778         &omap44xx_l4_per__timer11,
4779 };
4780
4781 static struct omap_hwmod omap44xx_timer11_hwmod = {
4782         .name           = "timer11",
4783         .class          = &omap44xx_timer_hwmod_class,
4784         .clkdm_name     = "l4_per_clkdm",
4785         .mpu_irqs       = omap44xx_timer11_irqs,
4786         .main_clk       = "timer11_fck",
4787         .prcm = {
4788                 .omap4 = {
4789                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4790                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4791                         .modulemode   = MODULEMODE_SWCTRL,
4792                 },
4793         },
4794         .slaves         = omap44xx_timer11_slaves,
4795         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4796 };
4797
4798 /*
4799  * 'uart' class
4800  * universal asynchronous receiver/transmitter (uart)
4801  */
4802
4803 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4804         .rev_offs       = 0x0050,
4805         .sysc_offs      = 0x0054,
4806         .syss_offs      = 0x0058,
4807         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4808                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4809                            SYSS_HAS_RESET_STATUS),
4810         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4811                            SIDLE_SMART_WKUP),
4812         .sysc_fields    = &omap_hwmod_sysc_type1,
4813 };
4814
4815 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4816         .name   = "uart",
4817         .sysc   = &omap44xx_uart_sysc,
4818 };
4819
4820 /* uart1 */
4821 static struct omap_hwmod omap44xx_uart1_hwmod;
4822 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4823         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4824         { .irq = -1 }
4825 };
4826
4827 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4828         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4829         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4830         { .dma_req = -1 }
4831 };
4832
4833 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4834         {
4835                 .pa_start       = 0x4806a000,
4836                 .pa_end         = 0x4806a0ff,
4837                 .flags          = ADDR_TYPE_RT
4838         },
4839         { }
4840 };
4841
4842 /* l4_per -> uart1 */
4843 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4844         .master         = &omap44xx_l4_per_hwmod,
4845         .slave          = &omap44xx_uart1_hwmod,
4846         .clk            = "l4_div_ck",
4847         .addr           = omap44xx_uart1_addrs,
4848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4849 };
4850
4851 /* uart1 slave ports */
4852 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4853         &omap44xx_l4_per__uart1,
4854 };
4855
4856 static struct omap_hwmod omap44xx_uart1_hwmod = {
4857         .name           = "uart1",
4858         .class          = &omap44xx_uart_hwmod_class,
4859         .clkdm_name     = "l4_per_clkdm",
4860         .mpu_irqs       = omap44xx_uart1_irqs,
4861         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4862         .main_clk       = "uart1_fck",
4863         .prcm = {
4864                 .omap4 = {
4865                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4866                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4867                         .modulemode   = MODULEMODE_SWCTRL,
4868                 },
4869         },
4870         .slaves         = omap44xx_uart1_slaves,
4871         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4872 };
4873
4874 /* uart2 */
4875 static struct omap_hwmod omap44xx_uart2_hwmod;
4876 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4877         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4878         { .irq = -1 }
4879 };
4880
4881 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4882         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4883         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4884         { .dma_req = -1 }
4885 };
4886
4887 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4888         {
4889                 .pa_start       = 0x4806c000,
4890                 .pa_end         = 0x4806c0ff,
4891                 .flags          = ADDR_TYPE_RT
4892         },
4893         { }
4894 };
4895
4896 /* l4_per -> uart2 */
4897 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4898         .master         = &omap44xx_l4_per_hwmod,
4899         .slave          = &omap44xx_uart2_hwmod,
4900         .clk            = "l4_div_ck",
4901         .addr           = omap44xx_uart2_addrs,
4902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4903 };
4904
4905 /* uart2 slave ports */
4906 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4907         &omap44xx_l4_per__uart2,
4908 };
4909
4910 static struct omap_hwmod omap44xx_uart2_hwmod = {
4911         .name           = "uart2",
4912         .class          = &omap44xx_uart_hwmod_class,
4913         .clkdm_name     = "l4_per_clkdm",
4914         .mpu_irqs       = omap44xx_uart2_irqs,
4915         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4916         .main_clk       = "uart2_fck",
4917         .prcm = {
4918                 .omap4 = {
4919                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4920                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4921                         .modulemode   = MODULEMODE_SWCTRL,
4922                 },
4923         },
4924         .slaves         = omap44xx_uart2_slaves,
4925         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4926 };
4927
4928 /* uart3 */
4929 static struct omap_hwmod omap44xx_uart3_hwmod;
4930 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4931         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4932         { .irq = -1 }
4933 };
4934
4935 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4936         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4937         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4938         { .dma_req = -1 }
4939 };
4940
4941 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4942         {
4943                 .pa_start       = 0x48020000,
4944                 .pa_end         = 0x480200ff,
4945                 .flags          = ADDR_TYPE_RT
4946         },
4947         { }
4948 };
4949
4950 /* l4_per -> uart3 */
4951 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4952         .master         = &omap44xx_l4_per_hwmod,
4953         .slave          = &omap44xx_uart3_hwmod,
4954         .clk            = "l4_div_ck",
4955         .addr           = omap44xx_uart3_addrs,
4956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4957 };
4958
4959 /* uart3 slave ports */
4960 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4961         &omap44xx_l4_per__uart3,
4962 };
4963
4964 static struct omap_hwmod omap44xx_uart3_hwmod = {
4965         .name           = "uart3",
4966         .class          = &omap44xx_uart_hwmod_class,
4967         .clkdm_name     = "l4_per_clkdm",
4968         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4969         .mpu_irqs       = omap44xx_uart3_irqs,
4970         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4971         .main_clk       = "uart3_fck",
4972         .prcm = {
4973                 .omap4 = {
4974                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
4975                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
4976                         .modulemode   = MODULEMODE_SWCTRL,
4977                 },
4978         },
4979         .slaves         = omap44xx_uart3_slaves,
4980         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4981 };
4982
4983 /* uart4 */
4984 static struct omap_hwmod omap44xx_uart4_hwmod;
4985 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4986         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4987         { .irq = -1 }
4988 };
4989
4990 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4991         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4992         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4993         { .dma_req = -1 }
4994 };
4995
4996 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4997         {
4998                 .pa_start       = 0x4806e000,
4999                 .pa_end         = 0x4806e0ff,
5000                 .flags          = ADDR_TYPE_RT
5001         },
5002         { }
5003 };
5004
5005 /* l4_per -> uart4 */
5006 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5007         .master         = &omap44xx_l4_per_hwmod,
5008         .slave          = &omap44xx_uart4_hwmod,
5009         .clk            = "l4_div_ck",
5010         .addr           = omap44xx_uart4_addrs,
5011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5012 };
5013
5014 /* uart4 slave ports */
5015 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5016         &omap44xx_l4_per__uart4,
5017 };
5018
5019 static struct omap_hwmod omap44xx_uart4_hwmod = {
5020         .name           = "uart4",
5021         .class          = &omap44xx_uart_hwmod_class,
5022         .clkdm_name     = "l4_per_clkdm",
5023         .mpu_irqs       = omap44xx_uart4_irqs,
5024         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5025         .main_clk       = "uart4_fck",
5026         .prcm = {
5027                 .omap4 = {
5028                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5029                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5030                         .modulemode   = MODULEMODE_SWCTRL,
5031                 },
5032         },
5033         .slaves         = omap44xx_uart4_slaves,
5034         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5035 };
5036
5037 /*
5038  * 'usb_otg_hs' class
5039  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5040  */
5041
5042 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5043         .rev_offs       = 0x0400,
5044         .sysc_offs      = 0x0404,
5045         .syss_offs      = 0x0408,
5046         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5047                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5048                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5049         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5050                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5051                            MSTANDBY_SMART),
5052         .sysc_fields    = &omap_hwmod_sysc_type1,
5053 };
5054
5055 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5056         .name   = "usb_otg_hs",
5057         .sysc   = &omap44xx_usb_otg_hs_sysc,
5058 };
5059
5060 /* usb_otg_hs */
5061 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5062         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5063         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5064         { .irq = -1 }
5065 };
5066
5067 /* usb_otg_hs master ports */
5068 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5069         &omap44xx_usb_otg_hs__l3_main_2,
5070 };
5071
5072 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5073         {
5074                 .pa_start       = 0x4a0ab000,
5075                 .pa_end         = 0x4a0ab003,
5076                 .flags          = ADDR_TYPE_RT
5077         },
5078         { }
5079 };
5080
5081 /* l4_cfg -> usb_otg_hs */
5082 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5083         .master         = &omap44xx_l4_cfg_hwmod,
5084         .slave          = &omap44xx_usb_otg_hs_hwmod,
5085         .clk            = "l4_div_ck",
5086         .addr           = omap44xx_usb_otg_hs_addrs,
5087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5088 };
5089
5090 /* usb_otg_hs slave ports */
5091 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5092         &omap44xx_l4_cfg__usb_otg_hs,
5093 };
5094
5095 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5096         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5097 };
5098
5099 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5100         .name           = "usb_otg_hs",
5101         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5102         .clkdm_name     = "l3_init_clkdm",
5103         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5104         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5105         .main_clk       = "usb_otg_hs_ick",
5106         .prcm = {
5107                 .omap4 = {
5108                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5109                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5110                         .modulemode   = MODULEMODE_HWCTRL,
5111                 },
5112         },
5113         .opt_clks       = usb_otg_hs_opt_clks,
5114         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5115         .slaves         = omap44xx_usb_otg_hs_slaves,
5116         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5117         .masters        = omap44xx_usb_otg_hs_masters,
5118         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5119 };
5120
5121 /*
5122  * 'wd_timer' class
5123  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5124  * overflow condition
5125  */
5126
5127 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5128         .rev_offs       = 0x0000,
5129         .sysc_offs      = 0x0010,
5130         .syss_offs      = 0x0014,
5131         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5132                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5134                            SIDLE_SMART_WKUP),
5135         .sysc_fields    = &omap_hwmod_sysc_type1,
5136 };
5137
5138 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5139         .name           = "wd_timer",
5140         .sysc           = &omap44xx_wd_timer_sysc,
5141         .pre_shutdown   = &omap2_wd_timer_disable,
5142 };
5143
5144 /* wd_timer2 */
5145 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5146 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5147         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5148         { .irq = -1 }
5149 };
5150
5151 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5152         {
5153                 .pa_start       = 0x4a314000,
5154                 .pa_end         = 0x4a31407f,
5155                 .flags          = ADDR_TYPE_RT
5156         },
5157         { }
5158 };
5159
5160 /* l4_wkup -> wd_timer2 */
5161 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5162         .master         = &omap44xx_l4_wkup_hwmod,
5163         .slave          = &omap44xx_wd_timer2_hwmod,
5164         .clk            = "l4_wkup_clk_mux_ck",
5165         .addr           = omap44xx_wd_timer2_addrs,
5166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5167 };
5168
5169 /* wd_timer2 slave ports */
5170 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5171         &omap44xx_l4_wkup__wd_timer2,
5172 };
5173
5174 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5175         .name           = "wd_timer2",
5176         .class          = &omap44xx_wd_timer_hwmod_class,
5177         .clkdm_name     = "l4_wkup_clkdm",
5178         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5179         .main_clk       = "wd_timer2_fck",
5180         .prcm = {
5181                 .omap4 = {
5182                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5183                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5184                         .modulemode   = MODULEMODE_SWCTRL,
5185                 },
5186         },
5187         .slaves         = omap44xx_wd_timer2_slaves,
5188         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5189 };
5190
5191 /* wd_timer3 */
5192 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5193 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5194         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5195         { .irq = -1 }
5196 };
5197
5198 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5199         {
5200                 .pa_start       = 0x40130000,
5201                 .pa_end         = 0x4013007f,
5202                 .flags          = ADDR_TYPE_RT
5203         },
5204         { }
5205 };
5206
5207 /* l4_abe -> wd_timer3 */
5208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5209         .master         = &omap44xx_l4_abe_hwmod,
5210         .slave          = &omap44xx_wd_timer3_hwmod,
5211         .clk            = "ocp_abe_iclk",
5212         .addr           = omap44xx_wd_timer3_addrs,
5213         .user           = OCP_USER_MPU,
5214 };
5215
5216 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5217         {
5218                 .pa_start       = 0x49030000,
5219                 .pa_end         = 0x4903007f,
5220                 .flags          = ADDR_TYPE_RT
5221         },
5222         { }
5223 };
5224
5225 /* l4_abe -> wd_timer3 (dma) */
5226 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5227         .master         = &omap44xx_l4_abe_hwmod,
5228         .slave          = &omap44xx_wd_timer3_hwmod,
5229         .clk            = "ocp_abe_iclk",
5230         .addr           = omap44xx_wd_timer3_dma_addrs,
5231         .user           = OCP_USER_SDMA,
5232 };
5233
5234 /* wd_timer3 slave ports */
5235 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5236         &omap44xx_l4_abe__wd_timer3,
5237         &omap44xx_l4_abe__wd_timer3_dma,
5238 };
5239
5240 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5241         .name           = "wd_timer3",
5242         .class          = &omap44xx_wd_timer_hwmod_class,
5243         .clkdm_name     = "abe_clkdm",
5244         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5245         .main_clk       = "wd_timer3_fck",
5246         .prcm = {
5247                 .omap4 = {
5248                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5249                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5250                         .modulemode   = MODULEMODE_SWCTRL,
5251                 },
5252         },
5253         .slaves         = omap44xx_wd_timer3_slaves,
5254         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5255 };
5256
5257 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5258
5259         /* dmm class */
5260         &omap44xx_dmm_hwmod,
5261
5262         /* emif_fw class */
5263         &omap44xx_emif_fw_hwmod,
5264
5265         /* l3 class */
5266         &omap44xx_l3_instr_hwmod,
5267         &omap44xx_l3_main_1_hwmod,
5268         &omap44xx_l3_main_2_hwmod,
5269         &omap44xx_l3_main_3_hwmod,
5270
5271         /* l4 class */
5272         &omap44xx_l4_abe_hwmod,
5273         &omap44xx_l4_cfg_hwmod,
5274         &omap44xx_l4_per_hwmod,
5275         &omap44xx_l4_wkup_hwmod,
5276
5277         /* mpu_bus class */
5278         &omap44xx_mpu_private_hwmod,
5279
5280         /* aess class */
5281 /*      &omap44xx_aess_hwmod, */
5282
5283         /* bandgap class */
5284         &omap44xx_bandgap_hwmod,
5285
5286         /* counter class */
5287 /*      &omap44xx_counter_32k_hwmod, */
5288
5289         /* dma class */
5290         &omap44xx_dma_system_hwmod,
5291
5292         /* dmic class */
5293         &omap44xx_dmic_hwmod,
5294
5295         /* dsp class */
5296         &omap44xx_dsp_hwmod,
5297         &omap44xx_dsp_c0_hwmod,
5298
5299         /* dss class */
5300         &omap44xx_dss_hwmod,
5301         &omap44xx_dss_dispc_hwmod,
5302         &omap44xx_dss_dsi1_hwmod,
5303         &omap44xx_dss_dsi2_hwmod,
5304         &omap44xx_dss_hdmi_hwmod,
5305         &omap44xx_dss_rfbi_hwmod,
5306         &omap44xx_dss_venc_hwmod,
5307
5308         /* gpio class */
5309         &omap44xx_gpio1_hwmod,
5310         &omap44xx_gpio2_hwmod,
5311         &omap44xx_gpio3_hwmod,
5312         &omap44xx_gpio4_hwmod,
5313         &omap44xx_gpio5_hwmod,
5314         &omap44xx_gpio6_hwmod,
5315
5316         /* hsi class */
5317 /*      &omap44xx_hsi_hwmod, */
5318
5319         /* i2c class */
5320         &omap44xx_i2c1_hwmod,
5321         &omap44xx_i2c2_hwmod,
5322         &omap44xx_i2c3_hwmod,
5323         &omap44xx_i2c4_hwmod,
5324
5325         /* ipu class */
5326         &omap44xx_ipu_hwmod,
5327         &omap44xx_ipu_c0_hwmod,
5328         &omap44xx_ipu_c1_hwmod,
5329
5330         /* iss class */
5331 /*      &omap44xx_iss_hwmod, */
5332
5333         /* iva class */
5334         &omap44xx_iva_hwmod,
5335         &omap44xx_iva_seq0_hwmod,
5336         &omap44xx_iva_seq1_hwmod,
5337
5338         /* kbd class */
5339         &omap44xx_kbd_hwmod,
5340
5341         /* mailbox class */
5342         &omap44xx_mailbox_hwmod,
5343
5344         /* mcbsp class */
5345         &omap44xx_mcbsp1_hwmod,
5346         &omap44xx_mcbsp2_hwmod,
5347         &omap44xx_mcbsp3_hwmod,
5348         &omap44xx_mcbsp4_hwmod,
5349
5350         /* mcpdm class */
5351 /*      &omap44xx_mcpdm_hwmod, */
5352
5353         /* mcspi class */
5354         &omap44xx_mcspi1_hwmod,
5355         &omap44xx_mcspi2_hwmod,
5356         &omap44xx_mcspi3_hwmod,
5357         &omap44xx_mcspi4_hwmod,
5358
5359         /* mmc class */
5360         &omap44xx_mmc1_hwmod,
5361         &omap44xx_mmc2_hwmod,
5362         &omap44xx_mmc3_hwmod,
5363         &omap44xx_mmc4_hwmod,
5364         &omap44xx_mmc5_hwmod,
5365
5366         /* mpu class */
5367         &omap44xx_mpu_hwmod,
5368
5369         /* smartreflex class */
5370         &omap44xx_smartreflex_core_hwmod,
5371         &omap44xx_smartreflex_iva_hwmod,
5372         &omap44xx_smartreflex_mpu_hwmod,
5373
5374         /* spinlock class */
5375         &omap44xx_spinlock_hwmod,
5376
5377         /* timer class */
5378         &omap44xx_timer1_hwmod,
5379         &omap44xx_timer2_hwmod,
5380         &omap44xx_timer3_hwmod,
5381         &omap44xx_timer4_hwmod,
5382         &omap44xx_timer5_hwmod,
5383         &omap44xx_timer6_hwmod,
5384         &omap44xx_timer7_hwmod,
5385         &omap44xx_timer8_hwmod,
5386         &omap44xx_timer9_hwmod,
5387         &omap44xx_timer10_hwmod,
5388         &omap44xx_timer11_hwmod,
5389
5390         /* uart class */
5391         &omap44xx_uart1_hwmod,
5392         &omap44xx_uart2_hwmod,
5393         &omap44xx_uart3_hwmod,
5394         &omap44xx_uart4_hwmod,
5395
5396         /* usb_otg_hs class */
5397         &omap44xx_usb_otg_hs_hwmod,
5398
5399         /* wd_timer class */
5400         &omap44xx_wd_timer2_hwmod,
5401         &omap44xx_wd_timer3_hwmod,
5402
5403         NULL,
5404 };
5405
5406 int __init omap44xx_hwmod_init(void)
5407 {
5408         return omap_hwmod_register(omap44xx_hwmods);
5409 }
5410