arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "smartreflex.h"
  33 #include "prm-regbits-34xx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "wd_timer.h"
  36 #include <mach/am35xx.h>
  37
  38 /*
  39  * OMAP3xxx hardware module integration data
  40  *
  41  * ALl of the data in this section should be autogeneratable from the
  42  * TI hardware database or other technical documentation.  Data that
  43  * is driver-specific or driver-kernel integration-specific belongs
  44  * elsewhere.
  45  */
  46
  47 static struct omap_hwmod omap3xxx_mpu_hwmod;
  48 static struct omap_hwmod omap3xxx_iva_hwmod;
  49 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  51 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  52 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  53 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  58 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  61 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  67 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  68 static struct omap_hwmod omap34xx_sr1_hwmod;
  69 static struct omap_hwmod omap34xx_sr2_hwmod;
  70 static struct omap_hwmod omap34xx_mcspi1;
  71 static struct omap_hwmod omap34xx_mcspi2;
  72 static struct omap_hwmod omap34xx_mcspi3;
  73 static struct omap_hwmod omap34xx_mcspi4;
  74 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  76 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  77 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  78
  79 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  80
  81 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  87 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  88
  89 /* L3 -> L4_CORE interface */
  90 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  91         .master = &omap3xxx_l3_main_hwmod,
  92         .slave  = &omap3xxx_l4_core_hwmod,
  93         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  94 };
  95
  96 /* L3 -> L4_PER interface */
  97 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  98         .master = &omap3xxx_l3_main_hwmod,
  99         .slave  = &omap3xxx_l4_per_hwmod,
 100         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 101 };
 102
 103 /* L3 taret configuration and error log registers */
 104 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 105         { .irq = INT_34XX_L3_DBG_IRQ },
 106         { .irq = INT_34XX_L3_APP_IRQ },
 107         { .irq = -1 }
 108 };
 109
 110 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 111         {
 112                 .pa_start       = 0x68000000,
 113                 .pa_end         = 0x6800ffff,
 114                 .flags          = ADDR_TYPE_RT,
 115         },
 116         { }
 117 };
 118
 119 /* MPU -> L3 interface */
 120 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 121         .master   = &omap3xxx_mpu_hwmod,
 122         .slave    = &omap3xxx_l3_main_hwmod,
 123         .addr     = omap3xxx_l3_main_addrs,
 124         .user   = OCP_USER_MPU,
 125 };
 126
 127 /* Slave interfaces on the L3 interconnect */
 128 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 129         &omap3xxx_mpu__l3_main,
 130 };
 131
 132 /* DSS -> l3 */
 133 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 134         .master         = &omap3xxx_dss_core_hwmod,
 135         .slave          = &omap3xxx_l3_main_hwmod,
 136         .fw = {
 137                 .omap2 = {
 138                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 139                         .flags  = OMAP_FIREWALL_L3,
 140                 }
 141         },
 142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 143 };
 144
 145 /* Master interfaces on the L3 interconnect */
 146 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 147         &omap3xxx_l3_main__l4_core,
 148         &omap3xxx_l3_main__l4_per,
 149 };
 150
 151 /* L3 */
 152 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 153         .name           = "l3_main",
 154         .class          = &l3_hwmod_class,
 155         .mpu_irqs       = omap3xxx_l3_main_irqs,
 156         .masters        = omap3xxx_l3_main_masters,
 157         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 158         .slaves         = omap3xxx_l3_main_slaves,
 159         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* L4 CORE -> SR1 interface */
 361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 362         {
 363                 .pa_start       = OMAP34XX_SR1_BASE,
 364                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 365                 .flags          = ADDR_TYPE_RT,
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 371         .master         = &omap3xxx_l4_core_hwmod,
 372         .slave          = &omap34xx_sr1_hwmod,
 373         .clk            = "sr_l4_ick",
 374         .addr           = omap3_sr1_addr_space,
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 /* L4 CORE -> SR1 interface */
 379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 380         {
 381                 .pa_start       = OMAP34XX_SR2_BASE,
 382                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 383                 .flags          = ADDR_TYPE_RT,
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 389         .master         = &omap3xxx_l4_core_hwmod,
 390         .slave          = &omap34xx_sr2_hwmod,
 391         .clk            = "sr_l4_ick",
 392         .addr           = omap3_sr2_addr_space,
 393         .user           = OCP_USER_MPU,
 394 };
 395
 396 /*
 397 * usbhsotg interface data
 398 */
 399
 400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 401         {
 402                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 403                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 404                 .flags          = ADDR_TYPE_RT
 405         },
 406         { }
 407 };
 408
 409 /* l4_core -> usbhsotg  */
 410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 411         .master         = &omap3xxx_l4_core_hwmod,
 412         .slave          = &omap3xxx_usbhsotg_hwmod,
 413         .clk            = "l4_ick",
 414         .addr           = omap3xxx_usbhsotg_addrs,
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 419         &omap3xxx_usbhsotg__l3,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 423         &omap3xxx_l4_core__usbhsotg,
 424 };
 425
 426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 427         {
 428                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 429                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 430                 .flags          = ADDR_TYPE_RT
 431         },
 432         { }
 433 };
 434
 435 /* l4_core -> usbhsotg  */
 436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 437         .master         = &omap3xxx_l4_core_hwmod,
 438         .slave          = &am35xx_usbhsotg_hwmod,
 439         .clk            = "l4_ick",
 440         .addr           = am35xx_usbhsotg_addrs,
 441         .user           = OCP_USER_MPU,
 442 };
 443
 444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 445         &am35xx_usbhsotg__l3,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 449         &am35xx_l4_core__usbhsotg,
 450 };
 451 /* Slave interfaces on the L4_CORE interconnect */
 452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 453         &omap3xxx_l3_main__l4_core,
 454 };
 455
 456 /* L4 CORE */
 457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 458         .name           = "l4_core",
 459         .class          = &l4_hwmod_class,
 460         .slaves         = omap3xxx_l4_core_slaves,
 461         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 462         .flags          = HWMOD_NO_IDLEST,
 463 };
 464
 465 /* Slave interfaces on the L4_PER interconnect */
 466 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 467         &omap3xxx_l3_main__l4_per,
 468 };
 469
 470 /* L4 PER */
 471 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 472         .name           = "l4_per",
 473         .class          = &l4_hwmod_class,
 474         .slaves         = omap3xxx_l4_per_slaves,
 475         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 476         .flags          = HWMOD_NO_IDLEST,
 477 };
 478
 479 /* Slave interfaces on the L4_WKUP interconnect */
 480 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 481         &omap3xxx_l4_core__l4_wkup,
 482 };
 483
 484 /* L4 WKUP */
 485 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 486         .name           = "l4_wkup",
 487         .class          = &l4_hwmod_class,
 488         .slaves         = omap3xxx_l4_wkup_slaves,
 489         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 490         .flags          = HWMOD_NO_IDLEST,
 491 };
 492
 493 /* Master interfaces on the MPU device */
 494 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 495         &omap3xxx_mpu__l3_main,
 496 };
 497
 498 /* MPU */
 499 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 500         .name           = "mpu",
 501         .class          = &mpu_hwmod_class,
 502         .main_clk       = "arm_fck",
 503         .masters        = omap3xxx_mpu_masters,
 504         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 505 };
 506
 507 /*
 508  * IVA2_2 interface data
 509  */
 510
 511 /* IVA2 <- L3 interface */
 512 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 513         .master         = &omap3xxx_l3_main_hwmod,
 514         .slave          = &omap3xxx_iva_hwmod,
 515         .clk            = "iva2_ck",
 516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 517 };
 518
 519 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 520         &omap3xxx_l3__iva,
 521 };
 522
 523 /*
 524  * IVA2 (IVA2)
 525  */
 526
 527 static struct omap_hwmod omap3xxx_iva_hwmod = {
 528         .name           = "iva",
 529         .class          = &iva_hwmod_class,
 530         .masters        = omap3xxx_iva_masters,
 531         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 532 };
 533
 534 /* timer class */
 535 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 536         .rev_offs       = 0x0000,
 537         .sysc_offs      = 0x0010,
 538         .syss_offs      = 0x0014,
 539         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 540                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 541                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 543         .sysc_fields    = &omap_hwmod_sysc_type1,
 544 };
 545
 546 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 547         .name = "timer",
 548         .sysc = &omap3xxx_timer_1ms_sysc,
 549         .rev = OMAP_TIMER_IP_VERSION_1,
 550 };
 551
 552 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 553         .rev_offs       = 0x0000,
 554         .sysc_offs      = 0x0010,
 555         .syss_offs      = 0x0014,
 556         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 557                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 558         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 559         .sysc_fields    = &omap_hwmod_sysc_type1,
 560 };
 561
 562 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 563         .name = "timer",
 564         .sysc = &omap3xxx_timer_sysc,
 565         .rev =  OMAP_TIMER_IP_VERSION_1,
 566 };
 567
 568 /* secure timers dev attribute */
 569 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 570         .timer_capability       = OMAP_TIMER_SECURE,
 571 };
 572
 573 /* always-on timers dev attribute */
 574 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 575         .timer_capability       = OMAP_TIMER_ALWON,
 576 };
 577
 578 /* pwm timers dev attribute */
 579 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 580         .timer_capability       = OMAP_TIMER_HAS_PWM,
 581 };
 582
 583 /* timer1 */
 584 static struct omap_hwmod omap3xxx_timer1_hwmod;
 585
 586 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 587         {
 588                 .pa_start       = 0x48318000,
 589                 .pa_end         = 0x48318000 + SZ_1K - 1,
 590                 .flags          = ADDR_TYPE_RT
 591         },
 592         { }
 593 };
 594
 595 /* l4_wkup -> timer1 */
 596 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 597         .master         = &omap3xxx_l4_wkup_hwmod,
 598         .slave          = &omap3xxx_timer1_hwmod,
 599         .clk            = "gpt1_ick",
 600         .addr           = omap3xxx_timer1_addrs,
 601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 602 };
 603
 604 /* timer1 slave port */
 605 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 606         &omap3xxx_l4_wkup__timer1,
 607 };
 608
 609 /* timer1 hwmod */
 610 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 611         .name           = "timer1",
 612         .mpu_irqs       = omap2_timer1_mpu_irqs,
 613         .main_clk       = "gpt1_fck",
 614         .prcm           = {
 615                 .omap2 = {
 616                         .prcm_reg_id = 1,
 617                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 618                         .module_offs = WKUP_MOD,
 619                         .idlest_reg_id = 1,
 620                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 621                 },
 622         },
 623         .dev_attr       = &capability_alwon_dev_attr,
 624         .slaves         = omap3xxx_timer1_slaves,
 625         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 626         .class          = &omap3xxx_timer_1ms_hwmod_class,
 627 };
 628
 629 /* timer2 */
 630 static struct omap_hwmod omap3xxx_timer2_hwmod;
 631
 632 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 633         {
 634                 .pa_start       = 0x49032000,
 635                 .pa_end         = 0x49032000 + SZ_1K - 1,
 636                 .flags          = ADDR_TYPE_RT
 637         },
 638         { }
 639 };
 640
 641 /* l4_per -> timer2 */
 642 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 643         .master         = &omap3xxx_l4_per_hwmod,
 644         .slave          = &omap3xxx_timer2_hwmod,
 645         .clk            = "gpt2_ick",
 646         .addr           = omap3xxx_timer2_addrs,
 647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 648 };
 649
 650 /* timer2 slave port */
 651 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 652         &omap3xxx_l4_per__timer2,
 653 };
 654
 655 /* timer2 hwmod */
 656 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 657         .name           = "timer2",
 658         .mpu_irqs       = omap2_timer2_mpu_irqs,
 659         .main_clk       = "gpt2_fck",
 660         .prcm           = {
 661                 .omap2 = {
 662                         .prcm_reg_id = 1,
 663                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 664                         .module_offs = OMAP3430_PER_MOD,
 665                         .idlest_reg_id = 1,
 666                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 667                 },
 668         },
 669         .dev_attr       = &capability_alwon_dev_attr,
 670         .slaves         = omap3xxx_timer2_slaves,
 671         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 672         .class          = &omap3xxx_timer_1ms_hwmod_class,
 673 };
 674
 675 /* timer3 */
 676 static struct omap_hwmod omap3xxx_timer3_hwmod;
 677
 678 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 679         {
 680                 .pa_start       = 0x49034000,
 681                 .pa_end         = 0x49034000 + SZ_1K - 1,
 682                 .flags          = ADDR_TYPE_RT
 683         },
 684         { }
 685 };
 686
 687 /* l4_per -> timer3 */
 688 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 689         .master         = &omap3xxx_l4_per_hwmod,
 690         .slave          = &omap3xxx_timer3_hwmod,
 691         .clk            = "gpt3_ick",
 692         .addr           = omap3xxx_timer3_addrs,
 693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 694 };
 695
 696 /* timer3 slave port */
 697 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 698         &omap3xxx_l4_per__timer3,
 699 };
 700
 701 /* timer3 hwmod */
 702 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 703         .name           = "timer3",
 704         .mpu_irqs       = omap2_timer3_mpu_irqs,
 705         .main_clk       = "gpt3_fck",
 706         .prcm           = {
 707                 .omap2 = {
 708                         .prcm_reg_id = 1,
 709                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 710                         .module_offs = OMAP3430_PER_MOD,
 711                         .idlest_reg_id = 1,
 712                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 713                 },
 714         },
 715         .dev_attr       = &capability_alwon_dev_attr,
 716         .slaves         = omap3xxx_timer3_slaves,
 717         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 718         .class          = &omap3xxx_timer_hwmod_class,
 719 };
 720
 721 /* timer4 */
 722 static struct omap_hwmod omap3xxx_timer4_hwmod;
 723
 724 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 725         {
 726                 .pa_start       = 0x49036000,
 727                 .pa_end         = 0x49036000 + SZ_1K - 1,
 728                 .flags          = ADDR_TYPE_RT
 729         },
 730         { }
 731 };
 732
 733 /* l4_per -> timer4 */
 734 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 735         .master         = &omap3xxx_l4_per_hwmod,
 736         .slave          = &omap3xxx_timer4_hwmod,
 737         .clk            = "gpt4_ick",
 738         .addr           = omap3xxx_timer4_addrs,
 739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 740 };
 741
 742 /* timer4 slave port */
 743 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 744         &omap3xxx_l4_per__timer4,
 745 };
 746
 747 /* timer4 hwmod */
 748 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 749         .name           = "timer4",
 750         .mpu_irqs       = omap2_timer4_mpu_irqs,
 751         .main_clk       = "gpt4_fck",
 752         .prcm           = {
 753                 .omap2 = {
 754                         .prcm_reg_id = 1,
 755                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 756                         .module_offs = OMAP3430_PER_MOD,
 757                         .idlest_reg_id = 1,
 758                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 759                 },
 760         },
 761         .dev_attr       = &capability_alwon_dev_attr,
 762         .slaves         = omap3xxx_timer4_slaves,
 763         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 764         .class          = &omap3xxx_timer_hwmod_class,
 765 };
 766
 767 /* timer5 */
 768 static struct omap_hwmod omap3xxx_timer5_hwmod;
 769
 770 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 771         {
 772                 .pa_start       = 0x49038000,
 773                 .pa_end         = 0x49038000 + SZ_1K - 1,
 774                 .flags          = ADDR_TYPE_RT
 775         },
 776         { }
 777 };
 778
 779 /* l4_per -> timer5 */
 780 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 781         .master         = &omap3xxx_l4_per_hwmod,
 782         .slave          = &omap3xxx_timer5_hwmod,
 783         .clk            = "gpt5_ick",
 784         .addr           = omap3xxx_timer5_addrs,
 785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 786 };
 787
 788 /* timer5 slave port */
 789 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 790         &omap3xxx_l4_per__timer5,
 791 };
 792
 793 /* timer5 hwmod */
 794 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 795         .name           = "timer5",
 796         .mpu_irqs       = omap2_timer5_mpu_irqs,
 797         .main_clk       = "gpt5_fck",
 798         .prcm           = {
 799                 .omap2 = {
 800                         .prcm_reg_id = 1,
 801                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 802                         .module_offs = OMAP3430_PER_MOD,
 803                         .idlest_reg_id = 1,
 804                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 805                 },
 806         },
 807         .dev_attr       = &capability_alwon_dev_attr,
 808         .slaves         = omap3xxx_timer5_slaves,
 809         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 810         .class          = &omap3xxx_timer_hwmod_class,
 811 };
 812
 813 /* timer6 */
 814 static struct omap_hwmod omap3xxx_timer6_hwmod;
 815
 816 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 817         {
 818                 .pa_start       = 0x4903A000,
 819                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 820                 .flags          = ADDR_TYPE_RT
 821         },
 822         { }
 823 };
 824
 825 /* l4_per -> timer6 */
 826 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 827         .master         = &omap3xxx_l4_per_hwmod,
 828         .slave          = &omap3xxx_timer6_hwmod,
 829         .clk            = "gpt6_ick",
 830         .addr           = omap3xxx_timer6_addrs,
 831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 832 };
 833
 834 /* timer6 slave port */
 835 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 836         &omap3xxx_l4_per__timer6,
 837 };
 838
 839 /* timer6 hwmod */
 840 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 841         .name           = "timer6",
 842         .mpu_irqs       = omap2_timer6_mpu_irqs,
 843         .main_clk       = "gpt6_fck",
 844         .prcm           = {
 845                 .omap2 = {
 846                         .prcm_reg_id = 1,
 847                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 848                         .module_offs = OMAP3430_PER_MOD,
 849                         .idlest_reg_id = 1,
 850                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 851                 },
 852         },
 853         .dev_attr       = &capability_alwon_dev_attr,
 854         .slaves         = omap3xxx_timer6_slaves,
 855         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 856         .class          = &omap3xxx_timer_hwmod_class,
 857 };
 858
 859 /* timer7 */
 860 static struct omap_hwmod omap3xxx_timer7_hwmod;
 861
 862 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 863         {
 864                 .pa_start       = 0x4903C000,
 865                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 866                 .flags          = ADDR_TYPE_RT
 867         },
 868         { }
 869 };
 870
 871 /* l4_per -> timer7 */
 872 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 873         .master         = &omap3xxx_l4_per_hwmod,
 874         .slave          = &omap3xxx_timer7_hwmod,
 875         .clk            = "gpt7_ick",
 876         .addr           = omap3xxx_timer7_addrs,
 877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 878 };
 879
 880 /* timer7 slave port */
 881 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 882         &omap3xxx_l4_per__timer7,
 883 };
 884
 885 /* timer7 hwmod */
 886 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 887         .name           = "timer7",
 888         .mpu_irqs       = omap2_timer7_mpu_irqs,
 889         .main_clk       = "gpt7_fck",
 890         .prcm           = {
 891                 .omap2 = {
 892                         .prcm_reg_id = 1,
 893                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 894                         .module_offs = OMAP3430_PER_MOD,
 895                         .idlest_reg_id = 1,
 896                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 897                 },
 898         },
 899         .dev_attr       = &capability_alwon_dev_attr,
 900         .slaves         = omap3xxx_timer7_slaves,
 901         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 902         .class          = &omap3xxx_timer_hwmod_class,
 903 };
 904
 905 /* timer8 */
 906 static struct omap_hwmod omap3xxx_timer8_hwmod;
 907
 908 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 909         {
 910                 .pa_start       = 0x4903E000,
 911                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 912                 .flags          = ADDR_TYPE_RT
 913         },
 914         { }
 915 };
 916
 917 /* l4_per -> timer8 */
 918 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 919         .master         = &omap3xxx_l4_per_hwmod,
 920         .slave          = &omap3xxx_timer8_hwmod,
 921         .clk            = "gpt8_ick",
 922         .addr           = omap3xxx_timer8_addrs,
 923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 924 };
 925
 926 /* timer8 slave port */
 927 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 928         &omap3xxx_l4_per__timer8,
 929 };
 930
 931 /* timer8 hwmod */
 932 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 933         .name           = "timer8",
 934         .mpu_irqs       = omap2_timer8_mpu_irqs,
 935         .main_clk       = "gpt8_fck",
 936         .prcm           = {
 937                 .omap2 = {
 938                         .prcm_reg_id = 1,
 939                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 940                         .module_offs = OMAP3430_PER_MOD,
 941                         .idlest_reg_id = 1,
 942                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 943                 },
 944         },
 945         .dev_attr       = &capability_pwm_dev_attr,
 946         .slaves         = omap3xxx_timer8_slaves,
 947         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 948         .class          = &omap3xxx_timer_hwmod_class,
 949 };
 950
 951 /* timer9 */
 952 static struct omap_hwmod omap3xxx_timer9_hwmod;
 953
 954 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 955         {
 956                 .pa_start       = 0x49040000,
 957                 .pa_end         = 0x49040000 + SZ_1K - 1,
 958                 .flags          = ADDR_TYPE_RT
 959         },
 960         { }
 961 };
 962
 963 /* l4_per -> timer9 */
 964 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 965         .master         = &omap3xxx_l4_per_hwmod,
 966         .slave          = &omap3xxx_timer9_hwmod,
 967         .clk            = "gpt9_ick",
 968         .addr           = omap3xxx_timer9_addrs,
 969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 970 };
 971
 972 /* timer9 slave port */
 973 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 974         &omap3xxx_l4_per__timer9,
 975 };
 976
 977 /* timer9 hwmod */
 978 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 979         .name           = "timer9",
 980         .mpu_irqs       = omap2_timer9_mpu_irqs,
 981         .main_clk       = "gpt9_fck",
 982         .prcm           = {
 983                 .omap2 = {
 984                         .prcm_reg_id = 1,
 985                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 986                         .module_offs = OMAP3430_PER_MOD,
 987                         .idlest_reg_id = 1,
 988                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 989                 },
 990         },
 991         .dev_attr       = &capability_pwm_dev_attr,
 992         .slaves         = omap3xxx_timer9_slaves,
 993         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 994         .class          = &omap3xxx_timer_hwmod_class,
 995 };
 996
 997 /* timer10 */
 998 static struct omap_hwmod omap3xxx_timer10_hwmod;
 999
1000 /* l4_core -> timer10 */
1001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1002         .master         = &omap3xxx_l4_core_hwmod,
1003         .slave          = &omap3xxx_timer10_hwmod,
1004         .clk            = "gpt10_ick",
1005         .addr           = omap2_timer10_addrs,
1006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1007 };
1008
1009 /* timer10 slave port */
1010 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1011         &omap3xxx_l4_core__timer10,
1012 };
1013
1014 /* timer10 hwmod */
1015 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1016         .name           = "timer10",
1017         .mpu_irqs       = omap2_timer10_mpu_irqs,
1018         .main_clk       = "gpt10_fck",
1019         .prcm           = {
1020                 .omap2 = {
1021                         .prcm_reg_id = 1,
1022                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1023                         .module_offs = CORE_MOD,
1024                         .idlest_reg_id = 1,
1025                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1026                 },
1027         },
1028         .dev_attr       = &capability_pwm_dev_attr,
1029         .slaves         = omap3xxx_timer10_slaves,
1030         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1031         .class          = &omap3xxx_timer_1ms_hwmod_class,
1032 };
1033
1034 /* timer11 */
1035 static struct omap_hwmod omap3xxx_timer11_hwmod;
1036
1037 /* l4_core -> timer11 */
1038 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1039         .master         = &omap3xxx_l4_core_hwmod,
1040         .slave          = &omap3xxx_timer11_hwmod,
1041         .clk            = "gpt11_ick",
1042         .addr           = omap2_timer11_addrs,
1043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1044 };
1045
1046 /* timer11 slave port */
1047 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1048         &omap3xxx_l4_core__timer11,
1049 };
1050
1051 /* timer11 hwmod */
1052 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1053         .name           = "timer11",
1054         .mpu_irqs       = omap2_timer11_mpu_irqs,
1055         .main_clk       = "gpt11_fck",
1056         .prcm           = {
1057                 .omap2 = {
1058                         .prcm_reg_id = 1,
1059                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1060                         .module_offs = CORE_MOD,
1061                         .idlest_reg_id = 1,
1062                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1063                 },
1064         },
1065         .dev_attr       = &capability_pwm_dev_attr,
1066         .slaves         = omap3xxx_timer11_slaves,
1067         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1068         .class          = &omap3xxx_timer_hwmod_class,
1069 };
1070
1071 /* timer12 */
1072 static struct omap_hwmod omap3xxx_timer12_hwmod;
1073 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1074         { .irq = 95, },
1075         { .irq = -1 }
1076 };
1077
1078 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1079         {
1080                 .pa_start       = 0x48304000,
1081                 .pa_end         = 0x48304000 + SZ_1K - 1,
1082                 .flags          = ADDR_TYPE_RT
1083         },
1084         { }
1085 };
1086
1087 /* l4_core -> timer12 */
1088 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1089         .master         = &omap3xxx_l4_core_hwmod,
1090         .slave          = &omap3xxx_timer12_hwmod,
1091         .clk            = "gpt12_ick",
1092         .addr           = omap3xxx_timer12_addrs,
1093         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1094 };
1095
1096 /* timer12 slave port */
1097 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1098         &omap3xxx_l4_core__timer12,
1099 };
1100
1101 /* timer12 hwmod */
1102 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1103         .name           = "timer12",
1104         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1105         .main_clk       = "gpt12_fck",
1106         .prcm           = {
1107                 .omap2 = {
1108                         .prcm_reg_id = 1,
1109                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1110                         .module_offs = WKUP_MOD,
1111                         .idlest_reg_id = 1,
1112                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1113                 },
1114         },
1115         .dev_attr       = &capability_secure_dev_attr,
1116         .slaves         = omap3xxx_timer12_slaves,
1117         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1118         .class          = &omap3xxx_timer_hwmod_class,
1119 };
1120
1121 /* l4_wkup -> wd_timer2 */
1122 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1123         {
1124                 .pa_start       = 0x48314000,
1125                 .pa_end         = 0x4831407f,
1126                 .flags          = ADDR_TYPE_RT
1127         },
1128         { }
1129 };
1130
1131 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1132         .master         = &omap3xxx_l4_wkup_hwmod,
1133         .slave          = &omap3xxx_wd_timer2_hwmod,
1134         .clk            = "wdt2_ick",
1135         .addr           = omap3xxx_wd_timer2_addrs,
1136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1137 };
1138
1139 /*
1140  * 'wd_timer' class
1141  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1142  * overflow condition
1143  */
1144
1145 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1146         .rev_offs       = 0x0000,
1147         .sysc_offs      = 0x0010,
1148         .syss_offs      = 0x0014,
1149         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1150                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1151                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1152                            SYSS_HAS_RESET_STATUS),
1153         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1154         .sysc_fields    = &omap_hwmod_sysc_type1,
1155 };
1156
1157 /* I2C common */
1158 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1159         .rev_offs       = 0x00,
1160         .sysc_offs      = 0x20,
1161         .syss_offs      = 0x10,
1162         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1163                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1164                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1165         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1166         .sysc_fields    = &omap_hwmod_sysc_type1,
1167 };
1168
1169 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1170         .name           = "wd_timer",
1171         .sysc           = &omap3xxx_wd_timer_sysc,
1172         .pre_shutdown   = &omap2_wd_timer_disable
1173 };
1174
1175 /* wd_timer2 */
1176 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1177         &omap3xxx_l4_wkup__wd_timer2,
1178 };
1179
1180 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1181         .name           = "wd_timer2",
1182         .class          = &omap3xxx_wd_timer_hwmod_class,
1183         .main_clk       = "wdt2_fck",
1184         .prcm           = {
1185                 .omap2 = {
1186                         .prcm_reg_id = 1,
1187                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1188                         .module_offs = WKUP_MOD,
1189                         .idlest_reg_id = 1,
1190                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1191                 },
1192         },
1193         .slaves         = omap3xxx_wd_timer2_slaves,
1194         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1195         /*
1196          * XXX: Use software supervised mode, HW supervised smartidle seems to
1197          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1198          */
1199         .flags          = HWMOD_SWSUP_SIDLE,
1200 };
1201
1202 /* UART1 */
1203
1204 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1205         &omap3_l4_core__uart1,
1206 };
1207
1208 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1209         .name           = "uart1",
1210         .mpu_irqs       = omap2_uart1_mpu_irqs,
1211         .sdma_reqs      = omap2_uart1_sdma_reqs,
1212         .main_clk       = "uart1_fck",
1213         .prcm           = {
1214                 .omap2 = {
1215                         .module_offs = CORE_MOD,
1216                         .prcm_reg_id = 1,
1217                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1218                         .idlest_reg_id = 1,
1219                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1220                 },
1221         },
1222         .slaves         = omap3xxx_uart1_slaves,
1223         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1224         .class          = &omap2_uart_class,
1225 };
1226
1227 /* UART2 */
1228
1229 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1230         &omap3_l4_core__uart2,
1231 };
1232
1233 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1234         .name           = "uart2",
1235         .mpu_irqs       = omap2_uart2_mpu_irqs,
1236         .sdma_reqs      = omap2_uart2_sdma_reqs,
1237         .main_clk       = "uart2_fck",
1238         .prcm           = {
1239                 .omap2 = {
1240                         .module_offs = CORE_MOD,
1241                         .prcm_reg_id = 1,
1242                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1243                         .idlest_reg_id = 1,
1244                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1245                 },
1246         },
1247         .slaves         = omap3xxx_uart2_slaves,
1248         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1249         .class          = &omap2_uart_class,
1250 };
1251
1252 /* UART3 */
1253
1254 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1255         &omap3_l4_per__uart3,
1256 };
1257
1258 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1259         .name           = "uart3",
1260         .mpu_irqs       = omap2_uart3_mpu_irqs,
1261         .sdma_reqs      = omap2_uart3_sdma_reqs,
1262         .main_clk       = "uart3_fck",
1263         .prcm           = {
1264                 .omap2 = {
1265                         .module_offs = OMAP3430_PER_MOD,
1266                         .prcm_reg_id = 1,
1267                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1268                         .idlest_reg_id = 1,
1269                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1270                 },
1271         },
1272         .slaves         = omap3xxx_uart3_slaves,
1273         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1274         .class          = &omap2_uart_class,
1275 };
1276
1277 /* UART4 */
1278
1279 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1280         { .irq = INT_36XX_UART4_IRQ, },
1281         { .irq = -1 }
1282 };
1283
1284 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1285         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1286         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1287         { .dma_req = -1 }
1288 };
1289
1290 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1291         &omap3_l4_per__uart4,
1292 };
1293
1294 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1295         .name           = "uart4",
1296         .mpu_irqs       = uart4_mpu_irqs,
1297         .sdma_reqs      = uart4_sdma_reqs,
1298         .main_clk       = "uart4_fck",
1299         .prcm           = {
1300                 .omap2 = {
1301                         .module_offs = OMAP3430_PER_MOD,
1302                         .prcm_reg_id = 1,
1303                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1304                         .idlest_reg_id = 1,
1305                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1306                 },
1307         },
1308         .slaves         = omap3xxx_uart4_slaves,
1309         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1310         .class          = &omap2_uart_class,
1311 };
1312
1313 static struct omap_hwmod_class i2c_class = {
1314         .name   = "i2c",
1315         .sysc   = &i2c_sysc,
1316         .rev    = OMAP_I2C_IP_VERSION_1,
1317         .reset  = &omap_i2c_reset,
1318 };
1319
1320 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1321         { .name = "dispc", .dma_req = 5 },
1322         { .name = "dsi1", .dma_req = 74 },
1323         { .dma_req = -1 }
1324 };
1325
1326 /* dss */
1327 /* dss master ports */
1328 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1329         &omap3xxx_dss__l3,
1330 };
1331
1332 /* l4_core -> dss */
1333 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1334         .master         = &omap3xxx_l4_core_hwmod,
1335         .slave          = &omap3430es1_dss_core_hwmod,
1336         .clk            = "dss_ick",
1337         .addr           = omap2_dss_addrs,
1338         .fw = {
1339                 .omap2 = {
1340                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1341                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1342                         .flags  = OMAP_FIREWALL_L4,
1343                 }
1344         },
1345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1346 };
1347
1348 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1349         .master         = &omap3xxx_l4_core_hwmod,
1350         .slave          = &omap3xxx_dss_core_hwmod,
1351         .clk            = "dss_ick",
1352         .addr           = omap2_dss_addrs,
1353         .fw = {
1354                 .omap2 = {
1355                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1356                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1357                         .flags  = OMAP_FIREWALL_L4,
1358                 }
1359         },
1360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1361 };
1362
1363 /* dss slave ports */
1364 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1365         &omap3430es1_l4_core__dss,
1366 };
1367
1368 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1369         &omap3xxx_l4_core__dss,
1370 };
1371
1372 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1373         /*
1374          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1375          * driver does not use these clocks.
1376          */
1377         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1378         { .role = "tv_clk", .clk = "dss_tv_fck" },
1379         /* required only on OMAP3430 */
1380         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1381 };
1382
1383 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1384         .name           = "dss_core",
1385         .class          = &omap2_dss_hwmod_class,
1386         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1387         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1388         .prcm           = {
1389                 .omap2 = {
1390                         .prcm_reg_id = 1,
1391                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1392                         .module_offs = OMAP3430_DSS_MOD,
1393                         .idlest_reg_id = 1,
1394                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1395                 },
1396         },
1397         .opt_clks       = dss_opt_clks,
1398         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1399         .slaves         = omap3430es1_dss_slaves,
1400         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1401         .masters        = omap3xxx_dss_masters,
1402         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1403         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1404 };
1405
1406 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1407         .name           = "dss_core",
1408         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1409         .class          = &omap2_dss_hwmod_class,
1410         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1411         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1412         .prcm           = {
1413                 .omap2 = {
1414                         .prcm_reg_id = 1,
1415                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1416                         .module_offs = OMAP3430_DSS_MOD,
1417                         .idlest_reg_id = 1,
1418                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1419                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1420                 },
1421         },
1422         .opt_clks       = dss_opt_clks,
1423         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1424         .slaves         = omap3xxx_dss_slaves,
1425         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1426         .masters        = omap3xxx_dss_masters,
1427         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1428 };
1429
1430 /*
1431  * 'dispc' class
1432  * display controller
1433  */
1434
1435 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1436         .rev_offs       = 0x0000,
1437         .sysc_offs      = 0x0010,
1438         .syss_offs      = 0x0014,
1439         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1440                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1441                            SYSC_HAS_ENAWAKEUP),
1442         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1443                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1444         .sysc_fields    = &omap_hwmod_sysc_type1,
1445 };
1446
1447 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1448         .name   = "dispc",
1449         .sysc   = &omap3_dispc_sysc,
1450 };
1451
1452 /* l4_core -> dss_dispc */
1453 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1454         .master         = &omap3xxx_l4_core_hwmod,
1455         .slave          = &omap3xxx_dss_dispc_hwmod,
1456         .clk            = "dss_ick",
1457         .addr           = omap2_dss_dispc_addrs,
1458         .fw = {
1459                 .omap2 = {
1460                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1461                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1462                         .flags  = OMAP_FIREWALL_L4,
1463                 }
1464         },
1465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1466 };
1467
1468 /* dss_dispc slave ports */
1469 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1470         &omap3xxx_l4_core__dss_dispc,
1471 };
1472
1473 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1474         .name           = "dss_dispc",
1475         .class          = &omap3_dispc_hwmod_class,
1476         .mpu_irqs       = omap2_dispc_irqs,
1477         .main_clk       = "dss1_alwon_fck",
1478         .prcm           = {
1479                 .omap2 = {
1480                         .prcm_reg_id = 1,
1481                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1482                         .module_offs = OMAP3430_DSS_MOD,
1483                 },
1484         },
1485         .slaves         = omap3xxx_dss_dispc_slaves,
1486         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1487         .flags          = HWMOD_NO_IDLEST,
1488         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1489 };
1490
1491 /*
1492  * 'dsi' class
1493  * display serial interface controller
1494  */
1495
1496 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1497         .name = "dsi",
1498 };
1499
1500 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1501         { .irq = 25 },
1502         { .irq = -1 }
1503 };
1504
1505 /* dss_dsi1 */
1506 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1507         {
1508                 .pa_start       = 0x4804FC00,
1509                 .pa_end         = 0x4804FFFF,
1510                 .flags          = ADDR_TYPE_RT
1511         },
1512         { }
1513 };
1514
1515 /* l4_core -> dss_dsi1 */
1516 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1517         .master         = &omap3xxx_l4_core_hwmod,
1518         .slave          = &omap3xxx_dss_dsi1_hwmod,
1519         .clk            = "dss_ick",
1520         .addr           = omap3xxx_dss_dsi1_addrs,
1521         .fw = {
1522                 .omap2 = {
1523                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1524                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1525                         .flags  = OMAP_FIREWALL_L4,
1526                 }
1527         },
1528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1529 };
1530
1531 /* dss_dsi1 slave ports */
1532 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1533         &omap3xxx_l4_core__dss_dsi1,
1534 };
1535
1536 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1537         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1538 };
1539
1540 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1541         .name           = "dss_dsi1",
1542         .class          = &omap3xxx_dsi_hwmod_class,
1543         .mpu_irqs       = omap3xxx_dsi1_irqs,
1544         .main_clk       = "dss1_alwon_fck",
1545         .prcm           = {
1546                 .omap2 = {
1547                         .prcm_reg_id = 1,
1548                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1549                         .module_offs = OMAP3430_DSS_MOD,
1550                 },
1551         },
1552         .opt_clks       = dss_dsi1_opt_clks,
1553         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1554         .slaves         = omap3xxx_dss_dsi1_slaves,
1555         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1556         .flags          = HWMOD_NO_IDLEST,
1557 };
1558
1559 /* l4_core -> dss_rfbi */
1560 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1561         .master         = &omap3xxx_l4_core_hwmod,
1562         .slave          = &omap3xxx_dss_rfbi_hwmod,
1563         .clk            = "dss_ick",
1564         .addr           = omap2_dss_rfbi_addrs,
1565         .fw = {
1566                 .omap2 = {
1567                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1568                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1569                         .flags  = OMAP_FIREWALL_L4,
1570                 }
1571         },
1572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1573 };
1574
1575 /* dss_rfbi slave ports */
1576 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1577         &omap3xxx_l4_core__dss_rfbi,
1578 };
1579
1580 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1581         { .role = "ick", .clk = "dss_ick" },
1582 };
1583
1584 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1585         .name           = "dss_rfbi",
1586         .class          = &omap2_rfbi_hwmod_class,
1587         .main_clk       = "dss1_alwon_fck",
1588         .prcm           = {
1589                 .omap2 = {
1590                         .prcm_reg_id = 1,
1591                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1592                         .module_offs = OMAP3430_DSS_MOD,
1593                 },
1594         },
1595         .opt_clks       = dss_rfbi_opt_clks,
1596         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1597         .slaves         = omap3xxx_dss_rfbi_slaves,
1598         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1599         .flags          = HWMOD_NO_IDLEST,
1600 };
1601
1602 /* l4_core -> dss_venc */
1603 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1604         .master         = &omap3xxx_l4_core_hwmod,
1605         .slave          = &omap3xxx_dss_venc_hwmod,
1606         .clk            = "dss_ick",
1607         .addr           = omap2_dss_venc_addrs,
1608         .fw = {
1609                 .omap2 = {
1610                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1611                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1612                         .flags  = OMAP_FIREWALL_L4,
1613                 }
1614         },
1615         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1616 };
1617
1618 /* dss_venc slave ports */
1619 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1620         &omap3xxx_l4_core__dss_venc,
1621 };
1622
1623 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1624         /* required only on OMAP3430 */
1625         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1626 };
1627
1628 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1629         .name           = "dss_venc",
1630         .class          = &omap2_venc_hwmod_class,
1631         .main_clk       = "dss_tv_fck",
1632         .prcm           = {
1633                 .omap2 = {
1634                         .prcm_reg_id = 1,
1635                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1636                         .module_offs = OMAP3430_DSS_MOD,
1637                 },
1638         },
1639         .opt_clks       = dss_venc_opt_clks,
1640         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1641         .slaves         = omap3xxx_dss_venc_slaves,
1642         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1643         .flags          = HWMOD_NO_IDLEST,
1644 };
1645
1646 /* I2C1 */
1647
1648 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1649         .fifo_depth     = 8, /* bytes */
1650         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1651                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1652                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1653 };
1654
1655 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1656         &omap3_l4_core__i2c1,
1657 };
1658
1659 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1660         .name           = "i2c1",
1661         .flags          = HWMOD_16BIT_REG,
1662         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1663         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1664         .main_clk       = "i2c1_fck",
1665         .prcm           = {
1666                 .omap2 = {
1667                         .module_offs = CORE_MOD,
1668                         .prcm_reg_id = 1,
1669                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1670                         .idlest_reg_id = 1,
1671                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1672                 },
1673         },
1674         .slaves         = omap3xxx_i2c1_slaves,
1675         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1676         .class          = &i2c_class,
1677         .dev_attr       = &i2c1_dev_attr,
1678 };
1679
1680 /* I2C2 */
1681
1682 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1683         .fifo_depth     = 8, /* bytes */
1684         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1685                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1686                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1687 };
1688
1689 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1690         &omap3_l4_core__i2c2,
1691 };
1692
1693 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1694         .name           = "i2c2",
1695         .flags          = HWMOD_16BIT_REG,
1696         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1697         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1698         .main_clk       = "i2c2_fck",
1699         .prcm           = {
1700                 .omap2 = {
1701                         .module_offs = CORE_MOD,
1702                         .prcm_reg_id = 1,
1703                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1704                         .idlest_reg_id = 1,
1705                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1706                 },
1707         },
1708         .slaves         = omap3xxx_i2c2_slaves,
1709         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1710         .class          = &i2c_class,
1711         .dev_attr       = &i2c2_dev_attr,
1712 };
1713
1714 /* I2C3 */
1715
1716 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1717         .fifo_depth     = 64, /* bytes */
1718         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1719                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1720                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1721 };
1722
1723 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1724         { .irq = INT_34XX_I2C3_IRQ, },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1729         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1730         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1731         { .dma_req = -1 }
1732 };
1733
1734 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1735         &omap3_l4_core__i2c3,
1736 };
1737
1738 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1739         .name           = "i2c3",
1740         .flags          = HWMOD_16BIT_REG,
1741         .mpu_irqs       = i2c3_mpu_irqs,
1742         .sdma_reqs      = i2c3_sdma_reqs,
1743         .main_clk       = "i2c3_fck",
1744         .prcm           = {
1745                 .omap2 = {
1746                         .module_offs = CORE_MOD,
1747                         .prcm_reg_id = 1,
1748                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1749                         .idlest_reg_id = 1,
1750                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1751                 },
1752         },
1753         .slaves         = omap3xxx_i2c3_slaves,
1754         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1755         .class          = &i2c_class,
1756         .dev_attr       = &i2c3_dev_attr,
1757 };
1758
1759 /* l4_wkup -> gpio1 */
1760 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1761         {
1762                 .pa_start       = 0x48310000,
1763                 .pa_end         = 0x483101ff,
1764                 .flags          = ADDR_TYPE_RT
1765         },
1766         { }
1767 };
1768
1769 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1770         .master         = &omap3xxx_l4_wkup_hwmod,
1771         .slave          = &omap3xxx_gpio1_hwmod,
1772         .addr           = omap3xxx_gpio1_addrs,
1773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1774 };
1775
1776 /* l4_per -> gpio2 */
1777 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1778         {
1779                 .pa_start       = 0x49050000,
1780                 .pa_end         = 0x490501ff,
1781                 .flags          = ADDR_TYPE_RT
1782         },
1783         { }
1784 };
1785
1786 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1787         .master         = &omap3xxx_l4_per_hwmod,
1788         .slave          = &omap3xxx_gpio2_hwmod,
1789         .addr           = omap3xxx_gpio2_addrs,
1790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1791 };
1792
1793 /* l4_per -> gpio3 */
1794 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1795         {
1796                 .pa_start       = 0x49052000,
1797                 .pa_end         = 0x490521ff,
1798                 .flags          = ADDR_TYPE_RT
1799         },
1800         { }
1801 };
1802
1803 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1804         .master         = &omap3xxx_l4_per_hwmod,
1805         .slave          = &omap3xxx_gpio3_hwmod,
1806         .addr           = omap3xxx_gpio3_addrs,
1807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1808 };
1809
1810 /* l4_per -> gpio4 */
1811 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1812         {
1813                 .pa_start       = 0x49054000,
1814                 .pa_end         = 0x490541ff,
1815                 .flags          = ADDR_TYPE_RT
1816         },
1817         { }
1818 };
1819
1820 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1821         .master         = &omap3xxx_l4_per_hwmod,
1822         .slave          = &omap3xxx_gpio4_hwmod,
1823         .addr           = omap3xxx_gpio4_addrs,
1824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1825 };
1826
1827 /* l4_per -> gpio5 */
1828 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1829         {
1830                 .pa_start       = 0x49056000,
1831                 .pa_end         = 0x490561ff,
1832                 .flags          = ADDR_TYPE_RT
1833         },
1834         { }
1835 };
1836
1837 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1838         .master         = &omap3xxx_l4_per_hwmod,
1839         .slave          = &omap3xxx_gpio5_hwmod,
1840         .addr           = omap3xxx_gpio5_addrs,
1841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1842 };
1843
1844 /* l4_per -> gpio6 */
1845 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1846         {
1847                 .pa_start       = 0x49058000,
1848                 .pa_end         = 0x490581ff,
1849                 .flags          = ADDR_TYPE_RT
1850         },
1851         { }
1852 };
1853
1854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1855         .master         = &omap3xxx_l4_per_hwmod,
1856         .slave          = &omap3xxx_gpio6_hwmod,
1857         .addr           = omap3xxx_gpio6_addrs,
1858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1859 };
1860
1861 /*
1862  * 'gpio' class
1863  * general purpose io module
1864  */
1865
1866 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1867         .rev_offs       = 0x0000,
1868         .sysc_offs      = 0x0010,
1869         .syss_offs      = 0x0014,
1870         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1871                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1872                            SYSS_HAS_RESET_STATUS),
1873         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1874         .sysc_fields    = &omap_hwmod_sysc_type1,
1875 };
1876
1877 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1878         .name = "gpio",
1879         .sysc = &omap3xxx_gpio_sysc,
1880         .rev = 1,
1881 };
1882
1883 /* gpio_dev_attr*/
1884 static struct omap_gpio_dev_attr gpio_dev_attr = {
1885         .bank_width = 32,
1886         .dbck_flag = true,
1887 };
1888
1889 /* gpio1 */
1890 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1891         { .role = "dbclk", .clk = "gpio1_dbck", },
1892 };
1893
1894 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1895         &omap3xxx_l4_wkup__gpio1,
1896 };
1897
1898 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1899         .name           = "gpio1",
1900         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1901         .mpu_irqs       = omap2_gpio1_irqs,
1902         .main_clk       = "gpio1_ick",
1903         .opt_clks       = gpio1_opt_clks,
1904         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1905         .prcm           = {
1906                 .omap2 = {
1907                         .prcm_reg_id = 1,
1908                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1909                         .module_offs = WKUP_MOD,
1910                         .idlest_reg_id = 1,
1911                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1912                 },
1913         },
1914         .slaves         = omap3xxx_gpio1_slaves,
1915         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1916         .class          = &omap3xxx_gpio_hwmod_class,
1917         .dev_attr       = &gpio_dev_attr,
1918 };
1919
1920 /* gpio2 */
1921 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1922         { .role = "dbclk", .clk = "gpio2_dbck", },
1923 };
1924
1925 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1926         &omap3xxx_l4_per__gpio2,
1927 };
1928
1929 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1930         .name           = "gpio2",
1931         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1932         .mpu_irqs       = omap2_gpio2_irqs,
1933         .main_clk       = "gpio2_ick",
1934         .opt_clks       = gpio2_opt_clks,
1935         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1936         .prcm           = {
1937                 .omap2 = {
1938                         .prcm_reg_id = 1,
1939                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1940                         .module_offs = OMAP3430_PER_MOD,
1941                         .idlest_reg_id = 1,
1942                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1943                 },
1944         },
1945         .slaves         = omap3xxx_gpio2_slaves,
1946         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1947         .class          = &omap3xxx_gpio_hwmod_class,
1948         .dev_attr       = &gpio_dev_attr,
1949 };
1950
1951 /* gpio3 */
1952 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1953         { .role = "dbclk", .clk = "gpio3_dbck", },
1954 };
1955
1956 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1957         &omap3xxx_l4_per__gpio3,
1958 };
1959
1960 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1961         .name           = "gpio3",
1962         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1963         .mpu_irqs       = omap2_gpio3_irqs,
1964         .main_clk       = "gpio3_ick",
1965         .opt_clks       = gpio3_opt_clks,
1966         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1967         .prcm           = {
1968                 .omap2 = {
1969                         .prcm_reg_id = 1,
1970                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1971                         .module_offs = OMAP3430_PER_MOD,
1972                         .idlest_reg_id = 1,
1973                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1974                 },
1975         },
1976         .slaves         = omap3xxx_gpio3_slaves,
1977         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1978         .class          = &omap3xxx_gpio_hwmod_class,
1979         .dev_attr       = &gpio_dev_attr,
1980 };
1981
1982 /* gpio4 */
1983 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1984         { .role = "dbclk", .clk = "gpio4_dbck", },
1985 };
1986
1987 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1988         &omap3xxx_l4_per__gpio4,
1989 };
1990
1991 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1992         .name           = "gpio4",
1993         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1994         .mpu_irqs       = omap2_gpio4_irqs,
1995         .main_clk       = "gpio4_ick",
1996         .opt_clks       = gpio4_opt_clks,
1997         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1998         .prcm           = {
1999                 .omap2 = {
2000                         .prcm_reg_id = 1,
2001                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2002                         .module_offs = OMAP3430_PER_MOD,
2003                         .idlest_reg_id = 1,
2004                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2005                 },
2006         },
2007         .slaves         = omap3xxx_gpio4_slaves,
2008         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2009         .class          = &omap3xxx_gpio_hwmod_class,
2010         .dev_attr       = &gpio_dev_attr,
2011 };
2012
2013 /* gpio5 */
2014 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2015         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2016         { .irq = -1 }
2017 };
2018
2019 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2020         { .role = "dbclk", .clk = "gpio5_dbck", },
2021 };
2022
2023 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2024         &omap3xxx_l4_per__gpio5,
2025 };
2026
2027 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2028         .name           = "gpio5",
2029         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2030         .mpu_irqs       = omap3xxx_gpio5_irqs,
2031         .main_clk       = "gpio5_ick",
2032         .opt_clks       = gpio5_opt_clks,
2033         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2034         .prcm           = {
2035                 .omap2 = {
2036                         .prcm_reg_id = 1,
2037                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2038                         .module_offs = OMAP3430_PER_MOD,
2039                         .idlest_reg_id = 1,
2040                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2041                 },
2042         },
2043         .slaves         = omap3xxx_gpio5_slaves,
2044         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2045         .class          = &omap3xxx_gpio_hwmod_class,
2046         .dev_attr       = &gpio_dev_attr,
2047 };
2048
2049 /* gpio6 */
2050 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2051         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2052         { .irq = -1 }
2053 };
2054
2055 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2056         { .role = "dbclk", .clk = "gpio6_dbck", },
2057 };
2058
2059 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2060         &omap3xxx_l4_per__gpio6,
2061 };
2062
2063 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2064         .name           = "gpio6",
2065         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2066         .mpu_irqs       = omap3xxx_gpio6_irqs,
2067         .main_clk       = "gpio6_ick",
2068         .opt_clks       = gpio6_opt_clks,
2069         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2070         .prcm           = {
2071                 .omap2 = {
2072                         .prcm_reg_id = 1,
2073                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2074                         .module_offs = OMAP3430_PER_MOD,
2075                         .idlest_reg_id = 1,
2076                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2077                 },
2078         },
2079         .slaves         = omap3xxx_gpio6_slaves,
2080         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2081         .class          = &omap3xxx_gpio_hwmod_class,
2082         .dev_attr       = &gpio_dev_attr,
2083 };
2084
2085 /* dma_system -> L3 */
2086 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2087         .master         = &omap3xxx_dma_system_hwmod,
2088         .slave          = &omap3xxx_l3_main_hwmod,
2089         .clk            = "core_l3_ick",
2090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2091 };
2092
2093 /* dma attributes */
2094 static struct omap_dma_dev_attr dma_dev_attr = {
2095         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2096                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2097         .lch_count = 32,
2098 };
2099
2100 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2101         .rev_offs       = 0x0000,
2102         .sysc_offs      = 0x002c,
2103         .syss_offs      = 0x0028,
2104         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2105                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2106                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2107                            SYSS_HAS_RESET_STATUS),
2108         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2109                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2110         .sysc_fields    = &omap_hwmod_sysc_type1,
2111 };
2112
2113 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2114         .name = "dma",
2115         .sysc = &omap3xxx_dma_sysc,
2116 };
2117
2118 /* dma_system */
2119 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2120         {
2121                 .pa_start       = 0x48056000,
2122                 .pa_end         = 0x48056fff,
2123                 .flags          = ADDR_TYPE_RT
2124         },
2125         { }
2126 };
2127
2128 /* dma_system master ports */
2129 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2130         &omap3xxx_dma_system__l3,
2131 };
2132
2133 /* l4_cfg -> dma_system */
2134 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2135         .master         = &omap3xxx_l4_core_hwmod,
2136         .slave          = &omap3xxx_dma_system_hwmod,
2137         .clk            = "core_l4_ick",
2138         .addr           = omap3xxx_dma_system_addrs,
2139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2140 };
2141
2142 /* dma_system slave ports */
2143 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2144         &omap3xxx_l4_core__dma_system,
2145 };
2146
2147 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2148         .name           = "dma",
2149         .class          = &omap3xxx_dma_hwmod_class,
2150         .mpu_irqs       = omap2_dma_system_irqs,
2151         .main_clk       = "core_l3_ick",
2152         .prcm = {
2153                 .omap2 = {
2154                         .module_offs            = CORE_MOD,
2155                         .prcm_reg_id            = 1,
2156                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2157                         .idlest_reg_id          = 1,
2158                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2159                 },
2160         },
2161         .slaves         = omap3xxx_dma_system_slaves,
2162         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2163         .masters        = omap3xxx_dma_system_masters,
2164         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2165         .dev_attr       = &dma_dev_attr,
2166         .flags          = HWMOD_NO_IDLEST,
2167 };
2168
2169 /*
2170  * 'mcbsp' class
2171  * multi channel buffered serial port controller
2172  */
2173
2174 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2175         .sysc_offs      = 0x008c,
2176         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2177                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2178         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2179         .sysc_fields    = &omap_hwmod_sysc_type1,
2180         .clockact       = 0x2,
2181 };
2182
2183 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2184         .name = "mcbsp",
2185         .sysc = &omap3xxx_mcbsp_sysc,
2186         .rev  = MCBSP_CONFIG_TYPE3,
2187 };
2188
2189 /* mcbsp1 */
2190 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2191         { .name = "irq", .irq = 16 },
2192         { .name = "tx", .irq = 59 },
2193         { .name = "rx", .irq = 60 },
2194         { .irq = -1 }
2195 };
2196
2197 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2198         {
2199                 .name           = "mpu",
2200                 .pa_start       = 0x48074000,
2201                 .pa_end         = 0x480740ff,
2202                 .flags          = ADDR_TYPE_RT
2203         },
2204         { }
2205 };
2206
2207 /* l4_core -> mcbsp1 */
2208 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2209         .master         = &omap3xxx_l4_core_hwmod,
2210         .slave          = &omap3xxx_mcbsp1_hwmod,
2211         .clk            = "mcbsp1_ick",
2212         .addr           = omap3xxx_mcbsp1_addrs,
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* mcbsp1 slave ports */
2217 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2218         &omap3xxx_l4_core__mcbsp1,
2219 };
2220
2221 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2222         .name           = "mcbsp1",
2223         .class          = &omap3xxx_mcbsp_hwmod_class,
2224         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2225         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2226         .main_clk       = "mcbsp1_fck",
2227         .prcm           = {
2228                 .omap2 = {
2229                         .prcm_reg_id = 1,
2230                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2231                         .module_offs = CORE_MOD,
2232                         .idlest_reg_id = 1,
2233                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2234                 },
2235         },
2236         .slaves         = omap3xxx_mcbsp1_slaves,
2237         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2238 };
2239
2240 /* mcbsp2 */
2241 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2242         { .name = "irq", .irq = 17 },
2243         { .name = "tx", .irq = 62 },
2244         { .name = "rx", .irq = 63 },
2245         { .irq = -1 }
2246 };
2247
2248 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2249         {
2250                 .name           = "mpu",
2251                 .pa_start       = 0x49022000,
2252                 .pa_end         = 0x490220ff,
2253                 .flags          = ADDR_TYPE_RT
2254         },
2255         { }
2256 };
2257
2258 /* l4_per -> mcbsp2 */
2259 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2260         .master         = &omap3xxx_l4_per_hwmod,
2261         .slave          = &omap3xxx_mcbsp2_hwmod,
2262         .clk            = "mcbsp2_ick",
2263         .addr           = omap3xxx_mcbsp2_addrs,
2264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2265 };
2266
2267 /* mcbsp2 slave ports */
2268 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2269         &omap3xxx_l4_per__mcbsp2,
2270 };
2271
2272 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2273         .sidetone       = "mcbsp2_sidetone",
2274 };
2275
2276 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2277         .name           = "mcbsp2",
2278         .class          = &omap3xxx_mcbsp_hwmod_class,
2279         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2280         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2281         .main_clk       = "mcbsp2_fck",
2282         .prcm           = {
2283                 .omap2 = {
2284                         .prcm_reg_id = 1,
2285                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2286                         .module_offs = OMAP3430_PER_MOD,
2287                         .idlest_reg_id = 1,
2288                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2289                 },
2290         },
2291         .slaves         = omap3xxx_mcbsp2_slaves,
2292         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2293         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2294 };
2295
2296 /* mcbsp3 */
2297 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2298         { .name = "irq", .irq = 22 },
2299         { .name = "tx", .irq = 89 },
2300         { .name = "rx", .irq = 90 },
2301         { .irq = -1 }
2302 };
2303
2304 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2305         {
2306                 .name           = "mpu",
2307                 .pa_start       = 0x49024000,
2308                 .pa_end         = 0x490240ff,
2309                 .flags          = ADDR_TYPE_RT
2310         },
2311         { }
2312 };
2313
2314 /* l4_per -> mcbsp3 */
2315 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2316         .master         = &omap3xxx_l4_per_hwmod,
2317         .slave          = &omap3xxx_mcbsp3_hwmod,
2318         .clk            = "mcbsp3_ick",
2319         .addr           = omap3xxx_mcbsp3_addrs,
2320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2321 };
2322
2323 /* mcbsp3 slave ports */
2324 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2325         &omap3xxx_l4_per__mcbsp3,
2326 };
2327
2328 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2329         .sidetone       = "mcbsp3_sidetone",
2330 };
2331
2332 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2333         .name           = "mcbsp3",
2334         .class          = &omap3xxx_mcbsp_hwmod_class,
2335         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2336         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2337         .main_clk       = "mcbsp3_fck",
2338         .prcm           = {
2339                 .omap2 = {
2340                         .prcm_reg_id = 1,
2341                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2342                         .module_offs = OMAP3430_PER_MOD,
2343                         .idlest_reg_id = 1,
2344                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2345                 },
2346         },
2347         .slaves         = omap3xxx_mcbsp3_slaves,
2348         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2349         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2350 };
2351
2352 /* mcbsp4 */
2353 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2354         { .name = "irq", .irq = 23 },
2355         { .name = "tx", .irq = 54 },
2356         { .name = "rx", .irq = 55 },
2357         { .irq = -1 }
2358 };
2359
2360 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2361         { .name = "rx", .dma_req = 20 },
2362         { .name = "tx", .dma_req = 19 },
2363         { .dma_req = -1 }
2364 };
2365
2366 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2367         {
2368                 .name           = "mpu",
2369                 .pa_start       = 0x49026000,
2370                 .pa_end         = 0x490260ff,
2371                 .flags          = ADDR_TYPE_RT
2372         },
2373         { }
2374 };
2375
2376 /* l4_per -> mcbsp4 */
2377 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2378         .master         = &omap3xxx_l4_per_hwmod,
2379         .slave          = &omap3xxx_mcbsp4_hwmod,
2380         .clk            = "mcbsp4_ick",
2381         .addr           = omap3xxx_mcbsp4_addrs,
2382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2383 };
2384
2385 /* mcbsp4 slave ports */
2386 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2387         &omap3xxx_l4_per__mcbsp4,
2388 };
2389
2390 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2391         .name           = "mcbsp4",
2392         .class          = &omap3xxx_mcbsp_hwmod_class,
2393         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2394         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2395         .main_clk       = "mcbsp4_fck",
2396         .prcm           = {
2397                 .omap2 = {
2398                         .prcm_reg_id = 1,
2399                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2400                         .module_offs = OMAP3430_PER_MOD,
2401                         .idlest_reg_id = 1,
2402                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2403                 },
2404         },
2405         .slaves         = omap3xxx_mcbsp4_slaves,
2406         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2407 };
2408
2409 /* mcbsp5 */
2410 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2411         { .name = "irq", .irq = 27 },
2412         { .name = "tx", .irq = 81 },
2413         { .name = "rx", .irq = 82 },
2414         { .irq = -1 }
2415 };
2416
2417 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2418         { .name = "rx", .dma_req = 22 },
2419         { .name = "tx", .dma_req = 21 },
2420         { .dma_req = -1 }
2421 };
2422
2423 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2424         {
2425                 .name           = "mpu",
2426                 .pa_start       = 0x48096000,
2427                 .pa_end         = 0x480960ff,
2428                 .flags          = ADDR_TYPE_RT
2429         },
2430         { }
2431 };
2432
2433 /* l4_core -> mcbsp5 */
2434 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2435         .master         = &omap3xxx_l4_core_hwmod,
2436         .slave          = &omap3xxx_mcbsp5_hwmod,
2437         .clk            = "mcbsp5_ick",
2438         .addr           = omap3xxx_mcbsp5_addrs,
2439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2440 };
2441
2442 /* mcbsp5 slave ports */
2443 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2444         &omap3xxx_l4_core__mcbsp5,
2445 };
2446
2447 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2448         .name           = "mcbsp5",
2449         .class          = &omap3xxx_mcbsp_hwmod_class,
2450         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2451         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2452         .main_clk       = "mcbsp5_fck",
2453         .prcm           = {
2454                 .omap2 = {
2455                         .prcm_reg_id = 1,
2456                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2457                         .module_offs = CORE_MOD,
2458                         .idlest_reg_id = 1,
2459                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2460                 },
2461         },
2462         .slaves         = omap3xxx_mcbsp5_slaves,
2463         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2464 };
2465 /* 'mcbsp sidetone' class */
2466
2467 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2468         .sysc_offs      = 0x0010,
2469         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2470         .sysc_fields    = &omap_hwmod_sysc_type1,
2471 };
2472
2473 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2474         .name = "mcbsp_sidetone",
2475         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2476 };
2477
2478 /* mcbsp2_sidetone */
2479 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2480         { .name = "irq", .irq = 4 },
2481         { .irq = -1 }
2482 };
2483
2484 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2485         {
2486                 .name           = "sidetone",
2487                 .pa_start       = 0x49028000,
2488                 .pa_end         = 0x490280ff,
2489                 .flags          = ADDR_TYPE_RT
2490         },
2491         { }
2492 };
2493
2494 /* l4_per -> mcbsp2_sidetone */
2495 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2496         .master         = &omap3xxx_l4_per_hwmod,
2497         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2498         .clk            = "mcbsp2_ick",
2499         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2500         .user           = OCP_USER_MPU,
2501 };
2502
2503 /* mcbsp2_sidetone slave ports */
2504 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2505         &omap3xxx_l4_per__mcbsp2_sidetone,
2506 };
2507
2508 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2509         .name           = "mcbsp2_sidetone",
2510         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2511         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2512         .main_clk       = "mcbsp2_fck",
2513         .prcm           = {
2514                 .omap2 = {
2515                         .prcm_reg_id = 1,
2516                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2517                         .module_offs = OMAP3430_PER_MOD,
2518                         .idlest_reg_id = 1,
2519                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2520                 },
2521         },
2522         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2523         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2524 };
2525
2526 /* mcbsp3_sidetone */
2527 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2528         { .name = "irq", .irq = 5 },
2529         { .irq = -1 }
2530 };
2531
2532 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2533         {
2534                 .name           = "sidetone",
2535                 .pa_start       = 0x4902A000,
2536                 .pa_end         = 0x4902A0ff,
2537                 .flags          = ADDR_TYPE_RT
2538         },
2539         { }
2540 };
2541
2542 /* l4_per -> mcbsp3_sidetone */
2543 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2544         .master         = &omap3xxx_l4_per_hwmod,
2545         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2546         .clk            = "mcbsp3_ick",
2547         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2548         .user           = OCP_USER_MPU,
2549 };
2550
2551 /* mcbsp3_sidetone slave ports */
2552 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2553         &omap3xxx_l4_per__mcbsp3_sidetone,
2554 };
2555
2556 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2557         .name           = "mcbsp3_sidetone",
2558         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2559         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2560         .main_clk       = "mcbsp3_fck",
2561         .prcm           = {
2562                 .omap2 = {
2563                         .prcm_reg_id = 1,
2564                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2565                         .module_offs = OMAP3430_PER_MOD,
2566                         .idlest_reg_id = 1,
2567                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2568                 },
2569         },
2570         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2571         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2572 };
2573
2574
2575 /* SR common */
2576 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2577         .clkact_shift   = 20,
2578 };
2579
2580 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2581         .sysc_offs      = 0x24,
2582         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2583         .clockact       = CLOCKACT_TEST_ICLK,
2584         .sysc_fields    = &omap34xx_sr_sysc_fields,
2585 };
2586
2587 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2588         .name = "smartreflex",
2589         .sysc = &omap34xx_sr_sysc,
2590         .rev  = 1,
2591 };
2592
2593 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2594         .sidle_shift    = 24,
2595         .enwkup_shift   = 26
2596 };
2597
2598 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2599         .sysc_offs      = 0x38,
2600         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2601         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2602                         SYSC_NO_CACHE),
2603         .sysc_fields    = &omap36xx_sr_sysc_fields,
2604 };
2605
2606 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2607         .name = "smartreflex",
2608         .sysc = &omap36xx_sr_sysc,
2609         .rev  = 2,
2610 };
2611
2612 /* SR1 */
2613 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2614         .sensor_voltdm_name   = "mpu_iva",
2615 };
2616
2617 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2618         &omap3_l4_core__sr1,
2619 };
2620
2621 static struct omap_hwmod omap34xx_sr1_hwmod = {
2622         .name           = "sr1",
2623         .class          = &omap34xx_smartreflex_hwmod_class,
2624         .main_clk       = "sr1_fck",
2625         .prcm           = {
2626                 .omap2 = {
2627                         .prcm_reg_id = 1,
2628                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2629                         .module_offs = WKUP_MOD,
2630                         .idlest_reg_id = 1,
2631                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2632                 },
2633         },
2634         .slaves         = omap3_sr1_slaves,
2635         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2636         .dev_attr       = &sr1_dev_attr,
2637         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2638 };
2639
2640 static struct omap_hwmod omap36xx_sr1_hwmod = {
2641         .name           = "sr1",
2642         .class          = &omap36xx_smartreflex_hwmod_class,
2643         .main_clk       = "sr1_fck",
2644         .prcm           = {
2645                 .omap2 = {
2646                         .prcm_reg_id = 1,
2647                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2648                         .module_offs = WKUP_MOD,
2649                         .idlest_reg_id = 1,
2650                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2651                 },
2652         },
2653         .slaves         = omap3_sr1_slaves,
2654         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2655         .dev_attr       = &sr1_dev_attr,
2656 };
2657
2658 /* SR2 */
2659 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2660         .sensor_voltdm_name     = "core",
2661 };
2662
2663 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2664         &omap3_l4_core__sr2,
2665 };
2666
2667 static struct omap_hwmod omap34xx_sr2_hwmod = {
2668         .name           = "sr2",
2669         .class          = &omap34xx_smartreflex_hwmod_class,
2670         .main_clk       = "sr2_fck",
2671         .prcm           = {
2672                 .omap2 = {
2673                         .prcm_reg_id = 1,
2674                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2675                         .module_offs = WKUP_MOD,
2676                         .idlest_reg_id = 1,
2677                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2678                 },
2679         },
2680         .slaves         = omap3_sr2_slaves,
2681         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2682         .dev_attr       = &sr2_dev_attr,
2683         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2684 };
2685
2686 static struct omap_hwmod omap36xx_sr2_hwmod = {
2687         .name           = "sr2",
2688         .class          = &omap36xx_smartreflex_hwmod_class,
2689         .main_clk       = "sr2_fck",
2690         .prcm           = {
2691                 .omap2 = {
2692                         .prcm_reg_id = 1,
2693                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2694                         .module_offs = WKUP_MOD,
2695                         .idlest_reg_id = 1,
2696                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2697                 },
2698         },
2699         .slaves         = omap3_sr2_slaves,
2700         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2701         .dev_attr       = &sr2_dev_attr,
2702 };
2703
2704 /*
2705  * 'mailbox' class
2706  * mailbox module allowing communication between the on-chip processors
2707  * using a queued mailbox-interrupt mechanism.
2708  */
2709
2710 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2711         .rev_offs       = 0x000,
2712         .sysc_offs      = 0x010,
2713         .syss_offs      = 0x014,
2714         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2715                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2716         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2717         .sysc_fields    = &omap_hwmod_sysc_type1,
2718 };
2719
2720 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2721         .name = "mailbox",
2722         .sysc = &omap3xxx_mailbox_sysc,
2723 };
2724
2725 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2726 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2727         { .irq = 26 },
2728         { .irq = -1 }
2729 };
2730
2731 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2732         {
2733                 .pa_start       = 0x48094000,
2734                 .pa_end         = 0x480941ff,
2735                 .flags          = ADDR_TYPE_RT,
2736         },
2737         { }
2738 };
2739
2740 /* l4_core -> mailbox */
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2742         .master         = &omap3xxx_l4_core_hwmod,
2743         .slave          = &omap3xxx_mailbox_hwmod,
2744         .addr           = omap3xxx_mailbox_addrs,
2745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2746 };
2747
2748 /* mailbox slave ports */
2749 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2750         &omap3xxx_l4_core__mailbox,
2751 };
2752
2753 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2754         .name           = "mailbox",
2755         .class          = &omap3xxx_mailbox_hwmod_class,
2756         .mpu_irqs       = omap3xxx_mailbox_irqs,
2757         .main_clk       = "mailboxes_ick",
2758         .prcm           = {
2759                 .omap2 = {
2760                         .prcm_reg_id = 1,
2761                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2762                         .module_offs = CORE_MOD,
2763                         .idlest_reg_id = 1,
2764                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2765                 },
2766         },
2767         .slaves         = omap3xxx_mailbox_slaves,
2768         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2769 };
2770
2771 /* l4 core -> mcspi1 interface */
2772 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2773         .master         = &omap3xxx_l4_core_hwmod,
2774         .slave          = &omap34xx_mcspi1,
2775         .clk            = "mcspi1_ick",
2776         .addr           = omap2_mcspi1_addr_space,
2777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2778 };
2779
2780 /* l4 core -> mcspi2 interface */
2781 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2782         .master         = &omap3xxx_l4_core_hwmod,
2783         .slave          = &omap34xx_mcspi2,
2784         .clk            = "mcspi2_ick",
2785         .addr           = omap2_mcspi2_addr_space,
2786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2787 };
2788
2789 /* l4 core -> mcspi3 interface */
2790 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2791         .master         = &omap3xxx_l4_core_hwmod,
2792         .slave          = &omap34xx_mcspi3,
2793         .clk            = "mcspi3_ick",
2794         .addr           = omap2430_mcspi3_addr_space,
2795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2796 };
2797
2798 /* l4 core -> mcspi4 interface */
2799 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2800         {
2801                 .pa_start       = 0x480ba000,
2802                 .pa_end         = 0x480ba0ff,
2803                 .flags          = ADDR_TYPE_RT,
2804         },
2805         { }
2806 };
2807
2808 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2809         .master         = &omap3xxx_l4_core_hwmod,
2810         .slave          = &omap34xx_mcspi4,
2811         .clk            = "mcspi4_ick",
2812         .addr           = omap34xx_mcspi4_addr_space,
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /*
2817  * 'mcspi' class
2818  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2819  * bus
2820  */
2821
2822 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2823         .rev_offs       = 0x0000,
2824         .sysc_offs      = 0x0010,
2825         .syss_offs      = 0x0014,
2826         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2827                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2828                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2829         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2830         .sysc_fields    = &omap_hwmod_sysc_type1,
2831 };
2832
2833 static struct omap_hwmod_class omap34xx_mcspi_class = {
2834         .name = "mcspi",
2835         .sysc = &omap34xx_mcspi_sysc,
2836         .rev = OMAP3_MCSPI_REV,
2837 };
2838
2839 /* mcspi1 */
2840 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2841         &omap34xx_l4_core__mcspi1,
2842 };
2843
2844 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2845         .num_chipselect = 4,
2846 };
2847
2848 static struct omap_hwmod omap34xx_mcspi1 = {
2849         .name           = "mcspi1",
2850         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2851         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2852         .main_clk       = "mcspi1_fck",
2853         .prcm           = {
2854                 .omap2 = {
2855                         .module_offs = CORE_MOD,
2856                         .prcm_reg_id = 1,
2857                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2858                         .idlest_reg_id = 1,
2859                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2860                 },
2861         },
2862         .slaves         = omap34xx_mcspi1_slaves,
2863         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2864         .class          = &omap34xx_mcspi_class,
2865         .dev_attr       = &omap_mcspi1_dev_attr,
2866 };
2867
2868 /* mcspi2 */
2869 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2870         &omap34xx_l4_core__mcspi2,
2871 };
2872
2873 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2874         .num_chipselect = 2,
2875 };
2876
2877 static struct omap_hwmod omap34xx_mcspi2 = {
2878         .name           = "mcspi2",
2879         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2880         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2881         .main_clk       = "mcspi2_fck",
2882         .prcm           = {
2883                 .omap2 = {
2884                         .module_offs = CORE_MOD,
2885                         .prcm_reg_id = 1,
2886                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2887                         .idlest_reg_id = 1,
2888                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2889                 },
2890         },
2891         .slaves         = omap34xx_mcspi2_slaves,
2892         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2893         .class          = &omap34xx_mcspi_class,
2894         .dev_attr       = &omap_mcspi2_dev_attr,
2895 };
2896
2897 /* mcspi3 */
2898 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2899         { .name = "irq", .irq = 91 }, /* 91 */
2900         { .irq = -1 }
2901 };
2902
2903 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2904         { .name = "tx0", .dma_req = 15 },
2905         { .name = "rx0", .dma_req = 16 },
2906         { .name = "tx1", .dma_req = 23 },
2907         { .name = "rx1", .dma_req = 24 },
2908         { .dma_req = -1 }
2909 };
2910
2911 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2912         &omap34xx_l4_core__mcspi3,
2913 };
2914
2915 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2916         .num_chipselect = 2,
2917 };
2918
2919 static struct omap_hwmod omap34xx_mcspi3 = {
2920         .name           = "mcspi3",
2921         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2922         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2923         .main_clk       = "mcspi3_fck",
2924         .prcm           = {
2925                 .omap2 = {
2926                         .module_offs = CORE_MOD,
2927                         .prcm_reg_id = 1,
2928                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2929                         .idlest_reg_id = 1,
2930                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2931                 },
2932         },
2933         .slaves         = omap34xx_mcspi3_slaves,
2934         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2935         .class          = &omap34xx_mcspi_class,
2936         .dev_attr       = &omap_mcspi3_dev_attr,
2937 };
2938
2939 /* SPI4 */
2940 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2941         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2942         { .irq = -1 }
2943 };
2944
2945 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2946         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2947         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2948         { .dma_req = -1 }
2949 };
2950
2951 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2952         &omap34xx_l4_core__mcspi4,
2953 };
2954
2955 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2956         .num_chipselect = 1,
2957 };
2958
2959 static struct omap_hwmod omap34xx_mcspi4 = {
2960         .name           = "mcspi4",
2961         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2962         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2963         .main_clk       = "mcspi4_fck",
2964         .prcm           = {
2965                 .omap2 = {
2966                         .module_offs = CORE_MOD,
2967                         .prcm_reg_id = 1,
2968                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2969                         .idlest_reg_id = 1,
2970                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2971                 },
2972         },
2973         .slaves         = omap34xx_mcspi4_slaves,
2974         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2975         .class          = &omap34xx_mcspi_class,
2976         .dev_attr       = &omap_mcspi4_dev_attr,
2977 };
2978
2979 /* temp. sensor */
2980 struct omap_hwmod_class omap34xx_bandgap_ts_class = {
2981         .name   = "bandgap_ts",
2982 };
2983
2984 static struct omap_hwmod_addr_space omap3xxx_bandgap_ts_addrs[] = {
2985         {
2986                 .name           = "mpu",
2987                 .pa_start       = 0x48002524,
2988                 .pa_end         = 0x48002524 + 4,
2989                 .flags          = ADDR_TYPE_RT
2990         },
2991         { }
2992 };
2993
2994 static struct omap_hwmod omap34xx_bandgap_ts;
2995
2996 /* l4_core -> bandgap */
2997 static struct omap_hwmod_ocp_if omap3xxx_l4_core__bandgap_ts = {
2998         .master         = &omap3xxx_l4_core_hwmod,
2999         .slave          = &omap34xx_bandgap_ts,
3000         .addr           = omap3xxx_bandgap_ts_addrs,
3001         .user           = OCP_USER_MPU,
3002 };
3003
3004 static struct omap_hwmod_ocp_if *omap3xxx_bandgap_ts_slaves[] = {
3005         &omap3xxx_l4_core__bandgap_ts,
3006 };
3007
3008 static struct omap_hwmod omap34xx_bandgap_ts = {
3009         .name           = "bandgap_ts",
3010         .main_clk       = "ts_fck",
3011         .slaves         = omap3xxx_bandgap_ts_slaves,
3012         .slaves_cnt     = ARRAY_SIZE(omap3xxx_bandgap_ts_slaves),
3013         .class          = &omap34xx_bandgap_ts_class,
3014         .flags          = HWMOD_NO_IDLEST,
3015 };
3016
3017 /*
3018  * usbhsotg
3019  */
3020 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3021         .rev_offs       = 0x0400,
3022         .sysc_offs      = 0x0404,
3023         .syss_offs      = 0x0408,
3024         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3025                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3026                           SYSC_HAS_AUTOIDLE),
3027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3028                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3029         .sysc_fields    = &omap_hwmod_sysc_type1,
3030 };
3031
3032 static struct omap_hwmod_class usbotg_class = {
3033         .name = "usbotg",
3034         .sysc = &omap3xxx_usbhsotg_sysc,
3035 };
3036 /* usb_otg_hs */
3037 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3038
3039         { .name = "mc", .irq = 92 },
3040         { .name = "dma", .irq = 93 },
3041         { .irq = -1 }
3042 };
3043
3044 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3045         .name           = "usb_otg_hs",
3046         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3047         .main_clk       = "hsotgusb_ick",
3048         .prcm           = {
3049                 .omap2 = {
3050                         .prcm_reg_id = 1,
3051                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3052                         .module_offs = CORE_MOD,
3053                         .idlest_reg_id = 1,
3054                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3055                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3056                 },
3057         },
3058         .masters        = omap3xxx_usbhsotg_masters,
3059         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3060         .slaves         = omap3xxx_usbhsotg_slaves,
3061         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3062         .class          = &usbotg_class,
3063
3064         /*
3065          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3066          * broken when autoidle is enabled
3067          * workaround is to disable the autoidle bit at module level.
3068          *
3069          * Enabling the device in any other MIDLEMODE setting but force-idle
3070          * causes core_pwrdm not enter idle states at least on OMAP3630.
3071          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
3072          * signal when MIDLEMODE is set to force-idle.
3073          */
3074         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3075                                 | HWMOD_FORCE_MSTANDBY,
3076 };
3077
3078 /* usb_otg_hs */
3079 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3080
3081         { .name = "mc", .irq = 71 },
3082         { .irq = -1 }
3083 };
3084
3085 static struct omap_hwmod_class am35xx_usbotg_class = {
3086         .name = "am35xx_usbotg",
3087         .sysc = NULL,
3088 };
3089
3090 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3091         .name           = "am35x_otg_hs",
3092         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3093         .main_clk       = NULL,
3094         .prcm = {
3095                 .omap2 = {
3096                 },
3097         },
3098         .masters        = am35xx_usbhsotg_masters,
3099         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3100         .slaves         = am35xx_usbhsotg_slaves,
3101         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3102         .class          = &am35xx_usbotg_class,
3103 };
3104
3105 /* MMC/SD/SDIO common */
3106
3107 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3108         .rev_offs       = 0x1fc,
3109         .sysc_offs      = 0x10,
3110         .syss_offs      = 0x14,
3111         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3112                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3113                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3114         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3115         .sysc_fields    = &omap_hwmod_sysc_type1,
3116 };
3117
3118 static struct omap_hwmod_class omap34xx_mmc_class = {
3119         .name = "mmc",
3120         .sysc = &omap34xx_mmc_sysc,
3121 };
3122
3123 /* MMC/SD/SDIO1 */
3124
3125 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3126         { .irq = 83, },
3127         { .irq = -1 }
3128 };
3129
3130 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3131         { .name = "tx", .dma_req = 61, },
3132         { .name = "rx", .dma_req = 62, },
3133         { .dma_req = -1 }
3134 };
3135
3136 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3137         { .role = "dbck", .clk = "omap_32k_fck", },
3138 };
3139
3140 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3141         &omap3xxx_l4_core__mmc1,
3142 };
3143
3144 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3145         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3146 };
3147
3148 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3149 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3150         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3151                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3152 };
3153
3154 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3155         .name           = "mmc1",
3156         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3157         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3158         .opt_clks       = omap34xx_mmc1_opt_clks,
3159         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3160         .main_clk       = "mmchs1_fck",
3161         .prcm           = {
3162                 .omap2 = {
3163                         .module_offs = CORE_MOD,
3164                         .prcm_reg_id = 1,
3165                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3166                         .idlest_reg_id = 1,
3167                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3168                 },
3169         },
3170         .dev_attr       = &mmc1_pre_es3_dev_attr,
3171         .slaves         = omap3xxx_mmc1_slaves,
3172         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3173         .class          = &omap34xx_mmc_class,
3174 };
3175
3176 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3177         .name           = "mmc1",
3178         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3179         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3180         .opt_clks       = omap34xx_mmc1_opt_clks,
3181         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3182         .main_clk       = "mmchs1_fck",
3183         .prcm           = {
3184                 .omap2 = {
3185                         .module_offs = CORE_MOD,
3186                         .prcm_reg_id = 1,
3187                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3188                         .idlest_reg_id = 1,
3189                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3190                 },
3191         },
3192         .dev_attr       = &mmc1_dev_attr,
3193         .slaves         = omap3xxx_mmc1_slaves,
3194         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3195         .class          = &omap34xx_mmc_class,
3196 };
3197
3198 /* MMC/SD/SDIO2 */
3199
3200 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3201         { .irq = INT_24XX_MMC2_IRQ, },
3202         { .irq = -1 }
3203 };
3204
3205 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3206         { .name = "tx", .dma_req = 47, },
3207         { .name = "rx", .dma_req = 48, },
3208         { .dma_req = -1 }
3209 };
3210
3211 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3212         { .role = "dbck", .clk = "omap_32k_fck", },
3213 };
3214
3215 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3216         &omap3xxx_l4_core__mmc2,
3217 };
3218
3219 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3220 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3221         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3222 };
3223
3224 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3225         .name           = "mmc2",
3226         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3227         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3228         .opt_clks       = omap34xx_mmc2_opt_clks,
3229         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3230         .main_clk       = "mmchs2_fck",
3231         .prcm           = {
3232                 .omap2 = {
3233                         .module_offs = CORE_MOD,
3234                         .prcm_reg_id = 1,
3235                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3236                         .idlest_reg_id = 1,
3237                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3238                 },
3239         },
3240         .dev_attr       = &mmc2_pre_es3_dev_attr,
3241         .slaves         = omap3xxx_mmc2_slaves,
3242         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3243         .class          = &omap34xx_mmc_class,
3244 };
3245
3246 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3247         .name           = "mmc2",
3248         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3249         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3250         .opt_clks       = omap34xx_mmc2_opt_clks,
3251         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3252         .main_clk       = "mmchs2_fck",
3253         .prcm           = {
3254                 .omap2 = {
3255                         .module_offs = CORE_MOD,
3256                         .prcm_reg_id = 1,
3257                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3258                         .idlest_reg_id = 1,
3259                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3260                 },
3261         },
3262         .slaves         = omap3xxx_mmc2_slaves,
3263         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3264         .class          = &omap34xx_mmc_class,
3265 };
3266
3267 /* MMC/SD/SDIO3 */
3268
3269 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3270         { .irq = 94, },
3271         { .irq = -1 }
3272 };
3273
3274 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3275         { .name = "tx", .dma_req = 77, },
3276         { .name = "rx", .dma_req = 78, },
3277         { .dma_req = -1 }
3278 };
3279
3280 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3281         { .role = "dbck", .clk = "omap_32k_fck", },
3282 };
3283
3284 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3285         &omap3xxx_l4_core__mmc3,
3286 };
3287
3288 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3289         .name           = "mmc3",
3290         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3291         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3292         .opt_clks       = omap34xx_mmc3_opt_clks,
3293         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3294         .main_clk       = "mmchs3_fck",
3295         .prcm           = {
3296                 .omap2 = {
3297                         .prcm_reg_id = 1,
3298                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3299                         .idlest_reg_id = 1,
3300                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3301                 },
3302         },
3303         .slaves         = omap3xxx_mmc3_slaves,
3304         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3305         .class          = &omap34xx_mmc_class,
3306 };
3307
3308 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3309         &omap3xxx_l3_main_hwmod,
3310         &omap3xxx_l4_core_hwmod,
3311         &omap3xxx_l4_per_hwmod,
3312         &omap3xxx_l4_wkup_hwmod,
3313         &omap3xxx_mmc3_hwmod,
3314         &omap3xxx_mpu_hwmod,
3315
3316         &omap3xxx_timer1_hwmod,
3317         &omap3xxx_timer2_hwmod,
3318         &omap3xxx_timer3_hwmod,
3319         &omap3xxx_timer4_hwmod,
3320         &omap3xxx_timer5_hwmod,
3321         &omap3xxx_timer6_hwmod,
3322         &omap3xxx_timer7_hwmod,
3323         &omap3xxx_timer8_hwmod,
3324         &omap3xxx_timer9_hwmod,
3325         &omap3xxx_timer10_hwmod,
3326         &omap3xxx_timer11_hwmod,
3327
3328         &omap3xxx_wd_timer2_hwmod,
3329         &omap3xxx_uart1_hwmod,
3330         &omap3xxx_uart2_hwmod,
3331         &omap3xxx_uart3_hwmod,
3332
3333         /* i2c class */
3334         &omap3xxx_i2c1_hwmod,
3335         &omap3xxx_i2c2_hwmod,
3336         &omap3xxx_i2c3_hwmod,
3337
3338         /* gpio class */
3339         &omap3xxx_gpio1_hwmod,
3340         &omap3xxx_gpio2_hwmod,
3341         &omap3xxx_gpio3_hwmod,
3342         &omap3xxx_gpio4_hwmod,
3343         &omap3xxx_gpio5_hwmod,
3344         &omap3xxx_gpio6_hwmod,
3345
3346         /* dma_system class*/
3347         &omap3xxx_dma_system_hwmod,
3348
3349         /* mcbsp class */
3350         &omap3xxx_mcbsp1_hwmod,
3351         &omap3xxx_mcbsp2_hwmod,
3352         &omap3xxx_mcbsp3_hwmod,
3353         &omap3xxx_mcbsp4_hwmod,
3354         &omap3xxx_mcbsp5_hwmod,
3355         &omap3xxx_mcbsp2_sidetone_hwmod,
3356         &omap3xxx_mcbsp3_sidetone_hwmod,
3357
3358
3359         /* mcspi class */
3360         &omap34xx_mcspi1,
3361         &omap34xx_mcspi2,
3362         &omap34xx_mcspi3,
3363         &omap34xx_mcspi4,
3364
3365         &omap34xx_bandgap_ts,
3366
3367         NULL,
3368 };
3369
3370 /* GP-only hwmods */
3371 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3372         &omap3xxx_timer12_hwmod,
3373         NULL
3374 };
3375
3376 /* 3430ES1-only hwmods */
3377 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3378         &omap3430es1_dss_core_hwmod,
3379         NULL
3380 };
3381
3382 /* 3430ES2+-only hwmods */
3383 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3384         &omap3xxx_dss_core_hwmod,
3385         &omap3xxx_usbhsotg_hwmod,
3386         NULL
3387 };
3388
3389 /* <= 3430ES3-only hwmods */
3390 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3391         &omap3xxx_pre_es3_mmc1_hwmod,
3392         &omap3xxx_pre_es3_mmc2_hwmod,
3393         NULL
3394 };
3395
3396 /* 3430ES3+-only hwmods */
3397 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3398         &omap3xxx_es3plus_mmc1_hwmod,
3399         &omap3xxx_es3plus_mmc2_hwmod,
3400         NULL
3401 };
3402
3403 /* 34xx-only hwmods (all ES revisions) */
3404 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3405         &omap3xxx_iva_hwmod,
3406         &omap34xx_sr1_hwmod,
3407         &omap34xx_sr2_hwmod,
3408         &omap3xxx_mailbox_hwmod,
3409         NULL
3410 };
3411
3412 /* 36xx-only hwmods (all ES revisions) */
3413 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3414         &omap3xxx_iva_hwmod,
3415         &omap3xxx_uart4_hwmod,
3416         &omap3xxx_dss_core_hwmod,
3417         &omap36xx_sr1_hwmod,
3418         &omap36xx_sr2_hwmod,
3419         &omap3xxx_usbhsotg_hwmod,
3420         &omap3xxx_mailbox_hwmod,
3421         &omap3xxx_es3plus_mmc1_hwmod,
3422         &omap3xxx_es3plus_mmc2_hwmod,
3423         NULL
3424 };
3425
3426 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3427         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3428         &am35xx_usbhsotg_hwmod,
3429         &omap3xxx_es3plus_mmc1_hwmod,
3430         &omap3xxx_es3plus_mmc2_hwmod,
3431         NULL
3432 };
3433
3434 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3435         /* dss class */
3436         &omap3xxx_dss_dispc_hwmod,
3437         &omap3xxx_dss_dsi1_hwmod,
3438         &omap3xxx_dss_rfbi_hwmod,
3439         &omap3xxx_dss_venc_hwmod,
3440         NULL
3441 };
3442
3443 int __init omap3xxx_hwmod_init(void)
3444 {
3445         int r;
3446         struct omap_hwmod **h = NULL;
3447         unsigned int rev;
3448
3449         /* Register hwmods common to all OMAP3 */
3450         r = omap_hwmod_register(omap3xxx_hwmods);
3451         if (r < 0)
3452                 return r;
3453
3454         /* Register GP-only hwmods. */
3455         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3456                 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3457                 if (r < 0)
3458                         return r;
3459         }
3460
3461         rev = omap_rev();
3462
3463         /*
3464          * Register hwmods common to individual OMAP3 families, all
3465          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3466          * All possible revisions should be included in this conditional.
3467          */
3468         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3469             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3470             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3471                 h = omap34xx_hwmods;
3472         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3473                 h = am35xx_hwmods;
3474         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3475                    rev == OMAP3630_REV_ES1_2) {
3476                 h = omap36xx_hwmods;
3477         } else {
3478                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3479                 return -EINVAL;
3480         };
3481
3482         r = omap_hwmod_register(h);
3483         if (r < 0)
3484                 return r;
3485
3486         /*
3487          * Register hwmods specific to certain ES levels of a
3488          * particular family of silicon (e.g., 34xx ES1.0)
3489          */
3490         h = NULL;
3491         if (rev == OMAP3430_REV_ES1_0) {
3492                 h = omap3430es1_hwmods;
3493         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3494                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3495                    rev == OMAP3430_REV_ES3_1_2) {
3496                 h = omap3430es2plus_hwmods;
3497         };
3498
3499         if (h) {
3500                 r = omap_hwmod_register(h);
3501                 if (r < 0)
3502                         return r;
3503         }
3504
3505         h = NULL;
3506         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3507             rev == OMAP3430_REV_ES2_1) {
3508                 h = omap3430_pre_es3_hwmods;
3509         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3510                    rev == OMAP3430_REV_ES3_1_2) {
3511                 h = omap3430_es3plus_hwmods;
3512         };
3513
3514         if (h)
3515                 r = omap_hwmod_register(h);
3516         if (r < 0)
3517                 return r;
3518
3519         /*
3520          * DSS code presumes that dss_core hwmod is handled first,
3521          * _before_ any other DSS related hwmods so register common
3522          * DSS hwmods last to ensure that dss_core is already registered.
3523          * Otherwise some change things may happen, for ex. if dispc
3524          * is handled before dss_core and DSS is enabled in bootloader
3525          * DIPSC will be reset with outputs enabled which sometimes leads
3526          * to unrecoverable L3 error.
3527          */
3528         r = omap_hwmod_register(omap3xxx_dss_hwmods);
3529
3530         return r;
3531 }