arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 163 static struct omap_hwmod omap3xxx_uart1_hwmod;
 164 static struct omap_hwmod omap3xxx_uart2_hwmod;
 165 static struct omap_hwmod omap3xxx_uart3_hwmod;
 166 static struct omap_hwmod omap3xxx_uart4_hwmod;
 167 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 168
 169 /* l3_core -> usbhsotg interface */
 170 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 171         .master         = &omap3xxx_usbhsotg_hwmod,
 172         .slave          = &omap3xxx_l3_main_hwmod,
 173         .clk            = "core_l3_ick",
 174         .user           = OCP_USER_MPU,
 175 };
 176
 177 /* l3_core -> am35xx_usbhsotg interface */
 178 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 179         .master         = &am35xx_usbhsotg_hwmod,
 180         .slave          = &omap3xxx_l3_main_hwmod,
 181         .clk            = "core_l3_ick",
 182         .user           = OCP_USER_MPU,
 183 };
 184 /* L4_CORE -> L4_WKUP interface */
 185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 186         .master = &omap3xxx_l4_core_hwmod,
 187         .slave  = &omap3xxx_l4_wkup_hwmod,
 188         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 189 };
 190
 191 /* L4 CORE -> MMC1 interface */
 192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 193         .master         = &omap3xxx_l4_core_hwmod,
 194         .slave          = &omap3xxx_mmc1_hwmod,
 195         .clk            = "mmchs1_ick",
 196         .addr           = omap2430_mmc1_addr_space,
 197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 198         .flags          = OMAP_FIREWALL_L4
 199 };
 200
 201 /* L4 CORE -> MMC2 interface */
 202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 203         .master         = &omap3xxx_l4_core_hwmod,
 204         .slave          = &omap3xxx_mmc2_hwmod,
 205         .clk            = "mmchs2_ick",
 206         .addr           = omap2430_mmc2_addr_space,
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208         .flags          = OMAP_FIREWALL_L4
 209 };
 210
 211 /* L4 CORE -> MMC3 interface */
 212 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 213         {
 214                 .pa_start       = 0x480ad000,
 215                 .pa_end         = 0x480ad1ff,
 216                 .flags          = ADDR_TYPE_RT,
 217         },
 218         { }
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_mmc3_hwmod,
 224         .clk            = "mmchs3_ick",
 225         .addr           = omap3xxx_mmc3_addr_space,
 226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 227         .flags          = OMAP_FIREWALL_L4
 228 };
 229
 230 /* L4 CORE -> UART1 interface */
 231 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 232         {
 233                 .pa_start       = OMAP3_UART1_BASE,
 234                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 235                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 236         },
 237         { }
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 241         .master         = &omap3xxx_l4_core_hwmod,
 242         .slave          = &omap3xxx_uart1_hwmod,
 243         .clk            = "uart1_ick",
 244         .addr           = omap3xxx_uart1_addr_space,
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246 };
 247
 248 /* L4 CORE -> UART2 interface */
 249 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 250         {
 251                 .pa_start       = OMAP3_UART2_BASE,
 252                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 253                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 254         },
 255         { }
 256 };
 257
 258 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 259         .master         = &omap3xxx_l4_core_hwmod,
 260         .slave          = &omap3xxx_uart2_hwmod,
 261         .clk            = "uart2_ick",
 262         .addr           = omap3xxx_uart2_addr_space,
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* L4 PER -> UART3 interface */
 267 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 268         {
 269                 .pa_start       = OMAP3_UART3_BASE,
 270                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 271                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 272         },
 273         { }
 274 };
 275
 276 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 277         .master         = &omap3xxx_l4_per_hwmod,
 278         .slave          = &omap3xxx_uart3_hwmod,
 279         .clk            = "uart3_ick",
 280         .addr           = omap3xxx_uart3_addr_space,
 281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 282 };
 283
 284 /* L4 PER -> UART4 interface */
 285 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 286         {
 287                 .pa_start       = OMAP3_UART4_BASE,
 288                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 289                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 290         },
 291         { }
 292 };
 293
 294 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 295         .master         = &omap3xxx_l4_per_hwmod,
 296         .slave          = &omap3xxx_uart4_hwmod,
 297         .clk            = "uart4_ick",
 298         .addr           = omap3xxx_uart4_addr_space,
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* L4 CORE -> I2C1 interface */
 303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 304         .master         = &omap3xxx_l4_core_hwmod,
 305         .slave          = &omap3xxx_i2c1_hwmod,
 306         .clk            = "i2c1_ick",
 307         .addr           = omap2_i2c1_addr_space,
 308         .fw = {
 309                 .omap2 = {
 310                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 311                         .l4_prot_group = 7,
 312                         .flags  = OMAP_FIREWALL_L4,
 313                 }
 314         },
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* L4 CORE -> I2C2 interface */
 319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 320         .master         = &omap3xxx_l4_core_hwmod,
 321         .slave          = &omap3xxx_i2c2_hwmod,
 322         .clk            = "i2c2_ick",
 323         .addr           = omap2_i2c2_addr_space,
 324         .fw = {
 325                 .omap2 = {
 326                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 327                         .l4_prot_group = 7,
 328                         .flags = OMAP_FIREWALL_L4,
 329                 }
 330         },
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* L4 CORE -> I2C3 interface */
 335 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 336         {
 337                 .pa_start       = 0x48060000,
 338                 .pa_end         = 0x48060000 + SZ_128 - 1,
 339                 .flags          = ADDR_TYPE_RT,
 340         },
 341         { }
 342 };
 343
 344 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 345         .master         = &omap3xxx_l4_core_hwmod,
 346         .slave          = &omap3xxx_i2c3_hwmod,
 347         .clk            = "i2c3_ick",
 348         .addr           = omap3xxx_i2c3_addr_space,
 349         .fw = {
 350                 .omap2 = {
 351                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 352                         .l4_prot_group = 7,
 353                         .flags = OMAP_FIREWALL_L4,
 354                 }
 355         },
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* L4 CORE -> SR1 interface */
 360 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 361         {
 362                 .pa_start       = OMAP34XX_SR1_BASE,
 363                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 364                 .flags          = ADDR_TYPE_RT,
 365         },
 366         { }
 367 };
 368
 369 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 370         .master         = &omap3xxx_l4_core_hwmod,
 371         .slave          = &omap34xx_sr1_hwmod,
 372         .clk            = "sr_l4_ick",
 373         .addr           = omap3_sr1_addr_space,
 374         .user           = OCP_USER_MPU,
 375 };
 376
 377 /* L4 CORE -> SR1 interface */
 378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 379         {
 380                 .pa_start       = OMAP34XX_SR2_BASE,
 381                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 382                 .flags          = ADDR_TYPE_RT,
 383         },
 384         { }
 385 };
 386
 387 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 388         .master         = &omap3xxx_l4_core_hwmod,
 389         .slave          = &omap34xx_sr2_hwmod,
 390         .clk            = "sr_l4_ick",
 391         .addr           = omap3_sr2_addr_space,
 392         .user           = OCP_USER_MPU,
 393 };
 394
 395 /*
 396 * usbhsotg interface data
 397 */
 398
 399 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 400         {
 401                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 402                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 403                 .flags          = ADDR_TYPE_RT
 404         },
 405         { }
 406 };
 407
 408 /* l4_core -> usbhsotg  */
 409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 410         .master         = &omap3xxx_l4_core_hwmod,
 411         .slave          = &omap3xxx_usbhsotg_hwmod,
 412         .clk            = "l4_ick",
 413         .addr           = omap3xxx_usbhsotg_addrs,
 414         .user           = OCP_USER_MPU,
 415 };
 416
 417 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 418         &omap3xxx_usbhsotg__l3,
 419 };
 420
 421 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 422         &omap3xxx_l4_core__usbhsotg,
 423 };
 424
 425 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 426         {
 427                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 428                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 429                 .flags          = ADDR_TYPE_RT
 430         },
 431         { }
 432 };
 433
 434 /* l4_core -> usbhsotg  */
 435 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 436         .master         = &omap3xxx_l4_core_hwmod,
 437         .slave          = &am35xx_usbhsotg_hwmod,
 438         .clk            = "l4_ick",
 439         .addr           = am35xx_usbhsotg_addrs,
 440         .user           = OCP_USER_MPU,
 441 };
 442
 443 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 444         &am35xx_usbhsotg__l3,
 445 };
 446
 447 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 448         &am35xx_l4_core__usbhsotg,
 449 };
 450 /* Slave interfaces on the L4_CORE interconnect */
 451 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 452         &omap3xxx_l3_main__l4_core,
 453 };
 454
 455 /* L4 CORE */
 456 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 457         .name           = "l4_core",
 458         .class          = &l4_hwmod_class,
 459         .slaves         = omap3xxx_l4_core_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 461         .flags          = HWMOD_NO_IDLEST,
 462 };
 463
 464 /* Slave interfaces on the L4_PER interconnect */
 465 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 466         &omap3xxx_l3_main__l4_per,
 467 };
 468
 469 /* L4 PER */
 470 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 471         .name           = "l4_per",
 472         .class          = &l4_hwmod_class,
 473         .slaves         = omap3xxx_l4_per_slaves,
 474         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 475         .flags          = HWMOD_NO_IDLEST,
 476 };
 477
 478 /* Slave interfaces on the L4_WKUP interconnect */
 479 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 480         &omap3xxx_l4_core__l4_wkup,
 481 };
 482
 483 /* L4 WKUP */
 484 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 485         .name           = "l4_wkup",
 486         .class          = &l4_hwmod_class,
 487         .slaves         = omap3xxx_l4_wkup_slaves,
 488         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 489         .flags          = HWMOD_NO_IDLEST,
 490 };
 491
 492 /* Master interfaces on the MPU device */
 493 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 494         &omap3xxx_mpu__l3_main,
 495 };
 496
 497 /* MPU */
 498 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 499         .name           = "mpu",
 500         .class          = &mpu_hwmod_class,
 501         .main_clk       = "arm_fck",
 502         .masters        = omap3xxx_mpu_masters,
 503         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 504 };
 505
 506 /*
 507  * IVA2_2 interface data
 508  */
 509
 510 /* IVA2 <- L3 interface */
 511 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 512         .master         = &omap3xxx_l3_main_hwmod,
 513         .slave          = &omap3xxx_iva_hwmod,
 514         .clk            = "iva2_ck",
 515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 516 };
 517
 518 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 519         &omap3xxx_l3__iva,
 520 };
 521
 522 /*
 523  * IVA2 (IVA2)
 524  */
 525
 526 static struct omap_hwmod omap3xxx_iva_hwmod = {
 527         .name           = "iva",
 528         .class          = &iva_hwmod_class,
 529         .masters        = omap3xxx_iva_masters,
 530         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 531 };
 532
 533 /* timer class */
 534 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x0010,
 537         .syss_offs      = 0x0014,
 538         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 539                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 540                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 546         .name = "timer",
 547         .sysc = &omap3xxx_timer_1ms_sysc,
 548         .rev = OMAP_TIMER_IP_VERSION_1,
 549 };
 550
 551 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 556                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 557         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 558         .sysc_fields    = &omap_hwmod_sysc_type1,
 559 };
 560
 561 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 562         .name = "timer",
 563         .sysc = &omap3xxx_timer_sysc,
 564         .rev =  OMAP_TIMER_IP_VERSION_1,
 565 };
 566
 567 /* timer1 */
 568 static struct omap_hwmod omap3xxx_timer1_hwmod;
 569
 570 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 571         {
 572                 .pa_start       = 0x48318000,
 573                 .pa_end         = 0x48318000 + SZ_1K - 1,
 574                 .flags          = ADDR_TYPE_RT
 575         },
 576         { }
 577 };
 578
 579 /* l4_wkup -> timer1 */
 580 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 581         .master         = &omap3xxx_l4_wkup_hwmod,
 582         .slave          = &omap3xxx_timer1_hwmod,
 583         .clk            = "gpt1_ick",
 584         .addr           = omap3xxx_timer1_addrs,
 585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 586 };
 587
 588 /* timer1 slave port */
 589 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 590         &omap3xxx_l4_wkup__timer1,
 591 };
 592
 593 /* timer1 hwmod */
 594 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 595         .name           = "timer1",
 596         .mpu_irqs       = omap2_timer1_mpu_irqs,
 597         .main_clk       = "gpt1_fck",
 598         .prcm           = {
 599                 .omap2 = {
 600                         .prcm_reg_id = 1,
 601                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 602                         .module_offs = WKUP_MOD,
 603                         .idlest_reg_id = 1,
 604                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 605                 },
 606         },
 607         .slaves         = omap3xxx_timer1_slaves,
 608         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 609         .class          = &omap3xxx_timer_1ms_hwmod_class,
 610 };
 611
 612 /* timer2 */
 613 static struct omap_hwmod omap3xxx_timer2_hwmod;
 614
 615 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 616         {
 617                 .pa_start       = 0x49032000,
 618                 .pa_end         = 0x49032000 + SZ_1K - 1,
 619                 .flags          = ADDR_TYPE_RT
 620         },
 621         { }
 622 };
 623
 624 /* l4_per -> timer2 */
 625 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 626         .master         = &omap3xxx_l4_per_hwmod,
 627         .slave          = &omap3xxx_timer2_hwmod,
 628         .clk            = "gpt2_ick",
 629         .addr           = omap3xxx_timer2_addrs,
 630         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 631 };
 632
 633 /* timer2 slave port */
 634 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 635         &omap3xxx_l4_per__timer2,
 636 };
 637
 638 /* timer2 hwmod */
 639 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 640         .name           = "timer2",
 641         .mpu_irqs       = omap2_timer2_mpu_irqs,
 642         .main_clk       = "gpt2_fck",
 643         .prcm           = {
 644                 .omap2 = {
 645                         .prcm_reg_id = 1,
 646                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 647                         .module_offs = OMAP3430_PER_MOD,
 648                         .idlest_reg_id = 1,
 649                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 650                 },
 651         },
 652         .slaves         = omap3xxx_timer2_slaves,
 653         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 654         .class          = &omap3xxx_timer_1ms_hwmod_class,
 655 };
 656
 657 /* timer3 */
 658 static struct omap_hwmod omap3xxx_timer3_hwmod;
 659
 660 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 661         {
 662                 .pa_start       = 0x49034000,
 663                 .pa_end         = 0x49034000 + SZ_1K - 1,
 664                 .flags          = ADDR_TYPE_RT
 665         },
 666         { }
 667 };
 668
 669 /* l4_per -> timer3 */
 670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 671         .master         = &omap3xxx_l4_per_hwmod,
 672         .slave          = &omap3xxx_timer3_hwmod,
 673         .clk            = "gpt3_ick",
 674         .addr           = omap3xxx_timer3_addrs,
 675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 676 };
 677
 678 /* timer3 slave port */
 679 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 680         &omap3xxx_l4_per__timer3,
 681 };
 682
 683 /* timer3 hwmod */
 684 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 685         .name           = "timer3",
 686         .mpu_irqs       = omap2_timer3_mpu_irqs,
 687         .main_clk       = "gpt3_fck",
 688         .prcm           = {
 689                 .omap2 = {
 690                         .prcm_reg_id = 1,
 691                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 692                         .module_offs = OMAP3430_PER_MOD,
 693                         .idlest_reg_id = 1,
 694                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 695                 },
 696         },
 697         .slaves         = omap3xxx_timer3_slaves,
 698         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 699         .class          = &omap3xxx_timer_hwmod_class,
 700 };
 701
 702 /* timer4 */
 703 static struct omap_hwmod omap3xxx_timer4_hwmod;
 704
 705 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 706         {
 707                 .pa_start       = 0x49036000,
 708                 .pa_end         = 0x49036000 + SZ_1K - 1,
 709                 .flags          = ADDR_TYPE_RT
 710         },
 711         { }
 712 };
 713
 714 /* l4_per -> timer4 */
 715 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 716         .master         = &omap3xxx_l4_per_hwmod,
 717         .slave          = &omap3xxx_timer4_hwmod,
 718         .clk            = "gpt4_ick",
 719         .addr           = omap3xxx_timer4_addrs,
 720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 721 };
 722
 723 /* timer4 slave port */
 724 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 725         &omap3xxx_l4_per__timer4,
 726 };
 727
 728 /* timer4 hwmod */
 729 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 730         .name           = "timer4",
 731         .mpu_irqs       = omap2_timer4_mpu_irqs,
 732         .main_clk       = "gpt4_fck",
 733         .prcm           = {
 734                 .omap2 = {
 735                         .prcm_reg_id = 1,
 736                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 737                         .module_offs = OMAP3430_PER_MOD,
 738                         .idlest_reg_id = 1,
 739                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 740                 },
 741         },
 742         .slaves         = omap3xxx_timer4_slaves,
 743         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 744         .class          = &omap3xxx_timer_hwmod_class,
 745 };
 746
 747 /* timer5 */
 748 static struct omap_hwmod omap3xxx_timer5_hwmod;
 749
 750 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 751         {
 752                 .pa_start       = 0x49038000,
 753                 .pa_end         = 0x49038000 + SZ_1K - 1,
 754                 .flags          = ADDR_TYPE_RT
 755         },
 756         { }
 757 };
 758
 759 /* l4_per -> timer5 */
 760 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 761         .master         = &omap3xxx_l4_per_hwmod,
 762         .slave          = &omap3xxx_timer5_hwmod,
 763         .clk            = "gpt5_ick",
 764         .addr           = omap3xxx_timer5_addrs,
 765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 766 };
 767
 768 /* timer5 slave port */
 769 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 770         &omap3xxx_l4_per__timer5,
 771 };
 772
 773 /* timer5 hwmod */
 774 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 775         .name           = "timer5",
 776         .mpu_irqs       = omap2_timer5_mpu_irqs,
 777         .main_clk       = "gpt5_fck",
 778         .prcm           = {
 779                 .omap2 = {
 780                         .prcm_reg_id = 1,
 781                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 782                         .module_offs = OMAP3430_PER_MOD,
 783                         .idlest_reg_id = 1,
 784                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 785                 },
 786         },
 787         .slaves         = omap3xxx_timer5_slaves,
 788         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 789         .class          = &omap3xxx_timer_hwmod_class,
 790 };
 791
 792 /* timer6 */
 793 static struct omap_hwmod omap3xxx_timer6_hwmod;
 794
 795 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 796         {
 797                 .pa_start       = 0x4903A000,
 798                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 799                 .flags          = ADDR_TYPE_RT
 800         },
 801         { }
 802 };
 803
 804 /* l4_per -> timer6 */
 805 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 806         .master         = &omap3xxx_l4_per_hwmod,
 807         .slave          = &omap3xxx_timer6_hwmod,
 808         .clk            = "gpt6_ick",
 809         .addr           = omap3xxx_timer6_addrs,
 810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 811 };
 812
 813 /* timer6 slave port */
 814 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 815         &omap3xxx_l4_per__timer6,
 816 };
 817
 818 /* timer6 hwmod */
 819 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 820         .name           = "timer6",
 821         .mpu_irqs       = omap2_timer6_mpu_irqs,
 822         .main_clk       = "gpt6_fck",
 823         .prcm           = {
 824                 .omap2 = {
 825                         .prcm_reg_id = 1,
 826                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 827                         .module_offs = OMAP3430_PER_MOD,
 828                         .idlest_reg_id = 1,
 829                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 830                 },
 831         },
 832         .slaves         = omap3xxx_timer6_slaves,
 833         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 834         .class          = &omap3xxx_timer_hwmod_class,
 835 };
 836
 837 /* timer7 */
 838 static struct omap_hwmod omap3xxx_timer7_hwmod;
 839
 840 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 841         {
 842                 .pa_start       = 0x4903C000,
 843                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 844                 .flags          = ADDR_TYPE_RT
 845         },
 846         { }
 847 };
 848
 849 /* l4_per -> timer7 */
 850 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 851         .master         = &omap3xxx_l4_per_hwmod,
 852         .slave          = &omap3xxx_timer7_hwmod,
 853         .clk            = "gpt7_ick",
 854         .addr           = omap3xxx_timer7_addrs,
 855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 856 };
 857
 858 /* timer7 slave port */
 859 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 860         &omap3xxx_l4_per__timer7,
 861 };
 862
 863 /* timer7 hwmod */
 864 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 865         .name           = "timer7",
 866         .mpu_irqs       = omap2_timer7_mpu_irqs,
 867         .main_clk       = "gpt7_fck",
 868         .prcm           = {
 869                 .omap2 = {
 870                         .prcm_reg_id = 1,
 871                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 872                         .module_offs = OMAP3430_PER_MOD,
 873                         .idlest_reg_id = 1,
 874                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 875                 },
 876         },
 877         .slaves         = omap3xxx_timer7_slaves,
 878         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 879         .class          = &omap3xxx_timer_hwmod_class,
 880 };
 881
 882 /* timer8 */
 883 static struct omap_hwmod omap3xxx_timer8_hwmod;
 884
 885 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 886         {
 887                 .pa_start       = 0x4903E000,
 888                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 889                 .flags          = ADDR_TYPE_RT
 890         },
 891         { }
 892 };
 893
 894 /* l4_per -> timer8 */
 895 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 896         .master         = &omap3xxx_l4_per_hwmod,
 897         .slave          = &omap3xxx_timer8_hwmod,
 898         .clk            = "gpt8_ick",
 899         .addr           = omap3xxx_timer8_addrs,
 900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 901 };
 902
 903 /* timer8 slave port */
 904 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 905         &omap3xxx_l4_per__timer8,
 906 };
 907
 908 /* timer8 hwmod */
 909 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 910         .name           = "timer8",
 911         .mpu_irqs       = omap2_timer8_mpu_irqs,
 912         .main_clk       = "gpt8_fck",
 913         .prcm           = {
 914                 .omap2 = {
 915                         .prcm_reg_id = 1,
 916                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 917                         .module_offs = OMAP3430_PER_MOD,
 918                         .idlest_reg_id = 1,
 919                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 920                 },
 921         },
 922         .slaves         = omap3xxx_timer8_slaves,
 923         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 924         .class          = &omap3xxx_timer_hwmod_class,
 925 };
 926
 927 /* timer9 */
 928 static struct omap_hwmod omap3xxx_timer9_hwmod;
 929
 930 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 931         {
 932                 .pa_start       = 0x49040000,
 933                 .pa_end         = 0x49040000 + SZ_1K - 1,
 934                 .flags          = ADDR_TYPE_RT
 935         },
 936         { }
 937 };
 938
 939 /* l4_per -> timer9 */
 940 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 941         .master         = &omap3xxx_l4_per_hwmod,
 942         .slave          = &omap3xxx_timer9_hwmod,
 943         .clk            = "gpt9_ick",
 944         .addr           = omap3xxx_timer9_addrs,
 945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 946 };
 947
 948 /* timer9 slave port */
 949 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 950         &omap3xxx_l4_per__timer9,
 951 };
 952
 953 /* timer9 hwmod */
 954 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 955         .name           = "timer9",
 956         .mpu_irqs       = omap2_timer9_mpu_irqs,
 957         .main_clk       = "gpt9_fck",
 958         .prcm           = {
 959                 .omap2 = {
 960                         .prcm_reg_id = 1,
 961                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 962                         .module_offs = OMAP3430_PER_MOD,
 963                         .idlest_reg_id = 1,
 964                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 965                 },
 966         },
 967         .slaves         = omap3xxx_timer9_slaves,
 968         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 969         .class          = &omap3xxx_timer_hwmod_class,
 970 };
 971
 972 /* timer10 */
 973 static struct omap_hwmod omap3xxx_timer10_hwmod;
 974
 975 /* l4_core -> timer10 */
 976 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
 977         .master         = &omap3xxx_l4_core_hwmod,
 978         .slave          = &omap3xxx_timer10_hwmod,
 979         .clk            = "gpt10_ick",
 980         .addr           = omap2_timer10_addrs,
 981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 982 };
 983
 984 /* timer10 slave port */
 985 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
 986         &omap3xxx_l4_core__timer10,
 987 };
 988
 989 /* timer10 hwmod */
 990 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 991         .name           = "timer10",
 992         .mpu_irqs       = omap2_timer10_mpu_irqs,
 993         .main_clk       = "gpt10_fck",
 994         .prcm           = {
 995                 .omap2 = {
 996                         .prcm_reg_id = 1,
 997                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 998                         .module_offs = CORE_MOD,
 999                         .idlest_reg_id = 1,
1000                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1001                 },
1002         },
1003         .slaves         = omap3xxx_timer10_slaves,
1004         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1005         .class          = &omap3xxx_timer_1ms_hwmod_class,
1006 };
1007
1008 /* timer11 */
1009 static struct omap_hwmod omap3xxx_timer11_hwmod;
1010
1011 /* l4_core -> timer11 */
1012 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1013         .master         = &omap3xxx_l4_core_hwmod,
1014         .slave          = &omap3xxx_timer11_hwmod,
1015         .clk            = "gpt11_ick",
1016         .addr           = omap2_timer11_addrs,
1017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1018 };
1019
1020 /* timer11 slave port */
1021 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1022         &omap3xxx_l4_core__timer11,
1023 };
1024
1025 /* timer11 hwmod */
1026 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1027         .name           = "timer11",
1028         .mpu_irqs       = omap2_timer11_mpu_irqs,
1029         .main_clk       = "gpt11_fck",
1030         .prcm           = {
1031                 .omap2 = {
1032                         .prcm_reg_id = 1,
1033                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1034                         .module_offs = CORE_MOD,
1035                         .idlest_reg_id = 1,
1036                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1037                 },
1038         },
1039         .slaves         = omap3xxx_timer11_slaves,
1040         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1041         .class          = &omap3xxx_timer_hwmod_class,
1042 };
1043
1044 /* timer12*/
1045 static struct omap_hwmod omap3xxx_timer12_hwmod;
1046 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1047         { .irq = 95, },
1048         { .irq = -1 }
1049 };
1050
1051 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1052         {
1053                 .pa_start       = 0x48304000,
1054                 .pa_end         = 0x48304000 + SZ_1K - 1,
1055                 .flags          = ADDR_TYPE_RT
1056         },
1057         { }
1058 };
1059
1060 /* l4_core -> timer12 */
1061 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1062         .master         = &omap3xxx_l4_core_hwmod,
1063         .slave          = &omap3xxx_timer12_hwmod,
1064         .clk            = "gpt12_ick",
1065         .addr           = omap3xxx_timer12_addrs,
1066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1067 };
1068
1069 /* timer12 slave port */
1070 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1071         &omap3xxx_l4_core__timer12,
1072 };
1073
1074 /* timer12 hwmod */
1075 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1076         .name           = "timer12",
1077         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1078         .main_clk       = "gpt12_fck",
1079         .prcm           = {
1080                 .omap2 = {
1081                         .prcm_reg_id = 1,
1082                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1083                         .module_offs = WKUP_MOD,
1084                         .idlest_reg_id = 1,
1085                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1086                 },
1087         },
1088         .slaves         = omap3xxx_timer12_slaves,
1089         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1090         .class          = &omap3xxx_timer_hwmod_class,
1091 };
1092
1093 /* l4_wkup -> wd_timer2 */
1094 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1095         {
1096                 .pa_start       = 0x48314000,
1097                 .pa_end         = 0x4831407f,
1098                 .flags          = ADDR_TYPE_RT
1099         },
1100         { }
1101 };
1102
1103 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1104         .master         = &omap3xxx_l4_wkup_hwmod,
1105         .slave          = &omap3xxx_wd_timer2_hwmod,
1106         .clk            = "wdt2_ick",
1107         .addr           = omap3xxx_wd_timer2_addrs,
1108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1109 };
1110
1111 /*
1112  * 'wd_timer' class
1113  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1114  * overflow condition
1115  */
1116
1117 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1118         .rev_offs       = 0x0000,
1119         .sysc_offs      = 0x0010,
1120         .syss_offs      = 0x0014,
1121         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1122                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1123                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1124                            SYSS_HAS_RESET_STATUS),
1125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1126         .sysc_fields    = &omap_hwmod_sysc_type1,
1127 };
1128
1129 /* I2C common */
1130 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1131         .rev_offs       = 0x00,
1132         .sysc_offs      = 0x20,
1133         .syss_offs      = 0x10,
1134         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1135                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1136                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1137         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1138         .sysc_fields    = &omap_hwmod_sysc_type1,
1139 };
1140
1141 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1142         .name           = "wd_timer",
1143         .sysc           = &omap3xxx_wd_timer_sysc,
1144         .pre_shutdown   = &omap2_wd_timer_disable
1145 };
1146
1147 /* wd_timer2 */
1148 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1149         &omap3xxx_l4_wkup__wd_timer2,
1150 };
1151
1152 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1153         .name           = "wd_timer2",
1154         .class          = &omap3xxx_wd_timer_hwmod_class,
1155         .main_clk       = "wdt2_fck",
1156         .prcm           = {
1157                 .omap2 = {
1158                         .prcm_reg_id = 1,
1159                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1160                         .module_offs = WKUP_MOD,
1161                         .idlest_reg_id = 1,
1162                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1163                 },
1164         },
1165         .slaves         = omap3xxx_wd_timer2_slaves,
1166         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1167         /*
1168          * XXX: Use software supervised mode, HW supervised smartidle seems to
1169          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1170          */
1171         .flags          = HWMOD_SWSUP_SIDLE,
1172 };
1173
1174 /* UART1 */
1175
1176 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1177         &omap3_l4_core__uart1,
1178 };
1179
1180 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1181         .name           = "uart1",
1182         .mpu_irqs       = omap2_uart1_mpu_irqs,
1183         .sdma_reqs      = omap2_uart1_sdma_reqs,
1184         .main_clk       = "uart1_fck",
1185         .prcm           = {
1186                 .omap2 = {
1187                         .module_offs = CORE_MOD,
1188                         .prcm_reg_id = 1,
1189                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1190                         .idlest_reg_id = 1,
1191                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1192                 },
1193         },
1194         .slaves         = omap3xxx_uart1_slaves,
1195         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1196         .class          = &omap2_uart_class,
1197 };
1198
1199 /* UART2 */
1200
1201 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1202         &omap3_l4_core__uart2,
1203 };
1204
1205 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1206         .name           = "uart2",
1207         .mpu_irqs       = omap2_uart2_mpu_irqs,
1208         .sdma_reqs      = omap2_uart2_sdma_reqs,
1209         .main_clk       = "uart2_fck",
1210         .prcm           = {
1211                 .omap2 = {
1212                         .module_offs = CORE_MOD,
1213                         .prcm_reg_id = 1,
1214                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1215                         .idlest_reg_id = 1,
1216                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1217                 },
1218         },
1219         .slaves         = omap3xxx_uart2_slaves,
1220         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1221         .class          = &omap2_uart_class,
1222 };
1223
1224 /* UART3 */
1225
1226 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1227         &omap3_l4_per__uart3,
1228 };
1229
1230 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1231         .name           = "uart3",
1232         .mpu_irqs       = omap2_uart3_mpu_irqs,
1233         .sdma_reqs      = omap2_uart3_sdma_reqs,
1234         .main_clk       = "uart3_fck",
1235         .prcm           = {
1236                 .omap2 = {
1237                         .module_offs = OMAP3430_PER_MOD,
1238                         .prcm_reg_id = 1,
1239                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1240                         .idlest_reg_id = 1,
1241                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1242                 },
1243         },
1244         .slaves         = omap3xxx_uart3_slaves,
1245         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1246         .class          = &omap2_uart_class,
1247 };
1248
1249 /* UART4 */
1250
1251 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1252         { .irq = INT_36XX_UART4_IRQ, },
1253         { .irq = -1 }
1254 };
1255
1256 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1257         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1258         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1259         { .dma_req = -1 }
1260 };
1261
1262 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1263         &omap3_l4_per__uart4,
1264 };
1265
1266 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1267         .name           = "uart4",
1268         .mpu_irqs       = uart4_mpu_irqs,
1269         .sdma_reqs      = uart4_sdma_reqs,
1270         .main_clk       = "uart4_fck",
1271         .prcm           = {
1272                 .omap2 = {
1273                         .module_offs = OMAP3430_PER_MOD,
1274                         .prcm_reg_id = 1,
1275                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1276                         .idlest_reg_id = 1,
1277                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1278                 },
1279         },
1280         .slaves         = omap3xxx_uart4_slaves,
1281         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1282         .class          = &omap2_uart_class,
1283 };
1284
1285 static struct omap_hwmod_class i2c_class = {
1286         .name   = "i2c",
1287         .sysc   = &i2c_sysc,
1288         .rev    = OMAP_I2C_IP_VERSION_1,
1289         .reset  = &omap_i2c_reset,
1290 };
1291
1292 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1293         { .name = "dispc", .dma_req = 5 },
1294         { .name = "dsi1", .dma_req = 74 },
1295         { .dma_req = -1 }
1296 };
1297
1298 /* dss */
1299 /* dss master ports */
1300 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1301         &omap3xxx_dss__l3,
1302 };
1303
1304 /* l4_core -> dss */
1305 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1306         .master         = &omap3xxx_l4_core_hwmod,
1307         .slave          = &omap3430es1_dss_core_hwmod,
1308         .clk            = "dss_ick",
1309         .addr           = omap2_dss_addrs,
1310         .fw = {
1311                 .omap2 = {
1312                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1313                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1314                         .flags  = OMAP_FIREWALL_L4,
1315                 }
1316         },
1317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1318 };
1319
1320 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1321         .master         = &omap3xxx_l4_core_hwmod,
1322         .slave          = &omap3xxx_dss_core_hwmod,
1323         .clk            = "dss_ick",
1324         .addr           = omap2_dss_addrs,
1325         .fw = {
1326                 .omap2 = {
1327                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1328                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1329                         .flags  = OMAP_FIREWALL_L4,
1330                 }
1331         },
1332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1333 };
1334
1335 /* dss slave ports */
1336 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1337         &omap3430es1_l4_core__dss,
1338 };
1339
1340 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1341         &omap3xxx_l4_core__dss,
1342 };
1343
1344 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1345         { .role = "tv_clk", .clk = "dss_tv_fck" },
1346         { .role = "video_clk", .clk = "dss_96m_fck" },
1347         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1348 };
1349
1350 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1351         .name           = "dss_core",
1352         .class          = &omap2_dss_hwmod_class,
1353         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1354         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1355         .prcm           = {
1356                 .omap2 = {
1357                         .prcm_reg_id = 1,
1358                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1359                         .module_offs = OMAP3430_DSS_MOD,
1360                         .idlest_reg_id = 1,
1361                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1362                 },
1363         },
1364         .opt_clks       = dss_opt_clks,
1365         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1366         .slaves         = omap3430es1_dss_slaves,
1367         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1368         .masters        = omap3xxx_dss_masters,
1369         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1370         .flags          = HWMOD_NO_IDLEST,
1371 };
1372
1373 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1374         .name           = "dss_core",
1375         .class          = &omap2_dss_hwmod_class,
1376         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1377         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1378         .prcm           = {
1379                 .omap2 = {
1380                         .prcm_reg_id = 1,
1381                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1382                         .module_offs = OMAP3430_DSS_MOD,
1383                         .idlest_reg_id = 1,
1384                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1385                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1386                 },
1387         },
1388         .opt_clks       = dss_opt_clks,
1389         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1390         .slaves         = omap3xxx_dss_slaves,
1391         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1392         .masters        = omap3xxx_dss_masters,
1393         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1394 };
1395
1396 /* l4_core -> dss_dispc */
1397 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1398         .master         = &omap3xxx_l4_core_hwmod,
1399         .slave          = &omap3xxx_dss_dispc_hwmod,
1400         .clk            = "dss_ick",
1401         .addr           = omap2_dss_dispc_addrs,
1402         .fw = {
1403                 .omap2 = {
1404                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1405                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1406                         .flags  = OMAP_FIREWALL_L4,
1407                 }
1408         },
1409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1410 };
1411
1412 /* dss_dispc slave ports */
1413 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1414         &omap3xxx_l4_core__dss_dispc,
1415 };
1416
1417 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1418         .name           = "dss_dispc",
1419         .class          = &omap2_dispc_hwmod_class,
1420         .mpu_irqs       = omap2_dispc_irqs,
1421         .main_clk       = "dss1_alwon_fck",
1422         .prcm           = {
1423                 .omap2 = {
1424                         .prcm_reg_id = 1,
1425                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1426                         .module_offs = OMAP3430_DSS_MOD,
1427                 },
1428         },
1429         .slaves         = omap3xxx_dss_dispc_slaves,
1430         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1431         .flags          = HWMOD_NO_IDLEST,
1432 };
1433
1434 /*
1435  * 'dsi' class
1436  * display serial interface controller
1437  */
1438
1439 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1440         .name = "dsi",
1441 };
1442
1443 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1444         { .irq = 25 },
1445         { .irq = -1 }
1446 };
1447
1448 /* dss_dsi1 */
1449 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1450         {
1451                 .pa_start       = 0x4804FC00,
1452                 .pa_end         = 0x4804FFFF,
1453                 .flags          = ADDR_TYPE_RT
1454         },
1455         { }
1456 };
1457
1458 /* l4_core -> dss_dsi1 */
1459 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1460         .master         = &omap3xxx_l4_core_hwmod,
1461         .slave          = &omap3xxx_dss_dsi1_hwmod,
1462         .addr           = omap3xxx_dss_dsi1_addrs,
1463         .fw = {
1464                 .omap2 = {
1465                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1466                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1467                         .flags  = OMAP_FIREWALL_L4,
1468                 }
1469         },
1470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1471 };
1472
1473 /* dss_dsi1 slave ports */
1474 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1475         &omap3xxx_l4_core__dss_dsi1,
1476 };
1477
1478 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1479         .name           = "dss_dsi1",
1480         .class          = &omap3xxx_dsi_hwmod_class,
1481         .mpu_irqs       = omap3xxx_dsi1_irqs,
1482         .main_clk       = "dss1_alwon_fck",
1483         .prcm           = {
1484                 .omap2 = {
1485                         .prcm_reg_id = 1,
1486                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1487                         .module_offs = OMAP3430_DSS_MOD,
1488                 },
1489         },
1490         .slaves         = omap3xxx_dss_dsi1_slaves,
1491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1492         .flags          = HWMOD_NO_IDLEST,
1493 };
1494
1495 /* l4_core -> dss_rfbi */
1496 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1497         .master         = &omap3xxx_l4_core_hwmod,
1498         .slave          = &omap3xxx_dss_rfbi_hwmod,
1499         .clk            = "dss_ick",
1500         .addr           = omap2_dss_rfbi_addrs,
1501         .fw = {
1502                 .omap2 = {
1503                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1504                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1505                         .flags  = OMAP_FIREWALL_L4,
1506                 }
1507         },
1508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1509 };
1510
1511 /* dss_rfbi slave ports */
1512 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1513         &omap3xxx_l4_core__dss_rfbi,
1514 };
1515
1516 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1517         .name           = "dss_rfbi",
1518         .class          = &omap2_rfbi_hwmod_class,
1519         .main_clk       = "dss1_alwon_fck",
1520         .prcm           = {
1521                 .omap2 = {
1522                         .prcm_reg_id = 1,
1523                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1524                         .module_offs = OMAP3430_DSS_MOD,
1525                 },
1526         },
1527         .slaves         = omap3xxx_dss_rfbi_slaves,
1528         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1529         .flags          = HWMOD_NO_IDLEST,
1530 };
1531
1532 /* l4_core -> dss_venc */
1533 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1534         .master         = &omap3xxx_l4_core_hwmod,
1535         .slave          = &omap3xxx_dss_venc_hwmod,
1536         .clk            = "dss_tv_fck",
1537         .addr           = omap2_dss_venc_addrs,
1538         .fw = {
1539                 .omap2 = {
1540                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1541                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1542                         .flags  = OMAP_FIREWALL_L4,
1543                 }
1544         },
1545         .flags          = OCPIF_SWSUP_IDLE,
1546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1547 };
1548
1549 /* dss_venc slave ports */
1550 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1551         &omap3xxx_l4_core__dss_venc,
1552 };
1553
1554 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1555         .name           = "dss_venc",
1556         .class          = &omap2_venc_hwmod_class,
1557         .main_clk       = "dss1_alwon_fck",
1558         .prcm           = {
1559                 .omap2 = {
1560                         .prcm_reg_id = 1,
1561                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1562                         .module_offs = OMAP3430_DSS_MOD,
1563                 },
1564         },
1565         .slaves         = omap3xxx_dss_venc_slaves,
1566         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1567         .flags          = HWMOD_NO_IDLEST,
1568 };
1569
1570 /* I2C1 */
1571
1572 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1573         .fifo_depth     = 8, /* bytes */
1574         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1575                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1576                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1577 };
1578
1579 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1580         &omap3_l4_core__i2c1,
1581 };
1582
1583 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1584         .name           = "i2c1",
1585         .flags          = HWMOD_16BIT_REG,
1586         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1587         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1588         .main_clk       = "i2c1_fck",
1589         .prcm           = {
1590                 .omap2 = {
1591                         .module_offs = CORE_MOD,
1592                         .prcm_reg_id = 1,
1593                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1594                         .idlest_reg_id = 1,
1595                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1596                 },
1597         },
1598         .slaves         = omap3xxx_i2c1_slaves,
1599         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1600         .class          = &i2c_class,
1601         .dev_attr       = &i2c1_dev_attr,
1602 };
1603
1604 /* I2C2 */
1605
1606 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1607         .fifo_depth     = 8, /* bytes */
1608         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1609                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1610                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1611 };
1612
1613 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1614         &omap3_l4_core__i2c2,
1615 };
1616
1617 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1618         .name           = "i2c2",
1619         .flags          = HWMOD_16BIT_REG,
1620         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1621         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1622         .main_clk       = "i2c2_fck",
1623         .prcm           = {
1624                 .omap2 = {
1625                         .module_offs = CORE_MOD,
1626                         .prcm_reg_id = 1,
1627                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1628                         .idlest_reg_id = 1,
1629                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1630                 },
1631         },
1632         .slaves         = omap3xxx_i2c2_slaves,
1633         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1634         .class          = &i2c_class,
1635         .dev_attr       = &i2c2_dev_attr,
1636 };
1637
1638 /* I2C3 */
1639
1640 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1641         .fifo_depth     = 64, /* bytes */
1642         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1643                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1644                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1645 };
1646
1647 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1648         { .irq = INT_34XX_I2C3_IRQ, },
1649         { .irq = -1 }
1650 };
1651
1652 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1653         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1654         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1655         { .dma_req = -1 }
1656 };
1657
1658 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1659         &omap3_l4_core__i2c3,
1660 };
1661
1662 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1663         .name           = "i2c3",
1664         .flags          = HWMOD_16BIT_REG,
1665         .mpu_irqs       = i2c3_mpu_irqs,
1666         .sdma_reqs      = i2c3_sdma_reqs,
1667         .main_clk       = "i2c3_fck",
1668         .prcm           = {
1669                 .omap2 = {
1670                         .module_offs = CORE_MOD,
1671                         .prcm_reg_id = 1,
1672                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1673                         .idlest_reg_id = 1,
1674                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1675                 },
1676         },
1677         .slaves         = omap3xxx_i2c3_slaves,
1678         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1679         .class          = &i2c_class,
1680         .dev_attr       = &i2c3_dev_attr,
1681 };
1682
1683 /* l4_wkup -> gpio1 */
1684 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1685         {
1686                 .pa_start       = 0x48310000,
1687                 .pa_end         = 0x483101ff,
1688                 .flags          = ADDR_TYPE_RT
1689         },
1690         { }
1691 };
1692
1693 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1694         .master         = &omap3xxx_l4_wkup_hwmod,
1695         .slave          = &omap3xxx_gpio1_hwmod,
1696         .addr           = omap3xxx_gpio1_addrs,
1697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1698 };
1699
1700 /* l4_per -> gpio2 */
1701 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1702         {
1703                 .pa_start       = 0x49050000,
1704                 .pa_end         = 0x490501ff,
1705                 .flags          = ADDR_TYPE_RT
1706         },
1707         { }
1708 };
1709
1710 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1711         .master         = &omap3xxx_l4_per_hwmod,
1712         .slave          = &omap3xxx_gpio2_hwmod,
1713         .addr           = omap3xxx_gpio2_addrs,
1714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1715 };
1716
1717 /* l4_per -> gpio3 */
1718 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1719         {
1720                 .pa_start       = 0x49052000,
1721                 .pa_end         = 0x490521ff,
1722                 .flags          = ADDR_TYPE_RT
1723         },
1724         { }
1725 };
1726
1727 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1728         .master         = &omap3xxx_l4_per_hwmod,
1729         .slave          = &omap3xxx_gpio3_hwmod,
1730         .addr           = omap3xxx_gpio3_addrs,
1731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1732 };
1733
1734 /* l4_per -> gpio4 */
1735 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1736         {
1737                 .pa_start       = 0x49054000,
1738                 .pa_end         = 0x490541ff,
1739                 .flags          = ADDR_TYPE_RT
1740         },
1741         { }
1742 };
1743
1744 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1745         .master         = &omap3xxx_l4_per_hwmod,
1746         .slave          = &omap3xxx_gpio4_hwmod,
1747         .addr           = omap3xxx_gpio4_addrs,
1748         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1749 };
1750
1751 /* l4_per -> gpio5 */
1752 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1753         {
1754                 .pa_start       = 0x49056000,
1755                 .pa_end         = 0x490561ff,
1756                 .flags          = ADDR_TYPE_RT
1757         },
1758         { }
1759 };
1760
1761 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1762         .master         = &omap3xxx_l4_per_hwmod,
1763         .slave          = &omap3xxx_gpio5_hwmod,
1764         .addr           = omap3xxx_gpio5_addrs,
1765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1766 };
1767
1768 /* l4_per -> gpio6 */
1769 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1770         {
1771                 .pa_start       = 0x49058000,
1772                 .pa_end         = 0x490581ff,
1773                 .flags          = ADDR_TYPE_RT
1774         },
1775         { }
1776 };
1777
1778 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1779         .master         = &omap3xxx_l4_per_hwmod,
1780         .slave          = &omap3xxx_gpio6_hwmod,
1781         .addr           = omap3xxx_gpio6_addrs,
1782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1783 };
1784
1785 /*
1786  * 'gpio' class
1787  * general purpose io module
1788  */
1789
1790 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1791         .rev_offs       = 0x0000,
1792         .sysc_offs      = 0x0010,
1793         .syss_offs      = 0x0014,
1794         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1795                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1796                            SYSS_HAS_RESET_STATUS),
1797         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1798         .sysc_fields    = &omap_hwmod_sysc_type1,
1799 };
1800
1801 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1802         .name = "gpio",
1803         .sysc = &omap3xxx_gpio_sysc,
1804         .rev = 1,
1805 };
1806
1807 /* gpio_dev_attr*/
1808 static struct omap_gpio_dev_attr gpio_dev_attr = {
1809         .bank_width = 32,
1810         .dbck_flag = true,
1811 };
1812
1813 /* gpio1 */
1814 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1815         { .role = "dbclk", .clk = "gpio1_dbck", },
1816 };
1817
1818 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1819         &omap3xxx_l4_wkup__gpio1,
1820 };
1821
1822 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1823         .name           = "gpio1",
1824         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1825         .mpu_irqs       = omap2_gpio1_irqs,
1826         .main_clk       = "gpio1_ick",
1827         .opt_clks       = gpio1_opt_clks,
1828         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1829         .prcm           = {
1830                 .omap2 = {
1831                         .prcm_reg_id = 1,
1832                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1833                         .module_offs = WKUP_MOD,
1834                         .idlest_reg_id = 1,
1835                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1836                 },
1837         },
1838         .slaves         = omap3xxx_gpio1_slaves,
1839         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1840         .class          = &omap3xxx_gpio_hwmod_class,
1841         .dev_attr       = &gpio_dev_attr,
1842 };
1843
1844 /* gpio2 */
1845 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1846         { .role = "dbclk", .clk = "gpio2_dbck", },
1847 };
1848
1849 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1850         &omap3xxx_l4_per__gpio2,
1851 };
1852
1853 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1854         .name           = "gpio2",
1855         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1856         .mpu_irqs       = omap2_gpio2_irqs,
1857         .main_clk       = "gpio2_ick",
1858         .opt_clks       = gpio2_opt_clks,
1859         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1860         .prcm           = {
1861                 .omap2 = {
1862                         .prcm_reg_id = 1,
1863                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1864                         .module_offs = OMAP3430_PER_MOD,
1865                         .idlest_reg_id = 1,
1866                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1867                 },
1868         },
1869         .slaves         = omap3xxx_gpio2_slaves,
1870         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1871         .class          = &omap3xxx_gpio_hwmod_class,
1872         .dev_attr       = &gpio_dev_attr,
1873 };
1874
1875 /* gpio3 */
1876 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1877         { .role = "dbclk", .clk = "gpio3_dbck", },
1878 };
1879
1880 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1881         &omap3xxx_l4_per__gpio3,
1882 };
1883
1884 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1885         .name           = "gpio3",
1886         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1887         .mpu_irqs       = omap2_gpio3_irqs,
1888         .main_clk       = "gpio3_ick",
1889         .opt_clks       = gpio3_opt_clks,
1890         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1891         .prcm           = {
1892                 .omap2 = {
1893                         .prcm_reg_id = 1,
1894                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1895                         .module_offs = OMAP3430_PER_MOD,
1896                         .idlest_reg_id = 1,
1897                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1898                 },
1899         },
1900         .slaves         = omap3xxx_gpio3_slaves,
1901         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1902         .class          = &omap3xxx_gpio_hwmod_class,
1903         .dev_attr       = &gpio_dev_attr,
1904 };
1905
1906 /* gpio4 */
1907 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1908         { .role = "dbclk", .clk = "gpio4_dbck", },
1909 };
1910
1911 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1912         &omap3xxx_l4_per__gpio4,
1913 };
1914
1915 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1916         .name           = "gpio4",
1917         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1918         .mpu_irqs       = omap2_gpio4_irqs,
1919         .main_clk       = "gpio4_ick",
1920         .opt_clks       = gpio4_opt_clks,
1921         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1922         .prcm           = {
1923                 .omap2 = {
1924                         .prcm_reg_id = 1,
1925                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1926                         .module_offs = OMAP3430_PER_MOD,
1927                         .idlest_reg_id = 1,
1928                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1929                 },
1930         },
1931         .slaves         = omap3xxx_gpio4_slaves,
1932         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1933         .class          = &omap3xxx_gpio_hwmod_class,
1934         .dev_attr       = &gpio_dev_attr,
1935 };
1936
1937 /* gpio5 */
1938 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1939         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1940         { .irq = -1 }
1941 };
1942
1943 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1944         { .role = "dbclk", .clk = "gpio5_dbck", },
1945 };
1946
1947 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1948         &omap3xxx_l4_per__gpio5,
1949 };
1950
1951 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1952         .name           = "gpio5",
1953         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1954         .mpu_irqs       = omap3xxx_gpio5_irqs,
1955         .main_clk       = "gpio5_ick",
1956         .opt_clks       = gpio5_opt_clks,
1957         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1958         .prcm           = {
1959                 .omap2 = {
1960                         .prcm_reg_id = 1,
1961                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1962                         .module_offs = OMAP3430_PER_MOD,
1963                         .idlest_reg_id = 1,
1964                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1965                 },
1966         },
1967         .slaves         = omap3xxx_gpio5_slaves,
1968         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1969         .class          = &omap3xxx_gpio_hwmod_class,
1970         .dev_attr       = &gpio_dev_attr,
1971 };
1972
1973 /* gpio6 */
1974 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1975         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1976         { .irq = -1 }
1977 };
1978
1979 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1980         { .role = "dbclk", .clk = "gpio6_dbck", },
1981 };
1982
1983 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1984         &omap3xxx_l4_per__gpio6,
1985 };
1986
1987 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1988         .name           = "gpio6",
1989         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1990         .mpu_irqs       = omap3xxx_gpio6_irqs,
1991         .main_clk       = "gpio6_ick",
1992         .opt_clks       = gpio6_opt_clks,
1993         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1994         .prcm           = {
1995                 .omap2 = {
1996                         .prcm_reg_id = 1,
1997                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1998                         .module_offs = OMAP3430_PER_MOD,
1999                         .idlest_reg_id = 1,
2000                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2001                 },
2002         },
2003         .slaves         = omap3xxx_gpio6_slaves,
2004         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2005         .class          = &omap3xxx_gpio_hwmod_class,
2006         .dev_attr       = &gpio_dev_attr,
2007 };
2008
2009 /* dma_system -> L3 */
2010 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2011         .master         = &omap3xxx_dma_system_hwmod,
2012         .slave          = &omap3xxx_l3_main_hwmod,
2013         .clk            = "core_l3_ick",
2014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2015 };
2016
2017 /* dma attributes */
2018 static struct omap_dma_dev_attr dma_dev_attr = {
2019         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2020                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2021         .lch_count = 32,
2022 };
2023
2024 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2025         .rev_offs       = 0x0000,
2026         .sysc_offs      = 0x002c,
2027         .syss_offs      = 0x0028,
2028         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2029                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2030                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2031                            SYSS_HAS_RESET_STATUS),
2032         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2033                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2034         .sysc_fields    = &omap_hwmod_sysc_type1,
2035 };
2036
2037 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2038         .name = "dma",
2039         .sysc = &omap3xxx_dma_sysc,
2040 };
2041
2042 /* dma_system */
2043 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2044         {
2045                 .pa_start       = 0x48056000,
2046                 .pa_end         = 0x48056fff,
2047                 .flags          = ADDR_TYPE_RT
2048         },
2049         { }
2050 };
2051
2052 /* dma_system master ports */
2053 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2054         &omap3xxx_dma_system__l3,
2055 };
2056
2057 /* l4_cfg -> dma_system */
2058 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2059         .master         = &omap3xxx_l4_core_hwmod,
2060         .slave          = &omap3xxx_dma_system_hwmod,
2061         .clk            = "core_l4_ick",
2062         .addr           = omap3xxx_dma_system_addrs,
2063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2064 };
2065
2066 /* dma_system slave ports */
2067 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2068         &omap3xxx_l4_core__dma_system,
2069 };
2070
2071 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2072         .name           = "dma",
2073         .class          = &omap3xxx_dma_hwmod_class,
2074         .mpu_irqs       = omap2_dma_system_irqs,
2075         .main_clk       = "core_l3_ick",
2076         .prcm = {
2077                 .omap2 = {
2078                         .module_offs            = CORE_MOD,
2079                         .prcm_reg_id            = 1,
2080                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2081                         .idlest_reg_id          = 1,
2082                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2083                 },
2084         },
2085         .slaves         = omap3xxx_dma_system_slaves,
2086         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2087         .masters        = omap3xxx_dma_system_masters,
2088         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2089         .dev_attr       = &dma_dev_attr,
2090         .flags          = HWMOD_NO_IDLEST,
2091 };
2092
2093 /*
2094  * 'mcbsp' class
2095  * multi channel buffered serial port controller
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2099         .sysc_offs      = 0x008c,
2100         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2101                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2102         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2103         .sysc_fields    = &omap_hwmod_sysc_type1,
2104         .clockact       = 0x2,
2105 };
2106
2107 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2108         .name = "mcbsp",
2109         .sysc = &omap3xxx_mcbsp_sysc,
2110         .rev  = MCBSP_CONFIG_TYPE3,
2111 };
2112
2113 /* mcbsp1 */
2114 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2115         { .name = "irq", .irq = 16 },
2116         { .name = "tx", .irq = 59 },
2117         { .name = "rx", .irq = 60 },
2118         { .irq = -1 }
2119 };
2120
2121 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2122         {
2123                 .name           = "mpu",
2124                 .pa_start       = 0x48074000,
2125                 .pa_end         = 0x480740ff,
2126                 .flags          = ADDR_TYPE_RT
2127         },
2128         { }
2129 };
2130
2131 /* l4_core -> mcbsp1 */
2132 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2133         .master         = &omap3xxx_l4_core_hwmod,
2134         .slave          = &omap3xxx_mcbsp1_hwmod,
2135         .clk            = "mcbsp1_ick",
2136         .addr           = omap3xxx_mcbsp1_addrs,
2137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2138 };
2139
2140 /* mcbsp1 slave ports */
2141 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2142         &omap3xxx_l4_core__mcbsp1,
2143 };
2144
2145 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2146         .name           = "mcbsp1",
2147         .class          = &omap3xxx_mcbsp_hwmod_class,
2148         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2149         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2150         .main_clk       = "mcbsp1_fck",
2151         .prcm           = {
2152                 .omap2 = {
2153                         .prcm_reg_id = 1,
2154                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2155                         .module_offs = CORE_MOD,
2156                         .idlest_reg_id = 1,
2157                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2158                 },
2159         },
2160         .slaves         = omap3xxx_mcbsp1_slaves,
2161         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2162 };
2163
2164 /* mcbsp2 */
2165 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2166         { .name = "irq", .irq = 17 },
2167         { .name = "tx", .irq = 62 },
2168         { .name = "rx", .irq = 63 },
2169         { .irq = -1 }
2170 };
2171
2172 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2173         {
2174                 .name           = "mpu",
2175                 .pa_start       = 0x49022000,
2176                 .pa_end         = 0x490220ff,
2177                 .flags          = ADDR_TYPE_RT
2178         },
2179         { }
2180 };
2181
2182 /* l4_per -> mcbsp2 */
2183 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2184         .master         = &omap3xxx_l4_per_hwmod,
2185         .slave          = &omap3xxx_mcbsp2_hwmod,
2186         .clk            = "mcbsp2_ick",
2187         .addr           = omap3xxx_mcbsp2_addrs,
2188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2189 };
2190
2191 /* mcbsp2 slave ports */
2192 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2193         &omap3xxx_l4_per__mcbsp2,
2194 };
2195
2196 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2197         .sidetone       = "mcbsp2_sidetone",
2198 };
2199
2200 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2201         .name           = "mcbsp2",
2202         .class          = &omap3xxx_mcbsp_hwmod_class,
2203         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2204         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2205         .main_clk       = "mcbsp2_fck",
2206         .prcm           = {
2207                 .omap2 = {
2208                         .prcm_reg_id = 1,
2209                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2210                         .module_offs = OMAP3430_PER_MOD,
2211                         .idlest_reg_id = 1,
2212                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2213                 },
2214         },
2215         .slaves         = omap3xxx_mcbsp2_slaves,
2216         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2217         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2218 };
2219
2220 /* mcbsp3 */
2221 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2222         { .name = "irq", .irq = 22 },
2223         { .name = "tx", .irq = 89 },
2224         { .name = "rx", .irq = 90 },
2225         { .irq = -1 }
2226 };
2227
2228 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2229         {
2230                 .name           = "mpu",
2231                 .pa_start       = 0x49024000,
2232                 .pa_end         = 0x490240ff,
2233                 .flags          = ADDR_TYPE_RT
2234         },
2235         { }
2236 };
2237
2238 /* l4_per -> mcbsp3 */
2239 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2240         .master         = &omap3xxx_l4_per_hwmod,
2241         .slave          = &omap3xxx_mcbsp3_hwmod,
2242         .clk            = "mcbsp3_ick",
2243         .addr           = omap3xxx_mcbsp3_addrs,
2244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2245 };
2246
2247 /* mcbsp3 slave ports */
2248 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2249         &omap3xxx_l4_per__mcbsp3,
2250 };
2251
2252 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2253         .sidetone       = "mcbsp3_sidetone",
2254 };
2255
2256 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2257         .name           = "mcbsp3",
2258         .class          = &omap3xxx_mcbsp_hwmod_class,
2259         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2260         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2261         .main_clk       = "mcbsp3_fck",
2262         .prcm           = {
2263                 .omap2 = {
2264                         .prcm_reg_id = 1,
2265                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2266                         .module_offs = OMAP3430_PER_MOD,
2267                         .idlest_reg_id = 1,
2268                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2269                 },
2270         },
2271         .slaves         = omap3xxx_mcbsp3_slaves,
2272         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2273         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2274 };
2275
2276 /* mcbsp4 */
2277 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2278         { .name = "irq", .irq = 23 },
2279         { .name = "tx", .irq = 54 },
2280         { .name = "rx", .irq = 55 },
2281         { .irq = -1 }
2282 };
2283
2284 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2285         { .name = "rx", .dma_req = 20 },
2286         { .name = "tx", .dma_req = 19 },
2287         { .dma_req = -1 }
2288 };
2289
2290 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2291         {
2292                 .name           = "mpu",
2293                 .pa_start       = 0x49026000,
2294                 .pa_end         = 0x490260ff,
2295                 .flags          = ADDR_TYPE_RT
2296         },
2297         { }
2298 };
2299
2300 /* l4_per -> mcbsp4 */
2301 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2302         .master         = &omap3xxx_l4_per_hwmod,
2303         .slave          = &omap3xxx_mcbsp4_hwmod,
2304         .clk            = "mcbsp4_ick",
2305         .addr           = omap3xxx_mcbsp4_addrs,
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* mcbsp4 slave ports */
2310 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2311         &omap3xxx_l4_per__mcbsp4,
2312 };
2313
2314 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2315         .name           = "mcbsp4",
2316         .class          = &omap3xxx_mcbsp_hwmod_class,
2317         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2318         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2319         .main_clk       = "mcbsp4_fck",
2320         .prcm           = {
2321                 .omap2 = {
2322                         .prcm_reg_id = 1,
2323                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2324                         .module_offs = OMAP3430_PER_MOD,
2325                         .idlest_reg_id = 1,
2326                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2327                 },
2328         },
2329         .slaves         = omap3xxx_mcbsp4_slaves,
2330         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2331 };
2332
2333 /* mcbsp5 */
2334 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2335         { .name = "irq", .irq = 27 },
2336         { .name = "tx", .irq = 81 },
2337         { .name = "rx", .irq = 82 },
2338         { .irq = -1 }
2339 };
2340
2341 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2342         { .name = "rx", .dma_req = 22 },
2343         { .name = "tx", .dma_req = 21 },
2344         { .dma_req = -1 }
2345 };
2346
2347 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2348         {
2349                 .name           = "mpu",
2350                 .pa_start       = 0x48096000,
2351                 .pa_end         = 0x480960ff,
2352                 .flags          = ADDR_TYPE_RT
2353         },
2354         { }
2355 };
2356
2357 /* l4_core -> mcbsp5 */
2358 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2359         .master         = &omap3xxx_l4_core_hwmod,
2360         .slave          = &omap3xxx_mcbsp5_hwmod,
2361         .clk            = "mcbsp5_ick",
2362         .addr           = omap3xxx_mcbsp5_addrs,
2363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2364 };
2365
2366 /* mcbsp5 slave ports */
2367 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2368         &omap3xxx_l4_core__mcbsp5,
2369 };
2370
2371 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2372         .name           = "mcbsp5",
2373         .class          = &omap3xxx_mcbsp_hwmod_class,
2374         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2375         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2376         .main_clk       = "mcbsp5_fck",
2377         .prcm           = {
2378                 .omap2 = {
2379                         .prcm_reg_id = 1,
2380                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2381                         .module_offs = CORE_MOD,
2382                         .idlest_reg_id = 1,
2383                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2384                 },
2385         },
2386         .slaves         = omap3xxx_mcbsp5_slaves,
2387         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2388 };
2389 /* 'mcbsp sidetone' class */
2390
2391 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2392         .sysc_offs      = 0x0010,
2393         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2394         .sysc_fields    = &omap_hwmod_sysc_type1,
2395 };
2396
2397 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2398         .name = "mcbsp_sidetone",
2399         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2400 };
2401
2402 /* mcbsp2_sidetone */
2403 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2404         { .name = "irq", .irq = 4 },
2405         { .irq = -1 }
2406 };
2407
2408 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2409         {
2410                 .name           = "sidetone",
2411                 .pa_start       = 0x49028000,
2412                 .pa_end         = 0x490280ff,
2413                 .flags          = ADDR_TYPE_RT
2414         },
2415         { }
2416 };
2417
2418 /* l4_per -> mcbsp2_sidetone */
2419 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2420         .master         = &omap3xxx_l4_per_hwmod,
2421         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2422         .clk            = "mcbsp2_ick",
2423         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2424         .user           = OCP_USER_MPU,
2425 };
2426
2427 /* mcbsp2_sidetone slave ports */
2428 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2429         &omap3xxx_l4_per__mcbsp2_sidetone,
2430 };
2431
2432 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2433         .name           = "mcbsp2_sidetone",
2434         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2435         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2436         .main_clk       = "mcbsp2_fck",
2437         .prcm           = {
2438                 .omap2 = {
2439                         .prcm_reg_id = 1,
2440                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2441                         .module_offs = OMAP3430_PER_MOD,
2442                         .idlest_reg_id = 1,
2443                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2444                 },
2445         },
2446         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2447         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2448 };
2449
2450 /* mcbsp3_sidetone */
2451 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2452         { .name = "irq", .irq = 5 },
2453         { .irq = -1 }
2454 };
2455
2456 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2457         {
2458                 .name           = "sidetone",
2459                 .pa_start       = 0x4902A000,
2460                 .pa_end         = 0x4902A0ff,
2461                 .flags          = ADDR_TYPE_RT
2462         },
2463         { }
2464 };
2465
2466 /* l4_per -> mcbsp3_sidetone */
2467 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2468         .master         = &omap3xxx_l4_per_hwmod,
2469         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2470         .clk            = "mcbsp3_ick",
2471         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2472         .user           = OCP_USER_MPU,
2473 };
2474
2475 /* mcbsp3_sidetone slave ports */
2476 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2477         &omap3xxx_l4_per__mcbsp3_sidetone,
2478 };
2479
2480 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2481         .name           = "mcbsp3_sidetone",
2482         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2483         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2484         .main_clk       = "mcbsp3_fck",
2485         .prcm           = {
2486                 .omap2 = {
2487                         .prcm_reg_id = 1,
2488                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2489                         .module_offs = OMAP3430_PER_MOD,
2490                         .idlest_reg_id = 1,
2491                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2492                 },
2493         },
2494         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2495         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2496 };
2497
2498
2499 /* SR common */
2500 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2501         .clkact_shift   = 20,
2502 };
2503
2504 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2505         .sysc_offs      = 0x24,
2506         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2507         .clockact       = CLOCKACT_TEST_ICLK,
2508         .sysc_fields    = &omap34xx_sr_sysc_fields,
2509 };
2510
2511 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2512         .name = "smartreflex",
2513         .sysc = &omap34xx_sr_sysc,
2514         .rev  = 1,
2515 };
2516
2517 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2518         .sidle_shift    = 24,
2519         .enwkup_shift   = 26
2520 };
2521
2522 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2523         .sysc_offs      = 0x38,
2524         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2525         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2526                         SYSC_NO_CACHE),
2527         .sysc_fields    = &omap36xx_sr_sysc_fields,
2528 };
2529
2530 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2531         .name = "smartreflex",
2532         .sysc = &omap36xx_sr_sysc,
2533         .rev  = 2,
2534 };
2535
2536 /* SR1 */
2537 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2538         &omap3_l4_core__sr1,
2539 };
2540
2541 static struct omap_hwmod omap34xx_sr1_hwmod = {
2542         .name           = "sr1_hwmod",
2543         .class          = &omap34xx_smartreflex_hwmod_class,
2544         .main_clk       = "sr1_fck",
2545         .vdd_name       = "mpu",
2546         .prcm           = {
2547                 .omap2 = {
2548                         .prcm_reg_id = 1,
2549                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2550                         .module_offs = WKUP_MOD,
2551                         .idlest_reg_id = 1,
2552                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2553                 },
2554         },
2555         .slaves         = omap3_sr1_slaves,
2556         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2557         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2558 };
2559
2560 static struct omap_hwmod omap36xx_sr1_hwmod = {
2561         .name           = "sr1_hwmod",
2562         .class          = &omap36xx_smartreflex_hwmod_class,
2563         .main_clk       = "sr1_fck",
2564         .vdd_name       = "mpu",
2565         .prcm           = {
2566                 .omap2 = {
2567                         .prcm_reg_id = 1,
2568                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2569                         .module_offs = WKUP_MOD,
2570                         .idlest_reg_id = 1,
2571                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2572                 },
2573         },
2574         .slaves         = omap3_sr1_slaves,
2575         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2576 };
2577
2578 /* SR2 */
2579 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2580         &omap3_l4_core__sr2,
2581 };
2582
2583 static struct omap_hwmod omap34xx_sr2_hwmod = {
2584         .name           = "sr2_hwmod",
2585         .class          = &omap34xx_smartreflex_hwmod_class,
2586         .main_clk       = "sr2_fck",
2587         .vdd_name       = "core",
2588         .prcm           = {
2589                 .omap2 = {
2590                         .prcm_reg_id = 1,
2591                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2592                         .module_offs = WKUP_MOD,
2593                         .idlest_reg_id = 1,
2594                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2595                 },
2596         },
2597         .slaves         = omap3_sr2_slaves,
2598         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2599         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2600 };
2601
2602 static struct omap_hwmod omap36xx_sr2_hwmod = {
2603         .name           = "sr2_hwmod",
2604         .class          = &omap36xx_smartreflex_hwmod_class,
2605         .main_clk       = "sr2_fck",
2606         .vdd_name       = "core",
2607         .prcm           = {
2608                 .omap2 = {
2609                         .prcm_reg_id = 1,
2610                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2611                         .module_offs = WKUP_MOD,
2612                         .idlest_reg_id = 1,
2613                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2614                 },
2615         },
2616         .slaves         = omap3_sr2_slaves,
2617         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2618 };
2619
2620 /*
2621  * 'mailbox' class
2622  * mailbox module allowing communication between the on-chip processors
2623  * using a queued mailbox-interrupt mechanism.
2624  */
2625
2626 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2627         .rev_offs       = 0x000,
2628         .sysc_offs      = 0x010,
2629         .syss_offs      = 0x014,
2630         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2631                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2632         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2633         .sysc_fields    = &omap_hwmod_sysc_type1,
2634 };
2635
2636 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2637         .name = "mailbox",
2638         .sysc = &omap3xxx_mailbox_sysc,
2639 };
2640
2641 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2642 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2643         { .irq = 26 },
2644         { .irq = -1 }
2645 };
2646
2647 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2648         {
2649                 .pa_start       = 0x48094000,
2650                 .pa_end         = 0x480941ff,
2651                 .flags          = ADDR_TYPE_RT,
2652         },
2653         { }
2654 };
2655
2656 /* l4_core -> mailbox */
2657 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2658         .master         = &omap3xxx_l4_core_hwmod,
2659         .slave          = &omap3xxx_mailbox_hwmod,
2660         .addr           = omap3xxx_mailbox_addrs,
2661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2663
2664 /* mailbox slave ports */
2665 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2666         &omap3xxx_l4_core__mailbox,
2667 };
2668
2669 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2670         .name           = "mailbox",
2671         .class          = &omap3xxx_mailbox_hwmod_class,
2672         .mpu_irqs       = omap3xxx_mailbox_irqs,
2673         .main_clk       = "mailboxes_ick",
2674         .prcm           = {
2675                 .omap2 = {
2676                         .prcm_reg_id = 1,
2677                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2678                         .module_offs = CORE_MOD,
2679                         .idlest_reg_id = 1,
2680                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2681                 },
2682         },
2683         .slaves         = omap3xxx_mailbox_slaves,
2684         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2685 };
2686
2687 /* l4 core -> mcspi1 interface */
2688 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2689         .master         = &omap3xxx_l4_core_hwmod,
2690         .slave          = &omap34xx_mcspi1,
2691         .clk            = "mcspi1_ick",
2692         .addr           = omap2_mcspi1_addr_space,
2693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2694 };
2695
2696 /* l4 core -> mcspi2 interface */
2697 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2698         .master         = &omap3xxx_l4_core_hwmod,
2699         .slave          = &omap34xx_mcspi2,
2700         .clk            = "mcspi2_ick",
2701         .addr           = omap2_mcspi2_addr_space,
2702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2703 };
2704
2705 /* l4 core -> mcspi3 interface */
2706 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2707         .master         = &omap3xxx_l4_core_hwmod,
2708         .slave          = &omap34xx_mcspi3,
2709         .clk            = "mcspi3_ick",
2710         .addr           = omap2430_mcspi3_addr_space,
2711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2712 };
2713
2714 /* l4 core -> mcspi4 interface */
2715 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2716         {
2717                 .pa_start       = 0x480ba000,
2718                 .pa_end         = 0x480ba0ff,
2719                 .flags          = ADDR_TYPE_RT,
2720         },
2721         { }
2722 };
2723
2724 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2725         .master         = &omap3xxx_l4_core_hwmod,
2726         .slave          = &omap34xx_mcspi4,
2727         .clk            = "mcspi4_ick",
2728         .addr           = omap34xx_mcspi4_addr_space,
2729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2730 };
2731
2732 /*
2733  * 'mcspi' class
2734  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2735  * bus
2736  */
2737
2738 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2739         .rev_offs       = 0x0000,
2740         .sysc_offs      = 0x0010,
2741         .syss_offs      = 0x0014,
2742         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2743                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2744                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2745         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2746         .sysc_fields    = &omap_hwmod_sysc_type1,
2747 };
2748
2749 static struct omap_hwmod_class omap34xx_mcspi_class = {
2750         .name = "mcspi",
2751         .sysc = &omap34xx_mcspi_sysc,
2752         .rev = OMAP3_MCSPI_REV,
2753 };
2754
2755 /* mcspi1 */
2756 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2757         &omap34xx_l4_core__mcspi1,
2758 };
2759
2760 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2761         .num_chipselect = 4,
2762 };
2763
2764 static struct omap_hwmod omap34xx_mcspi1 = {
2765         .name           = "mcspi1",
2766         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2767         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2768         .main_clk       = "mcspi1_fck",
2769         .prcm           = {
2770                 .omap2 = {
2771                         .module_offs = CORE_MOD,
2772                         .prcm_reg_id = 1,
2773                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2774                         .idlest_reg_id = 1,
2775                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2776                 },
2777         },
2778         .slaves         = omap34xx_mcspi1_slaves,
2779         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2780         .class          = &omap34xx_mcspi_class,
2781         .dev_attr       = &omap_mcspi1_dev_attr,
2782 };
2783
2784 /* mcspi2 */
2785 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2786         &omap34xx_l4_core__mcspi2,
2787 };
2788
2789 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2790         .num_chipselect = 2,
2791 };
2792
2793 static struct omap_hwmod omap34xx_mcspi2 = {
2794         .name           = "mcspi2",
2795         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2796         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2797         .main_clk       = "mcspi2_fck",
2798         .prcm           = {
2799                 .omap2 = {
2800                         .module_offs = CORE_MOD,
2801                         .prcm_reg_id = 1,
2802                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2803                         .idlest_reg_id = 1,
2804                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2805                 },
2806         },
2807         .slaves         = omap34xx_mcspi2_slaves,
2808         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2809         .class          = &omap34xx_mcspi_class,
2810         .dev_attr       = &omap_mcspi2_dev_attr,
2811 };
2812
2813 /* mcspi3 */
2814 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2815         { .name = "irq", .irq = 91 }, /* 91 */
2816         { .irq = -1 }
2817 };
2818
2819 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2820         { .name = "tx0", .dma_req = 15 },
2821         { .name = "rx0", .dma_req = 16 },
2822         { .name = "tx1", .dma_req = 23 },
2823         { .name = "rx1", .dma_req = 24 },
2824         { .dma_req = -1 }
2825 };
2826
2827 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2828         &omap34xx_l4_core__mcspi3,
2829 };
2830
2831 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2832         .num_chipselect = 2,
2833 };
2834
2835 static struct omap_hwmod omap34xx_mcspi3 = {
2836         .name           = "mcspi3",
2837         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2838         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2839         .main_clk       = "mcspi3_fck",
2840         .prcm           = {
2841                 .omap2 = {
2842                         .module_offs = CORE_MOD,
2843                         .prcm_reg_id = 1,
2844                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2845                         .idlest_reg_id = 1,
2846                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2847                 },
2848         },
2849         .slaves         = omap34xx_mcspi3_slaves,
2850         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2851         .class          = &omap34xx_mcspi_class,
2852         .dev_attr       = &omap_mcspi3_dev_attr,
2853 };
2854
2855 /* SPI4 */
2856 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2857         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2858         { .irq = -1 }
2859 };
2860
2861 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2862         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2863         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2864         { .dma_req = -1 }
2865 };
2866
2867 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2868         &omap34xx_l4_core__mcspi4,
2869 };
2870
2871 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2872         .num_chipselect = 1,
2873 };
2874
2875 static struct omap_hwmod omap34xx_mcspi4 = {
2876         .name           = "mcspi4",
2877         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2878         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2879         .main_clk       = "mcspi4_fck",
2880         .prcm           = {
2881                 .omap2 = {
2882                         .module_offs = CORE_MOD,
2883                         .prcm_reg_id = 1,
2884                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2885                         .idlest_reg_id = 1,
2886                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2887                 },
2888         },
2889         .slaves         = omap34xx_mcspi4_slaves,
2890         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2891         .class          = &omap34xx_mcspi_class,
2892         .dev_attr       = &omap_mcspi4_dev_attr,
2893 };
2894
2895 /*
2896  * usbhsotg
2897  */
2898 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2899         .rev_offs       = 0x0400,
2900         .sysc_offs      = 0x0404,
2901         .syss_offs      = 0x0408,
2902         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2903                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2904                           SYSC_HAS_AUTOIDLE),
2905         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2906                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2907         .sysc_fields    = &omap_hwmod_sysc_type1,
2908 };
2909
2910 static struct omap_hwmod_class usbotg_class = {
2911         .name = "usbotg",
2912         .sysc = &omap3xxx_usbhsotg_sysc,
2913 };
2914 /* usb_otg_hs */
2915 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2916
2917         { .name = "mc", .irq = 92 },
2918         { .name = "dma", .irq = 93 },
2919         { .irq = -1 }
2920 };
2921
2922 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2923         .name           = "usb_otg_hs",
2924         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2925         .main_clk       = "hsotgusb_ick",
2926         .prcm           = {
2927                 .omap2 = {
2928                         .prcm_reg_id = 1,
2929                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2930                         .module_offs = CORE_MOD,
2931                         .idlest_reg_id = 1,
2932                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2933                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2934                 },
2935         },
2936         .masters        = omap3xxx_usbhsotg_masters,
2937         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2938         .slaves         = omap3xxx_usbhsotg_slaves,
2939         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2940         .class          = &usbotg_class,
2941
2942         /*
2943          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2944          * broken when autoidle is enabled
2945          * workaround is to disable the autoidle bit at module level.
2946          */
2947         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2948                                 | HWMOD_SWSUP_MSTANDBY,
2949 };
2950
2951 /* usb_otg_hs */
2952 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2953
2954         { .name = "mc", .irq = 71 },
2955         { .irq = -1 }
2956 };
2957
2958 static struct omap_hwmod_class am35xx_usbotg_class = {
2959         .name = "am35xx_usbotg",
2960         .sysc = NULL,
2961 };
2962
2963 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2964         .name           = "am35x_otg_hs",
2965         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
2966         .main_clk       = NULL,
2967         .prcm = {
2968                 .omap2 = {
2969                 },
2970         },
2971         .masters        = am35xx_usbhsotg_masters,
2972         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
2973         .slaves         = am35xx_usbhsotg_slaves,
2974         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
2975         .class          = &am35xx_usbotg_class,
2976 };
2977
2978 /* MMC/SD/SDIO common */
2979
2980 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
2981         .rev_offs       = 0x1fc,
2982         .sysc_offs      = 0x10,
2983         .syss_offs      = 0x14,
2984         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2985                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2986                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2987         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2988         .sysc_fields    = &omap_hwmod_sysc_type1,
2989 };
2990
2991 static struct omap_hwmod_class omap34xx_mmc_class = {
2992         .name = "mmc",
2993         .sysc = &omap34xx_mmc_sysc,
2994 };
2995
2996 /* MMC/SD/SDIO1 */
2997
2998 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
2999         { .irq = 83, },
3000         { .irq = -1 }
3001 };
3002
3003 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3004         { .name = "tx", .dma_req = 61, },
3005         { .name = "rx", .dma_req = 62, },
3006         { .dma_req = -1 }
3007 };
3008
3009 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3010         { .role = "dbck", .clk = "omap_32k_fck", },
3011 };
3012
3013 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3014         &omap3xxx_l4_core__mmc1,
3015 };
3016
3017 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3018         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3019 };
3020
3021 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3022         .name           = "mmc1",
3023         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3024         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3025         .opt_clks       = omap34xx_mmc1_opt_clks,
3026         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3027         .main_clk       = "mmchs1_fck",
3028         .prcm           = {
3029                 .omap2 = {
3030                         .module_offs = CORE_MOD,
3031                         .prcm_reg_id = 1,
3032                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3033                         .idlest_reg_id = 1,
3034                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3035                 },
3036         },
3037         .dev_attr       = &mmc1_dev_attr,
3038         .slaves         = omap3xxx_mmc1_slaves,
3039         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3040         .class          = &omap34xx_mmc_class,
3041 };
3042
3043 /* MMC/SD/SDIO2 */
3044
3045 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3046         { .irq = INT_24XX_MMC2_IRQ, },
3047         { .irq = -1 }
3048 };
3049
3050 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3051         { .name = "tx", .dma_req = 47, },
3052         { .name = "rx", .dma_req = 48, },
3053         { .dma_req = -1 }
3054 };
3055
3056 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3057         { .role = "dbck", .clk = "omap_32k_fck", },
3058 };
3059
3060 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3061         &omap3xxx_l4_core__mmc2,
3062 };
3063
3064 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3065         .name           = "mmc2",
3066         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3067         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3068         .opt_clks       = omap34xx_mmc2_opt_clks,
3069         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3070         .main_clk       = "mmchs2_fck",
3071         .prcm           = {
3072                 .omap2 = {
3073                         .module_offs = CORE_MOD,
3074                         .prcm_reg_id = 1,
3075                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3076                         .idlest_reg_id = 1,
3077                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3078                 },
3079         },
3080         .slaves         = omap3xxx_mmc2_slaves,
3081         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3082         .class          = &omap34xx_mmc_class,
3083 };
3084
3085 /* MMC/SD/SDIO3 */
3086
3087 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3088         { .irq = 94, },
3089         { .irq = -1 }
3090 };
3091
3092 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3093         { .name = "tx", .dma_req = 77, },
3094         { .name = "rx", .dma_req = 78, },
3095         { .dma_req = -1 }
3096 };
3097
3098 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3099         { .role = "dbck", .clk = "omap_32k_fck", },
3100 };
3101
3102 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3103         &omap3xxx_l4_core__mmc3,
3104 };
3105
3106 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3107         .name           = "mmc3",
3108         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3109         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3110         .opt_clks       = omap34xx_mmc3_opt_clks,
3111         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3112         .main_clk       = "mmchs3_fck",
3113         .prcm           = {
3114                 .omap2 = {
3115                         .prcm_reg_id = 1,
3116                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3117                         .idlest_reg_id = 1,
3118                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3119                 },
3120         },
3121         .slaves         = omap3xxx_mmc3_slaves,
3122         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3123         .class          = &omap34xx_mmc_class,
3124 };
3125
3126 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3127         &omap3xxx_l3_main_hwmod,
3128         &omap3xxx_l4_core_hwmod,
3129         &omap3xxx_l4_per_hwmod,
3130         &omap3xxx_l4_wkup_hwmod,
3131         &omap3xxx_mmc1_hwmod,
3132         &omap3xxx_mmc2_hwmod,
3133         &omap3xxx_mmc3_hwmod,
3134         &omap3xxx_mpu_hwmod,
3135         &omap3xxx_iva_hwmod,
3136
3137         &omap3xxx_timer1_hwmod,
3138         &omap3xxx_timer2_hwmod,
3139         &omap3xxx_timer3_hwmod,
3140         &omap3xxx_timer4_hwmod,
3141         &omap3xxx_timer5_hwmod,
3142         &omap3xxx_timer6_hwmod,
3143         &omap3xxx_timer7_hwmod,
3144         &omap3xxx_timer8_hwmod,
3145         &omap3xxx_timer9_hwmod,
3146         &omap3xxx_timer10_hwmod,
3147         &omap3xxx_timer11_hwmod,
3148         &omap3xxx_timer12_hwmod,
3149
3150         &omap3xxx_wd_timer2_hwmod,
3151         &omap3xxx_uart1_hwmod,
3152         &omap3xxx_uart2_hwmod,
3153         &omap3xxx_uart3_hwmod,
3154         /* dss class */
3155         &omap3xxx_dss_dispc_hwmod,
3156         &omap3xxx_dss_dsi1_hwmod,
3157         &omap3xxx_dss_rfbi_hwmod,
3158         &omap3xxx_dss_venc_hwmod,
3159
3160         /* i2c class */
3161         &omap3xxx_i2c1_hwmod,
3162         &omap3xxx_i2c2_hwmod,
3163         &omap3xxx_i2c3_hwmod,
3164         &omap34xx_sr1_hwmod,
3165         &omap34xx_sr2_hwmod,
3166
3167         /* gpio class */
3168         &omap3xxx_gpio1_hwmod,
3169         &omap3xxx_gpio2_hwmod,
3170         &omap3xxx_gpio3_hwmod,
3171         &omap3xxx_gpio4_hwmod,
3172         &omap3xxx_gpio5_hwmod,
3173         &omap3xxx_gpio6_hwmod,
3174
3175         /* dma_system class*/
3176         &omap3xxx_dma_system_hwmod,
3177
3178         /* mcbsp class */
3179         &omap3xxx_mcbsp1_hwmod,
3180         &omap3xxx_mcbsp2_hwmod,
3181         &omap3xxx_mcbsp3_hwmod,
3182         &omap3xxx_mcbsp4_hwmod,
3183         &omap3xxx_mcbsp5_hwmod,
3184         &omap3xxx_mcbsp2_sidetone_hwmod,
3185         &omap3xxx_mcbsp3_sidetone_hwmod,
3186
3187         /* mailbox class */
3188         &omap3xxx_mailbox_hwmod,
3189
3190         /* mcspi class */
3191         &omap34xx_mcspi1,
3192         &omap34xx_mcspi2,
3193         &omap34xx_mcspi3,
3194         &omap34xx_mcspi4,
3195
3196         NULL,
3197 };
3198
3199 /* 3430ES1-only hwmods */
3200 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3201         &omap3430es1_dss_core_hwmod,
3202         NULL
3203 };
3204
3205 /* 3430ES2+-only hwmods */
3206 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3207         &omap3xxx_dss_core_hwmod,
3208         &omap3xxx_usbhsotg_hwmod,
3209         NULL
3210 };
3211
3212 /* 34xx-only hwmods (all ES revisions) */
3213 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3214         &omap34xx_sr1_hwmod,
3215         &omap34xx_sr2_hwmod,
3216         NULL
3217 };
3218
3219 /* 36xx-only hwmods (all ES revisions) */
3220 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3221         &omap3xxx_uart4_hwmod,
3222         &omap3xxx_dss_core_hwmod,
3223         &omap36xx_sr1_hwmod,
3224         &omap36xx_sr2_hwmod,
3225         &omap3xxx_usbhsotg_hwmod,
3226         NULL
3227 };
3228
3229 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3230         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3231         &am35xx_usbhsotg_hwmod,
3232         NULL
3233 };
3234
3235 int __init omap3xxx_hwmod_init(void)
3236 {
3237         int r;
3238         struct omap_hwmod **h = NULL;
3239         unsigned int rev;
3240
3241         /* Register hwmods common to all OMAP3 */
3242         r = omap_hwmod_register(omap3xxx_hwmods);
3243         if (!r)
3244                 return r;
3245
3246         rev = omap_rev();
3247
3248         /*
3249          * Register hwmods common to individual OMAP3 families, all
3250          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3251          * All possible revisions should be included in this conditional.
3252          */
3253         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3254             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3255             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3256                 h = omap34xx_hwmods;
3257         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3258                 h = am35xx_hwmods;
3259         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3260                    rev == OMAP3630_REV_ES1_2) {
3261                 h = omap36xx_hwmods;
3262         } else {
3263                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3264                 return -EINVAL;
3265         };
3266
3267         r = omap_hwmod_register(h);
3268         if (!r)
3269                 return r;
3270
3271         /*
3272          * Register hwmods specific to certain ES levels of a
3273          * particular family of silicon (e.g., 34xx ES1.0)
3274          */
3275         h = NULL;
3276         if (rev == OMAP3430_REV_ES1_0) {
3277                 h = omap3430es1_hwmods;
3278         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3279                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3280                    rev == OMAP3430_REV_ES3_1_2) {
3281                 h = omap3430es2plus_hwmods;
3282         };
3283
3284         if (h)
3285                 r = omap_hwmod_register(h);
3286
3287         return r;
3288 }