arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 163 static struct omap_hwmod omap3xxx_uart1_hwmod;
 164 static struct omap_hwmod omap3xxx_uart2_hwmod;
 165 static struct omap_hwmod omap3xxx_uart3_hwmod;
 166 static struct omap_hwmod omap3xxx_uart4_hwmod;
 167 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 168
 169 /* l3_core -> usbhsotg interface */
 170 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 171         .master         = &omap3xxx_usbhsotg_hwmod,
 172         .slave          = &omap3xxx_l3_main_hwmod,
 173         .clk            = "core_l3_ick",
 174         .user           = OCP_USER_MPU,
 175 };
 176
 177 /* l3_core -> am35xx_usbhsotg interface */
 178 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 179         .master         = &am35xx_usbhsotg_hwmod,
 180         .slave          = &omap3xxx_l3_main_hwmod,
 181         .clk            = "core_l3_ick",
 182         .user           = OCP_USER_MPU,
 183 };
 184 /* L4_CORE -> L4_WKUP interface */
 185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 186         .master = &omap3xxx_l4_core_hwmod,
 187         .slave  = &omap3xxx_l4_wkup_hwmod,
 188         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 189 };
 190
 191 /* L4 CORE -> MMC1 interface */
 192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 193         .master         = &omap3xxx_l4_core_hwmod,
 194         .slave          = &omap3xxx_mmc1_hwmod,
 195         .clk            = "mmchs1_ick",
 196         .addr           = omap2430_mmc1_addr_space,
 197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 198         .flags          = OMAP_FIREWALL_L4
 199 };
 200
 201 /* L4 CORE -> MMC2 interface */
 202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 203         .master         = &omap3xxx_l4_core_hwmod,
 204         .slave          = &omap3xxx_mmc2_hwmod,
 205         .clk            = "mmchs2_ick",
 206         .addr           = omap2430_mmc2_addr_space,
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208         .flags          = OMAP_FIREWALL_L4
 209 };
 210
 211 /* L4 CORE -> MMC3 interface */
 212 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 213         {
 214                 .pa_start       = 0x480ad000,
 215                 .pa_end         = 0x480ad1ff,
 216                 .flags          = ADDR_TYPE_RT,
 217         },
 218         { }
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_mmc3_hwmod,
 224         .clk            = "mmchs3_ick",
 225         .addr           = omap3xxx_mmc3_addr_space,
 226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 227         .flags          = OMAP_FIREWALL_L4
 228 };
 229
 230 /* L4 CORE -> UART1 interface */
 231 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 232         {
 233                 .pa_start       = OMAP3_UART1_BASE,
 234                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 235                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 236         },
 237         { }
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 241         .master         = &omap3xxx_l4_core_hwmod,
 242         .slave          = &omap3xxx_uart1_hwmod,
 243         .clk            = "uart1_ick",
 244         .addr           = omap3xxx_uart1_addr_space,
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246 };
 247
 248 /* L4 CORE -> UART2 interface */
 249 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 250         {
 251                 .pa_start       = OMAP3_UART2_BASE,
 252                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 253                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 254         },
 255         { }
 256 };
 257
 258 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 259         .master         = &omap3xxx_l4_core_hwmod,
 260         .slave          = &omap3xxx_uart2_hwmod,
 261         .clk            = "uart2_ick",
 262         .addr           = omap3xxx_uart2_addr_space,
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* L4 PER -> UART3 interface */
 267 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 268         {
 269                 .pa_start       = OMAP3_UART3_BASE,
 270                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 271                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 272         },
 273         { }
 274 };
 275
 276 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 277         .master         = &omap3xxx_l4_per_hwmod,
 278         .slave          = &omap3xxx_uart3_hwmod,
 279         .clk            = "uart3_ick",
 280         .addr           = omap3xxx_uart3_addr_space,
 281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 282 };
 283
 284 /* L4 PER -> UART4 interface */
 285 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 286         {
 287                 .pa_start       = OMAP3_UART4_BASE,
 288                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 289                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 290         },
 291         { }
 292 };
 293
 294 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 295         .master         = &omap3xxx_l4_per_hwmod,
 296         .slave          = &omap3xxx_uart4_hwmod,
 297         .clk            = "uart4_ick",
 298         .addr           = omap3xxx_uart4_addr_space,
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* L4 CORE -> I2C1 interface */
 303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 304         .master         = &omap3xxx_l4_core_hwmod,
 305         .slave          = &omap3xxx_i2c1_hwmod,
 306         .clk            = "i2c1_ick",
 307         .addr           = omap2_i2c1_addr_space,
 308         .fw = {
 309                 .omap2 = {
 310                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 311                         .l4_prot_group = 7,
 312                         .flags  = OMAP_FIREWALL_L4,
 313                 }
 314         },
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* L4 CORE -> I2C2 interface */
 319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 320         .master         = &omap3xxx_l4_core_hwmod,
 321         .slave          = &omap3xxx_i2c2_hwmod,
 322         .clk            = "i2c2_ick",
 323         .addr           = omap2_i2c2_addr_space,
 324         .fw = {
 325                 .omap2 = {
 326                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 327                         .l4_prot_group = 7,
 328                         .flags = OMAP_FIREWALL_L4,
 329                 }
 330         },
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* L4 CORE -> I2C3 interface */
 335 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 336         {
 337                 .pa_start       = 0x48060000,
 338                 .pa_end         = 0x48060000 + SZ_128 - 1,
 339                 .flags          = ADDR_TYPE_RT,
 340         },
 341         { }
 342 };
 343
 344 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 345         .master         = &omap3xxx_l4_core_hwmod,
 346         .slave          = &omap3xxx_i2c3_hwmod,
 347         .clk            = "i2c3_ick",
 348         .addr           = omap3xxx_i2c3_addr_space,
 349         .fw = {
 350                 .omap2 = {
 351                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 352                         .l4_prot_group = 7,
 353                         .flags = OMAP_FIREWALL_L4,
 354                 }
 355         },
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* L4 CORE -> SR1 interface */
 360 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 361         {
 362                 .pa_start       = OMAP34XX_SR1_BASE,
 363                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 364                 .flags          = ADDR_TYPE_RT,
 365         },
 366         { }
 367 };
 368
 369 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 370         .master         = &omap3xxx_l4_core_hwmod,
 371         .slave          = &omap34xx_sr1_hwmod,
 372         .clk            = "sr_l4_ick",
 373         .addr           = omap3_sr1_addr_space,
 374         .user           = OCP_USER_MPU,
 375 };
 376
 377 /* L4 CORE -> SR1 interface */
 378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 379         {
 380                 .pa_start       = OMAP34XX_SR2_BASE,
 381                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 382                 .flags          = ADDR_TYPE_RT,
 383         },
 384         { }
 385 };
 386
 387 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 388         .master         = &omap3xxx_l4_core_hwmod,
 389         .slave          = &omap34xx_sr2_hwmod,
 390         .clk            = "sr_l4_ick",
 391         .addr           = omap3_sr2_addr_space,
 392         .user           = OCP_USER_MPU,
 393 };
 394
 395 /*
 396 * usbhsotg interface data
 397 */
 398
 399 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 400         {
 401                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 402                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 403                 .flags          = ADDR_TYPE_RT
 404         },
 405         { }
 406 };
 407
 408 /* l4_core -> usbhsotg  */
 409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 410         .master         = &omap3xxx_l4_core_hwmod,
 411         .slave          = &omap3xxx_usbhsotg_hwmod,
 412         .clk            = "l4_ick",
 413         .addr           = omap3xxx_usbhsotg_addrs,
 414         .user           = OCP_USER_MPU,
 415 };
 416
 417 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 418         &omap3xxx_usbhsotg__l3,
 419 };
 420
 421 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 422         &omap3xxx_l4_core__usbhsotg,
 423 };
 424
 425 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 426         {
 427                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 428                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 429                 .flags          = ADDR_TYPE_RT
 430         },
 431         { }
 432 };
 433
 434 /* l4_core -> usbhsotg  */
 435 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 436         .master         = &omap3xxx_l4_core_hwmod,
 437         .slave          = &am35xx_usbhsotg_hwmod,
 438         .clk            = "l4_ick",
 439         .addr           = am35xx_usbhsotg_addrs,
 440         .user           = OCP_USER_MPU,
 441 };
 442
 443 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 444         &am35xx_usbhsotg__l3,
 445 };
 446
 447 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 448         &am35xx_l4_core__usbhsotg,
 449 };
 450 /* Slave interfaces on the L4_CORE interconnect */
 451 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 452         &omap3xxx_l3_main__l4_core,
 453 };
 454
 455 /* L4 CORE */
 456 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 457         .name           = "l4_core",
 458         .class          = &l4_hwmod_class,
 459         .slaves         = omap3xxx_l4_core_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 461         .flags          = HWMOD_NO_IDLEST,
 462 };
 463
 464 /* Slave interfaces on the L4_PER interconnect */
 465 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 466         &omap3xxx_l3_main__l4_per,
 467 };
 468
 469 /* L4 PER */
 470 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 471         .name           = "l4_per",
 472         .class          = &l4_hwmod_class,
 473         .slaves         = omap3xxx_l4_per_slaves,
 474         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 475         .flags          = HWMOD_NO_IDLEST,
 476 };
 477
 478 /* Slave interfaces on the L4_WKUP interconnect */
 479 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 480         &omap3xxx_l4_core__l4_wkup,
 481 };
 482
 483 /* L4 WKUP */
 484 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 485         .name           = "l4_wkup",
 486         .class          = &l4_hwmod_class,
 487         .slaves         = omap3xxx_l4_wkup_slaves,
 488         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 489         .flags          = HWMOD_NO_IDLEST,
 490 };
 491
 492 /* Master interfaces on the MPU device */
 493 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 494         &omap3xxx_mpu__l3_main,
 495 };
 496
 497 /* MPU */
 498 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 499         .name           = "mpu",
 500         .class          = &mpu_hwmod_class,
 501         .main_clk       = "arm_fck",
 502         .masters        = omap3xxx_mpu_masters,
 503         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 504 };
 505
 506 /*
 507  * IVA2_2 interface data
 508  */
 509
 510 /* IVA2 <- L3 interface */
 511 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 512         .master         = &omap3xxx_l3_main_hwmod,
 513         .slave          = &omap3xxx_iva_hwmod,
 514         .clk            = "iva2_ck",
 515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 516 };
 517
 518 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 519         &omap3xxx_l3__iva,
 520 };
 521
 522 /*
 523  * IVA2 (IVA2)
 524  */
 525
 526 static struct omap_hwmod omap3xxx_iva_hwmod = {
 527         .name           = "iva",
 528         .class          = &iva_hwmod_class,
 529         .masters        = omap3xxx_iva_masters,
 530         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 531 };
 532
 533 /* timer class */
 534 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x0010,
 537         .syss_offs      = 0x0014,
 538         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 539                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 540                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 546         .name = "timer",
 547         .sysc = &omap3xxx_timer_1ms_sysc,
 548         .rev = OMAP_TIMER_IP_VERSION_1,
 549 };
 550
 551 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 556                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 557         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 558         .sysc_fields    = &omap_hwmod_sysc_type1,
 559 };
 560
 561 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 562         .name = "timer",
 563         .sysc = &omap3xxx_timer_sysc,
 564         .rev =  OMAP_TIMER_IP_VERSION_1,
 565 };
 566
 567 /* secure timers dev attribute */
 568 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 569         .timer_capability       = OMAP_TIMER_SECURE,
 570 };
 571
 572 /* always-on timers dev attribute */
 573 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 574         .timer_capability       = OMAP_TIMER_ALWON,
 575 };
 576
 577 /* pwm timers dev attribute */
 578 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 579         .timer_capability       = OMAP_TIMER_HAS_PWM,
 580 };
 581
 582 /* timer1 */
 583 static struct omap_hwmod omap3xxx_timer1_hwmod;
 584
 585 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 586         {
 587                 .pa_start       = 0x48318000,
 588                 .pa_end         = 0x48318000 + SZ_1K - 1,
 589                 .flags          = ADDR_TYPE_RT
 590         },
 591         { }
 592 };
 593
 594 /* l4_wkup -> timer1 */
 595 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 596         .master         = &omap3xxx_l4_wkup_hwmod,
 597         .slave          = &omap3xxx_timer1_hwmod,
 598         .clk            = "gpt1_ick",
 599         .addr           = omap3xxx_timer1_addrs,
 600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 601 };
 602
 603 /* timer1 slave port */
 604 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 605         &omap3xxx_l4_wkup__timer1,
 606 };
 607
 608 /* timer1 hwmod */
 609 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 610         .name           = "timer1",
 611         .mpu_irqs       = omap2_timer1_mpu_irqs,
 612         .main_clk       = "gpt1_fck",
 613         .prcm           = {
 614                 .omap2 = {
 615                         .prcm_reg_id = 1,
 616                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 617                         .module_offs = WKUP_MOD,
 618                         .idlest_reg_id = 1,
 619                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 620                 },
 621         },
 622         .dev_attr       = &capability_alwon_dev_attr,
 623         .slaves         = omap3xxx_timer1_slaves,
 624         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 625         .class          = &omap3xxx_timer_1ms_hwmod_class,
 626 };
 627
 628 /* timer2 */
 629 static struct omap_hwmod omap3xxx_timer2_hwmod;
 630
 631 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 632         {
 633                 .pa_start       = 0x49032000,
 634                 .pa_end         = 0x49032000 + SZ_1K - 1,
 635                 .flags          = ADDR_TYPE_RT
 636         },
 637         { }
 638 };
 639
 640 /* l4_per -> timer2 */
 641 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 642         .master         = &omap3xxx_l4_per_hwmod,
 643         .slave          = &omap3xxx_timer2_hwmod,
 644         .clk            = "gpt2_ick",
 645         .addr           = omap3xxx_timer2_addrs,
 646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 647 };
 648
 649 /* timer2 slave port */
 650 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 651         &omap3xxx_l4_per__timer2,
 652 };
 653
 654 /* timer2 hwmod */
 655 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 656         .name           = "timer2",
 657         .mpu_irqs       = omap2_timer2_mpu_irqs,
 658         .main_clk       = "gpt2_fck",
 659         .prcm           = {
 660                 .omap2 = {
 661                         .prcm_reg_id = 1,
 662                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 663                         .module_offs = OMAP3430_PER_MOD,
 664                         .idlest_reg_id = 1,
 665                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 666                 },
 667         },
 668         .dev_attr       = &capability_alwon_dev_attr,
 669         .slaves         = omap3xxx_timer2_slaves,
 670         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 671         .class          = &omap3xxx_timer_1ms_hwmod_class,
 672 };
 673
 674 /* timer3 */
 675 static struct omap_hwmod omap3xxx_timer3_hwmod;
 676
 677 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 678         {
 679                 .pa_start       = 0x49034000,
 680                 .pa_end         = 0x49034000 + SZ_1K - 1,
 681                 .flags          = ADDR_TYPE_RT
 682         },
 683         { }
 684 };
 685
 686 /* l4_per -> timer3 */
 687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 688         .master         = &omap3xxx_l4_per_hwmod,
 689         .slave          = &omap3xxx_timer3_hwmod,
 690         .clk            = "gpt3_ick",
 691         .addr           = omap3xxx_timer3_addrs,
 692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 693 };
 694
 695 /* timer3 slave port */
 696 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 697         &omap3xxx_l4_per__timer3,
 698 };
 699
 700 /* timer3 hwmod */
 701 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 702         .name           = "timer3",
 703         .mpu_irqs       = omap2_timer3_mpu_irqs,
 704         .main_clk       = "gpt3_fck",
 705         .prcm           = {
 706                 .omap2 = {
 707                         .prcm_reg_id = 1,
 708                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 709                         .module_offs = OMAP3430_PER_MOD,
 710                         .idlest_reg_id = 1,
 711                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 712                 },
 713         },
 714         .dev_attr       = &capability_alwon_dev_attr,
 715         .slaves         = omap3xxx_timer3_slaves,
 716         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 717         .class          = &omap3xxx_timer_hwmod_class,
 718 };
 719
 720 /* timer4 */
 721 static struct omap_hwmod omap3xxx_timer4_hwmod;
 722
 723 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 724         {
 725                 .pa_start       = 0x49036000,
 726                 .pa_end         = 0x49036000 + SZ_1K - 1,
 727                 .flags          = ADDR_TYPE_RT
 728         },
 729         { }
 730 };
 731
 732 /* l4_per -> timer4 */
 733 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 734         .master         = &omap3xxx_l4_per_hwmod,
 735         .slave          = &omap3xxx_timer4_hwmod,
 736         .clk            = "gpt4_ick",
 737         .addr           = omap3xxx_timer4_addrs,
 738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 739 };
 740
 741 /* timer4 slave port */
 742 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 743         &omap3xxx_l4_per__timer4,
 744 };
 745
 746 /* timer4 hwmod */
 747 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 748         .name           = "timer4",
 749         .mpu_irqs       = omap2_timer4_mpu_irqs,
 750         .main_clk       = "gpt4_fck",
 751         .prcm           = {
 752                 .omap2 = {
 753                         .prcm_reg_id = 1,
 754                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 755                         .module_offs = OMAP3430_PER_MOD,
 756                         .idlest_reg_id = 1,
 757                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 758                 },
 759         },
 760         .dev_attr       = &capability_alwon_dev_attr,
 761         .slaves         = omap3xxx_timer4_slaves,
 762         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 763         .class          = &omap3xxx_timer_hwmod_class,
 764 };
 765
 766 /* timer5 */
 767 static struct omap_hwmod omap3xxx_timer5_hwmod;
 768
 769 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 770         {
 771                 .pa_start       = 0x49038000,
 772                 .pa_end         = 0x49038000 + SZ_1K - 1,
 773                 .flags          = ADDR_TYPE_RT
 774         },
 775         { }
 776 };
 777
 778 /* l4_per -> timer5 */
 779 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 780         .master         = &omap3xxx_l4_per_hwmod,
 781         .slave          = &omap3xxx_timer5_hwmod,
 782         .clk            = "gpt5_ick",
 783         .addr           = omap3xxx_timer5_addrs,
 784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 785 };
 786
 787 /* timer5 slave port */
 788 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 789         &omap3xxx_l4_per__timer5,
 790 };
 791
 792 /* timer5 hwmod */
 793 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 794         .name           = "timer5",
 795         .mpu_irqs       = omap2_timer5_mpu_irqs,
 796         .main_clk       = "gpt5_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 801                         .module_offs = OMAP3430_PER_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 804                 },
 805         },
 806         .dev_attr       = &capability_alwon_dev_attr,
 807         .slaves         = omap3xxx_timer5_slaves,
 808         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 809         .class          = &omap3xxx_timer_hwmod_class,
 810 };
 811
 812 /* timer6 */
 813 static struct omap_hwmod omap3xxx_timer6_hwmod;
 814
 815 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 816         {
 817                 .pa_start       = 0x4903A000,
 818                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 819                 .flags          = ADDR_TYPE_RT
 820         },
 821         { }
 822 };
 823
 824 /* l4_per -> timer6 */
 825 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 826         .master         = &omap3xxx_l4_per_hwmod,
 827         .slave          = &omap3xxx_timer6_hwmod,
 828         .clk            = "gpt6_ick",
 829         .addr           = omap3xxx_timer6_addrs,
 830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 831 };
 832
 833 /* timer6 slave port */
 834 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 835         &omap3xxx_l4_per__timer6,
 836 };
 837
 838 /* timer6 hwmod */
 839 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 840         .name           = "timer6",
 841         .mpu_irqs       = omap2_timer6_mpu_irqs,
 842         .main_clk       = "gpt6_fck",
 843         .prcm           = {
 844                 .omap2 = {
 845                         .prcm_reg_id = 1,
 846                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 847                         .module_offs = OMAP3430_PER_MOD,
 848                         .idlest_reg_id = 1,
 849                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 850                 },
 851         },
 852         .dev_attr       = &capability_alwon_dev_attr,
 853         .slaves         = omap3xxx_timer6_slaves,
 854         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 855         .class          = &omap3xxx_timer_hwmod_class,
 856 };
 857
 858 /* timer7 */
 859 static struct omap_hwmod omap3xxx_timer7_hwmod;
 860
 861 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 862         {
 863                 .pa_start       = 0x4903C000,
 864                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 865                 .flags          = ADDR_TYPE_RT
 866         },
 867         { }
 868 };
 869
 870 /* l4_per -> timer7 */
 871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 872         .master         = &omap3xxx_l4_per_hwmod,
 873         .slave          = &omap3xxx_timer7_hwmod,
 874         .clk            = "gpt7_ick",
 875         .addr           = omap3xxx_timer7_addrs,
 876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 877 };
 878
 879 /* timer7 slave port */
 880 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 881         &omap3xxx_l4_per__timer7,
 882 };
 883
 884 /* timer7 hwmod */
 885 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 886         .name           = "timer7",
 887         .mpu_irqs       = omap2_timer7_mpu_irqs,
 888         .main_clk       = "gpt7_fck",
 889         .prcm           = {
 890                 .omap2 = {
 891                         .prcm_reg_id = 1,
 892                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 893                         .module_offs = OMAP3430_PER_MOD,
 894                         .idlest_reg_id = 1,
 895                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 896                 },
 897         },
 898         .dev_attr       = &capability_alwon_dev_attr,
 899         .slaves         = omap3xxx_timer7_slaves,
 900         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 901         .class          = &omap3xxx_timer_hwmod_class,
 902 };
 903
 904 /* timer8 */
 905 static struct omap_hwmod omap3xxx_timer8_hwmod;
 906
 907 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 908         {
 909                 .pa_start       = 0x4903E000,
 910                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 911                 .flags          = ADDR_TYPE_RT
 912         },
 913         { }
 914 };
 915
 916 /* l4_per -> timer8 */
 917 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 918         .master         = &omap3xxx_l4_per_hwmod,
 919         .slave          = &omap3xxx_timer8_hwmod,
 920         .clk            = "gpt8_ick",
 921         .addr           = omap3xxx_timer8_addrs,
 922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 923 };
 924
 925 /* timer8 slave port */
 926 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 927         &omap3xxx_l4_per__timer8,
 928 };
 929
 930 /* timer8 hwmod */
 931 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 932         .name           = "timer8",
 933         .mpu_irqs       = omap2_timer8_mpu_irqs,
 934         .main_clk       = "gpt8_fck",
 935         .prcm           = {
 936                 .omap2 = {
 937                         .prcm_reg_id = 1,
 938                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 939                         .module_offs = OMAP3430_PER_MOD,
 940                         .idlest_reg_id = 1,
 941                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 942                 },
 943         },
 944         .dev_attr       = &capability_pwm_dev_attr,
 945         .slaves         = omap3xxx_timer8_slaves,
 946         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 947         .class          = &omap3xxx_timer_hwmod_class,
 948 };
 949
 950 /* timer9 */
 951 static struct omap_hwmod omap3xxx_timer9_hwmod;
 952
 953 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 954         {
 955                 .pa_start       = 0x49040000,
 956                 .pa_end         = 0x49040000 + SZ_1K - 1,
 957                 .flags          = ADDR_TYPE_RT
 958         },
 959         { }
 960 };
 961
 962 /* l4_per -> timer9 */
 963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 964         .master         = &omap3xxx_l4_per_hwmod,
 965         .slave          = &omap3xxx_timer9_hwmod,
 966         .clk            = "gpt9_ick",
 967         .addr           = omap3xxx_timer9_addrs,
 968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 969 };
 970
 971 /* timer9 slave port */
 972 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 973         &omap3xxx_l4_per__timer9,
 974 };
 975
 976 /* timer9 hwmod */
 977 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 978         .name           = "timer9",
 979         .mpu_irqs       = omap2_timer9_mpu_irqs,
 980         .main_clk       = "gpt9_fck",
 981         .prcm           = {
 982                 .omap2 = {
 983                         .prcm_reg_id = 1,
 984                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 985                         .module_offs = OMAP3430_PER_MOD,
 986                         .idlest_reg_id = 1,
 987                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 988                 },
 989         },
 990         .dev_attr       = &capability_pwm_dev_attr,
 991         .slaves         = omap3xxx_timer9_slaves,
 992         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 993         .class          = &omap3xxx_timer_hwmod_class,
 994 };
 995
 996 /* timer10 */
 997 static struct omap_hwmod omap3xxx_timer10_hwmod;
 998
 999 /* l4_core -> timer10 */
1000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1001         .master         = &omap3xxx_l4_core_hwmod,
1002         .slave          = &omap3xxx_timer10_hwmod,
1003         .clk            = "gpt10_ick",
1004         .addr           = omap2_timer10_addrs,
1005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1006 };
1007
1008 /* timer10 slave port */
1009 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1010         &omap3xxx_l4_core__timer10,
1011 };
1012
1013 /* timer10 hwmod */
1014 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1015         .name           = "timer10",
1016         .mpu_irqs       = omap2_timer10_mpu_irqs,
1017         .main_clk       = "gpt10_fck",
1018         .prcm           = {
1019                 .omap2 = {
1020                         .prcm_reg_id = 1,
1021                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1022                         .module_offs = CORE_MOD,
1023                         .idlest_reg_id = 1,
1024                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1025                 },
1026         },
1027         .dev_attr       = &capability_pwm_dev_attr,
1028         .slaves         = omap3xxx_timer10_slaves,
1029         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1030         .class          = &omap3xxx_timer_1ms_hwmod_class,
1031 };
1032
1033 /* timer11 */
1034 static struct omap_hwmod omap3xxx_timer11_hwmod;
1035
1036 /* l4_core -> timer11 */
1037 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1038         .master         = &omap3xxx_l4_core_hwmod,
1039         .slave          = &omap3xxx_timer11_hwmod,
1040         .clk            = "gpt11_ick",
1041         .addr           = omap2_timer11_addrs,
1042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1043 };
1044
1045 /* timer11 slave port */
1046 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1047         &omap3xxx_l4_core__timer11,
1048 };
1049
1050 /* timer11 hwmod */
1051 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1052         .name           = "timer11",
1053         .mpu_irqs       = omap2_timer11_mpu_irqs,
1054         .main_clk       = "gpt11_fck",
1055         .prcm           = {
1056                 .omap2 = {
1057                         .prcm_reg_id = 1,
1058                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1059                         .module_offs = CORE_MOD,
1060                         .idlest_reg_id = 1,
1061                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1062                 },
1063         },
1064         .dev_attr       = &capability_pwm_dev_attr,
1065         .slaves         = omap3xxx_timer11_slaves,
1066         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1067         .class          = &omap3xxx_timer_hwmod_class,
1068 };
1069
1070 /* timer12*/
1071 static struct omap_hwmod omap3xxx_timer12_hwmod;
1072 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1073         { .irq = 95, },
1074         { .irq = -1 }
1075 };
1076
1077 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1078         {
1079                 .pa_start       = 0x48304000,
1080                 .pa_end         = 0x48304000 + SZ_1K - 1,
1081                 .flags          = ADDR_TYPE_RT
1082         },
1083         { }
1084 };
1085
1086 /* l4_core -> timer12 */
1087 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1088         .master         = &omap3xxx_l4_core_hwmod,
1089         .slave          = &omap3xxx_timer12_hwmod,
1090         .clk            = "gpt12_ick",
1091         .addr           = omap3xxx_timer12_addrs,
1092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1093 };
1094
1095 /* timer12 slave port */
1096 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1097         &omap3xxx_l4_core__timer12,
1098 };
1099
1100 /* timer12 hwmod */
1101 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1102         .name           = "timer12",
1103         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1104         .main_clk       = "gpt12_fck",
1105         .prcm           = {
1106                 .omap2 = {
1107                         .prcm_reg_id = 1,
1108                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1109                         .module_offs = WKUP_MOD,
1110                         .idlest_reg_id = 1,
1111                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1112                 },
1113         },
1114         .dev_attr       = &capability_secure_dev_attr,
1115         .slaves         = omap3xxx_timer12_slaves,
1116         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1117         .class          = &omap3xxx_timer_hwmod_class,
1118 };
1119
1120 /* l4_wkup -> wd_timer2 */
1121 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1122         {
1123                 .pa_start       = 0x48314000,
1124                 .pa_end         = 0x4831407f,
1125                 .flags          = ADDR_TYPE_RT
1126         },
1127         { }
1128 };
1129
1130 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1131         .master         = &omap3xxx_l4_wkup_hwmod,
1132         .slave          = &omap3xxx_wd_timer2_hwmod,
1133         .clk            = "wdt2_ick",
1134         .addr           = omap3xxx_wd_timer2_addrs,
1135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1136 };
1137
1138 /*
1139  * 'wd_timer' class
1140  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1141  * overflow condition
1142  */
1143
1144 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1145         .rev_offs       = 0x0000,
1146         .sysc_offs      = 0x0010,
1147         .syss_offs      = 0x0014,
1148         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1149                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1150                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1151                            SYSS_HAS_RESET_STATUS),
1152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1153         .sysc_fields    = &omap_hwmod_sysc_type1,
1154 };
1155
1156 /* I2C common */
1157 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1158         .rev_offs       = 0x00,
1159         .sysc_offs      = 0x20,
1160         .syss_offs      = 0x10,
1161         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1162                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1163                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1165         .sysc_fields    = &omap_hwmod_sysc_type1,
1166 };
1167
1168 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1169         .name           = "wd_timer",
1170         .sysc           = &omap3xxx_wd_timer_sysc,
1171         .pre_shutdown   = &omap2_wd_timer_disable
1172 };
1173
1174 /* wd_timer2 */
1175 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1176         &omap3xxx_l4_wkup__wd_timer2,
1177 };
1178
1179 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1180         .name           = "wd_timer2",
1181         .class          = &omap3xxx_wd_timer_hwmod_class,
1182         .main_clk       = "wdt2_fck",
1183         .prcm           = {
1184                 .omap2 = {
1185                         .prcm_reg_id = 1,
1186                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1187                         .module_offs = WKUP_MOD,
1188                         .idlest_reg_id = 1,
1189                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1190                 },
1191         },
1192         .slaves         = omap3xxx_wd_timer2_slaves,
1193         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1194         /*
1195          * XXX: Use software supervised mode, HW supervised smartidle seems to
1196          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1197          */
1198         .flags          = HWMOD_SWSUP_SIDLE,
1199 };
1200
1201 /* UART1 */
1202
1203 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1204         &omap3_l4_core__uart1,
1205 };
1206
1207 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1208         .name           = "uart1",
1209         .mpu_irqs       = omap2_uart1_mpu_irqs,
1210         .sdma_reqs      = omap2_uart1_sdma_reqs,
1211         .main_clk       = "uart1_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .module_offs = CORE_MOD,
1215                         .prcm_reg_id = 1,
1216                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_uart1_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1223         .class          = &omap2_uart_class,
1224 };
1225
1226 /* UART2 */
1227
1228 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1229         &omap3_l4_core__uart2,
1230 };
1231
1232 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1233         .name           = "uart2",
1234         .mpu_irqs       = omap2_uart2_mpu_irqs,
1235         .sdma_reqs      = omap2_uart2_sdma_reqs,
1236         .main_clk       = "uart2_fck",
1237         .prcm           = {
1238                 .omap2 = {
1239                         .module_offs = CORE_MOD,
1240                         .prcm_reg_id = 1,
1241                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1242                         .idlest_reg_id = 1,
1243                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1244                 },
1245         },
1246         .slaves         = omap3xxx_uart2_slaves,
1247         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1248         .class          = &omap2_uart_class,
1249 };
1250
1251 /* UART3 */
1252
1253 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1254         &omap3_l4_per__uart3,
1255 };
1256
1257 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1258         .name           = "uart3",
1259         .mpu_irqs       = omap2_uart3_mpu_irqs,
1260         .sdma_reqs      = omap2_uart3_sdma_reqs,
1261         .main_clk       = "uart3_fck",
1262         .prcm           = {
1263                 .omap2 = {
1264                         .module_offs = OMAP3430_PER_MOD,
1265                         .prcm_reg_id = 1,
1266                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1267                         .idlest_reg_id = 1,
1268                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1269                 },
1270         },
1271         .slaves         = omap3xxx_uart3_slaves,
1272         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1273         .class          = &omap2_uart_class,
1274 };
1275
1276 /* UART4 */
1277
1278 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1279         { .irq = INT_36XX_UART4_IRQ, },
1280         { .irq = -1 }
1281 };
1282
1283 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1284         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1285         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1286         { .dma_req = -1 }
1287 };
1288
1289 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1290         &omap3_l4_per__uart4,
1291 };
1292
1293 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1294         .name           = "uart4",
1295         .mpu_irqs       = uart4_mpu_irqs,
1296         .sdma_reqs      = uart4_sdma_reqs,
1297         .main_clk       = "uart4_fck",
1298         .prcm           = {
1299                 .omap2 = {
1300                         .module_offs = OMAP3430_PER_MOD,
1301                         .prcm_reg_id = 1,
1302                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1303                         .idlest_reg_id = 1,
1304                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1305                 },
1306         },
1307         .slaves         = omap3xxx_uart4_slaves,
1308         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1309         .class          = &omap2_uart_class,
1310 };
1311
1312 static struct omap_hwmod_class i2c_class = {
1313         .name   = "i2c",
1314         .sysc   = &i2c_sysc,
1315         .rev    = OMAP_I2C_IP_VERSION_1,
1316         .reset  = &omap_i2c_reset,
1317 };
1318
1319 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1320         { .name = "dispc", .dma_req = 5 },
1321         { .name = "dsi1", .dma_req = 74 },
1322         { .dma_req = -1 }
1323 };
1324
1325 /* dss */
1326 /* dss master ports */
1327 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1328         &omap3xxx_dss__l3,
1329 };
1330
1331 /* l4_core -> dss */
1332 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1333         .master         = &omap3xxx_l4_core_hwmod,
1334         .slave          = &omap3430es1_dss_core_hwmod,
1335         .clk            = "dss_ick",
1336         .addr           = omap2_dss_addrs,
1337         .fw = {
1338                 .omap2 = {
1339                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1340                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1341                         .flags  = OMAP_FIREWALL_L4,
1342                 }
1343         },
1344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1345 };
1346
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1348         .master         = &omap3xxx_l4_core_hwmod,
1349         .slave          = &omap3xxx_dss_core_hwmod,
1350         .clk            = "dss_ick",
1351         .addr           = omap2_dss_addrs,
1352         .fw = {
1353                 .omap2 = {
1354                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1355                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1356                         .flags  = OMAP_FIREWALL_L4,
1357                 }
1358         },
1359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1360 };
1361
1362 /* dss slave ports */
1363 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1364         &omap3430es1_l4_core__dss,
1365 };
1366
1367 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1368         &omap3xxx_l4_core__dss,
1369 };
1370
1371 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372         /*
1373          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374          * driver does not use these clocks.
1375          */
1376         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377         { .role = "tv_clk", .clk = "dss_tv_fck" },
1378         /* required only on OMAP3430 */
1379         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1380 };
1381
1382 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1383         .name           = "dss_core",
1384         .class          = &omap2_dss_hwmod_class,
1385         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1386         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1387         .prcm           = {
1388                 .omap2 = {
1389                         .prcm_reg_id = 1,
1390                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1391                         .module_offs = OMAP3430_DSS_MOD,
1392                         .idlest_reg_id = 1,
1393                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1394                 },
1395         },
1396         .opt_clks       = dss_opt_clks,
1397         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1398         .slaves         = omap3430es1_dss_slaves,
1399         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1400         .masters        = omap3xxx_dss_masters,
1401         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1402         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1403 };
1404
1405 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1406         .name           = "dss_core",
1407         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1408         .class          = &omap2_dss_hwmod_class,
1409         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1410         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1411         .prcm           = {
1412                 .omap2 = {
1413                         .prcm_reg_id = 1,
1414                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1415                         .module_offs = OMAP3430_DSS_MOD,
1416                         .idlest_reg_id = 1,
1417                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1418                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1419                 },
1420         },
1421         .opt_clks       = dss_opt_clks,
1422         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1423         .slaves         = omap3xxx_dss_slaves,
1424         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1425         .masters        = omap3xxx_dss_masters,
1426         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1427 };
1428
1429 /*
1430  * 'dispc' class
1431  * display controller
1432  */
1433
1434 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1435         .rev_offs       = 0x0000,
1436         .sysc_offs      = 0x0010,
1437         .syss_offs      = 0x0014,
1438         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1439                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1440                            SYSC_HAS_ENAWAKEUP),
1441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1442                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1443         .sysc_fields    = &omap_hwmod_sysc_type1,
1444 };
1445
1446 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1447         .name   = "dispc",
1448         .sysc   = &omap3_dispc_sysc,
1449 };
1450
1451 /* l4_core -> dss_dispc */
1452 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1453         .master         = &omap3xxx_l4_core_hwmod,
1454         .slave          = &omap3xxx_dss_dispc_hwmod,
1455         .clk            = "dss_ick",
1456         .addr           = omap2_dss_dispc_addrs,
1457         .fw = {
1458                 .omap2 = {
1459                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1460                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1461                         .flags  = OMAP_FIREWALL_L4,
1462                 }
1463         },
1464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1465 };
1466
1467 /* dss_dispc slave ports */
1468 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1469         &omap3xxx_l4_core__dss_dispc,
1470 };
1471
1472 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1473         .name           = "dss_dispc",
1474         .class          = &omap3_dispc_hwmod_class,
1475         .mpu_irqs       = omap2_dispc_irqs,
1476         .main_clk       = "dss1_alwon_fck",
1477         .prcm           = {
1478                 .omap2 = {
1479                         .prcm_reg_id = 1,
1480                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1481                         .module_offs = OMAP3430_DSS_MOD,
1482                 },
1483         },
1484         .slaves         = omap3xxx_dss_dispc_slaves,
1485         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1486         .flags          = HWMOD_NO_IDLEST,
1487         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1488 };
1489
1490 /*
1491  * 'dsi' class
1492  * display serial interface controller
1493  */
1494
1495 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1496         .name = "dsi",
1497 };
1498
1499 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1500         { .irq = 25 },
1501         { .irq = -1 }
1502 };
1503
1504 /* dss_dsi1 */
1505 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1506         {
1507                 .pa_start       = 0x4804FC00,
1508                 .pa_end         = 0x4804FFFF,
1509                 .flags          = ADDR_TYPE_RT
1510         },
1511         { }
1512 };
1513
1514 /* l4_core -> dss_dsi1 */
1515 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1516         .master         = &omap3xxx_l4_core_hwmod,
1517         .slave          = &omap3xxx_dss_dsi1_hwmod,
1518         .clk            = "dss_ick",
1519         .addr           = omap3xxx_dss_dsi1_addrs,
1520         .fw = {
1521                 .omap2 = {
1522                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1523                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1524                         .flags  = OMAP_FIREWALL_L4,
1525                 }
1526         },
1527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1528 };
1529
1530 /* dss_dsi1 slave ports */
1531 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1532         &omap3xxx_l4_core__dss_dsi1,
1533 };
1534
1535 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1536         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1537 };
1538
1539 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1540         .name           = "dss_dsi1",
1541         .class          = &omap3xxx_dsi_hwmod_class,
1542         .mpu_irqs       = omap3xxx_dsi1_irqs,
1543         .main_clk       = "dss1_alwon_fck",
1544         .prcm           = {
1545                 .omap2 = {
1546                         .prcm_reg_id = 1,
1547                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1548                         .module_offs = OMAP3430_DSS_MOD,
1549                 },
1550         },
1551         .opt_clks       = dss_dsi1_opt_clks,
1552         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1553         .slaves         = omap3xxx_dss_dsi1_slaves,
1554         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1555         .flags          = HWMOD_NO_IDLEST,
1556 };
1557
1558 /* l4_core -> dss_rfbi */
1559 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1560         .master         = &omap3xxx_l4_core_hwmod,
1561         .slave          = &omap3xxx_dss_rfbi_hwmod,
1562         .clk            = "dss_ick",
1563         .addr           = omap2_dss_rfbi_addrs,
1564         .fw = {
1565                 .omap2 = {
1566                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1567                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1568                         .flags  = OMAP_FIREWALL_L4,
1569                 }
1570         },
1571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1572 };
1573
1574 /* dss_rfbi slave ports */
1575 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1576         &omap3xxx_l4_core__dss_rfbi,
1577 };
1578
1579 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1580         { .role = "ick", .clk = "dss_ick" },
1581 };
1582
1583 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1584         .name           = "dss_rfbi",
1585         .class          = &omap2_rfbi_hwmod_class,
1586         .main_clk       = "dss1_alwon_fck",
1587         .prcm           = {
1588                 .omap2 = {
1589                         .prcm_reg_id = 1,
1590                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1591                         .module_offs = OMAP3430_DSS_MOD,
1592                 },
1593         },
1594         .opt_clks       = dss_rfbi_opt_clks,
1595         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1596         .slaves         = omap3xxx_dss_rfbi_slaves,
1597         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1598         .flags          = HWMOD_NO_IDLEST,
1599 };
1600
1601 /* l4_core -> dss_venc */
1602 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1603         .master         = &omap3xxx_l4_core_hwmod,
1604         .slave          = &omap3xxx_dss_venc_hwmod,
1605         .clk            = "dss_ick",
1606         .addr           = omap2_dss_venc_addrs,
1607         .fw = {
1608                 .omap2 = {
1609                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1610                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1611                         .flags  = OMAP_FIREWALL_L4,
1612                 }
1613         },
1614         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1615 };
1616
1617 /* dss_venc slave ports */
1618 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1619         &omap3xxx_l4_core__dss_venc,
1620 };
1621
1622 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1623         /* required only on OMAP3430 */
1624         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1625 };
1626
1627 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1628         .name           = "dss_venc",
1629         .class          = &omap2_venc_hwmod_class,
1630         .main_clk       = "dss_tv_fck",
1631         .prcm           = {
1632                 .omap2 = {
1633                         .prcm_reg_id = 1,
1634                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1635                         .module_offs = OMAP3430_DSS_MOD,
1636                 },
1637         },
1638         .opt_clks       = dss_venc_opt_clks,
1639         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1640         .slaves         = omap3xxx_dss_venc_slaves,
1641         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1642         .flags          = HWMOD_NO_IDLEST,
1643 };
1644
1645 /* I2C1 */
1646
1647 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1648         .fifo_depth     = 8, /* bytes */
1649         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1650                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1651                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1652 };
1653
1654 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1655         &omap3_l4_core__i2c1,
1656 };
1657
1658 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1659         .name           = "i2c1",
1660         .flags          = HWMOD_16BIT_REG,
1661         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1662         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1663         .main_clk       = "i2c1_fck",
1664         .prcm           = {
1665                 .omap2 = {
1666                         .module_offs = CORE_MOD,
1667                         .prcm_reg_id = 1,
1668                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1669                         .idlest_reg_id = 1,
1670                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1671                 },
1672         },
1673         .slaves         = omap3xxx_i2c1_slaves,
1674         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1675         .class          = &i2c_class,
1676         .dev_attr       = &i2c1_dev_attr,
1677 };
1678
1679 /* I2C2 */
1680
1681 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1682         .fifo_depth     = 8, /* bytes */
1683         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1684                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1685                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1686 };
1687
1688 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1689         &omap3_l4_core__i2c2,
1690 };
1691
1692 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1693         .name           = "i2c2",
1694         .flags          = HWMOD_16BIT_REG,
1695         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1696         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1697         .main_clk       = "i2c2_fck",
1698         .prcm           = {
1699                 .omap2 = {
1700                         .module_offs = CORE_MOD,
1701                         .prcm_reg_id = 1,
1702                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1703                         .idlest_reg_id = 1,
1704                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1705                 },
1706         },
1707         .slaves         = omap3xxx_i2c2_slaves,
1708         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1709         .class          = &i2c_class,
1710         .dev_attr       = &i2c2_dev_attr,
1711 };
1712
1713 /* I2C3 */
1714
1715 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1716         .fifo_depth     = 64, /* bytes */
1717         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1718                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1719                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1720 };
1721
1722 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1723         { .irq = INT_34XX_I2C3_IRQ, },
1724         { .irq = -1 }
1725 };
1726
1727 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1728         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1729         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1730         { .dma_req = -1 }
1731 };
1732
1733 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1734         &omap3_l4_core__i2c3,
1735 };
1736
1737 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1738         .name           = "i2c3",
1739         .flags          = HWMOD_16BIT_REG,
1740         .mpu_irqs       = i2c3_mpu_irqs,
1741         .sdma_reqs      = i2c3_sdma_reqs,
1742         .main_clk       = "i2c3_fck",
1743         .prcm           = {
1744                 .omap2 = {
1745                         .module_offs = CORE_MOD,
1746                         .prcm_reg_id = 1,
1747                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1748                         .idlest_reg_id = 1,
1749                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1750                 },
1751         },
1752         .slaves         = omap3xxx_i2c3_slaves,
1753         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1754         .class          = &i2c_class,
1755         .dev_attr       = &i2c3_dev_attr,
1756 };
1757
1758 /* l4_wkup -> gpio1 */
1759 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1760         {
1761                 .pa_start       = 0x48310000,
1762                 .pa_end         = 0x483101ff,
1763                 .flags          = ADDR_TYPE_RT
1764         },
1765         { }
1766 };
1767
1768 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1769         .master         = &omap3xxx_l4_wkup_hwmod,
1770         .slave          = &omap3xxx_gpio1_hwmod,
1771         .addr           = omap3xxx_gpio1_addrs,
1772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1773 };
1774
1775 /* l4_per -> gpio2 */
1776 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1777         {
1778                 .pa_start       = 0x49050000,
1779                 .pa_end         = 0x490501ff,
1780                 .flags          = ADDR_TYPE_RT
1781         },
1782         { }
1783 };
1784
1785 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1786         .master         = &omap3xxx_l4_per_hwmod,
1787         .slave          = &omap3xxx_gpio2_hwmod,
1788         .addr           = omap3xxx_gpio2_addrs,
1789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1790 };
1791
1792 /* l4_per -> gpio3 */
1793 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1794         {
1795                 .pa_start       = 0x49052000,
1796                 .pa_end         = 0x490521ff,
1797                 .flags          = ADDR_TYPE_RT
1798         },
1799         { }
1800 };
1801
1802 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1803         .master         = &omap3xxx_l4_per_hwmod,
1804         .slave          = &omap3xxx_gpio3_hwmod,
1805         .addr           = omap3xxx_gpio3_addrs,
1806         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1807 };
1808
1809 /* l4_per -> gpio4 */
1810 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1811         {
1812                 .pa_start       = 0x49054000,
1813                 .pa_end         = 0x490541ff,
1814                 .flags          = ADDR_TYPE_RT
1815         },
1816         { }
1817 };
1818
1819 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1820         .master         = &omap3xxx_l4_per_hwmod,
1821         .slave          = &omap3xxx_gpio4_hwmod,
1822         .addr           = omap3xxx_gpio4_addrs,
1823         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1824 };
1825
1826 /* l4_per -> gpio5 */
1827 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1828         {
1829                 .pa_start       = 0x49056000,
1830                 .pa_end         = 0x490561ff,
1831                 .flags          = ADDR_TYPE_RT
1832         },
1833         { }
1834 };
1835
1836 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1837         .master         = &omap3xxx_l4_per_hwmod,
1838         .slave          = &omap3xxx_gpio5_hwmod,
1839         .addr           = omap3xxx_gpio5_addrs,
1840         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1841 };
1842
1843 /* l4_per -> gpio6 */
1844 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1845         {
1846                 .pa_start       = 0x49058000,
1847                 .pa_end         = 0x490581ff,
1848                 .flags          = ADDR_TYPE_RT
1849         },
1850         { }
1851 };
1852
1853 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1854         .master         = &omap3xxx_l4_per_hwmod,
1855         .slave          = &omap3xxx_gpio6_hwmod,
1856         .addr           = omap3xxx_gpio6_addrs,
1857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1858 };
1859
1860 /*
1861  * 'gpio' class
1862  * general purpose io module
1863  */
1864
1865 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1866         .rev_offs       = 0x0000,
1867         .sysc_offs      = 0x0010,
1868         .syss_offs      = 0x0014,
1869         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1870                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1871                            SYSS_HAS_RESET_STATUS),
1872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1873         .sysc_fields    = &omap_hwmod_sysc_type1,
1874 };
1875
1876 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1877         .name = "gpio",
1878         .sysc = &omap3xxx_gpio_sysc,
1879         .rev = 1,
1880 };
1881
1882 /* gpio_dev_attr*/
1883 static struct omap_gpio_dev_attr gpio_dev_attr = {
1884         .bank_width = 32,
1885         .dbck_flag = true,
1886 };
1887
1888 /* gpio1 */
1889 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1890         { .role = "dbclk", .clk = "gpio1_dbck", },
1891 };
1892
1893 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1894         &omap3xxx_l4_wkup__gpio1,
1895 };
1896
1897 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1898         .name           = "gpio1",
1899         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1900         .mpu_irqs       = omap2_gpio1_irqs,
1901         .main_clk       = "gpio1_ick",
1902         .opt_clks       = gpio1_opt_clks,
1903         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1904         .prcm           = {
1905                 .omap2 = {
1906                         .prcm_reg_id = 1,
1907                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1908                         .module_offs = WKUP_MOD,
1909                         .idlest_reg_id = 1,
1910                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1911                 },
1912         },
1913         .slaves         = omap3xxx_gpio1_slaves,
1914         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1915         .class          = &omap3xxx_gpio_hwmod_class,
1916         .dev_attr       = &gpio_dev_attr,
1917 };
1918
1919 /* gpio2 */
1920 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1921         { .role = "dbclk", .clk = "gpio2_dbck", },
1922 };
1923
1924 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1925         &omap3xxx_l4_per__gpio2,
1926 };
1927
1928 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1929         .name           = "gpio2",
1930         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1931         .mpu_irqs       = omap2_gpio2_irqs,
1932         .main_clk       = "gpio2_ick",
1933         .opt_clks       = gpio2_opt_clks,
1934         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1935         .prcm           = {
1936                 .omap2 = {
1937                         .prcm_reg_id = 1,
1938                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1939                         .module_offs = OMAP3430_PER_MOD,
1940                         .idlest_reg_id = 1,
1941                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1942                 },
1943         },
1944         .slaves         = omap3xxx_gpio2_slaves,
1945         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1946         .class          = &omap3xxx_gpio_hwmod_class,
1947         .dev_attr       = &gpio_dev_attr,
1948 };
1949
1950 /* gpio3 */
1951 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1952         { .role = "dbclk", .clk = "gpio3_dbck", },
1953 };
1954
1955 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1956         &omap3xxx_l4_per__gpio3,
1957 };
1958
1959 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1960         .name           = "gpio3",
1961         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1962         .mpu_irqs       = omap2_gpio3_irqs,
1963         .main_clk       = "gpio3_ick",
1964         .opt_clks       = gpio3_opt_clks,
1965         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1966         .prcm           = {
1967                 .omap2 = {
1968                         .prcm_reg_id = 1,
1969                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1970                         .module_offs = OMAP3430_PER_MOD,
1971                         .idlest_reg_id = 1,
1972                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1973                 },
1974         },
1975         .slaves         = omap3xxx_gpio3_slaves,
1976         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1977         .class          = &omap3xxx_gpio_hwmod_class,
1978         .dev_attr       = &gpio_dev_attr,
1979 };
1980
1981 /* gpio4 */
1982 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1983         { .role = "dbclk", .clk = "gpio4_dbck", },
1984 };
1985
1986 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1987         &omap3xxx_l4_per__gpio4,
1988 };
1989
1990 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1991         .name           = "gpio4",
1992         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1993         .mpu_irqs       = omap2_gpio4_irqs,
1994         .main_clk       = "gpio4_ick",
1995         .opt_clks       = gpio4_opt_clks,
1996         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1997         .prcm           = {
1998                 .omap2 = {
1999                         .prcm_reg_id = 1,
2000                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2001                         .module_offs = OMAP3430_PER_MOD,
2002                         .idlest_reg_id = 1,
2003                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2004                 },
2005         },
2006         .slaves         = omap3xxx_gpio4_slaves,
2007         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2008         .class          = &omap3xxx_gpio_hwmod_class,
2009         .dev_attr       = &gpio_dev_attr,
2010 };
2011
2012 /* gpio5 */
2013 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2014         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2015         { .irq = -1 }
2016 };
2017
2018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2019         { .role = "dbclk", .clk = "gpio5_dbck", },
2020 };
2021
2022 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2023         &omap3xxx_l4_per__gpio5,
2024 };
2025
2026 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2027         .name           = "gpio5",
2028         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2029         .mpu_irqs       = omap3xxx_gpio5_irqs,
2030         .main_clk       = "gpio5_ick",
2031         .opt_clks       = gpio5_opt_clks,
2032         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2033         .prcm           = {
2034                 .omap2 = {
2035                         .prcm_reg_id = 1,
2036                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2037                         .module_offs = OMAP3430_PER_MOD,
2038                         .idlest_reg_id = 1,
2039                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2040                 },
2041         },
2042         .slaves         = omap3xxx_gpio5_slaves,
2043         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2044         .class          = &omap3xxx_gpio_hwmod_class,
2045         .dev_attr       = &gpio_dev_attr,
2046 };
2047
2048 /* gpio6 */
2049 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2050         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2051         { .irq = -1 }
2052 };
2053
2054 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2055         { .role = "dbclk", .clk = "gpio6_dbck", },
2056 };
2057
2058 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2059         &omap3xxx_l4_per__gpio6,
2060 };
2061
2062 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2063         .name           = "gpio6",
2064         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2065         .mpu_irqs       = omap3xxx_gpio6_irqs,
2066         .main_clk       = "gpio6_ick",
2067         .opt_clks       = gpio6_opt_clks,
2068         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2069         .prcm           = {
2070                 .omap2 = {
2071                         .prcm_reg_id = 1,
2072                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2073                         .module_offs = OMAP3430_PER_MOD,
2074                         .idlest_reg_id = 1,
2075                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2076                 },
2077         },
2078         .slaves         = omap3xxx_gpio6_slaves,
2079         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2080         .class          = &omap3xxx_gpio_hwmod_class,
2081         .dev_attr       = &gpio_dev_attr,
2082 };
2083
2084 /* dma_system -> L3 */
2085 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2086         .master         = &omap3xxx_dma_system_hwmod,
2087         .slave          = &omap3xxx_l3_main_hwmod,
2088         .clk            = "core_l3_ick",
2089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2090 };
2091
2092 /* dma attributes */
2093 static struct omap_dma_dev_attr dma_dev_attr = {
2094         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2095                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2096         .lch_count = 32,
2097 };
2098
2099 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x002c,
2102         .syss_offs      = 0x0028,
2103         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2104                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2105                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2106                            SYSS_HAS_RESET_STATUS),
2107         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2108                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2109         .sysc_fields    = &omap_hwmod_sysc_type1,
2110 };
2111
2112 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2113         .name = "dma",
2114         .sysc = &omap3xxx_dma_sysc,
2115 };
2116
2117 /* dma_system */
2118 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2119         {
2120                 .pa_start       = 0x48056000,
2121                 .pa_end         = 0x48056fff,
2122                 .flags          = ADDR_TYPE_RT
2123         },
2124         { }
2125 };
2126
2127 /* dma_system master ports */
2128 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2129         &omap3xxx_dma_system__l3,
2130 };
2131
2132 /* l4_cfg -> dma_system */
2133 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2134         .master         = &omap3xxx_l4_core_hwmod,
2135         .slave          = &omap3xxx_dma_system_hwmod,
2136         .clk            = "core_l4_ick",
2137         .addr           = omap3xxx_dma_system_addrs,
2138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2139 };
2140
2141 /* dma_system slave ports */
2142 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2143         &omap3xxx_l4_core__dma_system,
2144 };
2145
2146 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2147         .name           = "dma",
2148         .class          = &omap3xxx_dma_hwmod_class,
2149         .mpu_irqs       = omap2_dma_system_irqs,
2150         .main_clk       = "core_l3_ick",
2151         .prcm = {
2152                 .omap2 = {
2153                         .module_offs            = CORE_MOD,
2154                         .prcm_reg_id            = 1,
2155                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2156                         .idlest_reg_id          = 1,
2157                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2158                 },
2159         },
2160         .slaves         = omap3xxx_dma_system_slaves,
2161         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2162         .masters        = omap3xxx_dma_system_masters,
2163         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2164         .dev_attr       = &dma_dev_attr,
2165         .flags          = HWMOD_NO_IDLEST,
2166 };
2167
2168 /*
2169  * 'mcbsp' class
2170  * multi channel buffered serial port controller
2171  */
2172
2173 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2174         .sysc_offs      = 0x008c,
2175         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2176                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2177         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2178         .sysc_fields    = &omap_hwmod_sysc_type1,
2179         .clockact       = 0x2,
2180 };
2181
2182 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2183         .name = "mcbsp",
2184         .sysc = &omap3xxx_mcbsp_sysc,
2185         .rev  = MCBSP_CONFIG_TYPE3,
2186 };
2187
2188 /* mcbsp1 */
2189 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2190         { .name = "irq", .irq = 16 },
2191         { .name = "tx", .irq = 59 },
2192         { .name = "rx", .irq = 60 },
2193         { .irq = -1 }
2194 };
2195
2196 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2197         {
2198                 .name           = "mpu",
2199                 .pa_start       = 0x48074000,
2200                 .pa_end         = 0x480740ff,
2201                 .flags          = ADDR_TYPE_RT
2202         },
2203         { }
2204 };
2205
2206 /* l4_core -> mcbsp1 */
2207 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2208         .master         = &omap3xxx_l4_core_hwmod,
2209         .slave          = &omap3xxx_mcbsp1_hwmod,
2210         .clk            = "mcbsp1_ick",
2211         .addr           = omap3xxx_mcbsp1_addrs,
2212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2213 };
2214
2215 /* mcbsp1 slave ports */
2216 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2217         &omap3xxx_l4_core__mcbsp1,
2218 };
2219
2220 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2221         .name           = "mcbsp1",
2222         .class          = &omap3xxx_mcbsp_hwmod_class,
2223         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2224         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2225         .main_clk       = "mcbsp1_fck",
2226         .prcm           = {
2227                 .omap2 = {
2228                         .prcm_reg_id = 1,
2229                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2230                         .module_offs = CORE_MOD,
2231                         .idlest_reg_id = 1,
2232                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2233                 },
2234         },
2235         .slaves         = omap3xxx_mcbsp1_slaves,
2236         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2237 };
2238
2239 /* mcbsp2 */
2240 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2241         { .name = "irq", .irq = 17 },
2242         { .name = "tx", .irq = 62 },
2243         { .name = "rx", .irq = 63 },
2244         { .irq = -1 }
2245 };
2246
2247 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2248         {
2249                 .name           = "mpu",
2250                 .pa_start       = 0x49022000,
2251                 .pa_end         = 0x490220ff,
2252                 .flags          = ADDR_TYPE_RT
2253         },
2254         { }
2255 };
2256
2257 /* l4_per -> mcbsp2 */
2258 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2259         .master         = &omap3xxx_l4_per_hwmod,
2260         .slave          = &omap3xxx_mcbsp2_hwmod,
2261         .clk            = "mcbsp2_ick",
2262         .addr           = omap3xxx_mcbsp2_addrs,
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* mcbsp2 slave ports */
2267 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2268         &omap3xxx_l4_per__mcbsp2,
2269 };
2270
2271 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2272         .sidetone       = "mcbsp2_sidetone",
2273 };
2274
2275 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2276         .name           = "mcbsp2",
2277         .class          = &omap3xxx_mcbsp_hwmod_class,
2278         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2279         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2280         .main_clk       = "mcbsp2_fck",
2281         .prcm           = {
2282                 .omap2 = {
2283                         .prcm_reg_id = 1,
2284                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2285                         .module_offs = OMAP3430_PER_MOD,
2286                         .idlest_reg_id = 1,
2287                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2288                 },
2289         },
2290         .slaves         = omap3xxx_mcbsp2_slaves,
2291         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2292         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2293 };
2294
2295 /* mcbsp3 */
2296 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2297         { .name = "irq", .irq = 22 },
2298         { .name = "tx", .irq = 89 },
2299         { .name = "rx", .irq = 90 },
2300         { .irq = -1 }
2301 };
2302
2303 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2304         {
2305                 .name           = "mpu",
2306                 .pa_start       = 0x49024000,
2307                 .pa_end         = 0x490240ff,
2308                 .flags          = ADDR_TYPE_RT
2309         },
2310         { }
2311 };
2312
2313 /* l4_per -> mcbsp3 */
2314 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2315         .master         = &omap3xxx_l4_per_hwmod,
2316         .slave          = &omap3xxx_mcbsp3_hwmod,
2317         .clk            = "mcbsp3_ick",
2318         .addr           = omap3xxx_mcbsp3_addrs,
2319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 /* mcbsp3 slave ports */
2323 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2324         &omap3xxx_l4_per__mcbsp3,
2325 };
2326
2327 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2328         .sidetone       = "mcbsp3_sidetone",
2329 };
2330
2331 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2332         .name           = "mcbsp3",
2333         .class          = &omap3xxx_mcbsp_hwmod_class,
2334         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2335         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2336         .main_clk       = "mcbsp3_fck",
2337         .prcm           = {
2338                 .omap2 = {
2339                         .prcm_reg_id = 1,
2340                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2341                         .module_offs = OMAP3430_PER_MOD,
2342                         .idlest_reg_id = 1,
2343                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2344                 },
2345         },
2346         .slaves         = omap3xxx_mcbsp3_slaves,
2347         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2348         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2349 };
2350
2351 /* mcbsp4 */
2352 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2353         { .name = "irq", .irq = 23 },
2354         { .name = "tx", .irq = 54 },
2355         { .name = "rx", .irq = 55 },
2356         { .irq = -1 }
2357 };
2358
2359 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2360         { .name = "rx", .dma_req = 20 },
2361         { .name = "tx", .dma_req = 19 },
2362         { .dma_req = -1 }
2363 };
2364
2365 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2366         {
2367                 .name           = "mpu",
2368                 .pa_start       = 0x49026000,
2369                 .pa_end         = 0x490260ff,
2370                 .flags          = ADDR_TYPE_RT
2371         },
2372         { }
2373 };
2374
2375 /* l4_per -> mcbsp4 */
2376 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2377         .master         = &omap3xxx_l4_per_hwmod,
2378         .slave          = &omap3xxx_mcbsp4_hwmod,
2379         .clk            = "mcbsp4_ick",
2380         .addr           = omap3xxx_mcbsp4_addrs,
2381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* mcbsp4 slave ports */
2385 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2386         &omap3xxx_l4_per__mcbsp4,
2387 };
2388
2389 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2390         .name           = "mcbsp4",
2391         .class          = &omap3xxx_mcbsp_hwmod_class,
2392         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2393         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2394         .main_clk       = "mcbsp4_fck",
2395         .prcm           = {
2396                 .omap2 = {
2397                         .prcm_reg_id = 1,
2398                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2399                         .module_offs = OMAP3430_PER_MOD,
2400                         .idlest_reg_id = 1,
2401                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2402                 },
2403         },
2404         .slaves         = omap3xxx_mcbsp4_slaves,
2405         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2406 };
2407
2408 /* mcbsp5 */
2409 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2410         { .name = "irq", .irq = 27 },
2411         { .name = "tx", .irq = 81 },
2412         { .name = "rx", .irq = 82 },
2413         { .irq = -1 }
2414 };
2415
2416 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2417         { .name = "rx", .dma_req = 22 },
2418         { .name = "tx", .dma_req = 21 },
2419         { .dma_req = -1 }
2420 };
2421
2422 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2423         {
2424                 .name           = "mpu",
2425                 .pa_start       = 0x48096000,
2426                 .pa_end         = 0x480960ff,
2427                 .flags          = ADDR_TYPE_RT
2428         },
2429         { }
2430 };
2431
2432 /* l4_core -> mcbsp5 */
2433 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2434         .master         = &omap3xxx_l4_core_hwmod,
2435         .slave          = &omap3xxx_mcbsp5_hwmod,
2436         .clk            = "mcbsp5_ick",
2437         .addr           = omap3xxx_mcbsp5_addrs,
2438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2439 };
2440
2441 /* mcbsp5 slave ports */
2442 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2443         &omap3xxx_l4_core__mcbsp5,
2444 };
2445
2446 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2447         .name           = "mcbsp5",
2448         .class          = &omap3xxx_mcbsp_hwmod_class,
2449         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2450         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2451         .main_clk       = "mcbsp5_fck",
2452         .prcm           = {
2453                 .omap2 = {
2454                         .prcm_reg_id = 1,
2455                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2456                         .module_offs = CORE_MOD,
2457                         .idlest_reg_id = 1,
2458                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2459                 },
2460         },
2461         .slaves         = omap3xxx_mcbsp5_slaves,
2462         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2463 };
2464 /* 'mcbsp sidetone' class */
2465
2466 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2467         .sysc_offs      = 0x0010,
2468         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2469         .sysc_fields    = &omap_hwmod_sysc_type1,
2470 };
2471
2472 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2473         .name = "mcbsp_sidetone",
2474         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2475 };
2476
2477 /* mcbsp2_sidetone */
2478 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2479         { .name = "irq", .irq = 4 },
2480         { .irq = -1 }
2481 };
2482
2483 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2484         {
2485                 .name           = "sidetone",
2486                 .pa_start       = 0x49028000,
2487                 .pa_end         = 0x490280ff,
2488                 .flags          = ADDR_TYPE_RT
2489         },
2490         { }
2491 };
2492
2493 /* l4_per -> mcbsp2_sidetone */
2494 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2495         .master         = &omap3xxx_l4_per_hwmod,
2496         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2497         .clk            = "mcbsp2_ick",
2498         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2499         .user           = OCP_USER_MPU,
2500 };
2501
2502 /* mcbsp2_sidetone slave ports */
2503 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2504         &omap3xxx_l4_per__mcbsp2_sidetone,
2505 };
2506
2507 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2508         .name           = "mcbsp2_sidetone",
2509         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2510         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2511         .main_clk       = "mcbsp2_fck",
2512         .prcm           = {
2513                 .omap2 = {
2514                         .prcm_reg_id = 1,
2515                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2516                         .module_offs = OMAP3430_PER_MOD,
2517                         .idlest_reg_id = 1,
2518                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2519                 },
2520         },
2521         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2522         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2523 };
2524
2525 /* mcbsp3_sidetone */
2526 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2527         { .name = "irq", .irq = 5 },
2528         { .irq = -1 }
2529 };
2530
2531 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2532         {
2533                 .name           = "sidetone",
2534                 .pa_start       = 0x4902A000,
2535                 .pa_end         = 0x4902A0ff,
2536                 .flags          = ADDR_TYPE_RT
2537         },
2538         { }
2539 };
2540
2541 /* l4_per -> mcbsp3_sidetone */
2542 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2543         .master         = &omap3xxx_l4_per_hwmod,
2544         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2545         .clk            = "mcbsp3_ick",
2546         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2547         .user           = OCP_USER_MPU,
2548 };
2549
2550 /* mcbsp3_sidetone slave ports */
2551 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2552         &omap3xxx_l4_per__mcbsp3_sidetone,
2553 };
2554
2555 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2556         .name           = "mcbsp3_sidetone",
2557         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2558         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2559         .main_clk       = "mcbsp3_fck",
2560         .prcm           = {
2561                 .omap2 = {
2562                         .prcm_reg_id = 1,
2563                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2564                         .module_offs = OMAP3430_PER_MOD,
2565                         .idlest_reg_id = 1,
2566                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2567                 },
2568         },
2569         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2570         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2571 };
2572
2573
2574 /* SR common */
2575 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2576         .clkact_shift   = 20,
2577 };
2578
2579 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2580         .sysc_offs      = 0x24,
2581         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2582         .clockact       = CLOCKACT_TEST_ICLK,
2583         .sysc_fields    = &omap34xx_sr_sysc_fields,
2584 };
2585
2586 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2587         .name = "smartreflex",
2588         .sysc = &omap34xx_sr_sysc,
2589         .rev  = 1,
2590 };
2591
2592 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2593         .sidle_shift    = 24,
2594         .enwkup_shift   = 26
2595 };
2596
2597 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2598         .sysc_offs      = 0x38,
2599         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2600         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2601                         SYSC_NO_CACHE),
2602         .sysc_fields    = &omap36xx_sr_sysc_fields,
2603 };
2604
2605 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2606         .name = "smartreflex",
2607         .sysc = &omap36xx_sr_sysc,
2608         .rev  = 2,
2609 };
2610
2611 /* SR1 */
2612 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2613         &omap3_l4_core__sr1,
2614 };
2615
2616 static struct omap_hwmod omap34xx_sr1_hwmod = {
2617         .name           = "sr1_hwmod",
2618         .class          = &omap34xx_smartreflex_hwmod_class,
2619         .main_clk       = "sr1_fck",
2620         .vdd_name       = "mpu_iva",
2621         .prcm           = {
2622                 .omap2 = {
2623                         .prcm_reg_id = 1,
2624                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2625                         .module_offs = WKUP_MOD,
2626                         .idlest_reg_id = 1,
2627                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2628                 },
2629         },
2630         .slaves         = omap3_sr1_slaves,
2631         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2632         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2633 };
2634
2635 static struct omap_hwmod omap36xx_sr1_hwmod = {
2636         .name           = "sr1_hwmod",
2637         .class          = &omap36xx_smartreflex_hwmod_class,
2638         .main_clk       = "sr1_fck",
2639         .vdd_name       = "mpu_iva",
2640         .prcm           = {
2641                 .omap2 = {
2642                         .prcm_reg_id = 1,
2643                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2644                         .module_offs = WKUP_MOD,
2645                         .idlest_reg_id = 1,
2646                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2647                 },
2648         },
2649         .slaves         = omap3_sr1_slaves,
2650         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2651 };
2652
2653 /* SR2 */
2654 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2655         &omap3_l4_core__sr2,
2656 };
2657
2658 static struct omap_hwmod omap34xx_sr2_hwmod = {
2659         .name           = "sr2_hwmod",
2660         .class          = &omap34xx_smartreflex_hwmod_class,
2661         .main_clk       = "sr2_fck",
2662         .vdd_name       = "core",
2663         .prcm           = {
2664                 .omap2 = {
2665                         .prcm_reg_id = 1,
2666                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2667                         .module_offs = WKUP_MOD,
2668                         .idlest_reg_id = 1,
2669                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2670                 },
2671         },
2672         .slaves         = omap3_sr2_slaves,
2673         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2674         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2675 };
2676
2677 static struct omap_hwmod omap36xx_sr2_hwmod = {
2678         .name           = "sr2_hwmod",
2679         .class          = &omap36xx_smartreflex_hwmod_class,
2680         .main_clk       = "sr2_fck",
2681         .vdd_name       = "core",
2682         .prcm           = {
2683                 .omap2 = {
2684                         .prcm_reg_id = 1,
2685                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2686                         .module_offs = WKUP_MOD,
2687                         .idlest_reg_id = 1,
2688                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2689                 },
2690         },
2691         .slaves         = omap3_sr2_slaves,
2692         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2693 };
2694
2695 /*
2696  * 'mailbox' class
2697  * mailbox module allowing communication between the on-chip processors
2698  * using a queued mailbox-interrupt mechanism.
2699  */
2700
2701 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2702         .rev_offs       = 0x000,
2703         .sysc_offs      = 0x010,
2704         .syss_offs      = 0x014,
2705         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2706                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2707         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2708         .sysc_fields    = &omap_hwmod_sysc_type1,
2709 };
2710
2711 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2712         .name = "mailbox",
2713         .sysc = &omap3xxx_mailbox_sysc,
2714 };
2715
2716 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2717 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2718         { .irq = 26 },
2719         { .irq = -1 }
2720 };
2721
2722 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2723         {
2724                 .pa_start       = 0x48094000,
2725                 .pa_end         = 0x480941ff,
2726                 .flags          = ADDR_TYPE_RT,
2727         },
2728         { }
2729 };
2730
2731 /* l4_core -> mailbox */
2732 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2733         .master         = &omap3xxx_l4_core_hwmod,
2734         .slave          = &omap3xxx_mailbox_hwmod,
2735         .addr           = omap3xxx_mailbox_addrs,
2736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2737 };
2738
2739 /* mailbox slave ports */
2740 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2741         &omap3xxx_l4_core__mailbox,
2742 };
2743
2744 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2745         .name           = "mailbox",
2746         .class          = &omap3xxx_mailbox_hwmod_class,
2747         .mpu_irqs       = omap3xxx_mailbox_irqs,
2748         .main_clk       = "mailboxes_ick",
2749         .prcm           = {
2750                 .omap2 = {
2751                         .prcm_reg_id = 1,
2752                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2753                         .module_offs = CORE_MOD,
2754                         .idlest_reg_id = 1,
2755                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2756                 },
2757         },
2758         .slaves         = omap3xxx_mailbox_slaves,
2759         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2760 };
2761
2762 /* l4 core -> mcspi1 interface */
2763 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2764         .master         = &omap3xxx_l4_core_hwmod,
2765         .slave          = &omap34xx_mcspi1,
2766         .clk            = "mcspi1_ick",
2767         .addr           = omap2_mcspi1_addr_space,
2768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2769 };
2770
2771 /* l4 core -> mcspi2 interface */
2772 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2773         .master         = &omap3xxx_l4_core_hwmod,
2774         .slave          = &omap34xx_mcspi2,
2775         .clk            = "mcspi2_ick",
2776         .addr           = omap2_mcspi2_addr_space,
2777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2778 };
2779
2780 /* l4 core -> mcspi3 interface */
2781 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2782         .master         = &omap3xxx_l4_core_hwmod,
2783         .slave          = &omap34xx_mcspi3,
2784         .clk            = "mcspi3_ick",
2785         .addr           = omap2430_mcspi3_addr_space,
2786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2787 };
2788
2789 /* l4 core -> mcspi4 interface */
2790 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2791         {
2792                 .pa_start       = 0x480ba000,
2793                 .pa_end         = 0x480ba0ff,
2794                 .flags          = ADDR_TYPE_RT,
2795         },
2796         { }
2797 };
2798
2799 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2800         .master         = &omap3xxx_l4_core_hwmod,
2801         .slave          = &omap34xx_mcspi4,
2802         .clk            = "mcspi4_ick",
2803         .addr           = omap34xx_mcspi4_addr_space,
2804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /*
2808  * 'mcspi' class
2809  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2810  * bus
2811  */
2812
2813 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2814         .rev_offs       = 0x0000,
2815         .sysc_offs      = 0x0010,
2816         .syss_offs      = 0x0014,
2817         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2818                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2819                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2821         .sysc_fields    = &omap_hwmod_sysc_type1,
2822 };
2823
2824 static struct omap_hwmod_class omap34xx_mcspi_class = {
2825         .name = "mcspi",
2826         .sysc = &omap34xx_mcspi_sysc,
2827         .rev = OMAP3_MCSPI_REV,
2828 };
2829
2830 /* mcspi1 */
2831 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2832         &omap34xx_l4_core__mcspi1,
2833 };
2834
2835 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2836         .num_chipselect = 4,
2837 };
2838
2839 static struct omap_hwmod omap34xx_mcspi1 = {
2840         .name           = "mcspi1",
2841         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2842         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2843         .main_clk       = "mcspi1_fck",
2844         .prcm           = {
2845                 .omap2 = {
2846                         .module_offs = CORE_MOD,
2847                         .prcm_reg_id = 1,
2848                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2849                         .idlest_reg_id = 1,
2850                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2851                 },
2852         },
2853         .slaves         = omap34xx_mcspi1_slaves,
2854         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2855         .class          = &omap34xx_mcspi_class,
2856         .dev_attr       = &omap_mcspi1_dev_attr,
2857 };
2858
2859 /* mcspi2 */
2860 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2861         &omap34xx_l4_core__mcspi2,
2862 };
2863
2864 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2865         .num_chipselect = 2,
2866 };
2867
2868 static struct omap_hwmod omap34xx_mcspi2 = {
2869         .name           = "mcspi2",
2870         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2871         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2872         .main_clk       = "mcspi2_fck",
2873         .prcm           = {
2874                 .omap2 = {
2875                         .module_offs = CORE_MOD,
2876                         .prcm_reg_id = 1,
2877                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2878                         .idlest_reg_id = 1,
2879                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2880                 },
2881         },
2882         .slaves         = omap34xx_mcspi2_slaves,
2883         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2884         .class          = &omap34xx_mcspi_class,
2885         .dev_attr       = &omap_mcspi2_dev_attr,
2886 };
2887
2888 /* mcspi3 */
2889 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2890         { .name = "irq", .irq = 91 }, /* 91 */
2891         { .irq = -1 }
2892 };
2893
2894 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2895         { .name = "tx0", .dma_req = 15 },
2896         { .name = "rx0", .dma_req = 16 },
2897         { .name = "tx1", .dma_req = 23 },
2898         { .name = "rx1", .dma_req = 24 },
2899         { .dma_req = -1 }
2900 };
2901
2902 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2903         &omap34xx_l4_core__mcspi3,
2904 };
2905
2906 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2907         .num_chipselect = 2,
2908 };
2909
2910 static struct omap_hwmod omap34xx_mcspi3 = {
2911         .name           = "mcspi3",
2912         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2913         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2914         .main_clk       = "mcspi3_fck",
2915         .prcm           = {
2916                 .omap2 = {
2917                         .module_offs = CORE_MOD,
2918                         .prcm_reg_id = 1,
2919                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2920                         .idlest_reg_id = 1,
2921                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2922                 },
2923         },
2924         .slaves         = omap34xx_mcspi3_slaves,
2925         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2926         .class          = &omap34xx_mcspi_class,
2927         .dev_attr       = &omap_mcspi3_dev_attr,
2928 };
2929
2930 /* SPI4 */
2931 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2932         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2933         { .irq = -1 }
2934 };
2935
2936 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2937         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2938         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2939         { .dma_req = -1 }
2940 };
2941
2942 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2943         &omap34xx_l4_core__mcspi4,
2944 };
2945
2946 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2947         .num_chipselect = 1,
2948 };
2949
2950 static struct omap_hwmod omap34xx_mcspi4 = {
2951         .name           = "mcspi4",
2952         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2953         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2954         .main_clk       = "mcspi4_fck",
2955         .prcm           = {
2956                 .omap2 = {
2957                         .module_offs = CORE_MOD,
2958                         .prcm_reg_id = 1,
2959                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2960                         .idlest_reg_id = 1,
2961                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2962                 },
2963         },
2964         .slaves         = omap34xx_mcspi4_slaves,
2965         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2966         .class          = &omap34xx_mcspi_class,
2967         .dev_attr       = &omap_mcspi4_dev_attr,
2968 };
2969
2970 /*
2971  * usbhsotg
2972  */
2973 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2974         .rev_offs       = 0x0400,
2975         .sysc_offs      = 0x0404,
2976         .syss_offs      = 0x0408,
2977         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2978                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2979                           SYSC_HAS_AUTOIDLE),
2980         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2981                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2982         .sysc_fields    = &omap_hwmod_sysc_type1,
2983 };
2984
2985 static struct omap_hwmod_class usbotg_class = {
2986         .name = "usbotg",
2987         .sysc = &omap3xxx_usbhsotg_sysc,
2988 };
2989 /* usb_otg_hs */
2990 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2991
2992         { .name = "mc", .irq = 92 },
2993         { .name = "dma", .irq = 93 },
2994         { .irq = -1 }
2995 };
2996
2997 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2998         .name           = "usb_otg_hs",
2999         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3000         .main_clk       = "hsotgusb_ick",
3001         .prcm           = {
3002                 .omap2 = {
3003                         .prcm_reg_id = 1,
3004                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3005                         .module_offs = CORE_MOD,
3006                         .idlest_reg_id = 1,
3007                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3008                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3009                 },
3010         },
3011         .masters        = omap3xxx_usbhsotg_masters,
3012         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3013         .slaves         = omap3xxx_usbhsotg_slaves,
3014         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3015         .class          = &usbotg_class,
3016
3017         /*
3018          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3019          * broken when autoidle is enabled
3020          * workaround is to disable the autoidle bit at module level.
3021          */
3022         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3023                                 | HWMOD_SWSUP_MSTANDBY,
3024 };
3025
3026 /* usb_otg_hs */
3027 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3028
3029         { .name = "mc", .irq = 71 },
3030         { .irq = -1 }
3031 };
3032
3033 static struct omap_hwmod_class am35xx_usbotg_class = {
3034         .name = "am35xx_usbotg",
3035         .sysc = NULL,
3036 };
3037
3038 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3039         .name           = "am35x_otg_hs",
3040         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3041         .main_clk       = NULL,
3042         .prcm = {
3043                 .omap2 = {
3044                 },
3045         },
3046         .masters        = am35xx_usbhsotg_masters,
3047         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3048         .slaves         = am35xx_usbhsotg_slaves,
3049         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3050         .class          = &am35xx_usbotg_class,
3051 };
3052
3053 /* MMC/SD/SDIO common */
3054
3055 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3056         .rev_offs       = 0x1fc,
3057         .sysc_offs      = 0x10,
3058         .syss_offs      = 0x14,
3059         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3060                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3061                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3062         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3063         .sysc_fields    = &omap_hwmod_sysc_type1,
3064 };
3065
3066 static struct omap_hwmod_class omap34xx_mmc_class = {
3067         .name = "mmc",
3068         .sysc = &omap34xx_mmc_sysc,
3069 };
3070
3071 /* MMC/SD/SDIO1 */
3072
3073 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3074         { .irq = 83, },
3075         { .irq = -1 }
3076 };
3077
3078 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3079         { .name = "tx", .dma_req = 61, },
3080         { .name = "rx", .dma_req = 62, },
3081         { .dma_req = -1 }
3082 };
3083
3084 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3085         { .role = "dbck", .clk = "omap_32k_fck", },
3086 };
3087
3088 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3089         &omap3xxx_l4_core__mmc1,
3090 };
3091
3092 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3093         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3094 };
3095
3096 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3097 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3098         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3099                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3100 };
3101
3102 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3103         .name           = "mmc1",
3104         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3105         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3106         .opt_clks       = omap34xx_mmc1_opt_clks,
3107         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3108         .main_clk       = "mmchs1_fck",
3109         .prcm           = {
3110                 .omap2 = {
3111                         .module_offs = CORE_MOD,
3112                         .prcm_reg_id = 1,
3113                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3114                         .idlest_reg_id = 1,
3115                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3116                 },
3117         },
3118         .dev_attr       = &mmc1_pre_es3_dev_attr,
3119         .slaves         = omap3xxx_mmc1_slaves,
3120         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3121         .class          = &omap34xx_mmc_class,
3122 };
3123
3124 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3125         .name           = "mmc1",
3126         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3127         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3128         .opt_clks       = omap34xx_mmc1_opt_clks,
3129         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3130         .main_clk       = "mmchs1_fck",
3131         .prcm           = {
3132                 .omap2 = {
3133                         .module_offs = CORE_MOD,
3134                         .prcm_reg_id = 1,
3135                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3136                         .idlest_reg_id = 1,
3137                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3138                 },
3139         },
3140         .dev_attr       = &mmc1_dev_attr,
3141         .slaves         = omap3xxx_mmc1_slaves,
3142         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3143         .class          = &omap34xx_mmc_class,
3144 };
3145
3146 /* MMC/SD/SDIO2 */
3147
3148 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3149         { .irq = INT_24XX_MMC2_IRQ, },
3150         { .irq = -1 }
3151 };
3152
3153 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3154         { .name = "tx", .dma_req = 47, },
3155         { .name = "rx", .dma_req = 48, },
3156         { .dma_req = -1 }
3157 };
3158
3159 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3160         { .role = "dbck", .clk = "omap_32k_fck", },
3161 };
3162
3163 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3164         &omap3xxx_l4_core__mmc2,
3165 };
3166
3167 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3168 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3169         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3170 };
3171
3172 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3173         .name           = "mmc2",
3174         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3175         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3176         .opt_clks       = omap34xx_mmc2_opt_clks,
3177         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3178         .main_clk       = "mmchs2_fck",
3179         .prcm           = {
3180                 .omap2 = {
3181                         .module_offs = CORE_MOD,
3182                         .prcm_reg_id = 1,
3183                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3184                         .idlest_reg_id = 1,
3185                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3186                 },
3187         },
3188         .dev_attr       = &mmc2_pre_es3_dev_attr,
3189         .slaves         = omap3xxx_mmc2_slaves,
3190         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3191         .class          = &omap34xx_mmc_class,
3192 };
3193
3194 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3195         .name           = "mmc2",
3196         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3197         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3198         .opt_clks       = omap34xx_mmc2_opt_clks,
3199         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3200         .main_clk       = "mmchs2_fck",
3201         .prcm           = {
3202                 .omap2 = {
3203                         .module_offs = CORE_MOD,
3204                         .prcm_reg_id = 1,
3205                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3206                         .idlest_reg_id = 1,
3207                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3208                 },
3209         },
3210         .slaves         = omap3xxx_mmc2_slaves,
3211         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3212         .class          = &omap34xx_mmc_class,
3213 };
3214
3215 /* MMC/SD/SDIO3 */
3216
3217 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3218         { .irq = 94, },
3219         { .irq = -1 }
3220 };
3221
3222 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3223         { .name = "tx", .dma_req = 77, },
3224         { .name = "rx", .dma_req = 78, },
3225         { .dma_req = -1 }
3226 };
3227
3228 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3229         { .role = "dbck", .clk = "omap_32k_fck", },
3230 };
3231
3232 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3233         &omap3xxx_l4_core__mmc3,
3234 };
3235
3236 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3237         .name           = "mmc3",
3238         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3239         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3240         .opt_clks       = omap34xx_mmc3_opt_clks,
3241         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3242         .main_clk       = "mmchs3_fck",
3243         .prcm           = {
3244                 .omap2 = {
3245                         .prcm_reg_id = 1,
3246                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3247                         .idlest_reg_id = 1,
3248                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3249                 },
3250         },
3251         .slaves         = omap3xxx_mmc3_slaves,
3252         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3253         .class          = &omap34xx_mmc_class,
3254 };
3255
3256 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3257         &omap3xxx_l3_main_hwmod,
3258         &omap3xxx_l4_core_hwmod,
3259         &omap3xxx_l4_per_hwmod,
3260         &omap3xxx_l4_wkup_hwmod,
3261         &omap3xxx_mmc3_hwmod,
3262         &omap3xxx_mpu_hwmod,
3263
3264         &omap3xxx_timer1_hwmod,
3265         &omap3xxx_timer2_hwmod,
3266         &omap3xxx_timer3_hwmod,
3267         &omap3xxx_timer4_hwmod,
3268         &omap3xxx_timer5_hwmod,
3269         &omap3xxx_timer6_hwmod,
3270         &omap3xxx_timer7_hwmod,
3271         &omap3xxx_timer8_hwmod,
3272         &omap3xxx_timer9_hwmod,
3273         &omap3xxx_timer10_hwmod,
3274         &omap3xxx_timer11_hwmod,
3275
3276         &omap3xxx_wd_timer2_hwmod,
3277         &omap3xxx_uart1_hwmod,
3278         &omap3xxx_uart2_hwmod,
3279         &omap3xxx_uart3_hwmod,
3280
3281         /* i2c class */
3282         &omap3xxx_i2c1_hwmod,
3283         &omap3xxx_i2c2_hwmod,
3284         &omap3xxx_i2c3_hwmod,
3285
3286         /* gpio class */
3287         &omap3xxx_gpio1_hwmod,
3288         &omap3xxx_gpio2_hwmod,
3289         &omap3xxx_gpio3_hwmod,
3290         &omap3xxx_gpio4_hwmod,
3291         &omap3xxx_gpio5_hwmod,
3292         &omap3xxx_gpio6_hwmod,
3293
3294         /* dma_system class*/
3295         &omap3xxx_dma_system_hwmod,
3296
3297         /* mcbsp class */
3298         &omap3xxx_mcbsp1_hwmod,
3299         &omap3xxx_mcbsp2_hwmod,
3300         &omap3xxx_mcbsp3_hwmod,
3301         &omap3xxx_mcbsp4_hwmod,
3302         &omap3xxx_mcbsp5_hwmod,
3303         &omap3xxx_mcbsp2_sidetone_hwmod,
3304         &omap3xxx_mcbsp3_sidetone_hwmod,
3305
3306
3307         /* mcspi class */
3308         &omap34xx_mcspi1,
3309         &omap34xx_mcspi2,
3310         &omap34xx_mcspi3,
3311         &omap34xx_mcspi4,
3312
3313         NULL,
3314 };
3315
3316 /* GP-only hwmods */
3317 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3318         &omap3xxx_timer12_hwmod,
3319         NULL
3320 };
3321
3322 /* 3430ES1-only hwmods */
3323 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3324         &omap3430es1_dss_core_hwmod,
3325         NULL
3326 };
3327
3328 /* 3430ES2+-only hwmods */
3329 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3330         &omap3xxx_dss_core_hwmod,
3331         &omap3xxx_usbhsotg_hwmod,
3332         NULL
3333 };
3334
3335 /* <= 3430ES3-only hwmods */
3336 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3337         &omap3xxx_pre_es3_mmc1_hwmod,
3338         &omap3xxx_pre_es3_mmc2_hwmod,
3339         NULL
3340 };
3341
3342 /* 3430ES3+-only hwmods */
3343 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3344         &omap3xxx_es3plus_mmc1_hwmod,
3345         &omap3xxx_es3plus_mmc2_hwmod,
3346         NULL
3347 };
3348
3349 /* 34xx-only hwmods (all ES revisions) */
3350 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3351         &omap3xxx_iva_hwmod,
3352         &omap34xx_sr1_hwmod,
3353         &omap34xx_sr2_hwmod,
3354         &omap3xxx_mailbox_hwmod,
3355         NULL
3356 };
3357
3358 /* 36xx-only hwmods (all ES revisions) */
3359 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3360         &omap3xxx_iva_hwmod,
3361         &omap3xxx_uart4_hwmod,
3362         &omap3xxx_dss_core_hwmod,
3363         &omap36xx_sr1_hwmod,
3364         &omap36xx_sr2_hwmod,
3365         &omap3xxx_usbhsotg_hwmod,
3366         &omap3xxx_mailbox_hwmod,
3367         &omap3xxx_es3plus_mmc1_hwmod,
3368         &omap3xxx_es3plus_mmc2_hwmod,
3369         NULL
3370 };
3371
3372 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3373         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3374         &am35xx_usbhsotg_hwmod,
3375         &omap3xxx_es3plus_mmc1_hwmod,
3376         &omap3xxx_es3plus_mmc2_hwmod,
3377         NULL
3378 };
3379
3380 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3381         /* dss class */
3382         &omap3xxx_dss_dispc_hwmod,
3383         &omap3xxx_dss_dsi1_hwmod,
3384         &omap3xxx_dss_rfbi_hwmod,
3385         &omap3xxx_dss_venc_hwmod,
3386         NULL
3387 };
3388
3389 int __init omap3xxx_hwmod_init(void)
3390 {
3391         int r;
3392         struct omap_hwmod **h = NULL;
3393         unsigned int rev;
3394
3395         /* Register hwmods common to all OMAP3 */
3396         r = omap_hwmod_register(omap3xxx_hwmods);
3397         if (r < 0)
3398                 return r;
3399
3400         /* Register GP-only hwmods. */
3401         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3402                 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3403                 if (r < 0)
3404                         return r;
3405         }
3406
3407         rev = omap_rev();
3408
3409         /*
3410          * Register hwmods common to individual OMAP3 families, all
3411          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3412          * All possible revisions should be included in this conditional.
3413          */
3414         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3415             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3416             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3417                 h = omap34xx_hwmods;
3418         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3419                 h = am35xx_hwmods;
3420         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3421                    rev == OMAP3630_REV_ES1_2) {
3422                 h = omap36xx_hwmods;
3423         } else {
3424                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3425                 return -EINVAL;
3426         };
3427
3428         r = omap_hwmod_register(h);
3429         if (r < 0)
3430                 return r;
3431
3432         /*
3433          * Register hwmods specific to certain ES levels of a
3434          * particular family of silicon (e.g., 34xx ES1.0)
3435          */
3436         h = NULL;
3437         if (rev == OMAP3430_REV_ES1_0) {
3438                 h = omap3430es1_hwmods;
3439         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3440                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3441                    rev == OMAP3430_REV_ES3_1_2) {
3442                 h = omap3430es2plus_hwmods;
3443         };
3444
3445         if (h) {
3446                 r = omap_hwmod_register(h);
3447                 if (r < 0)
3448                         return r;
3449         }
3450
3451         h = NULL;
3452         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3453             rev == OMAP3430_REV_ES2_1) {
3454                 h = omap3430_pre_es3_hwmods;
3455         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3456                    rev == OMAP3430_REV_ES3_1_2) {
3457                 h = omap3430_es3plus_hwmods;
3458         };
3459
3460         if (h)
3461                 r = omap_hwmod_register(h);
3462         if (r < 0)
3463                 return r;
3464
3465         /*
3466          * DSS code presumes that dss_core hwmod is handled first,
3467          * _before_ any other DSS related hwmods so register common
3468          * DSS hwmods last to ensure that dss_core is already registered.
3469          * Otherwise some change things may happen, for ex. if dispc
3470          * is handled before dss_core and DSS is enabled in bootloader
3471          * DIPSC will be reset with outputs enabled which sometimes leads
3472          * to unrecoverable L3 error.
3473          */
3474         r = omap_hwmod_register(omap3xxx_dss_hwmods);
3475
3476         return r;
3477 }