2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120 .master = &omap3xxx_mpu_hwmod,
121 .slave = &omap3xxx_l3_main_hwmod,
122 .addr = omap3xxx_l3_main_addrs,
123 .user = OCP_USER_MPU,
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .flags = HWMOD_NO_IDLEST,
162 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
163 static struct omap_hwmod omap3xxx_uart1_hwmod;
164 static struct omap_hwmod omap3xxx_uart2_hwmod;
165 static struct omap_hwmod omap3xxx_uart3_hwmod;
166 static struct omap_hwmod omap3xxx_uart4_hwmod;
167 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
169 /* l3_core -> usbhsotg interface */
170 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
171 .master = &omap3xxx_usbhsotg_hwmod,
172 .slave = &omap3xxx_l3_main_hwmod,
173 .clk = "core_l3_ick",
174 .user = OCP_USER_MPU,
177 /* l3_core -> am35xx_usbhsotg interface */
178 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
179 .master = &am35xx_usbhsotg_hwmod,
180 .slave = &omap3xxx_l3_main_hwmod,
181 .clk = "core_l3_ick",
182 .user = OCP_USER_MPU,
184 /* L4_CORE -> L4_WKUP interface */
185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
186 .master = &omap3xxx_l4_core_hwmod,
187 .slave = &omap3xxx_l4_wkup_hwmod,
188 .user = OCP_USER_MPU | OCP_USER_SDMA,
191 /* L4 CORE -> MMC1 interface */
192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
193 .master = &omap3xxx_l4_core_hwmod,
194 .slave = &omap3xxx_mmc1_hwmod,
196 .addr = omap2430_mmc1_addr_space,
197 .user = OCP_USER_MPU | OCP_USER_SDMA,
198 .flags = OMAP_FIREWALL_L4
201 /* L4 CORE -> MMC2 interface */
202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
203 .master = &omap3xxx_l4_core_hwmod,
204 .slave = &omap3xxx_mmc2_hwmod,
206 .addr = omap2430_mmc2_addr_space,
207 .user = OCP_USER_MPU | OCP_USER_SDMA,
208 .flags = OMAP_FIREWALL_L4
211 /* L4 CORE -> MMC3 interface */
212 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
214 .pa_start = 0x480ad000,
215 .pa_end = 0x480ad1ff,
216 .flags = ADDR_TYPE_RT,
221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
222 .master = &omap3xxx_l4_core_hwmod,
223 .slave = &omap3xxx_mmc3_hwmod,
225 .addr = omap3xxx_mmc3_addr_space,
226 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 .flags = OMAP_FIREWALL_L4
230 /* L4 CORE -> UART1 interface */
231 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
233 .pa_start = OMAP3_UART1_BASE,
234 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
235 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
240 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
241 .master = &omap3xxx_l4_core_hwmod,
242 .slave = &omap3xxx_uart1_hwmod,
244 .addr = omap3xxx_uart1_addr_space,
245 .user = OCP_USER_MPU | OCP_USER_SDMA,
248 /* L4 CORE -> UART2 interface */
249 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
251 .pa_start = OMAP3_UART2_BASE,
252 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
253 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
259 .master = &omap3xxx_l4_core_hwmod,
260 .slave = &omap3xxx_uart2_hwmod,
262 .addr = omap3xxx_uart2_addr_space,
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
266 /* L4 PER -> UART3 interface */
267 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
269 .pa_start = OMAP3_UART3_BASE,
270 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
271 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
277 .master = &omap3xxx_l4_per_hwmod,
278 .slave = &omap3xxx_uart3_hwmod,
280 .addr = omap3xxx_uart3_addr_space,
281 .user = OCP_USER_MPU | OCP_USER_SDMA,
284 /* L4 PER -> UART4 interface */
285 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
287 .pa_start = OMAP3_UART4_BASE,
288 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
289 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
295 .master = &omap3xxx_l4_per_hwmod,
296 .slave = &omap3xxx_uart4_hwmod,
298 .addr = omap3xxx_uart4_addr_space,
299 .user = OCP_USER_MPU | OCP_USER_SDMA,
302 /* L4 CORE -> I2C1 interface */
303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
304 .master = &omap3xxx_l4_core_hwmod,
305 .slave = &omap3xxx_i2c1_hwmod,
307 .addr = omap2_i2c1_addr_space,
310 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
312 .flags = OMAP_FIREWALL_L4,
315 .user = OCP_USER_MPU | OCP_USER_SDMA,
318 /* L4 CORE -> I2C2 interface */
319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
320 .master = &omap3xxx_l4_core_hwmod,
321 .slave = &omap3xxx_i2c2_hwmod,
323 .addr = omap2_i2c2_addr_space,
326 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
328 .flags = OMAP_FIREWALL_L4,
331 .user = OCP_USER_MPU | OCP_USER_SDMA,
334 /* L4 CORE -> I2C3 interface */
335 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
337 .pa_start = 0x48060000,
338 .pa_end = 0x48060000 + SZ_128 - 1,
339 .flags = ADDR_TYPE_RT,
344 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
345 .master = &omap3xxx_l4_core_hwmod,
346 .slave = &omap3xxx_i2c3_hwmod,
348 .addr = omap3xxx_i2c3_addr_space,
351 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
353 .flags = OMAP_FIREWALL_L4,
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
359 /* L4 CORE -> SR1 interface */
360 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
362 .pa_start = OMAP34XX_SR1_BASE,
363 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
364 .flags = ADDR_TYPE_RT,
369 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
370 .master = &omap3xxx_l4_core_hwmod,
371 .slave = &omap34xx_sr1_hwmod,
373 .addr = omap3_sr1_addr_space,
374 .user = OCP_USER_MPU,
377 /* L4 CORE -> SR1 interface */
378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
380 .pa_start = OMAP34XX_SR2_BASE,
381 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
382 .flags = ADDR_TYPE_RT,
387 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
388 .master = &omap3xxx_l4_core_hwmod,
389 .slave = &omap34xx_sr2_hwmod,
391 .addr = omap3_sr2_addr_space,
392 .user = OCP_USER_MPU,
396 * usbhsotg interface data
399 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
401 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
402 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
403 .flags = ADDR_TYPE_RT
408 /* l4_core -> usbhsotg */
409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
410 .master = &omap3xxx_l4_core_hwmod,
411 .slave = &omap3xxx_usbhsotg_hwmod,
413 .addr = omap3xxx_usbhsotg_addrs,
414 .user = OCP_USER_MPU,
417 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
418 &omap3xxx_usbhsotg__l3,
421 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
422 &omap3xxx_l4_core__usbhsotg,
425 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
427 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
428 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
429 .flags = ADDR_TYPE_RT
434 /* l4_core -> usbhsotg */
435 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
436 .master = &omap3xxx_l4_core_hwmod,
437 .slave = &am35xx_usbhsotg_hwmod,
439 .addr = am35xx_usbhsotg_addrs,
440 .user = OCP_USER_MPU,
443 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
444 &am35xx_usbhsotg__l3,
447 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
448 &am35xx_l4_core__usbhsotg,
450 /* Slave interfaces on the L4_CORE interconnect */
451 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
452 &omap3xxx_l3_main__l4_core,
456 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
458 .class = &l4_hwmod_class,
459 .slaves = omap3xxx_l4_core_slaves,
460 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
461 .flags = HWMOD_NO_IDLEST,
464 /* Slave interfaces on the L4_PER interconnect */
465 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
466 &omap3xxx_l3_main__l4_per,
470 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
472 .class = &l4_hwmod_class,
473 .slaves = omap3xxx_l4_per_slaves,
474 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
475 .flags = HWMOD_NO_IDLEST,
478 /* Slave interfaces on the L4_WKUP interconnect */
479 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
480 &omap3xxx_l4_core__l4_wkup,
484 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
486 .class = &l4_hwmod_class,
487 .slaves = omap3xxx_l4_wkup_slaves,
488 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
489 .flags = HWMOD_NO_IDLEST,
492 /* Master interfaces on the MPU device */
493 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
494 &omap3xxx_mpu__l3_main,
498 static struct omap_hwmod omap3xxx_mpu_hwmod = {
500 .class = &mpu_hwmod_class,
501 .main_clk = "arm_fck",
502 .masters = omap3xxx_mpu_masters,
503 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
507 * IVA2_2 interface data
510 /* IVA2 <- L3 interface */
511 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
512 .master = &omap3xxx_l3_main_hwmod,
513 .slave = &omap3xxx_iva_hwmod,
515 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
526 static struct omap_hwmod omap3xxx_iva_hwmod = {
528 .class = &iva_hwmod_class,
529 .masters = omap3xxx_iva_masters,
530 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
534 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
538 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
539 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
540 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
541 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
542 .sysc_fields = &omap_hwmod_sysc_type1,
545 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
547 .sysc = &omap3xxx_timer_1ms_sysc,
548 .rev = OMAP_TIMER_IP_VERSION_1,
551 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
555 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
556 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
558 .sysc_fields = &omap_hwmod_sysc_type1,
561 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
563 .sysc = &omap3xxx_timer_sysc,
564 .rev = OMAP_TIMER_IP_VERSION_1,
567 /* secure timers dev attribute */
568 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
569 .timer_capability = OMAP_TIMER_SECURE,
572 /* always-on timers dev attribute */
573 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
574 .timer_capability = OMAP_TIMER_ALWON,
577 /* pwm timers dev attribute */
578 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
579 .timer_capability = OMAP_TIMER_HAS_PWM,
583 static struct omap_hwmod omap3xxx_timer1_hwmod;
585 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
587 .pa_start = 0x48318000,
588 .pa_end = 0x48318000 + SZ_1K - 1,
589 .flags = ADDR_TYPE_RT
594 /* l4_wkup -> timer1 */
595 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
596 .master = &omap3xxx_l4_wkup_hwmod,
597 .slave = &omap3xxx_timer1_hwmod,
599 .addr = omap3xxx_timer1_addrs,
600 .user = OCP_USER_MPU | OCP_USER_SDMA,
603 /* timer1 slave port */
604 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
605 &omap3xxx_l4_wkup__timer1,
609 static struct omap_hwmod omap3xxx_timer1_hwmod = {
611 .mpu_irqs = omap2_timer1_mpu_irqs,
612 .main_clk = "gpt1_fck",
616 .module_bit = OMAP3430_EN_GPT1_SHIFT,
617 .module_offs = WKUP_MOD,
619 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
622 .dev_attr = &capability_alwon_dev_attr,
623 .slaves = omap3xxx_timer1_slaves,
624 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
625 .class = &omap3xxx_timer_1ms_hwmod_class,
629 static struct omap_hwmod omap3xxx_timer2_hwmod;
631 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
633 .pa_start = 0x49032000,
634 .pa_end = 0x49032000 + SZ_1K - 1,
635 .flags = ADDR_TYPE_RT
640 /* l4_per -> timer2 */
641 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
642 .master = &omap3xxx_l4_per_hwmod,
643 .slave = &omap3xxx_timer2_hwmod,
645 .addr = omap3xxx_timer2_addrs,
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
649 /* timer2 slave port */
650 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
651 &omap3xxx_l4_per__timer2,
655 static struct omap_hwmod omap3xxx_timer2_hwmod = {
657 .mpu_irqs = omap2_timer2_mpu_irqs,
658 .main_clk = "gpt2_fck",
662 .module_bit = OMAP3430_EN_GPT2_SHIFT,
663 .module_offs = OMAP3430_PER_MOD,
665 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
668 .dev_attr = &capability_alwon_dev_attr,
669 .slaves = omap3xxx_timer2_slaves,
670 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
671 .class = &omap3xxx_timer_1ms_hwmod_class,
675 static struct omap_hwmod omap3xxx_timer3_hwmod;
677 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
679 .pa_start = 0x49034000,
680 .pa_end = 0x49034000 + SZ_1K - 1,
681 .flags = ADDR_TYPE_RT
686 /* l4_per -> timer3 */
687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
688 .master = &omap3xxx_l4_per_hwmod,
689 .slave = &omap3xxx_timer3_hwmod,
691 .addr = omap3xxx_timer3_addrs,
692 .user = OCP_USER_MPU | OCP_USER_SDMA,
695 /* timer3 slave port */
696 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
697 &omap3xxx_l4_per__timer3,
701 static struct omap_hwmod omap3xxx_timer3_hwmod = {
703 .mpu_irqs = omap2_timer3_mpu_irqs,
704 .main_clk = "gpt3_fck",
708 .module_bit = OMAP3430_EN_GPT3_SHIFT,
709 .module_offs = OMAP3430_PER_MOD,
711 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
714 .dev_attr = &capability_alwon_dev_attr,
715 .slaves = omap3xxx_timer3_slaves,
716 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
717 .class = &omap3xxx_timer_hwmod_class,
721 static struct omap_hwmod omap3xxx_timer4_hwmod;
723 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
725 .pa_start = 0x49036000,
726 .pa_end = 0x49036000 + SZ_1K - 1,
727 .flags = ADDR_TYPE_RT
732 /* l4_per -> timer4 */
733 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
734 .master = &omap3xxx_l4_per_hwmod,
735 .slave = &omap3xxx_timer4_hwmod,
737 .addr = omap3xxx_timer4_addrs,
738 .user = OCP_USER_MPU | OCP_USER_SDMA,
741 /* timer4 slave port */
742 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
743 &omap3xxx_l4_per__timer4,
747 static struct omap_hwmod omap3xxx_timer4_hwmod = {
749 .mpu_irqs = omap2_timer4_mpu_irqs,
750 .main_clk = "gpt4_fck",
754 .module_bit = OMAP3430_EN_GPT4_SHIFT,
755 .module_offs = OMAP3430_PER_MOD,
757 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
760 .dev_attr = &capability_alwon_dev_attr,
761 .slaves = omap3xxx_timer4_slaves,
762 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
763 .class = &omap3xxx_timer_hwmod_class,
767 static struct omap_hwmod omap3xxx_timer5_hwmod;
769 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
771 .pa_start = 0x49038000,
772 .pa_end = 0x49038000 + SZ_1K - 1,
773 .flags = ADDR_TYPE_RT
778 /* l4_per -> timer5 */
779 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
780 .master = &omap3xxx_l4_per_hwmod,
781 .slave = &omap3xxx_timer5_hwmod,
783 .addr = omap3xxx_timer5_addrs,
784 .user = OCP_USER_MPU | OCP_USER_SDMA,
787 /* timer5 slave port */
788 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
789 &omap3xxx_l4_per__timer5,
793 static struct omap_hwmod omap3xxx_timer5_hwmod = {
795 .mpu_irqs = omap2_timer5_mpu_irqs,
796 .main_clk = "gpt5_fck",
800 .module_bit = OMAP3430_EN_GPT5_SHIFT,
801 .module_offs = OMAP3430_PER_MOD,
803 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
806 .dev_attr = &capability_alwon_dev_attr,
807 .slaves = omap3xxx_timer5_slaves,
808 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
809 .class = &omap3xxx_timer_hwmod_class,
813 static struct omap_hwmod omap3xxx_timer6_hwmod;
815 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
817 .pa_start = 0x4903A000,
818 .pa_end = 0x4903A000 + SZ_1K - 1,
819 .flags = ADDR_TYPE_RT
824 /* l4_per -> timer6 */
825 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
826 .master = &omap3xxx_l4_per_hwmod,
827 .slave = &omap3xxx_timer6_hwmod,
829 .addr = omap3xxx_timer6_addrs,
830 .user = OCP_USER_MPU | OCP_USER_SDMA,
833 /* timer6 slave port */
834 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
835 &omap3xxx_l4_per__timer6,
839 static struct omap_hwmod omap3xxx_timer6_hwmod = {
841 .mpu_irqs = omap2_timer6_mpu_irqs,
842 .main_clk = "gpt6_fck",
846 .module_bit = OMAP3430_EN_GPT6_SHIFT,
847 .module_offs = OMAP3430_PER_MOD,
849 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
852 .dev_attr = &capability_alwon_dev_attr,
853 .slaves = omap3xxx_timer6_slaves,
854 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
855 .class = &omap3xxx_timer_hwmod_class,
859 static struct omap_hwmod omap3xxx_timer7_hwmod;
861 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
863 .pa_start = 0x4903C000,
864 .pa_end = 0x4903C000 + SZ_1K - 1,
865 .flags = ADDR_TYPE_RT
870 /* l4_per -> timer7 */
871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
872 .master = &omap3xxx_l4_per_hwmod,
873 .slave = &omap3xxx_timer7_hwmod,
875 .addr = omap3xxx_timer7_addrs,
876 .user = OCP_USER_MPU | OCP_USER_SDMA,
879 /* timer7 slave port */
880 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
881 &omap3xxx_l4_per__timer7,
885 static struct omap_hwmod omap3xxx_timer7_hwmod = {
887 .mpu_irqs = omap2_timer7_mpu_irqs,
888 .main_clk = "gpt7_fck",
892 .module_bit = OMAP3430_EN_GPT7_SHIFT,
893 .module_offs = OMAP3430_PER_MOD,
895 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
898 .dev_attr = &capability_alwon_dev_attr,
899 .slaves = omap3xxx_timer7_slaves,
900 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
901 .class = &omap3xxx_timer_hwmod_class,
905 static struct omap_hwmod omap3xxx_timer8_hwmod;
907 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
909 .pa_start = 0x4903E000,
910 .pa_end = 0x4903E000 + SZ_1K - 1,
911 .flags = ADDR_TYPE_RT
916 /* l4_per -> timer8 */
917 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
918 .master = &omap3xxx_l4_per_hwmod,
919 .slave = &omap3xxx_timer8_hwmod,
921 .addr = omap3xxx_timer8_addrs,
922 .user = OCP_USER_MPU | OCP_USER_SDMA,
925 /* timer8 slave port */
926 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
927 &omap3xxx_l4_per__timer8,
931 static struct omap_hwmod omap3xxx_timer8_hwmod = {
933 .mpu_irqs = omap2_timer8_mpu_irqs,
934 .main_clk = "gpt8_fck",
938 .module_bit = OMAP3430_EN_GPT8_SHIFT,
939 .module_offs = OMAP3430_PER_MOD,
941 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
944 .dev_attr = &capability_pwm_dev_attr,
945 .slaves = omap3xxx_timer8_slaves,
946 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
947 .class = &omap3xxx_timer_hwmod_class,
951 static struct omap_hwmod omap3xxx_timer9_hwmod;
953 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
955 .pa_start = 0x49040000,
956 .pa_end = 0x49040000 + SZ_1K - 1,
957 .flags = ADDR_TYPE_RT
962 /* l4_per -> timer9 */
963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
964 .master = &omap3xxx_l4_per_hwmod,
965 .slave = &omap3xxx_timer9_hwmod,
967 .addr = omap3xxx_timer9_addrs,
968 .user = OCP_USER_MPU | OCP_USER_SDMA,
971 /* timer9 slave port */
972 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
973 &omap3xxx_l4_per__timer9,
977 static struct omap_hwmod omap3xxx_timer9_hwmod = {
979 .mpu_irqs = omap2_timer9_mpu_irqs,
980 .main_clk = "gpt9_fck",
984 .module_bit = OMAP3430_EN_GPT9_SHIFT,
985 .module_offs = OMAP3430_PER_MOD,
987 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
990 .dev_attr = &capability_pwm_dev_attr,
991 .slaves = omap3xxx_timer9_slaves,
992 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
993 .class = &omap3xxx_timer_hwmod_class,
997 static struct omap_hwmod omap3xxx_timer10_hwmod;
999 /* l4_core -> timer10 */
1000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1001 .master = &omap3xxx_l4_core_hwmod,
1002 .slave = &omap3xxx_timer10_hwmod,
1004 .addr = omap2_timer10_addrs,
1005 .user = OCP_USER_MPU | OCP_USER_SDMA,
1008 /* timer10 slave port */
1009 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1010 &omap3xxx_l4_core__timer10,
1014 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1016 .mpu_irqs = omap2_timer10_mpu_irqs,
1017 .main_clk = "gpt10_fck",
1021 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1022 .module_offs = CORE_MOD,
1024 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1027 .dev_attr = &capability_pwm_dev_attr,
1028 .slaves = omap3xxx_timer10_slaves,
1029 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1030 .class = &omap3xxx_timer_1ms_hwmod_class,
1034 static struct omap_hwmod omap3xxx_timer11_hwmod;
1036 /* l4_core -> timer11 */
1037 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1038 .master = &omap3xxx_l4_core_hwmod,
1039 .slave = &omap3xxx_timer11_hwmod,
1041 .addr = omap2_timer11_addrs,
1042 .user = OCP_USER_MPU | OCP_USER_SDMA,
1045 /* timer11 slave port */
1046 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1047 &omap3xxx_l4_core__timer11,
1051 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1053 .mpu_irqs = omap2_timer11_mpu_irqs,
1054 .main_clk = "gpt11_fck",
1058 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1059 .module_offs = CORE_MOD,
1061 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1064 .dev_attr = &capability_pwm_dev_attr,
1065 .slaves = omap3xxx_timer11_slaves,
1066 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1067 .class = &omap3xxx_timer_hwmod_class,
1071 static struct omap_hwmod omap3xxx_timer12_hwmod;
1072 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1077 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1079 .pa_start = 0x48304000,
1080 .pa_end = 0x48304000 + SZ_1K - 1,
1081 .flags = ADDR_TYPE_RT
1086 /* l4_core -> timer12 */
1087 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1088 .master = &omap3xxx_l4_core_hwmod,
1089 .slave = &omap3xxx_timer12_hwmod,
1091 .addr = omap3xxx_timer12_addrs,
1092 .user = OCP_USER_MPU | OCP_USER_SDMA,
1095 /* timer12 slave port */
1096 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1097 &omap3xxx_l4_core__timer12,
1101 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1103 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1104 .main_clk = "gpt12_fck",
1108 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1109 .module_offs = WKUP_MOD,
1111 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1114 .dev_attr = &capability_secure_dev_attr,
1115 .slaves = omap3xxx_timer12_slaves,
1116 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1117 .class = &omap3xxx_timer_hwmod_class,
1120 /* l4_wkup -> wd_timer2 */
1121 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1123 .pa_start = 0x48314000,
1124 .pa_end = 0x4831407f,
1125 .flags = ADDR_TYPE_RT
1130 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1131 .master = &omap3xxx_l4_wkup_hwmod,
1132 .slave = &omap3xxx_wd_timer2_hwmod,
1134 .addr = omap3xxx_wd_timer2_addrs,
1135 .user = OCP_USER_MPU | OCP_USER_SDMA,
1140 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1141 * overflow condition
1144 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1146 .sysc_offs = 0x0010,
1147 .syss_offs = 0x0014,
1148 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1149 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1150 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1151 SYSS_HAS_RESET_STATUS),
1152 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1153 .sysc_fields = &omap_hwmod_sysc_type1,
1157 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1161 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1162 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1163 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1165 .sysc_fields = &omap_hwmod_sysc_type1,
1168 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1170 .sysc = &omap3xxx_wd_timer_sysc,
1171 .pre_shutdown = &omap2_wd_timer_disable
1175 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1176 &omap3xxx_l4_wkup__wd_timer2,
1179 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1180 .name = "wd_timer2",
1181 .class = &omap3xxx_wd_timer_hwmod_class,
1182 .main_clk = "wdt2_fck",
1186 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1187 .module_offs = WKUP_MOD,
1189 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1192 .slaves = omap3xxx_wd_timer2_slaves,
1193 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1195 * XXX: Use software supervised mode, HW supervised smartidle seems to
1196 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1198 .flags = HWMOD_SWSUP_SIDLE,
1203 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1204 &omap3_l4_core__uart1,
1207 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1209 .mpu_irqs = omap2_uart1_mpu_irqs,
1210 .sdma_reqs = omap2_uart1_sdma_reqs,
1211 .main_clk = "uart1_fck",
1214 .module_offs = CORE_MOD,
1216 .module_bit = OMAP3430_EN_UART1_SHIFT,
1218 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1221 .slaves = omap3xxx_uart1_slaves,
1222 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1223 .class = &omap2_uart_class,
1228 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1229 &omap3_l4_core__uart2,
1232 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1234 .mpu_irqs = omap2_uart2_mpu_irqs,
1235 .sdma_reqs = omap2_uart2_sdma_reqs,
1236 .main_clk = "uart2_fck",
1239 .module_offs = CORE_MOD,
1241 .module_bit = OMAP3430_EN_UART2_SHIFT,
1243 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1246 .slaves = omap3xxx_uart2_slaves,
1247 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1248 .class = &omap2_uart_class,
1253 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1254 &omap3_l4_per__uart3,
1257 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1259 .mpu_irqs = omap2_uart3_mpu_irqs,
1260 .sdma_reqs = omap2_uart3_sdma_reqs,
1261 .main_clk = "uart3_fck",
1264 .module_offs = OMAP3430_PER_MOD,
1266 .module_bit = OMAP3430_EN_UART3_SHIFT,
1268 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1271 .slaves = omap3xxx_uart3_slaves,
1272 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1273 .class = &omap2_uart_class,
1278 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1279 { .irq = INT_36XX_UART4_IRQ, },
1283 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1284 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1285 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1289 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1290 &omap3_l4_per__uart4,
1293 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1295 .mpu_irqs = uart4_mpu_irqs,
1296 .sdma_reqs = uart4_sdma_reqs,
1297 .main_clk = "uart4_fck",
1300 .module_offs = OMAP3430_PER_MOD,
1302 .module_bit = OMAP3630_EN_UART4_SHIFT,
1304 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1307 .slaves = omap3xxx_uart4_slaves,
1308 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1309 .class = &omap2_uart_class,
1312 static struct omap_hwmod_class i2c_class = {
1315 .rev = OMAP_I2C_IP_VERSION_1,
1316 .reset = &omap_i2c_reset,
1319 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1320 { .name = "dispc", .dma_req = 5 },
1321 { .name = "dsi1", .dma_req = 74 },
1326 /* dss master ports */
1327 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1331 /* l4_core -> dss */
1332 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1333 .master = &omap3xxx_l4_core_hwmod,
1334 .slave = &omap3430es1_dss_core_hwmod,
1336 .addr = omap2_dss_addrs,
1339 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1340 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1341 .flags = OMAP_FIREWALL_L4,
1344 .user = OCP_USER_MPU | OCP_USER_SDMA,
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1348 .master = &omap3xxx_l4_core_hwmod,
1349 .slave = &omap3xxx_dss_core_hwmod,
1351 .addr = omap2_dss_addrs,
1354 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1355 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1356 .flags = OMAP_FIREWALL_L4,
1359 .user = OCP_USER_MPU | OCP_USER_SDMA,
1362 /* dss slave ports */
1363 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1364 &omap3430es1_l4_core__dss,
1367 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1368 &omap3xxx_l4_core__dss,
1371 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1373 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374 * driver does not use these clocks.
1376 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377 { .role = "tv_clk", .clk = "dss_tv_fck" },
1378 /* required only on OMAP3430 */
1379 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1382 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1384 .class = &omap2_dss_hwmod_class,
1385 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1386 .sdma_reqs = omap3xxx_dss_sdma_chs,
1390 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1391 .module_offs = OMAP3430_DSS_MOD,
1393 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1396 .opt_clks = dss_opt_clks,
1397 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1398 .slaves = omap3430es1_dss_slaves,
1399 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1400 .masters = omap3xxx_dss_masters,
1401 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1402 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1405 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1407 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1408 .class = &omap2_dss_hwmod_class,
1409 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1410 .sdma_reqs = omap3xxx_dss_sdma_chs,
1414 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1415 .module_offs = OMAP3430_DSS_MOD,
1417 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1418 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1421 .opt_clks = dss_opt_clks,
1422 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1423 .slaves = omap3xxx_dss_slaves,
1424 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1425 .masters = omap3xxx_dss_masters,
1426 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1431 * display controller
1434 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
1436 .sysc_offs = 0x0010,
1437 .syss_offs = 0x0014,
1438 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1439 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1440 SYSC_HAS_ENAWAKEUP),
1441 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1442 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1443 .sysc_fields = &omap_hwmod_sysc_type1,
1446 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1448 .sysc = &omap3_dispc_sysc,
1451 /* l4_core -> dss_dispc */
1452 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1453 .master = &omap3xxx_l4_core_hwmod,
1454 .slave = &omap3xxx_dss_dispc_hwmod,
1456 .addr = omap2_dss_dispc_addrs,
1459 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1460 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1461 .flags = OMAP_FIREWALL_L4,
1464 .user = OCP_USER_MPU | OCP_USER_SDMA,
1467 /* dss_dispc slave ports */
1468 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1469 &omap3xxx_l4_core__dss_dispc,
1472 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1473 .name = "dss_dispc",
1474 .class = &omap3_dispc_hwmod_class,
1475 .mpu_irqs = omap2_dispc_irqs,
1476 .main_clk = "dss1_alwon_fck",
1480 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1481 .module_offs = OMAP3430_DSS_MOD,
1484 .slaves = omap3xxx_dss_dispc_slaves,
1485 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1486 .flags = HWMOD_NO_IDLEST,
1487 .dev_attr = &omap2_3_dss_dispc_dev_attr
1492 * display serial interface controller
1495 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1499 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1505 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1507 .pa_start = 0x4804FC00,
1508 .pa_end = 0x4804FFFF,
1509 .flags = ADDR_TYPE_RT
1514 /* l4_core -> dss_dsi1 */
1515 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1516 .master = &omap3xxx_l4_core_hwmod,
1517 .slave = &omap3xxx_dss_dsi1_hwmod,
1519 .addr = omap3xxx_dss_dsi1_addrs,
1522 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1523 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1524 .flags = OMAP_FIREWALL_L4,
1527 .user = OCP_USER_MPU | OCP_USER_SDMA,
1530 /* dss_dsi1 slave ports */
1531 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1532 &omap3xxx_l4_core__dss_dsi1,
1535 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1536 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1539 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1541 .class = &omap3xxx_dsi_hwmod_class,
1542 .mpu_irqs = omap3xxx_dsi1_irqs,
1543 .main_clk = "dss1_alwon_fck",
1547 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1548 .module_offs = OMAP3430_DSS_MOD,
1551 .opt_clks = dss_dsi1_opt_clks,
1552 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1553 .slaves = omap3xxx_dss_dsi1_slaves,
1554 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1555 .flags = HWMOD_NO_IDLEST,
1558 /* l4_core -> dss_rfbi */
1559 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1560 .master = &omap3xxx_l4_core_hwmod,
1561 .slave = &omap3xxx_dss_rfbi_hwmod,
1563 .addr = omap2_dss_rfbi_addrs,
1566 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1567 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1568 .flags = OMAP_FIREWALL_L4,
1571 .user = OCP_USER_MPU | OCP_USER_SDMA,
1574 /* dss_rfbi slave ports */
1575 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1576 &omap3xxx_l4_core__dss_rfbi,
1579 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1580 { .role = "ick", .clk = "dss_ick" },
1583 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1585 .class = &omap2_rfbi_hwmod_class,
1586 .main_clk = "dss1_alwon_fck",
1590 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1591 .module_offs = OMAP3430_DSS_MOD,
1594 .opt_clks = dss_rfbi_opt_clks,
1595 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1596 .slaves = omap3xxx_dss_rfbi_slaves,
1597 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1598 .flags = HWMOD_NO_IDLEST,
1601 /* l4_core -> dss_venc */
1602 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1603 .master = &omap3xxx_l4_core_hwmod,
1604 .slave = &omap3xxx_dss_venc_hwmod,
1606 .addr = omap2_dss_venc_addrs,
1609 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1610 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1611 .flags = OMAP_FIREWALL_L4,
1614 .flags = OCPIF_SWSUP_IDLE,
1615 .user = OCP_USER_MPU | OCP_USER_SDMA,
1618 /* dss_venc slave ports */
1619 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1620 &omap3xxx_l4_core__dss_venc,
1623 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1624 /* required only on OMAP3430 */
1625 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1628 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1630 .class = &omap2_venc_hwmod_class,
1631 .main_clk = "dss_tv_fck",
1635 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1636 .module_offs = OMAP3430_DSS_MOD,
1639 .opt_clks = dss_venc_opt_clks,
1640 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1641 .slaves = omap3xxx_dss_venc_slaves,
1642 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1643 .flags = HWMOD_NO_IDLEST,
1648 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1649 .fifo_depth = 8, /* bytes */
1650 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1651 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1652 OMAP_I2C_FLAG_BUS_SHIFT_2,
1655 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1656 &omap3_l4_core__i2c1,
1659 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1661 .flags = HWMOD_16BIT_REG,
1662 .mpu_irqs = omap2_i2c1_mpu_irqs,
1663 .sdma_reqs = omap2_i2c1_sdma_reqs,
1664 .main_clk = "i2c1_fck",
1667 .module_offs = CORE_MOD,
1669 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1671 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1674 .slaves = omap3xxx_i2c1_slaves,
1675 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1676 .class = &i2c_class,
1677 .dev_attr = &i2c1_dev_attr,
1682 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1683 .fifo_depth = 8, /* bytes */
1684 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1685 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1686 OMAP_I2C_FLAG_BUS_SHIFT_2,
1689 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1690 &omap3_l4_core__i2c2,
1693 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1695 .flags = HWMOD_16BIT_REG,
1696 .mpu_irqs = omap2_i2c2_mpu_irqs,
1697 .sdma_reqs = omap2_i2c2_sdma_reqs,
1698 .main_clk = "i2c2_fck",
1701 .module_offs = CORE_MOD,
1703 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1705 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1708 .slaves = omap3xxx_i2c2_slaves,
1709 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1710 .class = &i2c_class,
1711 .dev_attr = &i2c2_dev_attr,
1716 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1717 .fifo_depth = 64, /* bytes */
1718 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1719 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1720 OMAP_I2C_FLAG_BUS_SHIFT_2,
1723 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1724 { .irq = INT_34XX_I2C3_IRQ, },
1728 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1729 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1730 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1734 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1735 &omap3_l4_core__i2c3,
1738 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1740 .flags = HWMOD_16BIT_REG,
1741 .mpu_irqs = i2c3_mpu_irqs,
1742 .sdma_reqs = i2c3_sdma_reqs,
1743 .main_clk = "i2c3_fck",
1746 .module_offs = CORE_MOD,
1748 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1750 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1753 .slaves = omap3xxx_i2c3_slaves,
1754 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1755 .class = &i2c_class,
1756 .dev_attr = &i2c3_dev_attr,
1759 /* l4_wkup -> gpio1 */
1760 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1762 .pa_start = 0x48310000,
1763 .pa_end = 0x483101ff,
1764 .flags = ADDR_TYPE_RT
1769 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1770 .master = &omap3xxx_l4_wkup_hwmod,
1771 .slave = &omap3xxx_gpio1_hwmod,
1772 .addr = omap3xxx_gpio1_addrs,
1773 .user = OCP_USER_MPU | OCP_USER_SDMA,
1776 /* l4_per -> gpio2 */
1777 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1779 .pa_start = 0x49050000,
1780 .pa_end = 0x490501ff,
1781 .flags = ADDR_TYPE_RT
1786 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1787 .master = &omap3xxx_l4_per_hwmod,
1788 .slave = &omap3xxx_gpio2_hwmod,
1789 .addr = omap3xxx_gpio2_addrs,
1790 .user = OCP_USER_MPU | OCP_USER_SDMA,
1793 /* l4_per -> gpio3 */
1794 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1796 .pa_start = 0x49052000,
1797 .pa_end = 0x490521ff,
1798 .flags = ADDR_TYPE_RT
1803 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1804 .master = &omap3xxx_l4_per_hwmod,
1805 .slave = &omap3xxx_gpio3_hwmod,
1806 .addr = omap3xxx_gpio3_addrs,
1807 .user = OCP_USER_MPU | OCP_USER_SDMA,
1810 /* l4_per -> gpio4 */
1811 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1813 .pa_start = 0x49054000,
1814 .pa_end = 0x490541ff,
1815 .flags = ADDR_TYPE_RT
1820 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1821 .master = &omap3xxx_l4_per_hwmod,
1822 .slave = &omap3xxx_gpio4_hwmod,
1823 .addr = omap3xxx_gpio4_addrs,
1824 .user = OCP_USER_MPU | OCP_USER_SDMA,
1827 /* l4_per -> gpio5 */
1828 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1830 .pa_start = 0x49056000,
1831 .pa_end = 0x490561ff,
1832 .flags = ADDR_TYPE_RT
1837 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1838 .master = &omap3xxx_l4_per_hwmod,
1839 .slave = &omap3xxx_gpio5_hwmod,
1840 .addr = omap3xxx_gpio5_addrs,
1841 .user = OCP_USER_MPU | OCP_USER_SDMA,
1844 /* l4_per -> gpio6 */
1845 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1847 .pa_start = 0x49058000,
1848 .pa_end = 0x490581ff,
1849 .flags = ADDR_TYPE_RT
1854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1855 .master = &omap3xxx_l4_per_hwmod,
1856 .slave = &omap3xxx_gpio6_hwmod,
1857 .addr = omap3xxx_gpio6_addrs,
1858 .user = OCP_USER_MPU | OCP_USER_SDMA,
1863 * general purpose io module
1866 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1868 .sysc_offs = 0x0010,
1869 .syss_offs = 0x0014,
1870 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1871 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1872 SYSS_HAS_RESET_STATUS),
1873 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1874 .sysc_fields = &omap_hwmod_sysc_type1,
1877 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1879 .sysc = &omap3xxx_gpio_sysc,
1884 static struct omap_gpio_dev_attr gpio_dev_attr = {
1890 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1891 { .role = "dbclk", .clk = "gpio1_dbck", },
1894 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1895 &omap3xxx_l4_wkup__gpio1,
1898 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1900 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1901 .mpu_irqs = omap2_gpio1_irqs,
1902 .main_clk = "gpio1_ick",
1903 .opt_clks = gpio1_opt_clks,
1904 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1908 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1909 .module_offs = WKUP_MOD,
1911 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1914 .slaves = omap3xxx_gpio1_slaves,
1915 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1916 .class = &omap3xxx_gpio_hwmod_class,
1917 .dev_attr = &gpio_dev_attr,
1921 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1922 { .role = "dbclk", .clk = "gpio2_dbck", },
1925 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1926 &omap3xxx_l4_per__gpio2,
1929 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1931 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1932 .mpu_irqs = omap2_gpio2_irqs,
1933 .main_clk = "gpio2_ick",
1934 .opt_clks = gpio2_opt_clks,
1935 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1939 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1940 .module_offs = OMAP3430_PER_MOD,
1942 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1945 .slaves = omap3xxx_gpio2_slaves,
1946 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1947 .class = &omap3xxx_gpio_hwmod_class,
1948 .dev_attr = &gpio_dev_attr,
1952 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1953 { .role = "dbclk", .clk = "gpio3_dbck", },
1956 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1957 &omap3xxx_l4_per__gpio3,
1960 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1962 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1963 .mpu_irqs = omap2_gpio3_irqs,
1964 .main_clk = "gpio3_ick",
1965 .opt_clks = gpio3_opt_clks,
1966 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1970 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1971 .module_offs = OMAP3430_PER_MOD,
1973 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1976 .slaves = omap3xxx_gpio3_slaves,
1977 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1978 .class = &omap3xxx_gpio_hwmod_class,
1979 .dev_attr = &gpio_dev_attr,
1983 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1984 { .role = "dbclk", .clk = "gpio4_dbck", },
1987 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1988 &omap3xxx_l4_per__gpio4,
1991 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1993 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1994 .mpu_irqs = omap2_gpio4_irqs,
1995 .main_clk = "gpio4_ick",
1996 .opt_clks = gpio4_opt_clks,
1997 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2001 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2002 .module_offs = OMAP3430_PER_MOD,
2004 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2007 .slaves = omap3xxx_gpio4_slaves,
2008 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2009 .class = &omap3xxx_gpio_hwmod_class,
2010 .dev_attr = &gpio_dev_attr,
2014 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2015 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2019 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2020 { .role = "dbclk", .clk = "gpio5_dbck", },
2023 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2024 &omap3xxx_l4_per__gpio5,
2027 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2029 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2030 .mpu_irqs = omap3xxx_gpio5_irqs,
2031 .main_clk = "gpio5_ick",
2032 .opt_clks = gpio5_opt_clks,
2033 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2037 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2038 .module_offs = OMAP3430_PER_MOD,
2040 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2043 .slaves = omap3xxx_gpio5_slaves,
2044 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2045 .class = &omap3xxx_gpio_hwmod_class,
2046 .dev_attr = &gpio_dev_attr,
2050 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2051 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2055 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2056 { .role = "dbclk", .clk = "gpio6_dbck", },
2059 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2060 &omap3xxx_l4_per__gpio6,
2063 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2065 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2066 .mpu_irqs = omap3xxx_gpio6_irqs,
2067 .main_clk = "gpio6_ick",
2068 .opt_clks = gpio6_opt_clks,
2069 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2073 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2074 .module_offs = OMAP3430_PER_MOD,
2076 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2079 .slaves = omap3xxx_gpio6_slaves,
2080 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2081 .class = &omap3xxx_gpio_hwmod_class,
2082 .dev_attr = &gpio_dev_attr,
2085 /* dma_system -> L3 */
2086 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2087 .master = &omap3xxx_dma_system_hwmod,
2088 .slave = &omap3xxx_l3_main_hwmod,
2089 .clk = "core_l3_ick",
2090 .user = OCP_USER_MPU | OCP_USER_SDMA,
2093 /* dma attributes */
2094 static struct omap_dma_dev_attr dma_dev_attr = {
2095 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2096 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2100 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2102 .sysc_offs = 0x002c,
2103 .syss_offs = 0x0028,
2104 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2105 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2106 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2107 SYSS_HAS_RESET_STATUS),
2108 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2109 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2110 .sysc_fields = &omap_hwmod_sysc_type1,
2113 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2115 .sysc = &omap3xxx_dma_sysc,
2119 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2121 .pa_start = 0x48056000,
2122 .pa_end = 0x48056fff,
2123 .flags = ADDR_TYPE_RT
2128 /* dma_system master ports */
2129 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2130 &omap3xxx_dma_system__l3,
2133 /* l4_cfg -> dma_system */
2134 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2135 .master = &omap3xxx_l4_core_hwmod,
2136 .slave = &omap3xxx_dma_system_hwmod,
2137 .clk = "core_l4_ick",
2138 .addr = omap3xxx_dma_system_addrs,
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2142 /* dma_system slave ports */
2143 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2144 &omap3xxx_l4_core__dma_system,
2147 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2149 .class = &omap3xxx_dma_hwmod_class,
2150 .mpu_irqs = omap2_dma_system_irqs,
2151 .main_clk = "core_l3_ick",
2154 .module_offs = CORE_MOD,
2156 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2158 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2161 .slaves = omap3xxx_dma_system_slaves,
2162 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2163 .masters = omap3xxx_dma_system_masters,
2164 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2165 .dev_attr = &dma_dev_attr,
2166 .flags = HWMOD_NO_IDLEST,
2171 * multi channel buffered serial port controller
2174 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2175 .sysc_offs = 0x008c,
2176 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2177 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2178 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2179 .sysc_fields = &omap_hwmod_sysc_type1,
2183 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2185 .sysc = &omap3xxx_mcbsp_sysc,
2186 .rev = MCBSP_CONFIG_TYPE3,
2190 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2191 { .name = "irq", .irq = 16 },
2192 { .name = "tx", .irq = 59 },
2193 { .name = "rx", .irq = 60 },
2197 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2200 .pa_start = 0x48074000,
2201 .pa_end = 0x480740ff,
2202 .flags = ADDR_TYPE_RT
2207 /* l4_core -> mcbsp1 */
2208 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2209 .master = &omap3xxx_l4_core_hwmod,
2210 .slave = &omap3xxx_mcbsp1_hwmod,
2211 .clk = "mcbsp1_ick",
2212 .addr = omap3xxx_mcbsp1_addrs,
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2216 /* mcbsp1 slave ports */
2217 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2218 &omap3xxx_l4_core__mcbsp1,
2221 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2223 .class = &omap3xxx_mcbsp_hwmod_class,
2224 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2225 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2226 .main_clk = "mcbsp1_fck",
2230 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2231 .module_offs = CORE_MOD,
2233 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2236 .slaves = omap3xxx_mcbsp1_slaves,
2237 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2241 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2242 { .name = "irq", .irq = 17 },
2243 { .name = "tx", .irq = 62 },
2244 { .name = "rx", .irq = 63 },
2248 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2251 .pa_start = 0x49022000,
2252 .pa_end = 0x490220ff,
2253 .flags = ADDR_TYPE_RT
2258 /* l4_per -> mcbsp2 */
2259 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2260 .master = &omap3xxx_l4_per_hwmod,
2261 .slave = &omap3xxx_mcbsp2_hwmod,
2262 .clk = "mcbsp2_ick",
2263 .addr = omap3xxx_mcbsp2_addrs,
2264 .user = OCP_USER_MPU | OCP_USER_SDMA,
2267 /* mcbsp2 slave ports */
2268 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2269 &omap3xxx_l4_per__mcbsp2,
2272 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2273 .sidetone = "mcbsp2_sidetone",
2276 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2278 .class = &omap3xxx_mcbsp_hwmod_class,
2279 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2280 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2281 .main_clk = "mcbsp2_fck",
2285 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2286 .module_offs = OMAP3430_PER_MOD,
2288 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2291 .slaves = omap3xxx_mcbsp2_slaves,
2292 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2293 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2297 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2298 { .name = "irq", .irq = 22 },
2299 { .name = "tx", .irq = 89 },
2300 { .name = "rx", .irq = 90 },
2304 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2307 .pa_start = 0x49024000,
2308 .pa_end = 0x490240ff,
2309 .flags = ADDR_TYPE_RT
2314 /* l4_per -> mcbsp3 */
2315 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2316 .master = &omap3xxx_l4_per_hwmod,
2317 .slave = &omap3xxx_mcbsp3_hwmod,
2318 .clk = "mcbsp3_ick",
2319 .addr = omap3xxx_mcbsp3_addrs,
2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2323 /* mcbsp3 slave ports */
2324 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2325 &omap3xxx_l4_per__mcbsp3,
2328 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2329 .sidetone = "mcbsp3_sidetone",
2332 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2334 .class = &omap3xxx_mcbsp_hwmod_class,
2335 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2336 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2337 .main_clk = "mcbsp3_fck",
2341 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2342 .module_offs = OMAP3430_PER_MOD,
2344 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2347 .slaves = omap3xxx_mcbsp3_slaves,
2348 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2349 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2353 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2354 { .name = "irq", .irq = 23 },
2355 { .name = "tx", .irq = 54 },
2356 { .name = "rx", .irq = 55 },
2360 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2361 { .name = "rx", .dma_req = 20 },
2362 { .name = "tx", .dma_req = 19 },
2366 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2369 .pa_start = 0x49026000,
2370 .pa_end = 0x490260ff,
2371 .flags = ADDR_TYPE_RT
2376 /* l4_per -> mcbsp4 */
2377 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2378 .master = &omap3xxx_l4_per_hwmod,
2379 .slave = &omap3xxx_mcbsp4_hwmod,
2380 .clk = "mcbsp4_ick",
2381 .addr = omap3xxx_mcbsp4_addrs,
2382 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385 /* mcbsp4 slave ports */
2386 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2387 &omap3xxx_l4_per__mcbsp4,
2390 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2392 .class = &omap3xxx_mcbsp_hwmod_class,
2393 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2394 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2395 .main_clk = "mcbsp4_fck",
2399 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2400 .module_offs = OMAP3430_PER_MOD,
2402 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2405 .slaves = omap3xxx_mcbsp4_slaves,
2406 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2410 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2411 { .name = "irq", .irq = 27 },
2412 { .name = "tx", .irq = 81 },
2413 { .name = "rx", .irq = 82 },
2417 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2418 { .name = "rx", .dma_req = 22 },
2419 { .name = "tx", .dma_req = 21 },
2423 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2426 .pa_start = 0x48096000,
2427 .pa_end = 0x480960ff,
2428 .flags = ADDR_TYPE_RT
2433 /* l4_core -> mcbsp5 */
2434 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2435 .master = &omap3xxx_l4_core_hwmod,
2436 .slave = &omap3xxx_mcbsp5_hwmod,
2437 .clk = "mcbsp5_ick",
2438 .addr = omap3xxx_mcbsp5_addrs,
2439 .user = OCP_USER_MPU | OCP_USER_SDMA,
2442 /* mcbsp5 slave ports */
2443 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2444 &omap3xxx_l4_core__mcbsp5,
2447 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2449 .class = &omap3xxx_mcbsp_hwmod_class,
2450 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2451 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2452 .main_clk = "mcbsp5_fck",
2456 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2457 .module_offs = CORE_MOD,
2459 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2462 .slaves = omap3xxx_mcbsp5_slaves,
2463 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2465 /* 'mcbsp sidetone' class */
2467 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2468 .sysc_offs = 0x0010,
2469 .sysc_flags = SYSC_HAS_AUTOIDLE,
2470 .sysc_fields = &omap_hwmod_sysc_type1,
2473 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2474 .name = "mcbsp_sidetone",
2475 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2478 /* mcbsp2_sidetone */
2479 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2480 { .name = "irq", .irq = 4 },
2484 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2487 .pa_start = 0x49028000,
2488 .pa_end = 0x490280ff,
2489 .flags = ADDR_TYPE_RT
2494 /* l4_per -> mcbsp2_sidetone */
2495 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2496 .master = &omap3xxx_l4_per_hwmod,
2497 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2498 .clk = "mcbsp2_ick",
2499 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2500 .user = OCP_USER_MPU,
2503 /* mcbsp2_sidetone slave ports */
2504 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2505 &omap3xxx_l4_per__mcbsp2_sidetone,
2508 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2509 .name = "mcbsp2_sidetone",
2510 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2511 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2512 .main_clk = "mcbsp2_fck",
2516 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2517 .module_offs = OMAP3430_PER_MOD,
2519 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2522 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2523 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2526 /* mcbsp3_sidetone */
2527 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2528 { .name = "irq", .irq = 5 },
2532 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2535 .pa_start = 0x4902A000,
2536 .pa_end = 0x4902A0ff,
2537 .flags = ADDR_TYPE_RT
2542 /* l4_per -> mcbsp3_sidetone */
2543 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2544 .master = &omap3xxx_l4_per_hwmod,
2545 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2546 .clk = "mcbsp3_ick",
2547 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2548 .user = OCP_USER_MPU,
2551 /* mcbsp3_sidetone slave ports */
2552 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2553 &omap3xxx_l4_per__mcbsp3_sidetone,
2556 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2557 .name = "mcbsp3_sidetone",
2558 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2559 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2560 .main_clk = "mcbsp3_fck",
2564 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2565 .module_offs = OMAP3430_PER_MOD,
2567 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2570 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2571 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2576 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2580 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2582 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2583 .clockact = CLOCKACT_TEST_ICLK,
2584 .sysc_fields = &omap34xx_sr_sysc_fields,
2587 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2588 .name = "smartreflex",
2589 .sysc = &omap34xx_sr_sysc,
2593 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2598 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2600 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2601 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2603 .sysc_fields = &omap36xx_sr_sysc_fields,
2606 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2607 .name = "smartreflex",
2608 .sysc = &omap36xx_sr_sysc,
2613 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2614 &omap3_l4_core__sr1,
2617 static struct omap_hwmod omap34xx_sr1_hwmod = {
2618 .name = "sr1_hwmod",
2619 .class = &omap34xx_smartreflex_hwmod_class,
2620 .main_clk = "sr1_fck",
2621 .vdd_name = "mpu_iva",
2625 .module_bit = OMAP3430_EN_SR1_SHIFT,
2626 .module_offs = WKUP_MOD,
2628 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2631 .slaves = omap3_sr1_slaves,
2632 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2633 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2636 static struct omap_hwmod omap36xx_sr1_hwmod = {
2637 .name = "sr1_hwmod",
2638 .class = &omap36xx_smartreflex_hwmod_class,
2639 .main_clk = "sr1_fck",
2640 .vdd_name = "mpu_iva",
2644 .module_bit = OMAP3430_EN_SR1_SHIFT,
2645 .module_offs = WKUP_MOD,
2647 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2650 .slaves = omap3_sr1_slaves,
2651 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2655 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2656 &omap3_l4_core__sr2,
2659 static struct omap_hwmod omap34xx_sr2_hwmod = {
2660 .name = "sr2_hwmod",
2661 .class = &omap34xx_smartreflex_hwmod_class,
2662 .main_clk = "sr2_fck",
2667 .module_bit = OMAP3430_EN_SR2_SHIFT,
2668 .module_offs = WKUP_MOD,
2670 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2673 .slaves = omap3_sr2_slaves,
2674 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2675 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2678 static struct omap_hwmod omap36xx_sr2_hwmod = {
2679 .name = "sr2_hwmod",
2680 .class = &omap36xx_smartreflex_hwmod_class,
2681 .main_clk = "sr2_fck",
2686 .module_bit = OMAP3430_EN_SR2_SHIFT,
2687 .module_offs = WKUP_MOD,
2689 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2692 .slaves = omap3_sr2_slaves,
2693 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2698 * mailbox module allowing communication between the on-chip processors
2699 * using a queued mailbox-interrupt mechanism.
2702 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2706 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2707 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2708 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2709 .sysc_fields = &omap_hwmod_sysc_type1,
2712 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2714 .sysc = &omap3xxx_mailbox_sysc,
2717 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2718 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2723 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2725 .pa_start = 0x48094000,
2726 .pa_end = 0x480941ff,
2727 .flags = ADDR_TYPE_RT,
2732 /* l4_core -> mailbox */
2733 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2734 .master = &omap3xxx_l4_core_hwmod,
2735 .slave = &omap3xxx_mailbox_hwmod,
2736 .addr = omap3xxx_mailbox_addrs,
2737 .user = OCP_USER_MPU | OCP_USER_SDMA,
2740 /* mailbox slave ports */
2741 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2742 &omap3xxx_l4_core__mailbox,
2745 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2747 .class = &omap3xxx_mailbox_hwmod_class,
2748 .mpu_irqs = omap3xxx_mailbox_irqs,
2749 .main_clk = "mailboxes_ick",
2753 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2754 .module_offs = CORE_MOD,
2756 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2759 .slaves = omap3xxx_mailbox_slaves,
2760 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2763 /* l4 core -> mcspi1 interface */
2764 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2765 .master = &omap3xxx_l4_core_hwmod,
2766 .slave = &omap34xx_mcspi1,
2767 .clk = "mcspi1_ick",
2768 .addr = omap2_mcspi1_addr_space,
2769 .user = OCP_USER_MPU | OCP_USER_SDMA,
2772 /* l4 core -> mcspi2 interface */
2773 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2774 .master = &omap3xxx_l4_core_hwmod,
2775 .slave = &omap34xx_mcspi2,
2776 .clk = "mcspi2_ick",
2777 .addr = omap2_mcspi2_addr_space,
2778 .user = OCP_USER_MPU | OCP_USER_SDMA,
2781 /* l4 core -> mcspi3 interface */
2782 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2783 .master = &omap3xxx_l4_core_hwmod,
2784 .slave = &omap34xx_mcspi3,
2785 .clk = "mcspi3_ick",
2786 .addr = omap2430_mcspi3_addr_space,
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2790 /* l4 core -> mcspi4 interface */
2791 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2793 .pa_start = 0x480ba000,
2794 .pa_end = 0x480ba0ff,
2795 .flags = ADDR_TYPE_RT,
2800 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2801 .master = &omap3xxx_l4_core_hwmod,
2802 .slave = &omap34xx_mcspi4,
2803 .clk = "mcspi4_ick",
2804 .addr = omap34xx_mcspi4_addr_space,
2805 .user = OCP_USER_MPU | OCP_USER_SDMA,
2810 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2814 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2816 .sysc_offs = 0x0010,
2817 .syss_offs = 0x0014,
2818 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2819 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2820 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2821 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2822 .sysc_fields = &omap_hwmod_sysc_type1,
2825 static struct omap_hwmod_class omap34xx_mcspi_class = {
2827 .sysc = &omap34xx_mcspi_sysc,
2828 .rev = OMAP3_MCSPI_REV,
2832 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2833 &omap34xx_l4_core__mcspi1,
2836 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2837 .num_chipselect = 4,
2840 static struct omap_hwmod omap34xx_mcspi1 = {
2842 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2843 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2844 .main_clk = "mcspi1_fck",
2847 .module_offs = CORE_MOD,
2849 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2851 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2854 .slaves = omap34xx_mcspi1_slaves,
2855 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2856 .class = &omap34xx_mcspi_class,
2857 .dev_attr = &omap_mcspi1_dev_attr,
2861 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2862 &omap34xx_l4_core__mcspi2,
2865 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2866 .num_chipselect = 2,
2869 static struct omap_hwmod omap34xx_mcspi2 = {
2871 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2872 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2873 .main_clk = "mcspi2_fck",
2876 .module_offs = CORE_MOD,
2878 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2880 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2883 .slaves = omap34xx_mcspi2_slaves,
2884 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2885 .class = &omap34xx_mcspi_class,
2886 .dev_attr = &omap_mcspi2_dev_attr,
2890 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2891 { .name = "irq", .irq = 91 }, /* 91 */
2895 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2896 { .name = "tx0", .dma_req = 15 },
2897 { .name = "rx0", .dma_req = 16 },
2898 { .name = "tx1", .dma_req = 23 },
2899 { .name = "rx1", .dma_req = 24 },
2903 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2904 &omap34xx_l4_core__mcspi3,
2907 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2908 .num_chipselect = 2,
2911 static struct omap_hwmod omap34xx_mcspi3 = {
2913 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2914 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2915 .main_clk = "mcspi3_fck",
2918 .module_offs = CORE_MOD,
2920 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2922 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2925 .slaves = omap34xx_mcspi3_slaves,
2926 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2927 .class = &omap34xx_mcspi_class,
2928 .dev_attr = &omap_mcspi3_dev_attr,
2932 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2933 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2937 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2938 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2939 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2943 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2944 &omap34xx_l4_core__mcspi4,
2947 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2948 .num_chipselect = 1,
2951 static struct omap_hwmod omap34xx_mcspi4 = {
2953 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2954 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2955 .main_clk = "mcspi4_fck",
2958 .module_offs = CORE_MOD,
2960 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2962 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2965 .slaves = omap34xx_mcspi4_slaves,
2966 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2967 .class = &omap34xx_mcspi_class,
2968 .dev_attr = &omap_mcspi4_dev_attr,
2974 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2976 .sysc_offs = 0x0404,
2977 .syss_offs = 0x0408,
2978 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2979 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2981 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2982 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2983 .sysc_fields = &omap_hwmod_sysc_type1,
2986 static struct omap_hwmod_class usbotg_class = {
2988 .sysc = &omap3xxx_usbhsotg_sysc,
2991 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2993 { .name = "mc", .irq = 92 },
2994 { .name = "dma", .irq = 93 },
2998 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2999 .name = "usb_otg_hs",
3000 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3001 .main_clk = "hsotgusb_ick",
3005 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3006 .module_offs = CORE_MOD,
3008 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3009 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3012 .masters = omap3xxx_usbhsotg_masters,
3013 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3014 .slaves = omap3xxx_usbhsotg_slaves,
3015 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3016 .class = &usbotg_class,
3019 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3020 * broken when autoidle is enabled
3021 * workaround is to disable the autoidle bit at module level.
3023 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3024 | HWMOD_SWSUP_MSTANDBY,
3028 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3030 { .name = "mc", .irq = 71 },
3034 static struct omap_hwmod_class am35xx_usbotg_class = {
3035 .name = "am35xx_usbotg",
3039 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3040 .name = "am35x_otg_hs",
3041 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3047 .masters = am35xx_usbhsotg_masters,
3048 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3049 .slaves = am35xx_usbhsotg_slaves,
3050 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3051 .class = &am35xx_usbotg_class,
3054 /* MMC/SD/SDIO common */
3056 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3060 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3061 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3062 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3063 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3064 .sysc_fields = &omap_hwmod_sysc_type1,
3067 static struct omap_hwmod_class omap34xx_mmc_class = {
3069 .sysc = &omap34xx_mmc_sysc,
3074 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3079 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3080 { .name = "tx", .dma_req = 61, },
3081 { .name = "rx", .dma_req = 62, },
3085 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3086 { .role = "dbck", .clk = "omap_32k_fck", },
3089 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3090 &omap3xxx_l4_core__mmc1,
3093 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3094 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3097 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3098 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
3099 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
3100 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
3103 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3105 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3106 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3107 .opt_clks = omap34xx_mmc1_opt_clks,
3108 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3109 .main_clk = "mmchs1_fck",
3112 .module_offs = CORE_MOD,
3114 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3116 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3119 .dev_attr = &mmc1_pre_es3_dev_attr,
3120 .slaves = omap3xxx_mmc1_slaves,
3121 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3122 .class = &omap34xx_mmc_class,
3125 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3127 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3128 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3129 .opt_clks = omap34xx_mmc1_opt_clks,
3130 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3131 .main_clk = "mmchs1_fck",
3134 .module_offs = CORE_MOD,
3136 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3138 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3141 .dev_attr = &mmc1_dev_attr,
3142 .slaves = omap3xxx_mmc1_slaves,
3143 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3144 .class = &omap34xx_mmc_class,
3149 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3150 { .irq = INT_24XX_MMC2_IRQ, },
3154 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3155 { .name = "tx", .dma_req = 47, },
3156 { .name = "rx", .dma_req = 48, },
3160 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3161 { .role = "dbck", .clk = "omap_32k_fck", },
3164 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3165 &omap3xxx_l4_core__mmc2,
3168 /* See 35xx errata 2.1.1.128 in SPRZ278F */
3169 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3170 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
3173 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3175 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3176 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3177 .opt_clks = omap34xx_mmc2_opt_clks,
3178 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3179 .main_clk = "mmchs2_fck",
3182 .module_offs = CORE_MOD,
3184 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3186 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3189 .dev_attr = &mmc2_pre_es3_dev_attr,
3190 .slaves = omap3xxx_mmc2_slaves,
3191 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3192 .class = &omap34xx_mmc_class,
3195 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3197 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3198 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3199 .opt_clks = omap34xx_mmc2_opt_clks,
3200 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3201 .main_clk = "mmchs2_fck",
3204 .module_offs = CORE_MOD,
3206 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3208 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3211 .slaves = omap3xxx_mmc2_slaves,
3212 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3213 .class = &omap34xx_mmc_class,
3218 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3223 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3224 { .name = "tx", .dma_req = 77, },
3225 { .name = "rx", .dma_req = 78, },
3229 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3230 { .role = "dbck", .clk = "omap_32k_fck", },
3233 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3234 &omap3xxx_l4_core__mmc3,
3237 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3239 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3240 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3241 .opt_clks = omap34xx_mmc3_opt_clks,
3242 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3243 .main_clk = "mmchs3_fck",
3247 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3249 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3252 .slaves = omap3xxx_mmc3_slaves,
3253 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3254 .class = &omap34xx_mmc_class,
3257 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3258 &omap3xxx_l3_main_hwmod,
3259 &omap3xxx_l4_core_hwmod,
3260 &omap3xxx_l4_per_hwmod,
3261 &omap3xxx_l4_wkup_hwmod,
3262 &omap3xxx_mmc3_hwmod,
3263 &omap3xxx_mpu_hwmod,
3265 &omap3xxx_timer1_hwmod,
3266 &omap3xxx_timer2_hwmod,
3267 &omap3xxx_timer3_hwmod,
3268 &omap3xxx_timer4_hwmod,
3269 &omap3xxx_timer5_hwmod,
3270 &omap3xxx_timer6_hwmod,
3271 &omap3xxx_timer7_hwmod,
3272 &omap3xxx_timer8_hwmod,
3273 &omap3xxx_timer9_hwmod,
3274 &omap3xxx_timer10_hwmod,
3275 &omap3xxx_timer11_hwmod,
3277 &omap3xxx_wd_timer2_hwmod,
3278 &omap3xxx_uart1_hwmod,
3279 &omap3xxx_uart2_hwmod,
3280 &omap3xxx_uart3_hwmod,
3283 &omap3xxx_i2c1_hwmod,
3284 &omap3xxx_i2c2_hwmod,
3285 &omap3xxx_i2c3_hwmod,
3288 &omap3xxx_gpio1_hwmod,
3289 &omap3xxx_gpio2_hwmod,
3290 &omap3xxx_gpio3_hwmod,
3291 &omap3xxx_gpio4_hwmod,
3292 &omap3xxx_gpio5_hwmod,
3293 &omap3xxx_gpio6_hwmod,
3295 /* dma_system class*/
3296 &omap3xxx_dma_system_hwmod,
3299 &omap3xxx_mcbsp1_hwmod,
3300 &omap3xxx_mcbsp2_hwmod,
3301 &omap3xxx_mcbsp3_hwmod,
3302 &omap3xxx_mcbsp4_hwmod,
3303 &omap3xxx_mcbsp5_hwmod,
3304 &omap3xxx_mcbsp2_sidetone_hwmod,
3305 &omap3xxx_mcbsp3_sidetone_hwmod,
3317 /* GP-only hwmods */
3318 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
3319 &omap3xxx_timer12_hwmod,
3323 /* 3430ES1-only hwmods */
3324 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3325 &omap3430es1_dss_core_hwmod,
3329 /* 3430ES2+-only hwmods */
3330 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3331 &omap3xxx_dss_core_hwmod,
3332 &omap3xxx_usbhsotg_hwmod,
3336 /* <= 3430ES3-only hwmods */
3337 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
3338 &omap3xxx_pre_es3_mmc1_hwmod,
3339 &omap3xxx_pre_es3_mmc2_hwmod,
3343 /* 3430ES3+-only hwmods */
3344 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
3345 &omap3xxx_es3plus_mmc1_hwmod,
3346 &omap3xxx_es3plus_mmc2_hwmod,
3350 /* 34xx-only hwmods (all ES revisions) */
3351 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3352 &omap3xxx_iva_hwmod,
3353 &omap34xx_sr1_hwmod,
3354 &omap34xx_sr2_hwmod,
3355 &omap3xxx_mailbox_hwmod,
3359 /* 36xx-only hwmods (all ES revisions) */
3360 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3361 &omap3xxx_iva_hwmod,
3362 &omap3xxx_uart4_hwmod,
3363 &omap3xxx_dss_core_hwmod,
3364 &omap36xx_sr1_hwmod,
3365 &omap36xx_sr2_hwmod,
3366 &omap3xxx_usbhsotg_hwmod,
3367 &omap3xxx_mailbox_hwmod,
3368 &omap3xxx_es3plus_mmc1_hwmod,
3369 &omap3xxx_es3plus_mmc2_hwmod,
3373 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3374 &omap3xxx_dss_core_hwmod, /* XXX ??? */
3375 &am35xx_usbhsotg_hwmod,
3376 &omap3xxx_es3plus_mmc1_hwmod,
3377 &omap3xxx_es3plus_mmc2_hwmod,
3381 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
3383 &omap3xxx_dss_dispc_hwmod,
3384 &omap3xxx_dss_dsi1_hwmod,
3385 &omap3xxx_dss_rfbi_hwmod,
3386 &omap3xxx_dss_venc_hwmod,
3390 int __init omap3xxx_hwmod_init(void)
3393 struct omap_hwmod **h = NULL;
3396 /* Register hwmods common to all OMAP3 */
3397 r = omap_hwmod_register(omap3xxx_hwmods);
3401 /* Register GP-only hwmods. */
3402 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3403 r = omap_hwmod_register(omap3xxx_gp_hwmods);
3411 * Register hwmods common to individual OMAP3 families, all
3412 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3413 * All possible revisions should be included in this conditional.
3415 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3416 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3417 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3418 h = omap34xx_hwmods;
3419 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3421 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3422 rev == OMAP3630_REV_ES1_2) {
3423 h = omap36xx_hwmods;
3425 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3429 r = omap_hwmod_register(h);
3434 * Register hwmods specific to certain ES levels of a
3435 * particular family of silicon (e.g., 34xx ES1.0)
3438 if (rev == OMAP3430_REV_ES1_0) {
3439 h = omap3430es1_hwmods;
3440 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3441 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3442 rev == OMAP3430_REV_ES3_1_2) {
3443 h = omap3430es2plus_hwmods;
3447 r = omap_hwmod_register(h);
3453 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3454 rev == OMAP3430_REV_ES2_1) {
3455 h = omap3430_pre_es3_hwmods;
3456 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3457 rev == OMAP3430_REV_ES3_1_2) {
3458 h = omap3430_es3plus_hwmods;
3462 r = omap_hwmod_register(h);
3467 * DSS code presumes that dss_core hwmod is handled first,
3468 * _before_ any other DSS related hwmods so register common
3469 * DSS hwmods last to ensure that dss_core is already registered.
3470 * Otherwise some change things may happen, for ex. if dispc
3471 * is handled before dss_core and DSS is enabled in bootloader
3472 * DIPSC will be reset with outputs enabled which sometimes leads
3473 * to unrecoverable L3 error.
3475 r = omap_hwmod_register(omap3xxx_dss_hwmods);