2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
25 #include <plat/smartreflex.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
29 #include "omap_hwmod_common_data.h"
31 #include "prm-regbits-34xx.h"
32 #include "cm-regbits-34xx.h"
34 #include <mach/am35xx.h>
37 * OMAP3xxx hardware module integration data
39 * ALl of the data in this section should be autogeneratable from the
40 * TI hardware database or other technical documentation. Data that
41 * is driver-specific or driver-kernel integration-specific belongs
45 static struct omap_hwmod omap3xxx_mpu_hwmod;
46 static struct omap_hwmod omap3xxx_iva_hwmod;
47 static struct omap_hwmod omap3xxx_l3_main_hwmod;
48 static struct omap_hwmod omap3xxx_l4_core_hwmod;
49 static struct omap_hwmod omap3xxx_l4_per_hwmod;
50 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
51 static struct omap_hwmod omap3430es1_dss_core_hwmod;
52 static struct omap_hwmod omap3xxx_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
55 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
56 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
57 static struct omap_hwmod omap3xxx_i2c1_hwmod;
58 static struct omap_hwmod omap3xxx_i2c2_hwmod;
59 static struct omap_hwmod omap3xxx_i2c3_hwmod;
60 static struct omap_hwmod omap3xxx_gpio1_hwmod;
61 static struct omap_hwmod omap3xxx_gpio2_hwmod;
62 static struct omap_hwmod omap3xxx_gpio3_hwmod;
63 static struct omap_hwmod omap3xxx_gpio4_hwmod;
64 static struct omap_hwmod omap3xxx_gpio5_hwmod;
65 static struct omap_hwmod omap3xxx_gpio6_hwmod;
66 static struct omap_hwmod omap34xx_sr1_hwmod;
67 static struct omap_hwmod omap34xx_sr2_hwmod;
68 static struct omap_hwmod omap34xx_mcspi1;
69 static struct omap_hwmod omap34xx_mcspi2;
70 static struct omap_hwmod omap34xx_mcspi3;
71 static struct omap_hwmod omap34xx_mcspi4;
72 static struct omap_hwmod am35xx_usbhsotg_hwmod;
74 static struct omap_hwmod omap3xxx_dma_system_hwmod;
76 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
77 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
78 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
79 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
84 /* L3 -> L4_CORE interface */
85 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
86 .master = &omap3xxx_l3_main_hwmod,
87 .slave = &omap3xxx_l4_core_hwmod,
88 .user = OCP_USER_MPU | OCP_USER_SDMA,
91 /* L3 -> L4_PER interface */
92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_per_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
98 /* MPU -> L3 interface */
99 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
100 .master = &omap3xxx_mpu_hwmod,
101 .slave = &omap3xxx_l3_main_hwmod,
102 .user = OCP_USER_MPU,
105 /* Slave interfaces on the L3 interconnect */
106 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
107 &omap3xxx_mpu__l3_main,
111 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
112 .master = &omap3xxx_dss_core_hwmod,
113 .slave = &omap3xxx_l3_main_hwmod,
116 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
117 .flags = OMAP_FIREWALL_L3,
120 .user = OCP_USER_MPU | OCP_USER_SDMA,
123 /* Master interfaces on the L3 interconnect */
124 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
125 &omap3xxx_l3_main__l4_core,
126 &omap3xxx_l3_main__l4_per,
130 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
132 .class = &l3_hwmod_class,
133 .masters = omap3xxx_l3_main_masters,
134 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
135 .slaves = omap3xxx_l3_main_slaves,
136 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
138 .flags = HWMOD_NO_IDLEST,
141 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
142 static struct omap_hwmod omap3xxx_uart1_hwmod;
143 static struct omap_hwmod omap3xxx_uart2_hwmod;
144 static struct omap_hwmod omap3xxx_uart3_hwmod;
145 static struct omap_hwmod omap3xxx_uart4_hwmod;
146 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
148 /* l3_core -> usbhsotg interface */
149 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
150 .master = &omap3xxx_usbhsotg_hwmod,
151 .slave = &omap3xxx_l3_main_hwmod,
152 .clk = "core_l3_ick",
153 .user = OCP_USER_MPU,
156 /* l3_core -> am35xx_usbhsotg interface */
157 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
158 .master = &am35xx_usbhsotg_hwmod,
159 .slave = &omap3xxx_l3_main_hwmod,
160 .clk = "core_l3_ick",
161 .user = OCP_USER_MPU,
163 /* L4_CORE -> L4_WKUP interface */
164 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
165 .master = &omap3xxx_l4_core_hwmod,
166 .slave = &omap3xxx_l4_wkup_hwmod,
167 .user = OCP_USER_MPU | OCP_USER_SDMA,
170 /* L4 CORE -> UART1 interface */
171 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
173 .pa_start = OMAP3_UART1_BASE,
174 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
175 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
179 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
180 .master = &omap3xxx_l4_core_hwmod,
181 .slave = &omap3xxx_uart1_hwmod,
183 .addr = omap3xxx_uart1_addr_space,
184 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
185 .user = OCP_USER_MPU | OCP_USER_SDMA,
188 /* L4 CORE -> UART2 interface */
189 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
191 .pa_start = OMAP3_UART2_BASE,
192 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
193 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
197 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
198 .master = &omap3xxx_l4_core_hwmod,
199 .slave = &omap3xxx_uart2_hwmod,
201 .addr = omap3xxx_uart2_addr_space,
202 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
206 /* L4 PER -> UART3 interface */
207 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
209 .pa_start = OMAP3_UART3_BASE,
210 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
211 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
215 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
216 .master = &omap3xxx_l4_per_hwmod,
217 .slave = &omap3xxx_uart3_hwmod,
219 .addr = omap3xxx_uart3_addr_space,
220 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
224 /* L4 PER -> UART4 interface */
225 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
227 .pa_start = OMAP3_UART4_BASE,
228 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
229 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
233 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
234 .master = &omap3xxx_l4_per_hwmod,
235 .slave = &omap3xxx_uart4_hwmod,
237 .addr = omap3xxx_uart4_addr_space,
238 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
242 /* I2C IP block address space length (in bytes) */
243 #define OMAP2_I2C_AS_LEN 128
245 /* L4 CORE -> I2C1 interface */
246 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
248 .pa_start = 0x48070000,
249 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
250 .flags = ADDR_TYPE_RT,
254 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
255 .master = &omap3xxx_l4_core_hwmod,
256 .slave = &omap3xxx_i2c1_hwmod,
258 .addr = omap3xxx_i2c1_addr_space,
259 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
262 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
264 .flags = OMAP_FIREWALL_L4,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
270 /* L4 CORE -> I2C2 interface */
271 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
273 .pa_start = 0x48072000,
274 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
275 .flags = ADDR_TYPE_RT,
279 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
280 .master = &omap3xxx_l4_core_hwmod,
281 .slave = &omap3xxx_i2c2_hwmod,
283 .addr = omap3xxx_i2c2_addr_space,
284 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
287 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
289 .flags = OMAP_FIREWALL_L4,
292 .user = OCP_USER_MPU | OCP_USER_SDMA,
295 /* L4 CORE -> I2C3 interface */
296 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
298 .pa_start = 0x48060000,
299 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
300 .flags = ADDR_TYPE_RT,
304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap3xxx_i2c3_hwmod,
308 .addr = omap3xxx_i2c3_addr_space,
309 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
312 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
314 .flags = OMAP_FIREWALL_L4,
317 .user = OCP_USER_MPU | OCP_USER_SDMA,
320 /* L4 CORE -> SR1 interface */
321 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
323 .pa_start = OMAP34XX_SR1_BASE,
324 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
325 .flags = ADDR_TYPE_RT,
329 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
330 .master = &omap3xxx_l4_core_hwmod,
331 .slave = &omap34xx_sr1_hwmod,
333 .addr = omap3_sr1_addr_space,
334 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
335 .user = OCP_USER_MPU,
338 /* L4 CORE -> SR1 interface */
339 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
341 .pa_start = OMAP34XX_SR2_BASE,
342 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
343 .flags = ADDR_TYPE_RT,
347 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
348 .master = &omap3xxx_l4_core_hwmod,
349 .slave = &omap34xx_sr2_hwmod,
351 .addr = omap3_sr2_addr_space,
352 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
353 .user = OCP_USER_MPU,
357 * usbhsotg interface data
360 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
362 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
363 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
364 .flags = ADDR_TYPE_RT
368 /* l4_core -> usbhsotg */
369 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
370 .master = &omap3xxx_l4_core_hwmod,
371 .slave = &omap3xxx_usbhsotg_hwmod,
373 .addr = omap3xxx_usbhsotg_addrs,
374 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
375 .user = OCP_USER_MPU,
378 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
379 &omap3xxx_usbhsotg__l3,
382 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
383 &omap3xxx_l4_core__usbhsotg,
386 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
388 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
389 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
390 .flags = ADDR_TYPE_RT
394 /* l4_core -> usbhsotg */
395 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
396 .master = &omap3xxx_l4_core_hwmod,
397 .slave = &am35xx_usbhsotg_hwmod,
399 .addr = am35xx_usbhsotg_addrs,
400 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
401 .user = OCP_USER_MPU,
404 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
405 &am35xx_usbhsotg__l3,
408 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
409 &am35xx_l4_core__usbhsotg,
411 /* Slave interfaces on the L4_CORE interconnect */
412 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
413 &omap3xxx_l3_main__l4_core,
418 /* Master interfaces on the L4_CORE interconnect */
419 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
420 &omap3xxx_l4_core__l4_wkup,
421 &omap3_l4_core__uart1,
422 &omap3_l4_core__uart2,
423 &omap3_l4_core__i2c1,
424 &omap3_l4_core__i2c2,
425 &omap3_l4_core__i2c3,
429 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
431 .class = &l4_hwmod_class,
432 .masters = omap3xxx_l4_core_masters,
433 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
434 .slaves = omap3xxx_l4_core_slaves,
435 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
436 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
437 .flags = HWMOD_NO_IDLEST,
440 /* Slave interfaces on the L4_PER interconnect */
441 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
442 &omap3xxx_l3_main__l4_per,
445 /* Master interfaces on the L4_PER interconnect */
446 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
447 &omap3_l4_per__uart3,
448 &omap3_l4_per__uart4,
452 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
454 .class = &l4_hwmod_class,
455 .masters = omap3xxx_l4_per_masters,
456 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
457 .slaves = omap3xxx_l4_per_slaves,
458 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
459 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
460 .flags = HWMOD_NO_IDLEST,
463 /* Slave interfaces on the L4_WKUP interconnect */
464 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
465 &omap3xxx_l4_core__l4_wkup,
468 /* Master interfaces on the L4_WKUP interconnect */
469 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
473 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
475 .class = &l4_hwmod_class,
476 .masters = omap3xxx_l4_wkup_masters,
477 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
478 .slaves = omap3xxx_l4_wkup_slaves,
479 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
480 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
481 .flags = HWMOD_NO_IDLEST,
484 /* Master interfaces on the MPU device */
485 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
486 &omap3xxx_mpu__l3_main,
490 static struct omap_hwmod omap3xxx_mpu_hwmod = {
492 .class = &mpu_hwmod_class,
493 .main_clk = "arm_fck",
494 .masters = omap3xxx_mpu_masters,
495 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
496 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
500 * IVA2_2 interface data
503 /* IVA2 <- L3 interface */
504 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
505 .master = &omap3xxx_l3_main_hwmod,
506 .slave = &omap3xxx_iva_hwmod,
508 .user = OCP_USER_MPU | OCP_USER_SDMA,
511 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
519 static struct omap_hwmod omap3xxx_iva_hwmod = {
521 .class = &iva_hwmod_class,
522 .masters = omap3xxx_iva_masters,
523 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
527 /* l4_wkup -> wd_timer2 */
528 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
530 .pa_start = 0x48314000,
531 .pa_end = 0x4831407f,
532 .flags = ADDR_TYPE_RT
536 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
537 .master = &omap3xxx_l4_wkup_hwmod,
538 .slave = &omap3xxx_wd_timer2_hwmod,
540 .addr = omap3xxx_wd_timer2_addrs,
541 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
542 .user = OCP_USER_MPU | OCP_USER_SDMA,
547 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
551 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
555 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
556 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
557 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
558 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
559 .sysc_fields = &omap_hwmod_sysc_type1,
563 static struct omap_hwmod_class_sysconfig i2c_sysc = {
567 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
568 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
570 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
571 .sysc_fields = &omap_hwmod_sysc_type1,
574 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
576 .sysc = &omap3xxx_wd_timer_sysc,
577 .pre_shutdown = &omap2_wd_timer_disable
581 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
582 &omap3xxx_l4_wkup__wd_timer2,
585 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
587 .class = &omap3xxx_wd_timer_hwmod_class,
588 .main_clk = "wdt2_fck",
592 .module_bit = OMAP3430_EN_WDT2_SHIFT,
593 .module_offs = WKUP_MOD,
595 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
598 .slaves = omap3xxx_wd_timer2_slaves,
599 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
600 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
605 static struct omap_hwmod_class_sysconfig uart_sysc = {
609 .sysc_flags = (SYSC_HAS_SIDLEMODE |
610 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
616 static struct omap_hwmod_class uart_class = {
623 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
624 { .irq = INT_24XX_UART1_IRQ, },
627 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
628 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
629 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
632 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
633 &omap3_l4_core__uart1,
636 static struct omap_hwmod omap3xxx_uart1_hwmod = {
638 .mpu_irqs = uart1_mpu_irqs,
639 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
640 .sdma_reqs = uart1_sdma_reqs,
641 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
642 .main_clk = "uart1_fck",
645 .module_offs = CORE_MOD,
647 .module_bit = OMAP3430_EN_UART1_SHIFT,
649 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
652 .slaves = omap3xxx_uart1_slaves,
653 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
654 .class = &uart_class,
655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
660 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
661 { .irq = INT_24XX_UART2_IRQ, },
664 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
665 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
666 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
669 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
670 &omap3_l4_core__uart2,
673 static struct omap_hwmod omap3xxx_uart2_hwmod = {
675 .mpu_irqs = uart2_mpu_irqs,
676 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
677 .sdma_reqs = uart2_sdma_reqs,
678 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
679 .main_clk = "uart2_fck",
682 .module_offs = CORE_MOD,
684 .module_bit = OMAP3430_EN_UART2_SHIFT,
686 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
689 .slaves = omap3xxx_uart2_slaves,
690 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
691 .class = &uart_class,
692 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
697 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
698 { .irq = INT_24XX_UART3_IRQ, },
701 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
702 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
703 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
706 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
707 &omap3_l4_per__uart3,
710 static struct omap_hwmod omap3xxx_uart3_hwmod = {
712 .mpu_irqs = uart3_mpu_irqs,
713 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
714 .sdma_reqs = uart3_sdma_reqs,
715 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
716 .main_clk = "uart3_fck",
719 .module_offs = OMAP3430_PER_MOD,
721 .module_bit = OMAP3430_EN_UART3_SHIFT,
723 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
726 .slaves = omap3xxx_uart3_slaves,
727 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
728 .class = &uart_class,
729 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
734 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
735 { .irq = INT_36XX_UART4_IRQ, },
738 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
739 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
740 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
743 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
744 &omap3_l4_per__uart4,
747 static struct omap_hwmod omap3xxx_uart4_hwmod = {
749 .mpu_irqs = uart4_mpu_irqs,
750 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
751 .sdma_reqs = uart4_sdma_reqs,
752 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
753 .main_clk = "uart4_fck",
756 .module_offs = OMAP3430_PER_MOD,
758 .module_bit = OMAP3630_EN_UART4_SHIFT,
760 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
763 .slaves = omap3xxx_uart4_slaves,
764 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
765 .class = &uart_class,
766 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
769 static struct omap_hwmod_class i2c_class = {
779 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
783 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
784 .sysc_fields = &omap_hwmod_sysc_type1,
787 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
789 .sysc = &omap3xxx_dss_sysc,
793 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
797 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
798 { .name = "dispc", .dma_req = 5 },
799 { .name = "dsi1", .dma_req = 74 },
803 /* dss master ports */
804 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
808 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
810 .pa_start = 0x48050000,
811 .pa_end = 0x480503FF,
812 .flags = ADDR_TYPE_RT
817 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
818 .master = &omap3xxx_l4_core_hwmod,
819 .slave = &omap3430es1_dss_core_hwmod,
821 .addr = omap3xxx_dss_addrs,
822 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
825 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
826 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
827 .flags = OMAP_FIREWALL_L4,
830 .user = OCP_USER_MPU | OCP_USER_SDMA,
833 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
834 .master = &omap3xxx_l4_core_hwmod,
835 .slave = &omap3xxx_dss_core_hwmod,
837 .addr = omap3xxx_dss_addrs,
838 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
841 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
842 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
843 .flags = OMAP_FIREWALL_L4,
846 .user = OCP_USER_MPU | OCP_USER_SDMA,
849 /* dss slave ports */
850 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
851 &omap3430es1_l4_core__dss,
854 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
855 &omap3xxx_l4_core__dss,
858 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
859 { .role = "tv_clk", .clk = "dss_tv_fck" },
860 { .role = "dssclk", .clk = "dss_96m_fck" },
861 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
864 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
866 .class = &omap3xxx_dss_hwmod_class,
867 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
868 .mpu_irqs = omap3xxx_dss_irqs,
869 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
870 .sdma_reqs = omap3xxx_dss_sdma_chs,
871 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
876 .module_bit = OMAP3430_EN_DSS1_SHIFT,
877 .module_offs = OMAP3430_DSS_MOD,
879 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
882 .opt_clks = dss_opt_clks,
883 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
884 .slaves = omap3430es1_dss_slaves,
885 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
886 .masters = omap3xxx_dss_masters,
887 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
888 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
889 .flags = HWMOD_NO_IDLEST,
892 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
894 .class = &omap3xxx_dss_hwmod_class,
895 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
896 .mpu_irqs = omap3xxx_dss_irqs,
897 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs),
898 .sdma_reqs = omap3xxx_dss_sdma_chs,
899 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
904 .module_bit = OMAP3430_EN_DSS1_SHIFT,
905 .module_offs = OMAP3430_DSS_MOD,
907 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
908 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
911 .opt_clks = dss_opt_clks,
912 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
913 .slaves = omap3xxx_dss_slaves,
914 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
915 .masters = omap3xxx_dss_masters,
916 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
917 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
918 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
926 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
930 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
931 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
932 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
933 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
934 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
935 .sysc_fields = &omap_hwmod_sysc_type1,
938 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
940 .sysc = &omap3xxx_dispc_sysc,
943 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
945 .pa_start = 0x48050400,
946 .pa_end = 0x480507FF,
947 .flags = ADDR_TYPE_RT
951 /* l4_core -> dss_dispc */
952 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
953 .master = &omap3xxx_l4_core_hwmod,
954 .slave = &omap3xxx_dss_dispc_hwmod,
956 .addr = omap3xxx_dss_dispc_addrs,
957 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
960 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
961 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
962 .flags = OMAP_FIREWALL_L4,
965 .user = OCP_USER_MPU | OCP_USER_SDMA,
968 /* dss_dispc slave ports */
969 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
970 &omap3xxx_l4_core__dss_dispc,
973 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
975 .class = &omap3xxx_dispc_hwmod_class,
976 .main_clk = "dss1_alwon_fck",
980 .module_bit = OMAP3430_EN_DSS1_SHIFT,
981 .module_offs = OMAP3430_DSS_MOD,
984 .slaves = omap3xxx_dss_dispc_slaves,
985 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
986 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
987 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
988 CHIP_GE_OMAP3630ES1_1),
989 .flags = HWMOD_NO_IDLEST,
994 * display serial interface controller
997 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1002 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1004 .pa_start = 0x4804FC00,
1005 .pa_end = 0x4804FFFF,
1006 .flags = ADDR_TYPE_RT
1010 /* l4_core -> dss_dsi1 */
1011 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1012 .master = &omap3xxx_l4_core_hwmod,
1013 .slave = &omap3xxx_dss_dsi1_hwmod,
1014 .addr = omap3xxx_dss_dsi1_addrs,
1015 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1018 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1019 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1020 .flags = OMAP_FIREWALL_L4,
1023 .user = OCP_USER_MPU | OCP_USER_SDMA,
1026 /* dss_dsi1 slave ports */
1027 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1028 &omap3xxx_l4_core__dss_dsi1,
1031 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1033 .class = &omap3xxx_dsi_hwmod_class,
1034 .main_clk = "dss1_alwon_fck",
1038 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1039 .module_offs = OMAP3430_DSS_MOD,
1042 .slaves = omap3xxx_dss_dsi1_slaves,
1043 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1044 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1045 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1046 CHIP_GE_OMAP3630ES1_1),
1047 .flags = HWMOD_NO_IDLEST,
1052 * remote frame buffer interface
1055 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1057 .sysc_offs = 0x0010,
1058 .syss_offs = 0x0014,
1059 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1061 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1062 .sysc_fields = &omap_hwmod_sysc_type1,
1065 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1067 .sysc = &omap3xxx_rfbi_sysc,
1070 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1072 .pa_start = 0x48050800,
1073 .pa_end = 0x48050BFF,
1074 .flags = ADDR_TYPE_RT
1078 /* l4_core -> dss_rfbi */
1079 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1080 .master = &omap3xxx_l4_core_hwmod,
1081 .slave = &omap3xxx_dss_rfbi_hwmod,
1083 .addr = omap3xxx_dss_rfbi_addrs,
1084 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1087 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1088 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1089 .flags = OMAP_FIREWALL_L4,
1092 .user = OCP_USER_MPU | OCP_USER_SDMA,
1095 /* dss_rfbi slave ports */
1096 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1097 &omap3xxx_l4_core__dss_rfbi,
1100 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1102 .class = &omap3xxx_rfbi_hwmod_class,
1103 .main_clk = "dss1_alwon_fck",
1107 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1108 .module_offs = OMAP3430_DSS_MOD,
1111 .slaves = omap3xxx_dss_rfbi_slaves,
1112 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1113 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1114 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1115 CHIP_GE_OMAP3630ES1_1),
1116 .flags = HWMOD_NO_IDLEST,
1124 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1129 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1131 .pa_start = 0x48050C00,
1132 .pa_end = 0x48050FFF,
1133 .flags = ADDR_TYPE_RT
1137 /* l4_core -> dss_venc */
1138 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1139 .master = &omap3xxx_l4_core_hwmod,
1140 .slave = &omap3xxx_dss_venc_hwmod,
1141 .clk = "dss_tv_fck",
1142 .addr = omap3xxx_dss_venc_addrs,
1143 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1146 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1147 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1148 .flags = OMAP_FIREWALL_L4,
1151 .user = OCP_USER_MPU | OCP_USER_SDMA,
1154 /* dss_venc slave ports */
1155 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1156 &omap3xxx_l4_core__dss_venc,
1159 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1161 .class = &omap3xxx_venc_hwmod_class,
1162 .main_clk = "dss1_alwon_fck",
1166 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1167 .module_offs = OMAP3430_DSS_MOD,
1170 .slaves = omap3xxx_dss_venc_slaves,
1171 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1172 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1173 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1174 CHIP_GE_OMAP3630ES1_1),
1175 .flags = HWMOD_NO_IDLEST,
1180 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1181 .fifo_depth = 8, /* bytes */
1184 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1185 { .irq = INT_24XX_I2C1_IRQ, },
1188 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1189 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1190 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1193 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1194 &omap3_l4_core__i2c1,
1197 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1199 .mpu_irqs = i2c1_mpu_irqs,
1200 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1201 .sdma_reqs = i2c1_sdma_reqs,
1202 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1203 .main_clk = "i2c1_fck",
1206 .module_offs = CORE_MOD,
1208 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1210 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1213 .slaves = omap3xxx_i2c1_slaves,
1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1215 .class = &i2c_class,
1216 .dev_attr = &i2c1_dev_attr,
1217 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1222 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1223 .fifo_depth = 8, /* bytes */
1226 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1227 { .irq = INT_24XX_I2C2_IRQ, },
1230 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1231 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1232 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1235 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1236 &omap3_l4_core__i2c2,
1239 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1241 .mpu_irqs = i2c2_mpu_irqs,
1242 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1243 .sdma_reqs = i2c2_sdma_reqs,
1244 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1245 .main_clk = "i2c2_fck",
1248 .module_offs = CORE_MOD,
1250 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1252 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1255 .slaves = omap3xxx_i2c2_slaves,
1256 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1257 .class = &i2c_class,
1258 .dev_attr = &i2c2_dev_attr,
1259 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1264 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1265 .fifo_depth = 64, /* bytes */
1268 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1269 { .irq = INT_34XX_I2C3_IRQ, },
1272 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1273 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1274 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1277 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1278 &omap3_l4_core__i2c3,
1281 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1283 .mpu_irqs = i2c3_mpu_irqs,
1284 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1285 .sdma_reqs = i2c3_sdma_reqs,
1286 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1287 .main_clk = "i2c3_fck",
1290 .module_offs = CORE_MOD,
1292 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1294 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1297 .slaves = omap3xxx_i2c3_slaves,
1298 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1299 .class = &i2c_class,
1300 .dev_attr = &i2c3_dev_attr,
1301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1304 /* l4_wkup -> gpio1 */
1305 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1307 .pa_start = 0x48310000,
1308 .pa_end = 0x483101ff,
1309 .flags = ADDR_TYPE_RT
1313 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1314 .master = &omap3xxx_l4_wkup_hwmod,
1315 .slave = &omap3xxx_gpio1_hwmod,
1316 .addr = omap3xxx_gpio1_addrs,
1317 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
1318 .user = OCP_USER_MPU | OCP_USER_SDMA,
1321 /* l4_per -> gpio2 */
1322 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1324 .pa_start = 0x49050000,
1325 .pa_end = 0x490501ff,
1326 .flags = ADDR_TYPE_RT
1330 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1331 .master = &omap3xxx_l4_per_hwmod,
1332 .slave = &omap3xxx_gpio2_hwmod,
1333 .addr = omap3xxx_gpio2_addrs,
1334 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
1335 .user = OCP_USER_MPU | OCP_USER_SDMA,
1338 /* l4_per -> gpio3 */
1339 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1341 .pa_start = 0x49052000,
1342 .pa_end = 0x490521ff,
1343 .flags = ADDR_TYPE_RT
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1348 .master = &omap3xxx_l4_per_hwmod,
1349 .slave = &omap3xxx_gpio3_hwmod,
1350 .addr = omap3xxx_gpio3_addrs,
1351 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
1352 .user = OCP_USER_MPU | OCP_USER_SDMA,
1355 /* l4_per -> gpio4 */
1356 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1358 .pa_start = 0x49054000,
1359 .pa_end = 0x490541ff,
1360 .flags = ADDR_TYPE_RT
1364 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1365 .master = &omap3xxx_l4_per_hwmod,
1366 .slave = &omap3xxx_gpio4_hwmod,
1367 .addr = omap3xxx_gpio4_addrs,
1368 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
1369 .user = OCP_USER_MPU | OCP_USER_SDMA,
1372 /* l4_per -> gpio5 */
1373 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1375 .pa_start = 0x49056000,
1376 .pa_end = 0x490561ff,
1377 .flags = ADDR_TYPE_RT
1381 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1382 .master = &omap3xxx_l4_per_hwmod,
1383 .slave = &omap3xxx_gpio5_hwmod,
1384 .addr = omap3xxx_gpio5_addrs,
1385 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
1386 .user = OCP_USER_MPU | OCP_USER_SDMA,
1389 /* l4_per -> gpio6 */
1390 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1392 .pa_start = 0x49058000,
1393 .pa_end = 0x490581ff,
1394 .flags = ADDR_TYPE_RT
1398 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1399 .master = &omap3xxx_l4_per_hwmod,
1400 .slave = &omap3xxx_gpio6_hwmod,
1401 .addr = omap3xxx_gpio6_addrs,
1402 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
1403 .user = OCP_USER_MPU | OCP_USER_SDMA,
1408 * general purpose io module
1411 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1413 .sysc_offs = 0x0010,
1414 .syss_offs = 0x0014,
1415 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1416 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1417 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1418 .sysc_fields = &omap_hwmod_sysc_type1,
1421 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1423 .sysc = &omap3xxx_gpio_sysc,
1428 static struct omap_gpio_dev_attr gpio_dev_attr = {
1434 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
1435 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
1438 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1439 { .role = "dbclk", .clk = "gpio1_dbck", },
1442 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1443 &omap3xxx_l4_wkup__gpio1,
1446 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1448 .mpu_irqs = omap3xxx_gpio1_irqs,
1449 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
1450 .main_clk = "gpio1_ick",
1451 .opt_clks = gpio1_opt_clks,
1452 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1456 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1457 .module_offs = WKUP_MOD,
1459 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1462 .slaves = omap3xxx_gpio1_slaves,
1463 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1464 .class = &omap3xxx_gpio_hwmod_class,
1465 .dev_attr = &gpio_dev_attr,
1466 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1470 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
1471 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
1474 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1475 { .role = "dbclk", .clk = "gpio2_dbck", },
1478 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1479 &omap3xxx_l4_per__gpio2,
1482 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1484 .mpu_irqs = omap3xxx_gpio2_irqs,
1485 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
1486 .main_clk = "gpio2_ick",
1487 .opt_clks = gpio2_opt_clks,
1488 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1492 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1493 .module_offs = OMAP3430_PER_MOD,
1495 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1498 .slaves = omap3xxx_gpio2_slaves,
1499 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1500 .class = &omap3xxx_gpio_hwmod_class,
1501 .dev_attr = &gpio_dev_attr,
1502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1506 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
1507 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
1510 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1511 { .role = "dbclk", .clk = "gpio3_dbck", },
1514 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1515 &omap3xxx_l4_per__gpio3,
1518 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1520 .mpu_irqs = omap3xxx_gpio3_irqs,
1521 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
1522 .main_clk = "gpio3_ick",
1523 .opt_clks = gpio3_opt_clks,
1524 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1528 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1529 .module_offs = OMAP3430_PER_MOD,
1531 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1534 .slaves = omap3xxx_gpio3_slaves,
1535 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1536 .class = &omap3xxx_gpio_hwmod_class,
1537 .dev_attr = &gpio_dev_attr,
1538 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1542 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
1543 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
1546 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1547 { .role = "dbclk", .clk = "gpio4_dbck", },
1550 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1551 &omap3xxx_l4_per__gpio4,
1554 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1556 .mpu_irqs = omap3xxx_gpio4_irqs,
1557 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1558 .main_clk = "gpio4_ick",
1559 .opt_clks = gpio4_opt_clks,
1560 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1564 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1565 .module_offs = OMAP3430_PER_MOD,
1567 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1570 .slaves = omap3xxx_gpio4_slaves,
1571 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1572 .class = &omap3xxx_gpio_hwmod_class,
1573 .dev_attr = &gpio_dev_attr,
1574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1578 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1579 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1582 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1583 { .role = "dbclk", .clk = "gpio5_dbck", },
1586 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1587 &omap3xxx_l4_per__gpio5,
1590 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1592 .mpu_irqs = omap3xxx_gpio5_irqs,
1593 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1594 .main_clk = "gpio5_ick",
1595 .opt_clks = gpio5_opt_clks,
1596 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1600 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1601 .module_offs = OMAP3430_PER_MOD,
1603 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1606 .slaves = omap3xxx_gpio5_slaves,
1607 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1608 .class = &omap3xxx_gpio_hwmod_class,
1609 .dev_attr = &gpio_dev_attr,
1610 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1614 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1615 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1618 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1619 { .role = "dbclk", .clk = "gpio6_dbck", },
1622 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1623 &omap3xxx_l4_per__gpio6,
1626 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1628 .mpu_irqs = omap3xxx_gpio6_irqs,
1629 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1630 .main_clk = "gpio6_ick",
1631 .opt_clks = gpio6_opt_clks,
1632 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1636 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1637 .module_offs = OMAP3430_PER_MOD,
1639 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1642 .slaves = omap3xxx_gpio6_slaves,
1643 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1644 .class = &omap3xxx_gpio_hwmod_class,
1645 .dev_attr = &gpio_dev_attr,
1646 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1649 /* dma_system -> L3 */
1650 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1651 .master = &omap3xxx_dma_system_hwmod,
1652 .slave = &omap3xxx_l3_main_hwmod,
1653 .clk = "core_l3_ick",
1654 .user = OCP_USER_MPU | OCP_USER_SDMA,
1657 /* dma attributes */
1658 static struct omap_dma_dev_attr dma_dev_attr = {
1659 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1660 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1664 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1666 .sysc_offs = 0x002c,
1667 .syss_offs = 0x0028,
1668 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1669 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1670 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1671 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1672 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1673 .sysc_fields = &omap_hwmod_sysc_type1,
1676 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1678 .sysc = &omap3xxx_dma_sysc,
1682 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1683 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1684 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1685 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1686 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1689 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1691 .pa_start = 0x48056000,
1692 .pa_end = 0x4a0560ff,
1693 .flags = ADDR_TYPE_RT
1697 /* dma_system master ports */
1698 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1699 &omap3xxx_dma_system__l3,
1702 /* l4_cfg -> dma_system */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1704 .master = &omap3xxx_l4_core_hwmod,
1705 .slave = &omap3xxx_dma_system_hwmod,
1706 .clk = "core_l4_ick",
1707 .addr = omap3xxx_dma_system_addrs,
1708 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1709 .user = OCP_USER_MPU | OCP_USER_SDMA,
1712 /* dma_system slave ports */
1713 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1714 &omap3xxx_l4_core__dma_system,
1717 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1719 .class = &omap3xxx_dma_hwmod_class,
1720 .mpu_irqs = omap3xxx_dma_system_irqs,
1721 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1722 .main_clk = "core_l3_ick",
1725 .module_offs = CORE_MOD,
1727 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1729 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1732 .slaves = omap3xxx_dma_system_slaves,
1733 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1734 .masters = omap3xxx_dma_system_masters,
1735 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
1736 .dev_attr = &dma_dev_attr,
1737 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1738 .flags = HWMOD_NO_IDLEST,
1743 * multi channel buffered serial port controller
1746 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1747 .sysc_offs = 0x008c,
1748 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1749 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1750 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1751 .sysc_fields = &omap_hwmod_sysc_type1,
1755 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1757 .sysc = &omap3xxx_mcbsp_sysc,
1758 .rev = MCBSP_CONFIG_TYPE3,
1762 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1763 { .name = "irq", .irq = 16 },
1764 { .name = "tx", .irq = 59 },
1765 { .name = "rx", .irq = 60 },
1768 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
1769 { .name = "rx", .dma_req = 32 },
1770 { .name = "tx", .dma_req = 31 },
1773 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
1776 .pa_start = 0x48074000,
1777 .pa_end = 0x480740ff,
1778 .flags = ADDR_TYPE_RT
1782 /* l4_core -> mcbsp1 */
1783 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
1784 .master = &omap3xxx_l4_core_hwmod,
1785 .slave = &omap3xxx_mcbsp1_hwmod,
1786 .clk = "mcbsp1_ick",
1787 .addr = omap3xxx_mcbsp1_addrs,
1788 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
1789 .user = OCP_USER_MPU | OCP_USER_SDMA,
1792 /* mcbsp1 slave ports */
1793 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
1794 &omap3xxx_l4_core__mcbsp1,
1797 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1799 .class = &omap3xxx_mcbsp_hwmod_class,
1800 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1801 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
1802 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
1803 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
1804 .main_clk = "mcbsp1_fck",
1808 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1809 .module_offs = CORE_MOD,
1811 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1814 .slaves = omap3xxx_mcbsp1_slaves,
1815 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
1816 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1820 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1821 { .name = "irq", .irq = 17 },
1822 { .name = "tx", .irq = 62 },
1823 { .name = "rx", .irq = 63 },
1826 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
1827 { .name = "rx", .dma_req = 34 },
1828 { .name = "tx", .dma_req = 33 },
1831 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
1834 .pa_start = 0x49022000,
1835 .pa_end = 0x490220ff,
1836 .flags = ADDR_TYPE_RT
1840 /* l4_per -> mcbsp2 */
1841 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
1842 .master = &omap3xxx_l4_per_hwmod,
1843 .slave = &omap3xxx_mcbsp2_hwmod,
1844 .clk = "mcbsp2_ick",
1845 .addr = omap3xxx_mcbsp2_addrs,
1846 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
1847 .user = OCP_USER_MPU | OCP_USER_SDMA,
1850 /* mcbsp2 slave ports */
1851 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
1852 &omap3xxx_l4_per__mcbsp2,
1855 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1857 .class = &omap3xxx_mcbsp_hwmod_class,
1858 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1859 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
1860 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
1861 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
1862 .main_clk = "mcbsp2_fck",
1866 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1867 .module_offs = OMAP3430_PER_MOD,
1869 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1872 .slaves = omap3xxx_mcbsp2_slaves,
1873 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
1874 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1878 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1879 { .name = "irq", .irq = 22 },
1880 { .name = "tx", .irq = 89 },
1881 { .name = "rx", .irq = 90 },
1884 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
1885 { .name = "rx", .dma_req = 18 },
1886 { .name = "tx", .dma_req = 17 },
1889 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
1892 .pa_start = 0x49024000,
1893 .pa_end = 0x490240ff,
1894 .flags = ADDR_TYPE_RT
1898 /* l4_per -> mcbsp3 */
1899 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
1900 .master = &omap3xxx_l4_per_hwmod,
1901 .slave = &omap3xxx_mcbsp3_hwmod,
1902 .clk = "mcbsp3_ick",
1903 .addr = omap3xxx_mcbsp3_addrs,
1904 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1908 /* mcbsp3 slave ports */
1909 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
1910 &omap3xxx_l4_per__mcbsp3,
1913 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1915 .class = &omap3xxx_mcbsp_hwmod_class,
1916 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1917 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
1918 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
1919 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
1920 .main_clk = "mcbsp3_fck",
1924 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1925 .module_offs = OMAP3430_PER_MOD,
1927 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1930 .slaves = omap3xxx_mcbsp3_slaves,
1931 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
1932 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1936 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1937 { .name = "irq", .irq = 23 },
1938 { .name = "tx", .irq = 54 },
1939 { .name = "rx", .irq = 55 },
1942 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1943 { .name = "rx", .dma_req = 20 },
1944 { .name = "tx", .dma_req = 19 },
1947 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
1950 .pa_start = 0x49026000,
1951 .pa_end = 0x490260ff,
1952 .flags = ADDR_TYPE_RT
1956 /* l4_per -> mcbsp4 */
1957 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
1958 .master = &omap3xxx_l4_per_hwmod,
1959 .slave = &omap3xxx_mcbsp4_hwmod,
1960 .clk = "mcbsp4_ick",
1961 .addr = omap3xxx_mcbsp4_addrs,
1962 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
1963 .user = OCP_USER_MPU | OCP_USER_SDMA,
1966 /* mcbsp4 slave ports */
1967 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
1968 &omap3xxx_l4_per__mcbsp4,
1971 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1973 .class = &omap3xxx_mcbsp_hwmod_class,
1974 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1975 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
1976 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1977 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
1978 .main_clk = "mcbsp4_fck",
1982 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1983 .module_offs = OMAP3430_PER_MOD,
1985 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1988 .slaves = omap3xxx_mcbsp4_slaves,
1989 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
1990 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1994 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1995 { .name = "irq", .irq = 27 },
1996 { .name = "tx", .irq = 81 },
1997 { .name = "rx", .irq = 82 },
2000 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2001 { .name = "rx", .dma_req = 22 },
2002 { .name = "tx", .dma_req = 21 },
2005 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2008 .pa_start = 0x48096000,
2009 .pa_end = 0x480960ff,
2010 .flags = ADDR_TYPE_RT
2014 /* l4_core -> mcbsp5 */
2015 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2016 .master = &omap3xxx_l4_core_hwmod,
2017 .slave = &omap3xxx_mcbsp5_hwmod,
2018 .clk = "mcbsp5_ick",
2019 .addr = omap3xxx_mcbsp5_addrs,
2020 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2021 .user = OCP_USER_MPU | OCP_USER_SDMA,
2024 /* mcbsp5 slave ports */
2025 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2026 &omap3xxx_l4_core__mcbsp5,
2029 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2031 .class = &omap3xxx_mcbsp_hwmod_class,
2032 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2033 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2034 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2035 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2036 .main_clk = "mcbsp5_fck",
2040 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2041 .module_offs = CORE_MOD,
2043 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2046 .slaves = omap3xxx_mcbsp5_slaves,
2047 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2048 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2050 /* 'mcbsp sidetone' class */
2052 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2053 .sysc_offs = 0x0010,
2054 .sysc_flags = SYSC_HAS_AUTOIDLE,
2055 .sysc_fields = &omap_hwmod_sysc_type1,
2058 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2059 .name = "mcbsp_sidetone",
2060 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2063 /* mcbsp2_sidetone */
2064 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2065 { .name = "irq", .irq = 4 },
2068 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2071 .pa_start = 0x49028000,
2072 .pa_end = 0x490280ff,
2073 .flags = ADDR_TYPE_RT
2077 /* l4_per -> mcbsp2_sidetone */
2078 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2079 .master = &omap3xxx_l4_per_hwmod,
2080 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2081 .clk = "mcbsp2_ick",
2082 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2083 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2084 .user = OCP_USER_MPU,
2087 /* mcbsp2_sidetone slave ports */
2088 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2089 &omap3xxx_l4_per__mcbsp2_sidetone,
2092 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2093 .name = "mcbsp2_sidetone",
2094 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2095 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2096 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2097 .main_clk = "mcbsp2_fck",
2101 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2102 .module_offs = OMAP3430_PER_MOD,
2104 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2107 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2108 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2109 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2112 /* mcbsp3_sidetone */
2113 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2114 { .name = "irq", .irq = 5 },
2117 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2120 .pa_start = 0x4902A000,
2121 .pa_end = 0x4902A0ff,
2122 .flags = ADDR_TYPE_RT
2126 /* l4_per -> mcbsp3_sidetone */
2127 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2128 .master = &omap3xxx_l4_per_hwmod,
2129 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2130 .clk = "mcbsp3_ick",
2131 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2132 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2133 .user = OCP_USER_MPU,
2136 /* mcbsp3_sidetone slave ports */
2137 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2138 &omap3xxx_l4_per__mcbsp3_sidetone,
2141 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2142 .name = "mcbsp3_sidetone",
2143 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2144 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2145 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2146 .main_clk = "mcbsp3_fck",
2150 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2151 .module_offs = OMAP3430_PER_MOD,
2153 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2156 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2157 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2158 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2163 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2167 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2169 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2170 .clockact = CLOCKACT_TEST_ICLK,
2171 .sysc_fields = &omap34xx_sr_sysc_fields,
2174 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2175 .name = "smartreflex",
2176 .sysc = &omap34xx_sr_sysc,
2180 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2185 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2187 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2188 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2190 .sysc_fields = &omap36xx_sr_sysc_fields,
2193 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2194 .name = "smartreflex",
2195 .sysc = &omap36xx_sr_sysc,
2200 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2201 &omap3_l4_core__sr1,
2204 static struct omap_hwmod omap34xx_sr1_hwmod = {
2205 .name = "sr1_hwmod",
2206 .class = &omap34xx_smartreflex_hwmod_class,
2207 .main_clk = "sr1_fck",
2212 .module_bit = OMAP3430_EN_SR1_SHIFT,
2213 .module_offs = WKUP_MOD,
2215 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2218 .slaves = omap3_sr1_slaves,
2219 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2220 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2221 CHIP_IS_OMAP3430ES3_0 |
2222 CHIP_IS_OMAP3430ES3_1),
2223 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2226 static struct omap_hwmod omap36xx_sr1_hwmod = {
2227 .name = "sr1_hwmod",
2228 .class = &omap36xx_smartreflex_hwmod_class,
2229 .main_clk = "sr1_fck",
2234 .module_bit = OMAP3430_EN_SR1_SHIFT,
2235 .module_offs = WKUP_MOD,
2237 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2240 .slaves = omap3_sr1_slaves,
2241 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2246 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2247 &omap3_l4_core__sr2,
2250 static struct omap_hwmod omap34xx_sr2_hwmod = {
2251 .name = "sr2_hwmod",
2252 .class = &omap34xx_smartreflex_hwmod_class,
2253 .main_clk = "sr2_fck",
2258 .module_bit = OMAP3430_EN_SR2_SHIFT,
2259 .module_offs = WKUP_MOD,
2261 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2264 .slaves = omap3_sr2_slaves,
2265 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2266 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2267 CHIP_IS_OMAP3430ES3_0 |
2268 CHIP_IS_OMAP3430ES3_1),
2269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2272 static struct omap_hwmod omap36xx_sr2_hwmod = {
2273 .name = "sr2_hwmod",
2274 .class = &omap36xx_smartreflex_hwmod_class,
2275 .main_clk = "sr2_fck",
2280 .module_bit = OMAP3430_EN_SR2_SHIFT,
2281 .module_offs = WKUP_MOD,
2283 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2286 .slaves = omap3_sr2_slaves,
2287 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2288 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2293 * mailbox module allowing communication between the on-chip processors
2294 * using a queued mailbox-interrupt mechanism.
2297 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2301 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2302 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2304 .sysc_fields = &omap_hwmod_sysc_type1,
2307 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2309 .sysc = &omap3xxx_mailbox_sysc,
2312 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2313 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2317 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2319 .pa_start = 0x48094000,
2320 .pa_end = 0x480941ff,
2321 .flags = ADDR_TYPE_RT,
2325 /* l4_core -> mailbox */
2326 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2327 .master = &omap3xxx_l4_core_hwmod,
2328 .slave = &omap3xxx_mailbox_hwmod,
2329 .addr = omap3xxx_mailbox_addrs,
2330 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
2331 .user = OCP_USER_MPU | OCP_USER_SDMA,
2334 /* mailbox slave ports */
2335 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2336 &omap3xxx_l4_core__mailbox,
2339 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2341 .class = &omap3xxx_mailbox_hwmod_class,
2342 .mpu_irqs = omap3xxx_mailbox_irqs,
2343 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
2344 .main_clk = "mailboxes_ick",
2348 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2349 .module_offs = CORE_MOD,
2351 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2354 .slaves = omap3xxx_mailbox_slaves,
2355 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2356 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2359 /* l4 core -> mcspi1 interface */
2360 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
2362 .pa_start = 0x48098000,
2363 .pa_end = 0x480980ff,
2364 .flags = ADDR_TYPE_RT,
2368 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2369 .master = &omap3xxx_l4_core_hwmod,
2370 .slave = &omap34xx_mcspi1,
2371 .clk = "mcspi1_ick",
2372 .addr = omap34xx_mcspi1_addr_space,
2373 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
2374 .user = OCP_USER_MPU | OCP_USER_SDMA,
2377 /* l4 core -> mcspi2 interface */
2378 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
2380 .pa_start = 0x4809a000,
2381 .pa_end = 0x4809a0ff,
2382 .flags = ADDR_TYPE_RT,
2386 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2387 .master = &omap3xxx_l4_core_hwmod,
2388 .slave = &omap34xx_mcspi2,
2389 .clk = "mcspi2_ick",
2390 .addr = omap34xx_mcspi2_addr_space,
2391 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2395 /* l4 core -> mcspi3 interface */
2396 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
2398 .pa_start = 0x480b8000,
2399 .pa_end = 0x480b80ff,
2400 .flags = ADDR_TYPE_RT,
2404 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2405 .master = &omap3xxx_l4_core_hwmod,
2406 .slave = &omap34xx_mcspi3,
2407 .clk = "mcspi3_ick",
2408 .addr = omap34xx_mcspi3_addr_space,
2409 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
2410 .user = OCP_USER_MPU | OCP_USER_SDMA,
2413 /* l4 core -> mcspi4 interface */
2414 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2416 .pa_start = 0x480ba000,
2417 .pa_end = 0x480ba0ff,
2418 .flags = ADDR_TYPE_RT,
2422 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2423 .master = &omap3xxx_l4_core_hwmod,
2424 .slave = &omap34xx_mcspi4,
2425 .clk = "mcspi4_ick",
2426 .addr = omap34xx_mcspi4_addr_space,
2427 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
2428 .user = OCP_USER_MPU | OCP_USER_SDMA,
2433 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2437 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2439 .sysc_offs = 0x0010,
2440 .syss_offs = 0x0014,
2441 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2442 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2443 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2444 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2445 .sysc_fields = &omap_hwmod_sysc_type1,
2448 static struct omap_hwmod_class omap34xx_mcspi_class = {
2450 .sysc = &omap34xx_mcspi_sysc,
2451 .rev = OMAP3_MCSPI_REV,
2455 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
2456 { .name = "irq", .irq = 65 },
2459 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2460 { .name = "tx0", .dma_req = 35 },
2461 { .name = "rx0", .dma_req = 36 },
2462 { .name = "tx1", .dma_req = 37 },
2463 { .name = "rx1", .dma_req = 38 },
2464 { .name = "tx2", .dma_req = 39 },
2465 { .name = "rx2", .dma_req = 40 },
2466 { .name = "tx3", .dma_req = 41 },
2467 { .name = "rx3", .dma_req = 42 },
2470 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2471 &omap34xx_l4_core__mcspi1,
2474 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2475 .num_chipselect = 4,
2478 static struct omap_hwmod omap34xx_mcspi1 = {
2480 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
2481 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
2482 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
2483 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
2484 .main_clk = "mcspi1_fck",
2487 .module_offs = CORE_MOD,
2489 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2491 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2494 .slaves = omap34xx_mcspi1_slaves,
2495 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2496 .class = &omap34xx_mcspi_class,
2497 .dev_attr = &omap_mcspi1_dev_attr,
2498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2502 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
2503 { .name = "irq", .irq = 66 },
2506 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2507 { .name = "tx0", .dma_req = 43 },
2508 { .name = "rx0", .dma_req = 44 },
2509 { .name = "tx1", .dma_req = 45 },
2510 { .name = "rx1", .dma_req = 46 },
2513 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2514 &omap34xx_l4_core__mcspi2,
2517 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2518 .num_chipselect = 2,
2521 static struct omap_hwmod omap34xx_mcspi2 = {
2523 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
2524 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
2525 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
2526 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
2527 .main_clk = "mcspi2_fck",
2530 .module_offs = CORE_MOD,
2532 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2534 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2537 .slaves = omap34xx_mcspi2_slaves,
2538 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2539 .class = &omap34xx_mcspi_class,
2540 .dev_attr = &omap_mcspi2_dev_attr,
2541 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2545 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2546 { .name = "irq", .irq = 91 }, /* 91 */
2549 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2550 { .name = "tx0", .dma_req = 15 },
2551 { .name = "rx0", .dma_req = 16 },
2552 { .name = "tx1", .dma_req = 23 },
2553 { .name = "rx1", .dma_req = 24 },
2556 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2557 &omap34xx_l4_core__mcspi3,
2560 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2561 .num_chipselect = 2,
2564 static struct omap_hwmod omap34xx_mcspi3 = {
2566 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2567 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
2568 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2569 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
2570 .main_clk = "mcspi3_fck",
2573 .module_offs = CORE_MOD,
2575 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2577 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2580 .slaves = omap34xx_mcspi3_slaves,
2581 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2582 .class = &omap34xx_mcspi_class,
2583 .dev_attr = &omap_mcspi3_dev_attr,
2584 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2588 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2589 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2592 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2593 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2594 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2597 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2598 &omap34xx_l4_core__mcspi4,
2601 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2602 .num_chipselect = 1,
2605 static struct omap_hwmod omap34xx_mcspi4 = {
2607 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2608 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
2609 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2610 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
2611 .main_clk = "mcspi4_fck",
2614 .module_offs = CORE_MOD,
2616 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2618 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2621 .slaves = omap34xx_mcspi4_slaves,
2622 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2623 .class = &omap34xx_mcspi_class,
2624 .dev_attr = &omap_mcspi4_dev_attr,
2625 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2631 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2633 .sysc_offs = 0x0404,
2634 .syss_offs = 0x0408,
2635 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2636 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2638 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2639 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2640 .sysc_fields = &omap_hwmod_sysc_type1,
2643 static struct omap_hwmod_class usbotg_class = {
2645 .sysc = &omap3xxx_usbhsotg_sysc,
2648 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2650 { .name = "mc", .irq = 92 },
2651 { .name = "dma", .irq = 93 },
2654 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2655 .name = "usb_otg_hs",
2656 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
2657 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
2658 .main_clk = "hsotgusb_ick",
2662 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2663 .module_offs = CORE_MOD,
2665 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2666 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2669 .masters = omap3xxx_usbhsotg_masters,
2670 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2671 .slaves = omap3xxx_usbhsotg_slaves,
2672 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2673 .class = &usbotg_class,
2676 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2677 * broken when autoidle is enabled
2678 * workaround is to disable the autoidle bit at module level.
2680 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2681 | HWMOD_SWSUP_MSTANDBY,
2682 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
2686 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2688 { .name = "mc", .irq = 71 },
2691 static struct omap_hwmod_class am35xx_usbotg_class = {
2692 .name = "am35xx_usbotg",
2696 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2697 .name = "am35x_otg_hs",
2698 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
2699 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
2705 .masters = am35xx_usbhsotg_masters,
2706 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
2707 .slaves = am35xx_usbhsotg_slaves,
2708 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
2709 .class = &am35xx_usbotg_class,
2710 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2713 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2714 &omap3xxx_l3_main_hwmod,
2715 &omap3xxx_l4_core_hwmod,
2716 &omap3xxx_l4_per_hwmod,
2717 &omap3xxx_l4_wkup_hwmod,
2718 &omap3xxx_mpu_hwmod,
2719 &omap3xxx_iva_hwmod,
2720 &omap3xxx_wd_timer2_hwmod,
2721 &omap3xxx_uart1_hwmod,
2722 &omap3xxx_uart2_hwmod,
2723 &omap3xxx_uart3_hwmod,
2724 &omap3xxx_uart4_hwmod,
2726 &omap3430es1_dss_core_hwmod,
2727 &omap3xxx_dss_core_hwmod,
2728 &omap3xxx_dss_dispc_hwmod,
2729 &omap3xxx_dss_dsi1_hwmod,
2730 &omap3xxx_dss_rfbi_hwmod,
2731 &omap3xxx_dss_venc_hwmod,
2734 &omap3xxx_i2c1_hwmod,
2735 &omap3xxx_i2c2_hwmod,
2736 &omap3xxx_i2c3_hwmod,
2737 &omap34xx_sr1_hwmod,
2738 &omap34xx_sr2_hwmod,
2739 &omap36xx_sr1_hwmod,
2740 &omap36xx_sr2_hwmod,
2744 &omap3xxx_gpio1_hwmod,
2745 &omap3xxx_gpio2_hwmod,
2746 &omap3xxx_gpio3_hwmod,
2747 &omap3xxx_gpio4_hwmod,
2748 &omap3xxx_gpio5_hwmod,
2749 &omap3xxx_gpio6_hwmod,
2751 /* dma_system class*/
2752 &omap3xxx_dma_system_hwmod,
2755 &omap3xxx_mcbsp1_hwmod,
2756 &omap3xxx_mcbsp2_hwmod,
2757 &omap3xxx_mcbsp3_hwmod,
2758 &omap3xxx_mcbsp4_hwmod,
2759 &omap3xxx_mcbsp5_hwmod,
2760 &omap3xxx_mcbsp2_sidetone_hwmod,
2761 &omap3xxx_mcbsp3_sidetone_hwmod,
2764 &omap3xxx_mailbox_hwmod,
2773 &omap3xxx_usbhsotg_hwmod,
2775 /* usbotg for am35x */
2776 &am35xx_usbhsotg_hwmod,
2781 int __init omap3xxx_hwmod_init(void)
2783 return omap_hwmod_init(omap3xxx_hwmods);