arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106 };
 107
 108 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 109         {
 110                 .pa_start       = 0x68000000,
 111                 .pa_end         = 0x6800ffff,
 112                 .flags          = ADDR_TYPE_RT,
 113         },
 114 };
 115
 116 /* MPU -> L3 interface */
 117 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 118         .master   = &omap3xxx_mpu_hwmod,
 119         .slave    = &omap3xxx_l3_main_hwmod,
 120         .addr     = omap3xxx_l3_main_addrs,
 121         .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
 122         .user   = OCP_USER_MPU,
 123 };
 124
 125 /* Slave interfaces on the L3 interconnect */
 126 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 127         &omap3xxx_mpu__l3_main,
 128 };
 129
 130 /* DSS -> l3 */
 131 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 132         .master         = &omap3xxx_dss_core_hwmod,
 133         .slave          = &omap3xxx_l3_main_hwmod,
 134         .fw = {
 135                 .omap2 = {
 136                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 137                         .flags  = OMAP_FIREWALL_L3,
 138                 }
 139         },
 140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 141 };
 142
 143 /* Master interfaces on the L3 interconnect */
 144 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 145         &omap3xxx_l3_main__l4_core,
 146         &omap3xxx_l3_main__l4_per,
 147 };
 148
 149 /* L3 */
 150 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 151         .name           = "l3_main",
 152         .class          = &l3_hwmod_class,
 153         .mpu_irqs       = omap3xxx_l3_main_irqs,
 154         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
 194         {
 195                 .pa_start       = 0x4809c000,
 196                 .pa_end         = 0x4809c1ff,
 197                 .flags          = ADDR_TYPE_RT,
 198         },
 199 };
 200
 201 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 202         .master         = &omap3xxx_l4_core_hwmod,
 203         .slave          = &omap3xxx_mmc1_hwmod,
 204         .clk            = "mmchs1_ick",
 205         .addr           = omap3xxx_mmc1_addr_space,
 206         .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208         .flags          = OMAP_FIREWALL_L4
 209 };
 210
 211 /* L4 CORE -> MMC2 interface */
 212 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
 213         {
 214                 .pa_start       = 0x480b4000,
 215                 .pa_end         = 0x480b41ff,
 216                 .flags          = ADDR_TYPE_RT,
 217         },
 218 };
 219
 220 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 221         .master         = &omap3xxx_l4_core_hwmod,
 222         .slave          = &omap3xxx_mmc2_hwmod,
 223         .clk            = "mmchs2_ick",
 224         .addr           = omap3xxx_mmc2_addr_space,
 225         .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
 226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 227         .flags          = OMAP_FIREWALL_L4
 228 };
 229
 230 /* L4 CORE -> MMC3 interface */
 231 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 232         {
 233                 .pa_start       = 0x480ad000,
 234                 .pa_end         = 0x480ad1ff,
 235                 .flags          = ADDR_TYPE_RT,
 236         },
 237 };
 238
 239 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 240         .master         = &omap3xxx_l4_core_hwmod,
 241         .slave          = &omap3xxx_mmc3_hwmod,
 242         .clk            = "mmchs3_ick",
 243         .addr           = omap3xxx_mmc3_addr_space,
 244         .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246         .flags          = OMAP_FIREWALL_L4
 247 };
 248
 249 /* L4 CORE -> UART1 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART1_BASE,
 253                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256 };
 257
 258 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 259         .master         = &omap3xxx_l4_core_hwmod,
 260         .slave          = &omap3xxx_uart1_hwmod,
 261         .clk            = "uart1_ick",
 262         .addr           = omap3xxx_uart1_addr_space,
 263         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 CORE -> UART2 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART2_BASE,
 271                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274 };
 275
 276 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 277         .master         = &omap3xxx_l4_core_hwmod,
 278         .slave          = &omap3xxx_uart2_hwmod,
 279         .clk            = "uart2_ick",
 280         .addr           = omap3xxx_uart2_addr_space,
 281         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART3 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART3_BASE,
 289                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292 };
 293
 294 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 295         .master         = &omap3xxx_l4_per_hwmod,
 296         .slave          = &omap3xxx_uart3_hwmod,
 297         .clk            = "uart3_ick",
 298         .addr           = omap3xxx_uart3_addr_space,
 299         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 PER -> UART4 interface */
 304 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 305         {
 306                 .pa_start       = OMAP3_UART4_BASE,
 307                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 308                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 309         },
 310 };
 311
 312 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 313         .master         = &omap3xxx_l4_per_hwmod,
 314         .slave          = &omap3xxx_uart4_hwmod,
 315         .clk            = "uart4_ick",
 316         .addr           = omap3xxx_uart4_addr_space,
 317         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* I2C IP block address space length (in bytes) */
 322 #define OMAP2_I2C_AS_LEN                128
 323
 324 /* L4 CORE -> I2C1 interface */
 325 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 326         {
 327                 .pa_start       = 0x48070000,
 328                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 329                 .flags          = ADDR_TYPE_RT,
 330         },
 331 };
 332
 333 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 334         .master         = &omap3xxx_l4_core_hwmod,
 335         .slave          = &omap3xxx_i2c1_hwmod,
 336         .clk            = "i2c1_ick",
 337         .addr           = omap3xxx_i2c1_addr_space,
 338         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
 339         .fw = {
 340                 .omap2 = {
 341                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 342                         .l4_prot_group = 7,
 343                         .flags  = OMAP_FIREWALL_L4,
 344                 }
 345         },
 346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 347 };
 348
 349 /* L4 CORE -> I2C2 interface */
 350 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 351         {
 352                 .pa_start       = 0x48072000,
 353                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 354                 .flags          = ADDR_TYPE_RT,
 355         },
 356 };
 357
 358 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 359         .master         = &omap3xxx_l4_core_hwmod,
 360         .slave          = &omap3xxx_i2c2_hwmod,
 361         .clk            = "i2c2_ick",
 362         .addr           = omap3xxx_i2c2_addr_space,
 363         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
 364         .fw = {
 365                 .omap2 = {
 366                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 367                         .l4_prot_group = 7,
 368                         .flags = OMAP_FIREWALL_L4,
 369                 }
 370         },
 371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 372 };
 373
 374 /* L4 CORE -> I2C3 interface */
 375 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 376         {
 377                 .pa_start       = 0x48060000,
 378                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 379                 .flags          = ADDR_TYPE_RT,
 380         },
 381 };
 382
 383 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 384         .master         = &omap3xxx_l4_core_hwmod,
 385         .slave          = &omap3xxx_i2c3_hwmod,
 386         .clk            = "i2c3_ick",
 387         .addr           = omap3xxx_i2c3_addr_space,
 388         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
 389         .fw = {
 390                 .omap2 = {
 391                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 392                         .l4_prot_group = 7,
 393                         .flags = OMAP_FIREWALL_L4,
 394                 }
 395         },
 396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 397 };
 398
 399 /* L4 CORE -> SR1 interface */
 400 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 401         {
 402                 .pa_start       = OMAP34XX_SR1_BASE,
 403                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 404                 .flags          = ADDR_TYPE_RT,
 405         },
 406 };
 407
 408 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 409         .master         = &omap3xxx_l4_core_hwmod,
 410         .slave          = &omap34xx_sr1_hwmod,
 411         .clk            = "sr_l4_ick",
 412         .addr           = omap3_sr1_addr_space,
 413         .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
 414         .user           = OCP_USER_MPU,
 415 };
 416
 417 /* L4 CORE -> SR1 interface */
 418 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 419         {
 420                 .pa_start       = OMAP34XX_SR2_BASE,
 421                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 422                 .flags          = ADDR_TYPE_RT,
 423         },
 424 };
 425
 426 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 427         .master         = &omap3xxx_l4_core_hwmod,
 428         .slave          = &omap34xx_sr2_hwmod,
 429         .clk            = "sr_l4_ick",
 430         .addr           = omap3_sr2_addr_space,
 431         .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
 432         .user           = OCP_USER_MPU,
 433 };
 434
 435 /*
 436 * usbhsotg interface data
 437 */
 438
 439 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 440         {
 441                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 442                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 443                 .flags          = ADDR_TYPE_RT
 444         },
 445 };
 446
 447 /* l4_core -> usbhsotg  */
 448 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 449         .master         = &omap3xxx_l4_core_hwmod,
 450         .slave          = &omap3xxx_usbhsotg_hwmod,
 451         .clk            = "l4_ick",
 452         .addr           = omap3xxx_usbhsotg_addrs,
 453         .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
 454         .user           = OCP_USER_MPU,
 455 };
 456
 457 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 458         &omap3xxx_usbhsotg__l3,
 459 };
 460
 461 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 462         &omap3xxx_l4_core__usbhsotg,
 463 };
 464
 465 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 466         {
 467                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 468                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 469                 .flags          = ADDR_TYPE_RT
 470         },
 471 };
 472
 473 /* l4_core -> usbhsotg  */
 474 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 475         .master         = &omap3xxx_l4_core_hwmod,
 476         .slave          = &am35xx_usbhsotg_hwmod,
 477         .clk            = "l4_ick",
 478         .addr           = am35xx_usbhsotg_addrs,
 479         .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
 480         .user           = OCP_USER_MPU,
 481 };
 482
 483 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 484         &am35xx_usbhsotg__l3,
 485 };
 486
 487 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 488         &am35xx_l4_core__usbhsotg,
 489 };
 490 /* Slave interfaces on the L4_CORE interconnect */
 491 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 492         &omap3xxx_l3_main__l4_core,
 493 };
 494
 495 /* L4 CORE */
 496 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 497         .name           = "l4_core",
 498         .class          = &l4_hwmod_class,
 499         .slaves         = omap3xxx_l4_core_slaves,
 500         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 501         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 502         .flags          = HWMOD_NO_IDLEST,
 503 };
 504
 505 /* Slave interfaces on the L4_PER interconnect */
 506 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 507         &omap3xxx_l3_main__l4_per,
 508 };
 509
 510 /* L4 PER */
 511 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 512         .name           = "l4_per",
 513         .class          = &l4_hwmod_class,
 514         .slaves         = omap3xxx_l4_per_slaves,
 515         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 516         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 517         .flags          = HWMOD_NO_IDLEST,
 518 };
 519
 520 /* Slave interfaces on the L4_WKUP interconnect */
 521 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 522         &omap3xxx_l4_core__l4_wkup,
 523 };
 524
 525 /* L4 WKUP */
 526 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 527         .name           = "l4_wkup",
 528         .class          = &l4_hwmod_class,
 529         .slaves         = omap3xxx_l4_wkup_slaves,
 530         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 531         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 532         .flags          = HWMOD_NO_IDLEST,
 533 };
 534
 535 /* Master interfaces on the MPU device */
 536 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 537         &omap3xxx_mpu__l3_main,
 538 };
 539
 540 /* MPU */
 541 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 542         .name           = "mpu",
 543         .class          = &mpu_hwmod_class,
 544         .main_clk       = "arm_fck",
 545         .masters        = omap3xxx_mpu_masters,
 546         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 547         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 548 };
 549
 550 /*
 551  * IVA2_2 interface data
 552  */
 553
 554 /* IVA2 <- L3 interface */
 555 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 556         .master         = &omap3xxx_l3_main_hwmod,
 557         .slave          = &omap3xxx_iva_hwmod,
 558         .clk            = "iva2_ck",
 559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 560 };
 561
 562 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 563         &omap3xxx_l3__iva,
 564 };
 565
 566 /*
 567  * IVA2 (IVA2)
 568  */
 569
 570 static struct omap_hwmod omap3xxx_iva_hwmod = {
 571         .name           = "iva",
 572         .class          = &iva_hwmod_class,
 573         .masters        = omap3xxx_iva_masters,
 574         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 575         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 576 };
 577
 578 /* timer class */
 579 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 580         .rev_offs       = 0x0000,
 581         .sysc_offs      = 0x0010,
 582         .syss_offs      = 0x0014,
 583         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 584                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 585                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 591         .name = "timer",
 592         .sysc = &omap3xxx_timer_1ms_sysc,
 593         .rev = OMAP_TIMER_IP_VERSION_1,
 594 };
 595
 596 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 597         .rev_offs       = 0x0000,
 598         .sysc_offs      = 0x0010,
 599         .syss_offs      = 0x0014,
 600         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 601                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 602         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 603         .sysc_fields    = &omap_hwmod_sysc_type1,
 604 };
 605
 606 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 607         .name = "timer",
 608         .sysc = &omap3xxx_timer_sysc,
 609         .rev =  OMAP_TIMER_IP_VERSION_1,
 610 };
 611
 612 /* timer1 */
 613 static struct omap_hwmod omap3xxx_timer1_hwmod;
 614 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
 615         { .irq = 37, },
 616 };
 617
 618 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 619         {
 620                 .pa_start       = 0x48318000,
 621                 .pa_end         = 0x48318000 + SZ_1K - 1,
 622                 .flags          = ADDR_TYPE_RT
 623         },
 624 };
 625
 626 /* l4_wkup -> timer1 */
 627 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 628         .master         = &omap3xxx_l4_wkup_hwmod,
 629         .slave          = &omap3xxx_timer1_hwmod,
 630         .clk            = "gpt1_ick",
 631         .addr           = omap3xxx_timer1_addrs,
 632         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
 633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 634 };
 635
 636 /* timer1 slave port */
 637 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 638         &omap3xxx_l4_wkup__timer1,
 639 };
 640
 641 /* timer1 hwmod */
 642 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 643         .name           = "timer1",
 644         .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
 645         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
 646         .main_clk       = "gpt1_fck",
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 651                         .module_offs = WKUP_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 654                 },
 655         },
 656         .slaves         = omap3xxx_timer1_slaves,
 657         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 658         .class          = &omap3xxx_timer_1ms_hwmod_class,
 659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 660 };
 661
 662 /* timer2 */
 663 static struct omap_hwmod omap3xxx_timer2_hwmod;
 664 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
 665         { .irq = 38, },
 666 };
 667
 668 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 669         {
 670                 .pa_start       = 0x49032000,
 671                 .pa_end         = 0x49032000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674 };
 675
 676 /* l4_per -> timer2 */
 677 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 678         .master         = &omap3xxx_l4_per_hwmod,
 679         .slave          = &omap3xxx_timer2_hwmod,
 680         .clk            = "gpt2_ick",
 681         .addr           = omap3xxx_timer2_addrs,
 682         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer2 slave port */
 687 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 688         &omap3xxx_l4_per__timer2,
 689 };
 690
 691 /* timer2 hwmod */
 692 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 693         .name           = "timer2",
 694         .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
 695         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
 696         .main_clk       = "gpt2_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 701                         .module_offs = OMAP3430_PER_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap3xxx_timer2_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 708         .class          = &omap3xxx_timer_1ms_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 710 };
 711
 712 /* timer3 */
 713 static struct omap_hwmod omap3xxx_timer3_hwmod;
 714 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
 715         { .irq = 39, },
 716 };
 717
 718 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 719         {
 720                 .pa_start       = 0x49034000,
 721                 .pa_end         = 0x49034000 + SZ_1K - 1,
 722                 .flags          = ADDR_TYPE_RT
 723         },
 724 };
 725
 726 /* l4_per -> timer3 */
 727 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 728         .master         = &omap3xxx_l4_per_hwmod,
 729         .slave          = &omap3xxx_timer3_hwmod,
 730         .clk            = "gpt3_ick",
 731         .addr           = omap3xxx_timer3_addrs,
 732         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
 733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 734 };
 735
 736 /* timer3 slave port */
 737 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 738         &omap3xxx_l4_per__timer3,
 739 };
 740
 741 /* timer3 hwmod */
 742 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 743         .name           = "timer3",
 744         .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
 745         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
 746         .main_clk       = "gpt3_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .prcm_reg_id = 1,
 750                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 751                         .module_offs = OMAP3430_PER_MOD,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 754                 },
 755         },
 756         .slaves         = omap3xxx_timer3_slaves,
 757         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 758         .class          = &omap3xxx_timer_hwmod_class,
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 760 };
 761
 762 /* timer4 */
 763 static struct omap_hwmod omap3xxx_timer4_hwmod;
 764 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
 765         { .irq = 40, },
 766 };
 767
 768 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 769         {
 770                 .pa_start       = 0x49036000,
 771                 .pa_end         = 0x49036000 + SZ_1K - 1,
 772                 .flags          = ADDR_TYPE_RT
 773         },
 774 };
 775
 776 /* l4_per -> timer4 */
 777 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 778         .master         = &omap3xxx_l4_per_hwmod,
 779         .slave          = &omap3xxx_timer4_hwmod,
 780         .clk            = "gpt4_ick",
 781         .addr           = omap3xxx_timer4_addrs,
 782         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
 783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 784 };
 785
 786 /* timer4 slave port */
 787 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 788         &omap3xxx_l4_per__timer4,
 789 };
 790
 791 /* timer4 hwmod */
 792 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 793         .name           = "timer4",
 794         .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
 795         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
 796         .main_clk       = "gpt4_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 801                         .module_offs = OMAP3430_PER_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap3xxx_timer4_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 808         .class          = &omap3xxx_timer_hwmod_class,
 809         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 810 };
 811
 812 /* timer5 */
 813 static struct omap_hwmod omap3xxx_timer5_hwmod;
 814 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
 815         { .irq = 41, },
 816 };
 817
 818 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 819         {
 820                 .pa_start       = 0x49038000,
 821                 .pa_end         = 0x49038000 + SZ_1K - 1,
 822                 .flags          = ADDR_TYPE_RT
 823         },
 824 };
 825
 826 /* l4_per -> timer5 */
 827 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 828         .master         = &omap3xxx_l4_per_hwmod,
 829         .slave          = &omap3xxx_timer5_hwmod,
 830         .clk            = "gpt5_ick",
 831         .addr           = omap3xxx_timer5_addrs,
 832         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
 833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 834 };
 835
 836 /* timer5 slave port */
 837 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 838         &omap3xxx_l4_per__timer5,
 839 };
 840
 841 /* timer5 hwmod */
 842 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 843         .name           = "timer5",
 844         .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
 845         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
 846         .main_clk       = "gpt5_fck",
 847         .prcm           = {
 848                 .omap2 = {
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 851                         .module_offs = OMAP3430_PER_MOD,
 852                         .idlest_reg_id = 1,
 853                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 854                 },
 855         },
 856         .slaves         = omap3xxx_timer5_slaves,
 857         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 858         .class          = &omap3xxx_timer_hwmod_class,
 859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 860 };
 861
 862 /* timer6 */
 863 static struct omap_hwmod omap3xxx_timer6_hwmod;
 864 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
 865         { .irq = 42, },
 866 };
 867
 868 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 869         {
 870                 .pa_start       = 0x4903A000,
 871                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 872                 .flags          = ADDR_TYPE_RT
 873         },
 874 };
 875
 876 /* l4_per -> timer6 */
 877 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 878         .master         = &omap3xxx_l4_per_hwmod,
 879         .slave          = &omap3xxx_timer6_hwmod,
 880         .clk            = "gpt6_ick",
 881         .addr           = omap3xxx_timer6_addrs,
 882         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
 883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 884 };
 885
 886 /* timer6 slave port */
 887 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 888         &omap3xxx_l4_per__timer6,
 889 };
 890
 891 /* timer6 hwmod */
 892 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 893         .name           = "timer6",
 894         .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
 895         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
 896         .main_clk       = "gpt6_fck",
 897         .prcm           = {
 898                 .omap2 = {
 899                         .prcm_reg_id = 1,
 900                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 901                         .module_offs = OMAP3430_PER_MOD,
 902                         .idlest_reg_id = 1,
 903                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 904                 },
 905         },
 906         .slaves         = omap3xxx_timer6_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 908         .class          = &omap3xxx_timer_hwmod_class,
 909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 910 };
 911
 912 /* timer7 */
 913 static struct omap_hwmod omap3xxx_timer7_hwmod;
 914 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
 915         { .irq = 43, },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 919         {
 920                 .pa_start       = 0x4903C000,
 921                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924 };
 925
 926 /* l4_per -> timer7 */
 927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 928         .master         = &omap3xxx_l4_per_hwmod,
 929         .slave          = &omap3xxx_timer7_hwmod,
 930         .clk            = "gpt7_ick",
 931         .addr           = omap3xxx_timer7_addrs,
 932         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
 933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 934 };
 935
 936 /* timer7 slave port */
 937 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 938         &omap3xxx_l4_per__timer7,
 939 };
 940
 941 /* timer7 hwmod */
 942 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 943         .name           = "timer7",
 944         .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
 945         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
 946         .main_clk       = "gpt7_fck",
 947         .prcm           = {
 948                 .omap2 = {
 949                         .prcm_reg_id = 1,
 950                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 951                         .module_offs = OMAP3430_PER_MOD,
 952                         .idlest_reg_id = 1,
 953                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 954                 },
 955         },
 956         .slaves         = omap3xxx_timer7_slaves,
 957         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 958         .class          = &omap3xxx_timer_hwmod_class,
 959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 960 };
 961
 962 /* timer8 */
 963 static struct omap_hwmod omap3xxx_timer8_hwmod;
 964 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
 965         { .irq = 44, },
 966 };
 967
 968 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 969         {
 970                 .pa_start       = 0x4903E000,
 971                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 972                 .flags          = ADDR_TYPE_RT
 973         },
 974 };
 975
 976 /* l4_per -> timer8 */
 977 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 978         .master         = &omap3xxx_l4_per_hwmod,
 979         .slave          = &omap3xxx_timer8_hwmod,
 980         .clk            = "gpt8_ick",
 981         .addr           = omap3xxx_timer8_addrs,
 982         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
 983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 984 };
 985
 986 /* timer8 slave port */
 987 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 988         &omap3xxx_l4_per__timer8,
 989 };
 990
 991 /* timer8 hwmod */
 992 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 993         .name           = "timer8",
 994         .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
 995         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
 996         .main_clk       = "gpt8_fck",
 997         .prcm           = {
 998                 .omap2 = {
 999                         .prcm_reg_id = 1,
1000                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
1001                         .module_offs = OMAP3430_PER_MOD,
1002                         .idlest_reg_id = 1,
1003                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1004                 },
1005         },
1006         .slaves         = omap3xxx_timer8_slaves,
1007         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
1008         .class          = &omap3xxx_timer_hwmod_class,
1009         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1010 };
1011
1012 /* timer9 */
1013 static struct omap_hwmod omap3xxx_timer9_hwmod;
1014 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1015         { .irq = 45, },
1016 };
1017
1018 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1019         {
1020                 .pa_start       = 0x49040000,
1021                 .pa_end         = 0x49040000 + SZ_1K - 1,
1022                 .flags          = ADDR_TYPE_RT
1023         },
1024 };
1025
1026 /* l4_per -> timer9 */
1027 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1028         .master         = &omap3xxx_l4_per_hwmod,
1029         .slave          = &omap3xxx_timer9_hwmod,
1030         .clk            = "gpt9_ick",
1031         .addr           = omap3xxx_timer9_addrs,
1032         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer9 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1038         &omap3xxx_l4_per__timer9,
1039 };
1040
1041 /* timer9 hwmod */
1042 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1043         .name           = "timer9",
1044         .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
1045         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1046         .main_clk       = "gpt9_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .prcm_reg_id = 1,
1050                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1051                         .module_offs = OMAP3430_PER_MOD,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1054                 },
1055         },
1056         .slaves         = omap3xxx_timer9_slaves,
1057         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1058         .class          = &omap3xxx_timer_hwmod_class,
1059         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1060 };
1061
1062 /* timer10 */
1063 static struct omap_hwmod omap3xxx_timer10_hwmod;
1064 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1065         { .irq = 46, },
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1069         {
1070                 .pa_start       = 0x48086000,
1071                 .pa_end         = 0x48086000 + SZ_1K - 1,
1072                 .flags          = ADDR_TYPE_RT
1073         },
1074 };
1075
1076 /* l4_core -> timer10 */
1077 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1078         .master         = &omap3xxx_l4_core_hwmod,
1079         .slave          = &omap3xxx_timer10_hwmod,
1080         .clk            = "gpt10_ick",
1081         .addr           = omap3xxx_timer10_addrs,
1082         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer10 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1088         &omap3xxx_l4_core__timer10,
1089 };
1090
1091 /* timer10 hwmod */
1092 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1093         .name           = "timer10",
1094         .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
1095         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1096         .main_clk       = "gpt10_fck",
1097         .prcm           = {
1098                 .omap2 = {
1099                         .prcm_reg_id = 1,
1100                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1101                         .module_offs = CORE_MOD,
1102                         .idlest_reg_id = 1,
1103                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1104                 },
1105         },
1106         .slaves         = omap3xxx_timer10_slaves,
1107         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1108         .class          = &omap3xxx_timer_1ms_hwmod_class,
1109         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1110 };
1111
1112 /* timer11 */
1113 static struct omap_hwmod omap3xxx_timer11_hwmod;
1114 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1115         { .irq = 47, },
1116 };
1117
1118 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1119         {
1120                 .pa_start       = 0x48088000,
1121                 .pa_end         = 0x48088000 + SZ_1K - 1,
1122                 .flags          = ADDR_TYPE_RT
1123         },
1124 };
1125
1126 /* l4_core -> timer11 */
1127 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1128         .master         = &omap3xxx_l4_core_hwmod,
1129         .slave          = &omap3xxx_timer11_hwmod,
1130         .clk            = "gpt11_ick",
1131         .addr           = omap3xxx_timer11_addrs,
1132         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
1133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1134 };
1135
1136 /* timer11 slave port */
1137 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1138         &omap3xxx_l4_core__timer11,
1139 };
1140
1141 /* timer11 hwmod */
1142 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1143         .name           = "timer11",
1144         .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
1145         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1146         .main_clk       = "gpt11_fck",
1147         .prcm           = {
1148                 .omap2 = {
1149                         .prcm_reg_id = 1,
1150                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1151                         .module_offs = CORE_MOD,
1152                         .idlest_reg_id = 1,
1153                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1154                 },
1155         },
1156         .slaves         = omap3xxx_timer11_slaves,
1157         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1158         .class          = &omap3xxx_timer_hwmod_class,
1159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1160 };
1161
1162 /* timer12*/
1163 static struct omap_hwmod omap3xxx_timer12_hwmod;
1164 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1165         { .irq = 95, },
1166 };
1167
1168 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1169         {
1170                 .pa_start       = 0x48304000,
1171                 .pa_end         = 0x48304000 + SZ_1K - 1,
1172                 .flags          = ADDR_TYPE_RT
1173         },
1174 };
1175
1176 /* l4_core -> timer12 */
1177 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1178         .master         = &omap3xxx_l4_core_hwmod,
1179         .slave          = &omap3xxx_timer12_hwmod,
1180         .clk            = "gpt12_ick",
1181         .addr           = omap3xxx_timer12_addrs,
1182         .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
1183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1184 };
1185
1186 /* timer12 slave port */
1187 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1188         &omap3xxx_l4_core__timer12,
1189 };
1190
1191 /* timer12 hwmod */
1192 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1193         .name           = "timer12",
1194         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1195         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1196         .main_clk       = "gpt12_fck",
1197         .prcm           = {
1198                 .omap2 = {
1199                         .prcm_reg_id = 1,
1200                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1201                         .module_offs = WKUP_MOD,
1202                         .idlest_reg_id = 1,
1203                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1204                 },
1205         },
1206         .slaves         = omap3xxx_timer12_slaves,
1207         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1208         .class          = &omap3xxx_timer_hwmod_class,
1209         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1210 };
1211
1212 /* l4_wkup -> wd_timer2 */
1213 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1214         {
1215                 .pa_start       = 0x48314000,
1216                 .pa_end         = 0x4831407f,
1217                 .flags          = ADDR_TYPE_RT
1218         },
1219 };
1220
1221 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1222         .master         = &omap3xxx_l4_wkup_hwmod,
1223         .slave          = &omap3xxx_wd_timer2_hwmod,
1224         .clk            = "wdt2_ick",
1225         .addr           = omap3xxx_wd_timer2_addrs,
1226         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1228 };
1229
1230 /*
1231  * 'wd_timer' class
1232  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1233  * overflow condition
1234  */
1235
1236 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1237         .rev_offs       = 0x0000,
1238         .sysc_offs      = 0x0010,
1239         .syss_offs      = 0x0014,
1240         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1241                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1242                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1243                            SYSS_HAS_RESET_STATUS),
1244         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1245         .sysc_fields    = &omap_hwmod_sysc_type1,
1246 };
1247
1248 /* I2C common */
1249 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1250         .rev_offs       = 0x00,
1251         .sysc_offs      = 0x20,
1252         .syss_offs      = 0x10,
1253         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1254                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1255                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1256         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1257         .sysc_fields    = &omap_hwmod_sysc_type1,
1258 };
1259
1260 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1261         .name           = "wd_timer",
1262         .sysc           = &omap3xxx_wd_timer_sysc,
1263         .pre_shutdown   = &omap2_wd_timer_disable
1264 };
1265
1266 /* wd_timer2 */
1267 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1268         &omap3xxx_l4_wkup__wd_timer2,
1269 };
1270
1271 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1272         .name           = "wd_timer2",
1273         .class          = &omap3xxx_wd_timer_hwmod_class,
1274         .main_clk       = "wdt2_fck",
1275         .prcm           = {
1276                 .omap2 = {
1277                         .prcm_reg_id = 1,
1278                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1279                         .module_offs = WKUP_MOD,
1280                         .idlest_reg_id = 1,
1281                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1282                 },
1283         },
1284         .slaves         = omap3xxx_wd_timer2_slaves,
1285         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1286         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1287         /*
1288          * XXX: Use software supervised mode, HW supervised smartidle seems to
1289          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1290          */
1291         .flags          = HWMOD_SWSUP_SIDLE,
1292 };
1293
1294 /* UART common */
1295
1296 static struct omap_hwmod_class_sysconfig uart_sysc = {
1297         .rev_offs       = 0x50,
1298         .sysc_offs      = 0x54,
1299         .syss_offs      = 0x58,
1300         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1301                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1302                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1303         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304         .sysc_fields    = &omap_hwmod_sysc_type1,
1305 };
1306
1307 static struct omap_hwmod_class uart_class = {
1308         .name = "uart",
1309         .sysc = &uart_sysc,
1310 };
1311
1312 /* UART1 */
1313
1314 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1315         { .irq = INT_24XX_UART1_IRQ, },
1316 };
1317
1318 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1319         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1320         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1321 };
1322
1323 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1324         &omap3_l4_core__uart1,
1325 };
1326
1327 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1328         .name           = "uart1",
1329         .mpu_irqs       = uart1_mpu_irqs,
1330         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1331         .sdma_reqs      = uart1_sdma_reqs,
1332         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1333         .main_clk       = "uart1_fck",
1334         .prcm           = {
1335                 .omap2 = {
1336                         .module_offs = CORE_MOD,
1337                         .prcm_reg_id = 1,
1338                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1339                         .idlest_reg_id = 1,
1340                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1341                 },
1342         },
1343         .slaves         = omap3xxx_uart1_slaves,
1344         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1345         .class          = &uart_class,
1346         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1347 };
1348
1349 /* UART2 */
1350
1351 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1352         { .irq = INT_24XX_UART2_IRQ, },
1353 };
1354
1355 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1356         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1357         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1358 };
1359
1360 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1361         &omap3_l4_core__uart2,
1362 };
1363
1364 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1365         .name           = "uart2",
1366         .mpu_irqs       = uart2_mpu_irqs,
1367         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1368         .sdma_reqs      = uart2_sdma_reqs,
1369         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1370         .main_clk       = "uart2_fck",
1371         .prcm           = {
1372                 .omap2 = {
1373                         .module_offs = CORE_MOD,
1374                         .prcm_reg_id = 1,
1375                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1376                         .idlest_reg_id = 1,
1377                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1378                 },
1379         },
1380         .slaves         = omap3xxx_uart2_slaves,
1381         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1382         .class          = &uart_class,
1383         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1384 };
1385
1386 /* UART3 */
1387
1388 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1389         { .irq = INT_24XX_UART3_IRQ, },
1390 };
1391
1392 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1393         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1394         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1395 };
1396
1397 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1398         &omap3_l4_per__uart3,
1399 };
1400
1401 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1402         .name           = "uart3",
1403         .mpu_irqs       = uart3_mpu_irqs,
1404         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1405         .sdma_reqs      = uart3_sdma_reqs,
1406         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1407         .main_clk       = "uart3_fck",
1408         .prcm           = {
1409                 .omap2 = {
1410                         .module_offs = OMAP3430_PER_MOD,
1411                         .prcm_reg_id = 1,
1412                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1413                         .idlest_reg_id = 1,
1414                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1415                 },
1416         },
1417         .slaves         = omap3xxx_uart3_slaves,
1418         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1419         .class          = &uart_class,
1420         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1421 };
1422
1423 /* UART4 */
1424
1425 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1426         { .irq = INT_36XX_UART4_IRQ, },
1427 };
1428
1429 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1430         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1431         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1432 };
1433
1434 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1435         &omap3_l4_per__uart4,
1436 };
1437
1438 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1439         .name           = "uart4",
1440         .mpu_irqs       = uart4_mpu_irqs,
1441         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
1442         .sdma_reqs      = uart4_sdma_reqs,
1443         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
1444         .main_clk       = "uart4_fck",
1445         .prcm           = {
1446                 .omap2 = {
1447                         .module_offs = OMAP3430_PER_MOD,
1448                         .prcm_reg_id = 1,
1449                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1450                         .idlest_reg_id = 1,
1451                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1452                 },
1453         },
1454         .slaves         = omap3xxx_uart4_slaves,
1455         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1456         .class          = &uart_class,
1457         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1458 };
1459
1460 static struct omap_hwmod_class i2c_class = {
1461         .name = "i2c",
1462         .sysc = &i2c_sysc,
1463 };
1464
1465 /*
1466  * 'dss' class
1467  * display sub-system
1468  */
1469
1470 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1471         .rev_offs       = 0x0000,
1472         .sysc_offs      = 0x0010,
1473         .syss_offs      = 0x0014,
1474         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1479         .name = "dss",
1480         .sysc = &omap3xxx_dss_sysc,
1481 };
1482
1483 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1484         { .name = "dispc", .dma_req = 5 },
1485         { .name = "dsi1", .dma_req = 74 },
1486 };
1487
1488 /* dss */
1489 /* dss master ports */
1490 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1491         &omap3xxx_dss__l3,
1492 };
1493
1494 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1495         {
1496                 .pa_start       = 0x48050000,
1497                 .pa_end         = 0x480503FF,
1498                 .flags          = ADDR_TYPE_RT
1499         },
1500 };
1501
1502 /* l4_core -> dss */
1503 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1504         .master         = &omap3xxx_l4_core_hwmod,
1505         .slave          = &omap3430es1_dss_core_hwmod,
1506         .clk            = "dss_ick",
1507         .addr           = omap3xxx_dss_addrs,
1508         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
1509         .fw = {
1510                 .omap2 = {
1511                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1512                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1513                         .flags  = OMAP_FIREWALL_L4,
1514                 }
1515         },
1516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1517 };
1518
1519 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1520         .master         = &omap3xxx_l4_core_hwmod,
1521         .slave          = &omap3xxx_dss_core_hwmod,
1522         .clk            = "dss_ick",
1523         .addr           = omap3xxx_dss_addrs,
1524         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
1525         .fw = {
1526                 .omap2 = {
1527                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1528                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1529                         .flags  = OMAP_FIREWALL_L4,
1530                 }
1531         },
1532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1533 };
1534
1535 /* dss slave ports */
1536 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1537         &omap3430es1_l4_core__dss,
1538 };
1539
1540 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1541         &omap3xxx_l4_core__dss,
1542 };
1543
1544 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1545         { .role = "tv_clk", .clk = "dss_tv_fck" },
1546         { .role = "video_clk", .clk = "dss_96m_fck" },
1547         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1548 };
1549
1550 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1551         .name           = "dss_core",
1552         .class          = &omap3xxx_dss_hwmod_class,
1553         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1554         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1555         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1556
1557         .prcm           = {
1558                 .omap2 = {
1559                         .prcm_reg_id = 1,
1560                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1561                         .module_offs = OMAP3430_DSS_MOD,
1562                         .idlest_reg_id = 1,
1563                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1564                 },
1565         },
1566         .opt_clks       = dss_opt_clks,
1567         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1568         .slaves         = omap3430es1_dss_slaves,
1569         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1570         .masters        = omap3xxx_dss_masters,
1571         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1572         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1573         .flags          = HWMOD_NO_IDLEST,
1574 };
1575
1576 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1577         .name           = "dss_core",
1578         .class          = &omap3xxx_dss_hwmod_class,
1579         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1580         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1581         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1582
1583         .prcm           = {
1584                 .omap2 = {
1585                         .prcm_reg_id = 1,
1586                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1587                         .module_offs = OMAP3430_DSS_MOD,
1588                         .idlest_reg_id = 1,
1589                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1590                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1591                 },
1592         },
1593         .opt_clks       = dss_opt_clks,
1594         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1595         .slaves         = omap3xxx_dss_slaves,
1596         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1597         .masters        = omap3xxx_dss_masters,
1598         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1599         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1600                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1601 };
1602
1603 /*
1604  * 'dispc' class
1605  * display controller
1606  */
1607
1608 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1609         .rev_offs       = 0x0000,
1610         .sysc_offs      = 0x0010,
1611         .syss_offs      = 0x0014,
1612         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1613                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1614                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1616                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1617         .sysc_fields    = &omap_hwmod_sysc_type1,
1618 };
1619
1620 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1621         .name = "dispc",
1622         .sysc = &omap3xxx_dispc_sysc,
1623 };
1624
1625 static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1626         { .irq = 25 },
1627 };
1628
1629 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1630         {
1631                 .pa_start       = 0x48050400,
1632                 .pa_end         = 0x480507FF,
1633                 .flags          = ADDR_TYPE_RT
1634         },
1635 };
1636
1637 /* l4_core -> dss_dispc */
1638 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1639         .master         = &omap3xxx_l4_core_hwmod,
1640         .slave          = &omap3xxx_dss_dispc_hwmod,
1641         .clk            = "dss_ick",
1642         .addr           = omap3xxx_dss_dispc_addrs,
1643         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1644         .fw = {
1645                 .omap2 = {
1646                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1647                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1648                         .flags  = OMAP_FIREWALL_L4,
1649                 }
1650         },
1651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1652 };
1653
1654 /* dss_dispc slave ports */
1655 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1656         &omap3xxx_l4_core__dss_dispc,
1657 };
1658
1659 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1660         .name           = "dss_dispc",
1661         .class          = &omap3xxx_dispc_hwmod_class,
1662         .mpu_irqs       = omap3xxx_dispc_irqs,
1663         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dispc_irqs),
1664         .main_clk       = "dss1_alwon_fck",
1665         .prcm           = {
1666                 .omap2 = {
1667                         .prcm_reg_id = 1,
1668                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1669                         .module_offs = OMAP3430_DSS_MOD,
1670                 },
1671         },
1672         .slaves         = omap3xxx_dss_dispc_slaves,
1673         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1674         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1675                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1676                                 CHIP_GE_OMAP3630ES1_1),
1677         .flags          = HWMOD_NO_IDLEST,
1678 };
1679
1680 /*
1681  * 'dsi' class
1682  * display serial interface controller
1683  */
1684
1685 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1686         .name = "dsi",
1687 };
1688
1689 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1690         { .irq = 25 },
1691 };
1692
1693 /* dss_dsi1 */
1694 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1695         {
1696                 .pa_start       = 0x4804FC00,
1697                 .pa_end         = 0x4804FFFF,
1698                 .flags          = ADDR_TYPE_RT
1699         },
1700 };
1701
1702 /* l4_core -> dss_dsi1 */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704         .master         = &omap3xxx_l4_core_hwmod,
1705         .slave          = &omap3xxx_dss_dsi1_hwmod,
1706         .addr           = omap3xxx_dss_dsi1_addrs,
1707         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1708         .fw = {
1709                 .omap2 = {
1710                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1711                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1712                         .flags  = OMAP_FIREWALL_L4,
1713                 }
1714         },
1715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1716 };
1717
1718 /* dss_dsi1 slave ports */
1719 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1720         &omap3xxx_l4_core__dss_dsi1,
1721 };
1722
1723 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1724         .name           = "dss_dsi1",
1725         .class          = &omap3xxx_dsi_hwmod_class,
1726         .mpu_irqs       = omap3xxx_dsi1_irqs,
1727         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1728         .main_clk       = "dss1_alwon_fck",
1729         .prcm           = {
1730                 .omap2 = {
1731                         .prcm_reg_id = 1,
1732                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1733                         .module_offs = OMAP3430_DSS_MOD,
1734                 },
1735         },
1736         .slaves         = omap3xxx_dss_dsi1_slaves,
1737         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1738         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1739                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1740                                 CHIP_GE_OMAP3630ES1_1),
1741         .flags          = HWMOD_NO_IDLEST,
1742 };
1743
1744 /*
1745  * 'rfbi' class
1746  * remote frame buffer interface
1747  */
1748
1749 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1750         .rev_offs       = 0x0000,
1751         .sysc_offs      = 0x0010,
1752         .syss_offs      = 0x0014,
1753         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1754                            SYSC_HAS_AUTOIDLE),
1755         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1756         .sysc_fields    = &omap_hwmod_sysc_type1,
1757 };
1758
1759 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1760         .name = "rfbi",
1761         .sysc = &omap3xxx_rfbi_sysc,
1762 };
1763
1764 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1765         {
1766                 .pa_start       = 0x48050800,
1767                 .pa_end         = 0x48050BFF,
1768                 .flags          = ADDR_TYPE_RT
1769         },
1770 };
1771
1772 /* l4_core -> dss_rfbi */
1773 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1774         .master         = &omap3xxx_l4_core_hwmod,
1775         .slave          = &omap3xxx_dss_rfbi_hwmod,
1776         .clk            = "dss_ick",
1777         .addr           = omap3xxx_dss_rfbi_addrs,
1778         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1779         .fw = {
1780                 .omap2 = {
1781                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1782                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1783                         .flags  = OMAP_FIREWALL_L4,
1784                 }
1785         },
1786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1787 };
1788
1789 /* dss_rfbi slave ports */
1790 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1791         &omap3xxx_l4_core__dss_rfbi,
1792 };
1793
1794 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1795         .name           = "dss_rfbi",
1796         .class          = &omap3xxx_rfbi_hwmod_class,
1797         .main_clk       = "dss1_alwon_fck",
1798         .prcm           = {
1799                 .omap2 = {
1800                         .prcm_reg_id = 1,
1801                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1802                         .module_offs = OMAP3430_DSS_MOD,
1803                 },
1804         },
1805         .slaves         = omap3xxx_dss_rfbi_slaves,
1806         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1807         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1808                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1809                                 CHIP_GE_OMAP3630ES1_1),
1810         .flags          = HWMOD_NO_IDLEST,
1811 };
1812
1813 /*
1814  * 'venc' class
1815  * video encoder
1816  */
1817
1818 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1819         .name = "venc",
1820 };
1821
1822 /* dss_venc */
1823 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1824         {
1825                 .pa_start       = 0x48050C00,
1826                 .pa_end         = 0x48050FFF,
1827                 .flags          = ADDR_TYPE_RT
1828         },
1829 };
1830
1831 /* l4_core -> dss_venc */
1832 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1833         .master         = &omap3xxx_l4_core_hwmod,
1834         .slave          = &omap3xxx_dss_venc_hwmod,
1835         .clk            = "dss_tv_fck",
1836         .addr           = omap3xxx_dss_venc_addrs,
1837         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1838         .fw = {
1839                 .omap2 = {
1840                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1841                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1842                         .flags  = OMAP_FIREWALL_L4,
1843                 }
1844         },
1845         .flags          = OCPIF_SWSUP_IDLE,
1846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1847 };
1848
1849 /* dss_venc slave ports */
1850 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1851         &omap3xxx_l4_core__dss_venc,
1852 };
1853
1854 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1855         .name           = "dss_venc",
1856         .class          = &omap3xxx_venc_hwmod_class,
1857         .main_clk       = "dss1_alwon_fck",
1858         .prcm           = {
1859                 .omap2 = {
1860                         .prcm_reg_id = 1,
1861                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1862                         .module_offs = OMAP3430_DSS_MOD,
1863                 },
1864         },
1865         .slaves         = omap3xxx_dss_venc_slaves,
1866         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1867         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1868                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1869                                 CHIP_GE_OMAP3630ES1_1),
1870         .flags          = HWMOD_NO_IDLEST,
1871 };
1872
1873 /* I2C1 */
1874
1875 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1876         .fifo_depth     = 8, /* bytes */
1877 };
1878
1879 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1880         { .irq = INT_24XX_I2C1_IRQ, },
1881 };
1882
1883 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1884         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1885         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1886 };
1887
1888 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1889         &omap3_l4_core__i2c1,
1890 };
1891
1892 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1893         .name           = "i2c1",
1894         .mpu_irqs       = i2c1_mpu_irqs,
1895         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1896         .sdma_reqs      = i2c1_sdma_reqs,
1897         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1898         .main_clk       = "i2c1_fck",
1899         .prcm           = {
1900                 .omap2 = {
1901                         .module_offs = CORE_MOD,
1902                         .prcm_reg_id = 1,
1903                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1904                         .idlest_reg_id = 1,
1905                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1906                 },
1907         },
1908         .slaves         = omap3xxx_i2c1_slaves,
1909         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1910         .class          = &i2c_class,
1911         .dev_attr       = &i2c1_dev_attr,
1912         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1913 };
1914
1915 /* I2C2 */
1916
1917 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1918         .fifo_depth     = 8, /* bytes */
1919 };
1920
1921 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1922         { .irq = INT_24XX_I2C2_IRQ, },
1923 };
1924
1925 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1926         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1927         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1928 };
1929
1930 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1931         &omap3_l4_core__i2c2,
1932 };
1933
1934 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1935         .name           = "i2c2",
1936         .mpu_irqs       = i2c2_mpu_irqs,
1937         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1938         .sdma_reqs      = i2c2_sdma_reqs,
1939         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1940         .main_clk       = "i2c2_fck",
1941         .prcm           = {
1942                 .omap2 = {
1943                         .module_offs = CORE_MOD,
1944                         .prcm_reg_id = 1,
1945                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1946                         .idlest_reg_id = 1,
1947                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1948                 },
1949         },
1950         .slaves         = omap3xxx_i2c2_slaves,
1951         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1952         .class          = &i2c_class,
1953         .dev_attr       = &i2c2_dev_attr,
1954         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1955 };
1956
1957 /* I2C3 */
1958
1959 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1960         .fifo_depth     = 64, /* bytes */
1961 };
1962
1963 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1964         { .irq = INT_34XX_I2C3_IRQ, },
1965 };
1966
1967 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1968         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1969         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1970 };
1971
1972 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1973         &omap3_l4_core__i2c3,
1974 };
1975
1976 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1977         .name           = "i2c3",
1978         .mpu_irqs       = i2c3_mpu_irqs,
1979         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
1980         .sdma_reqs      = i2c3_sdma_reqs,
1981         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1982         .main_clk       = "i2c3_fck",
1983         .prcm           = {
1984                 .omap2 = {
1985                         .module_offs = CORE_MOD,
1986                         .prcm_reg_id = 1,
1987                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1988                         .idlest_reg_id = 1,
1989                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1990                 },
1991         },
1992         .slaves         = omap3xxx_i2c3_slaves,
1993         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1994         .class          = &i2c_class,
1995         .dev_attr       = &i2c3_dev_attr,
1996         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1997 };
1998
1999 /* l4_wkup -> gpio1 */
2000 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2001         {
2002                 .pa_start       = 0x48310000,
2003                 .pa_end         = 0x483101ff,
2004                 .flags          = ADDR_TYPE_RT
2005         },
2006 };
2007
2008 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2009         .master         = &omap3xxx_l4_wkup_hwmod,
2010         .slave          = &omap3xxx_gpio1_hwmod,
2011         .addr           = omap3xxx_gpio1_addrs,
2012         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2014 };
2015
2016 /* l4_per -> gpio2 */
2017 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2018         {
2019                 .pa_start       = 0x49050000,
2020                 .pa_end         = 0x490501ff,
2021                 .flags          = ADDR_TYPE_RT
2022         },
2023 };
2024
2025 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2026         .master         = &omap3xxx_l4_per_hwmod,
2027         .slave          = &omap3xxx_gpio2_hwmod,
2028         .addr           = omap3xxx_gpio2_addrs,
2029         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2031 };
2032
2033 /* l4_per -> gpio3 */
2034 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2035         {
2036                 .pa_start       = 0x49052000,
2037                 .pa_end         = 0x490521ff,
2038                 .flags          = ADDR_TYPE_RT
2039         },
2040 };
2041
2042 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2043         .master         = &omap3xxx_l4_per_hwmod,
2044         .slave          = &omap3xxx_gpio3_hwmod,
2045         .addr           = omap3xxx_gpio3_addrs,
2046         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2048 };
2049
2050 /* l4_per -> gpio4 */
2051 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2052         {
2053                 .pa_start       = 0x49054000,
2054                 .pa_end         = 0x490541ff,
2055                 .flags          = ADDR_TYPE_RT
2056         },
2057 };
2058
2059 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2060         .master         = &omap3xxx_l4_per_hwmod,
2061         .slave          = &omap3xxx_gpio4_hwmod,
2062         .addr           = omap3xxx_gpio4_addrs,
2063         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2065 };
2066
2067 /* l4_per -> gpio5 */
2068 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2069         {
2070                 .pa_start       = 0x49056000,
2071                 .pa_end         = 0x490561ff,
2072                 .flags          = ADDR_TYPE_RT
2073         },
2074 };
2075
2076 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2077         .master         = &omap3xxx_l4_per_hwmod,
2078         .slave          = &omap3xxx_gpio5_hwmod,
2079         .addr           = omap3xxx_gpio5_addrs,
2080         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2082 };
2083
2084 /* l4_per -> gpio6 */
2085 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2086         {
2087                 .pa_start       = 0x49058000,
2088                 .pa_end         = 0x490581ff,
2089                 .flags          = ADDR_TYPE_RT
2090         },
2091 };
2092
2093 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2094         .master         = &omap3xxx_l4_per_hwmod,
2095         .slave          = &omap3xxx_gpio6_hwmod,
2096         .addr           = omap3xxx_gpio6_addrs,
2097         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2099 };
2100
2101 /*
2102  * 'gpio' class
2103  * general purpose io module
2104  */
2105
2106 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2107         .rev_offs       = 0x0000,
2108         .sysc_offs      = 0x0010,
2109         .syss_offs      = 0x0014,
2110         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2111                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2112                            SYSS_HAS_RESET_STATUS),
2113         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2114         .sysc_fields    = &omap_hwmod_sysc_type1,
2115 };
2116
2117 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2118         .name = "gpio",
2119         .sysc = &omap3xxx_gpio_sysc,
2120         .rev = 1,
2121 };
2122
2123 /* gpio_dev_attr*/
2124 static struct omap_gpio_dev_attr gpio_dev_attr = {
2125         .bank_width = 32,
2126         .dbck_flag = true,
2127 };
2128
2129 /* gpio1 */
2130 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2131         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2132 };
2133
2134 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2135         { .role = "dbclk", .clk = "gpio1_dbck", },
2136 };
2137
2138 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2139         &omap3xxx_l4_wkup__gpio1,
2140 };
2141
2142 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2143         .name           = "gpio1",
2144         .mpu_irqs       = omap3xxx_gpio1_irqs,
2145         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2146         .main_clk       = "gpio1_ick",
2147         .opt_clks       = gpio1_opt_clks,
2148         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
2149         .prcm           = {
2150                 .omap2 = {
2151                         .prcm_reg_id = 1,
2152                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2153                         .module_offs = WKUP_MOD,
2154                         .idlest_reg_id = 1,
2155                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2156                 },
2157         },
2158         .slaves         = omap3xxx_gpio1_slaves,
2159         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2160         .class          = &omap3xxx_gpio_hwmod_class,
2161         .dev_attr       = &gpio_dev_attr,
2162         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2163 };
2164
2165 /* gpio2 */
2166 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2167         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2168 };
2169
2170 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2171         { .role = "dbclk", .clk = "gpio2_dbck", },
2172 };
2173
2174 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2175         &omap3xxx_l4_per__gpio2,
2176 };
2177
2178 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2179         .name           = "gpio2",
2180         .mpu_irqs       = omap3xxx_gpio2_irqs,
2181         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2182         .main_clk       = "gpio2_ick",
2183         .opt_clks       = gpio2_opt_clks,
2184         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2185         .prcm           = {
2186                 .omap2 = {
2187                         .prcm_reg_id = 1,
2188                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2189                         .module_offs = OMAP3430_PER_MOD,
2190                         .idlest_reg_id = 1,
2191                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2192                 },
2193         },
2194         .slaves         = omap3xxx_gpio2_slaves,
2195         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2196         .class          = &omap3xxx_gpio_hwmod_class,
2197         .dev_attr       = &gpio_dev_attr,
2198         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2199 };
2200
2201 /* gpio3 */
2202 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2203         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2204 };
2205
2206 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2207         { .role = "dbclk", .clk = "gpio3_dbck", },
2208 };
2209
2210 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2211         &omap3xxx_l4_per__gpio3,
2212 };
2213
2214 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2215         .name           = "gpio3",
2216         .mpu_irqs       = omap3xxx_gpio3_irqs,
2217         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2218         .main_clk       = "gpio3_ick",
2219         .opt_clks       = gpio3_opt_clks,
2220         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2221         .prcm           = {
2222                 .omap2 = {
2223                         .prcm_reg_id = 1,
2224                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2225                         .module_offs = OMAP3430_PER_MOD,
2226                         .idlest_reg_id = 1,
2227                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2228                 },
2229         },
2230         .slaves         = omap3xxx_gpio3_slaves,
2231         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2232         .class          = &omap3xxx_gpio_hwmod_class,
2233         .dev_attr       = &gpio_dev_attr,
2234         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2235 };
2236
2237 /* gpio4 */
2238 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2239         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2240 };
2241
2242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2243         { .role = "dbclk", .clk = "gpio4_dbck", },
2244 };
2245
2246 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2247         &omap3xxx_l4_per__gpio4,
2248 };
2249
2250 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2251         .name           = "gpio4",
2252         .mpu_irqs       = omap3xxx_gpio4_irqs,
2253         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2254         .main_clk       = "gpio4_ick",
2255         .opt_clks       = gpio4_opt_clks,
2256         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2257         .prcm           = {
2258                 .omap2 = {
2259                         .prcm_reg_id = 1,
2260                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2261                         .module_offs = OMAP3430_PER_MOD,
2262                         .idlest_reg_id = 1,
2263                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2264                 },
2265         },
2266         .slaves         = omap3xxx_gpio4_slaves,
2267         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2268         .class          = &omap3xxx_gpio_hwmod_class,
2269         .dev_attr       = &gpio_dev_attr,
2270         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2271 };
2272
2273 /* gpio5 */
2274 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2275         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2276 };
2277
2278 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2279         { .role = "dbclk", .clk = "gpio5_dbck", },
2280 };
2281
2282 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2283         &omap3xxx_l4_per__gpio5,
2284 };
2285
2286 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2287         .name           = "gpio5",
2288         .mpu_irqs       = omap3xxx_gpio5_irqs,
2289         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2290         .main_clk       = "gpio5_ick",
2291         .opt_clks       = gpio5_opt_clks,
2292         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2293         .prcm           = {
2294                 .omap2 = {
2295                         .prcm_reg_id = 1,
2296                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2297                         .module_offs = OMAP3430_PER_MOD,
2298                         .idlest_reg_id = 1,
2299                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2300                 },
2301         },
2302         .slaves         = omap3xxx_gpio5_slaves,
2303         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2304         .class          = &omap3xxx_gpio_hwmod_class,
2305         .dev_attr       = &gpio_dev_attr,
2306         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2307 };
2308
2309 /* gpio6 */
2310 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2311         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2312 };
2313
2314 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2315         { .role = "dbclk", .clk = "gpio6_dbck", },
2316 };
2317
2318 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2319         &omap3xxx_l4_per__gpio6,
2320 };
2321
2322 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2323         .name           = "gpio6",
2324         .mpu_irqs       = omap3xxx_gpio6_irqs,
2325         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2326         .main_clk       = "gpio6_ick",
2327         .opt_clks       = gpio6_opt_clks,
2328         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2329         .prcm           = {
2330                 .omap2 = {
2331                         .prcm_reg_id = 1,
2332                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2333                         .module_offs = OMAP3430_PER_MOD,
2334                         .idlest_reg_id = 1,
2335                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2336                 },
2337         },
2338         .slaves         = omap3xxx_gpio6_slaves,
2339         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2340         .class          = &omap3xxx_gpio_hwmod_class,
2341         .dev_attr       = &gpio_dev_attr,
2342         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2343 };
2344
2345 /* dma_system -> L3 */
2346 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2347         .master         = &omap3xxx_dma_system_hwmod,
2348         .slave          = &omap3xxx_l3_main_hwmod,
2349         .clk            = "core_l3_ick",
2350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352
2353 /* dma attributes */
2354 static struct omap_dma_dev_attr dma_dev_attr = {
2355         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2356                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2357         .lch_count = 32,
2358 };
2359
2360 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2361         .rev_offs       = 0x0000,
2362         .sysc_offs      = 0x002c,
2363         .syss_offs      = 0x0028,
2364         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2365                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2366                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2367                            SYSS_HAS_RESET_STATUS),
2368         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2369                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2370         .sysc_fields    = &omap_hwmod_sysc_type1,
2371 };
2372
2373 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2374         .name = "dma",
2375         .sysc = &omap3xxx_dma_sysc,
2376 };
2377
2378 /* dma_system */
2379 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2380         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2381         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2382         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2383         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2384 };
2385
2386 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2387         {
2388                 .pa_start       = 0x48056000,
2389                 .pa_end         = 0x4a0560ff,
2390                 .flags          = ADDR_TYPE_RT
2391         },
2392 };
2393
2394 /* dma_system master ports */
2395 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2396         &omap3xxx_dma_system__l3,
2397 };
2398
2399 /* l4_cfg -> dma_system */
2400 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2401         .master         = &omap3xxx_l4_core_hwmod,
2402         .slave          = &omap3xxx_dma_system_hwmod,
2403         .clk            = "core_l4_ick",
2404         .addr           = omap3xxx_dma_system_addrs,
2405         .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2407 };
2408
2409 /* dma_system slave ports */
2410 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2411         &omap3xxx_l4_core__dma_system,
2412 };
2413
2414 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2415         .name           = "dma",
2416         .class          = &omap3xxx_dma_hwmod_class,
2417         .mpu_irqs       = omap3xxx_dma_system_irqs,
2418         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2419         .main_clk       = "core_l3_ick",
2420         .prcm = {
2421                 .omap2 = {
2422                         .module_offs            = CORE_MOD,
2423                         .prcm_reg_id            = 1,
2424                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2425                         .idlest_reg_id          = 1,
2426                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2427                 },
2428         },
2429         .slaves         = omap3xxx_dma_system_slaves,
2430         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2431         .masters        = omap3xxx_dma_system_masters,
2432         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2433         .dev_attr       = &dma_dev_attr,
2434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2435         .flags          = HWMOD_NO_IDLEST,
2436 };
2437
2438 /*
2439  * 'mcbsp' class
2440  * multi channel buffered serial port controller
2441  */
2442
2443 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2444         .sysc_offs      = 0x008c,
2445         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2446                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2448         .sysc_fields    = &omap_hwmod_sysc_type1,
2449         .clockact       = 0x2,
2450 };
2451
2452 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2453         .name = "mcbsp",
2454         .sysc = &omap3xxx_mcbsp_sysc,
2455         .rev  = MCBSP_CONFIG_TYPE3,
2456 };
2457
2458 /* mcbsp1 */
2459 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2460         { .name = "irq", .irq = 16 },
2461         { .name = "tx", .irq = 59 },
2462         { .name = "rx", .irq = 60 },
2463 };
2464
2465 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2466         { .name = "rx", .dma_req = 32 },
2467         { .name = "tx", .dma_req = 31 },
2468 };
2469
2470 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2471         {
2472                 .name           = "mpu",
2473                 .pa_start       = 0x48074000,
2474                 .pa_end         = 0x480740ff,
2475                 .flags          = ADDR_TYPE_RT
2476         },
2477 };
2478
2479 /* l4_core -> mcbsp1 */
2480 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2481         .master         = &omap3xxx_l4_core_hwmod,
2482         .slave          = &omap3xxx_mcbsp1_hwmod,
2483         .clk            = "mcbsp1_ick",
2484         .addr           = omap3xxx_mcbsp1_addrs,
2485         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* mcbsp1 slave ports */
2490 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2491         &omap3xxx_l4_core__mcbsp1,
2492 };
2493
2494 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2495         .name           = "mcbsp1",
2496         .class          = &omap3xxx_mcbsp_hwmod_class,
2497         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2498         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2499         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
2500         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2501         .main_clk       = "mcbsp1_fck",
2502         .prcm           = {
2503                 .omap2 = {
2504                         .prcm_reg_id = 1,
2505                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2506                         .module_offs = CORE_MOD,
2507                         .idlest_reg_id = 1,
2508                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2509                 },
2510         },
2511         .slaves         = omap3xxx_mcbsp1_slaves,
2512         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2513         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2514 };
2515
2516 /* mcbsp2 */
2517 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2518         { .name = "irq", .irq = 17 },
2519         { .name = "tx", .irq = 62 },
2520         { .name = "rx", .irq = 63 },
2521 };
2522
2523 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2524         { .name = "rx", .dma_req = 34 },
2525         { .name = "tx", .dma_req = 33 },
2526 };
2527
2528 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2529         {
2530                 .name           = "mpu",
2531                 .pa_start       = 0x49022000,
2532                 .pa_end         = 0x490220ff,
2533                 .flags          = ADDR_TYPE_RT
2534         },
2535 };
2536
2537 /* l4_per -> mcbsp2 */
2538 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2539         .master         = &omap3xxx_l4_per_hwmod,
2540         .slave          = &omap3xxx_mcbsp2_hwmod,
2541         .clk            = "mcbsp2_ick",
2542         .addr           = omap3xxx_mcbsp2_addrs,
2543         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2545 };
2546
2547 /* mcbsp2 slave ports */
2548 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2549         &omap3xxx_l4_per__mcbsp2,
2550 };
2551
2552 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2553         .sidetone       = "mcbsp2_sidetone",
2554 };
2555
2556 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2557         .name           = "mcbsp2",
2558         .class          = &omap3xxx_mcbsp_hwmod_class,
2559         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2560         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2561         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
2562         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2563         .main_clk       = "mcbsp2_fck",
2564         .prcm           = {
2565                 .omap2 = {
2566                         .prcm_reg_id = 1,
2567                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2568                         .module_offs = OMAP3430_PER_MOD,
2569                         .idlest_reg_id = 1,
2570                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2571                 },
2572         },
2573         .slaves         = omap3xxx_mcbsp2_slaves,
2574         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2575         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2577 };
2578
2579 /* mcbsp3 */
2580 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2581         { .name = "irq", .irq = 22 },
2582         { .name = "tx", .irq = 89 },
2583         { .name = "rx", .irq = 90 },
2584 };
2585
2586 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2587         { .name = "rx", .dma_req = 18 },
2588         { .name = "tx", .dma_req = 17 },
2589 };
2590
2591 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2592         {
2593                 .name           = "mpu",
2594                 .pa_start       = 0x49024000,
2595                 .pa_end         = 0x490240ff,
2596                 .flags          = ADDR_TYPE_RT
2597         },
2598 };
2599
2600 /* l4_per -> mcbsp3 */
2601 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2602         .master         = &omap3xxx_l4_per_hwmod,
2603         .slave          = &omap3xxx_mcbsp3_hwmod,
2604         .clk            = "mcbsp3_ick",
2605         .addr           = omap3xxx_mcbsp3_addrs,
2606         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2608 };
2609
2610 /* mcbsp3 slave ports */
2611 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2612         &omap3xxx_l4_per__mcbsp3,
2613 };
2614
2615 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2616         .sidetone       = "mcbsp3_sidetone",
2617 };
2618
2619 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2620         .name           = "mcbsp3",
2621         .class          = &omap3xxx_mcbsp_hwmod_class,
2622         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2623         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2624         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
2625         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2626         .main_clk       = "mcbsp3_fck",
2627         .prcm           = {
2628                 .omap2 = {
2629                         .prcm_reg_id = 1,
2630                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2631                         .module_offs = OMAP3430_PER_MOD,
2632                         .idlest_reg_id = 1,
2633                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2634                 },
2635         },
2636         .slaves         = omap3xxx_mcbsp3_slaves,
2637         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2638         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2639         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2640 };
2641
2642 /* mcbsp4 */
2643 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2644         { .name = "irq", .irq = 23 },
2645         { .name = "tx", .irq = 54 },
2646         { .name = "rx", .irq = 55 },
2647 };
2648
2649 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2650         { .name = "rx", .dma_req = 20 },
2651         { .name = "tx", .dma_req = 19 },
2652 };
2653
2654 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2655         {
2656                 .name           = "mpu",
2657                 .pa_start       = 0x49026000,
2658                 .pa_end         = 0x490260ff,
2659                 .flags          = ADDR_TYPE_RT
2660         },
2661 };
2662
2663 /* l4_per -> mcbsp4 */
2664 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2665         .master         = &omap3xxx_l4_per_hwmod,
2666         .slave          = &omap3xxx_mcbsp4_hwmod,
2667         .clk            = "mcbsp4_ick",
2668         .addr           = omap3xxx_mcbsp4_addrs,
2669         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2671 };
2672
2673 /* mcbsp4 slave ports */
2674 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2675         &omap3xxx_l4_per__mcbsp4,
2676 };
2677
2678 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2679         .name           = "mcbsp4",
2680         .class          = &omap3xxx_mcbsp_hwmod_class,
2681         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2682         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2683         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2684         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2685         .main_clk       = "mcbsp4_fck",
2686         .prcm           = {
2687                 .omap2 = {
2688                         .prcm_reg_id = 1,
2689                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2690                         .module_offs = OMAP3430_PER_MOD,
2691                         .idlest_reg_id = 1,
2692                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2693                 },
2694         },
2695         .slaves         = omap3xxx_mcbsp4_slaves,
2696         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2697         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2698 };
2699
2700 /* mcbsp5 */
2701 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2702         { .name = "irq", .irq = 27 },
2703         { .name = "tx", .irq = 81 },
2704         { .name = "rx", .irq = 82 },
2705 };
2706
2707 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2708         { .name = "rx", .dma_req = 22 },
2709         { .name = "tx", .dma_req = 21 },
2710 };
2711
2712 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2713         {
2714                 .name           = "mpu",
2715                 .pa_start       = 0x48096000,
2716                 .pa_end         = 0x480960ff,
2717                 .flags          = ADDR_TYPE_RT
2718         },
2719 };
2720
2721 /* l4_core -> mcbsp5 */
2722 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2723         .master         = &omap3xxx_l4_core_hwmod,
2724         .slave          = &omap3xxx_mcbsp5_hwmod,
2725         .clk            = "mcbsp5_ick",
2726         .addr           = omap3xxx_mcbsp5_addrs,
2727         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 /* mcbsp5 slave ports */
2732 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2733         &omap3xxx_l4_core__mcbsp5,
2734 };
2735
2736 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2737         .name           = "mcbsp5",
2738         .class          = &omap3xxx_mcbsp_hwmod_class,
2739         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2740         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2741         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2742         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2743         .main_clk       = "mcbsp5_fck",
2744         .prcm           = {
2745                 .omap2 = {
2746                         .prcm_reg_id = 1,
2747                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2748                         .module_offs = CORE_MOD,
2749                         .idlest_reg_id = 1,
2750                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2751                 },
2752         },
2753         .slaves         = omap3xxx_mcbsp5_slaves,
2754         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2755         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2756 };
2757 /* 'mcbsp sidetone' class */
2758
2759 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2760         .sysc_offs      = 0x0010,
2761         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2762         .sysc_fields    = &omap_hwmod_sysc_type1,
2763 };
2764
2765 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2766         .name = "mcbsp_sidetone",
2767         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2768 };
2769
2770 /* mcbsp2_sidetone */
2771 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2772         { .name = "irq", .irq = 4 },
2773 };
2774
2775 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2776         {
2777                 .name           = "sidetone",
2778                 .pa_start       = 0x49028000,
2779                 .pa_end         = 0x490280ff,
2780                 .flags          = ADDR_TYPE_RT
2781         },
2782 };
2783
2784 /* l4_per -> mcbsp2_sidetone */
2785 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2786         .master         = &omap3xxx_l4_per_hwmod,
2787         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2788         .clk            = "mcbsp2_ick",
2789         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2790         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2791         .user           = OCP_USER_MPU,
2792 };
2793
2794 /* mcbsp2_sidetone slave ports */
2795 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2796         &omap3xxx_l4_per__mcbsp2_sidetone,
2797 };
2798
2799 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2800         .name           = "mcbsp2_sidetone",
2801         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2802         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2803         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2804         .main_clk       = "mcbsp2_fck",
2805         .prcm           = {
2806                 .omap2 = {
2807                         .prcm_reg_id = 1,
2808                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2809                         .module_offs = OMAP3430_PER_MOD,
2810                         .idlest_reg_id = 1,
2811                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2812                 },
2813         },
2814         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2815         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2816         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2817 };
2818
2819 /* mcbsp3_sidetone */
2820 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2821         { .name = "irq", .irq = 5 },
2822 };
2823
2824 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2825         {
2826                 .name           = "sidetone",
2827                 .pa_start       = 0x4902A000,
2828                 .pa_end         = 0x4902A0ff,
2829                 .flags          = ADDR_TYPE_RT
2830         },
2831 };
2832
2833 /* l4_per -> mcbsp3_sidetone */
2834 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2835         .master         = &omap3xxx_l4_per_hwmod,
2836         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2837         .clk            = "mcbsp3_ick",
2838         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2839         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2840         .user           = OCP_USER_MPU,
2841 };
2842
2843 /* mcbsp3_sidetone slave ports */
2844 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2845         &omap3xxx_l4_per__mcbsp3_sidetone,
2846 };
2847
2848 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2849         .name           = "mcbsp3_sidetone",
2850         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2851         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2852         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2853         .main_clk       = "mcbsp3_fck",
2854         .prcm           = {
2855                 .omap2 = {
2856                         .prcm_reg_id = 1,
2857                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2858                         .module_offs = OMAP3430_PER_MOD,
2859                         .idlest_reg_id = 1,
2860                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2861                 },
2862         },
2863         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2864         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2865         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2866 };
2867
2868
2869 /* SR common */
2870 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2871         .clkact_shift   = 20,
2872 };
2873
2874 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2875         .sysc_offs      = 0x24,
2876         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2877         .clockact       = CLOCKACT_TEST_ICLK,
2878         .sysc_fields    = &omap34xx_sr_sysc_fields,
2879 };
2880
2881 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2882         .name = "smartreflex",
2883         .sysc = &omap34xx_sr_sysc,
2884         .rev  = 1,
2885 };
2886
2887 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2888         .sidle_shift    = 24,
2889         .enwkup_shift   = 26
2890 };
2891
2892 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2893         .sysc_offs      = 0x38,
2894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2895         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2896                         SYSC_NO_CACHE),
2897         .sysc_fields    = &omap36xx_sr_sysc_fields,
2898 };
2899
2900 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2901         .name = "smartreflex",
2902         .sysc = &omap36xx_sr_sysc,
2903         .rev  = 2,
2904 };
2905
2906 /* SR1 */
2907 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2908         &omap3_l4_core__sr1,
2909 };
2910
2911 static struct omap_hwmod omap34xx_sr1_hwmod = {
2912         .name           = "sr1_hwmod",
2913         .class          = &omap34xx_smartreflex_hwmod_class,
2914         .main_clk       = "sr1_fck",
2915         .vdd_name       = "mpu",
2916         .prcm           = {
2917                 .omap2 = {
2918                         .prcm_reg_id = 1,
2919                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2920                         .module_offs = WKUP_MOD,
2921                         .idlest_reg_id = 1,
2922                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2923                 },
2924         },
2925         .slaves         = omap3_sr1_slaves,
2926         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2927         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2928                                         CHIP_IS_OMAP3430ES3_0 |
2929                                         CHIP_IS_OMAP3430ES3_1),
2930         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2931 };
2932
2933 static struct omap_hwmod omap36xx_sr1_hwmod = {
2934         .name           = "sr1_hwmod",
2935         .class          = &omap36xx_smartreflex_hwmod_class,
2936         .main_clk       = "sr1_fck",
2937         .vdd_name       = "mpu",
2938         .prcm           = {
2939                 .omap2 = {
2940                         .prcm_reg_id = 1,
2941                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2942                         .module_offs = WKUP_MOD,
2943                         .idlest_reg_id = 1,
2944                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2945                 },
2946         },
2947         .slaves         = omap3_sr1_slaves,
2948         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2949         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2950 };
2951
2952 /* SR2 */
2953 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2954         &omap3_l4_core__sr2,
2955 };
2956
2957 static struct omap_hwmod omap34xx_sr2_hwmod = {
2958         .name           = "sr2_hwmod",
2959         .class          = &omap34xx_smartreflex_hwmod_class,
2960         .main_clk       = "sr2_fck",
2961         .vdd_name       = "core",
2962         .prcm           = {
2963                 .omap2 = {
2964                         .prcm_reg_id = 1,
2965                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2966                         .module_offs = WKUP_MOD,
2967                         .idlest_reg_id = 1,
2968                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2969                 },
2970         },
2971         .slaves         = omap3_sr2_slaves,
2972         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2973         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2974                                         CHIP_IS_OMAP3430ES3_0 |
2975                                         CHIP_IS_OMAP3430ES3_1),
2976         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2977 };
2978
2979 static struct omap_hwmod omap36xx_sr2_hwmod = {
2980         .name           = "sr2_hwmod",
2981         .class          = &omap36xx_smartreflex_hwmod_class,
2982         .main_clk       = "sr2_fck",
2983         .vdd_name       = "core",
2984         .prcm           = {
2985                 .omap2 = {
2986                         .prcm_reg_id = 1,
2987                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2988                         .module_offs = WKUP_MOD,
2989                         .idlest_reg_id = 1,
2990                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2991                 },
2992         },
2993         .slaves         = omap3_sr2_slaves,
2994         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2995         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2996 };
2997
2998 /*
2999  * 'mailbox' class
3000  * mailbox module allowing communication between the on-chip processors
3001  * using a queued mailbox-interrupt mechanism.
3002  */
3003
3004 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3005         .rev_offs       = 0x000,
3006         .sysc_offs      = 0x010,
3007         .syss_offs      = 0x014,
3008         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3009                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3010         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3011         .sysc_fields    = &omap_hwmod_sysc_type1,
3012 };
3013
3014 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3015         .name = "mailbox",
3016         .sysc = &omap3xxx_mailbox_sysc,
3017 };
3018
3019 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3020 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3021         { .irq = 26 },
3022 };
3023
3024 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3025         {
3026                 .pa_start       = 0x48094000,
3027                 .pa_end         = 0x480941ff,
3028                 .flags          = ADDR_TYPE_RT,
3029         },
3030 };
3031
3032 /* l4_core -> mailbox */
3033 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3034         .master         = &omap3xxx_l4_core_hwmod,
3035         .slave          = &omap3xxx_mailbox_hwmod,
3036         .addr           = omap3xxx_mailbox_addrs,
3037         .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3039 };
3040
3041 /* mailbox slave ports */
3042 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3043         &omap3xxx_l4_core__mailbox,
3044 };
3045
3046 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3047         .name           = "mailbox",
3048         .class          = &omap3xxx_mailbox_hwmod_class,
3049         .mpu_irqs       = omap3xxx_mailbox_irqs,
3050         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3051         .main_clk       = "mailboxes_ick",
3052         .prcm           = {
3053                 .omap2 = {
3054                         .prcm_reg_id = 1,
3055                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3056                         .module_offs = CORE_MOD,
3057                         .idlest_reg_id = 1,
3058                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3059                 },
3060         },
3061         .slaves         = omap3xxx_mailbox_slaves,
3062         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3063         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3064 };
3065
3066 /* l4 core -> mcspi1 interface */
3067 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3068         {
3069                 .pa_start       = 0x48098000,
3070                 .pa_end         = 0x480980ff,
3071                 .flags          = ADDR_TYPE_RT,
3072         },
3073 };
3074
3075 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3076         .master         = &omap3xxx_l4_core_hwmod,
3077         .slave          = &omap34xx_mcspi1,
3078         .clk            = "mcspi1_ick",
3079         .addr           = omap34xx_mcspi1_addr_space,
3080         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3082 };
3083
3084 /* l4 core -> mcspi2 interface */
3085 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3086         {
3087                 .pa_start       = 0x4809a000,
3088                 .pa_end         = 0x4809a0ff,
3089                 .flags          = ADDR_TYPE_RT,
3090         },
3091 };
3092
3093 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3094         .master         = &omap3xxx_l4_core_hwmod,
3095         .slave          = &omap34xx_mcspi2,
3096         .clk            = "mcspi2_ick",
3097         .addr           = omap34xx_mcspi2_addr_space,
3098         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3100 };
3101
3102 /* l4 core -> mcspi3 interface */
3103 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3104         {
3105                 .pa_start       = 0x480b8000,
3106                 .pa_end         = 0x480b80ff,
3107                 .flags          = ADDR_TYPE_RT,
3108         },
3109 };
3110
3111 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3112         .master         = &omap3xxx_l4_core_hwmod,
3113         .slave          = &omap34xx_mcspi3,
3114         .clk            = "mcspi3_ick",
3115         .addr           = omap34xx_mcspi3_addr_space,
3116         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3118 };
3119
3120 /* l4 core -> mcspi4 interface */
3121 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3122         {
3123                 .pa_start       = 0x480ba000,
3124                 .pa_end         = 0x480ba0ff,
3125                 .flags          = ADDR_TYPE_RT,
3126         },
3127 };
3128
3129 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3130         .master         = &omap3xxx_l4_core_hwmod,
3131         .slave          = &omap34xx_mcspi4,
3132         .clk            = "mcspi4_ick",
3133         .addr           = omap34xx_mcspi4_addr_space,
3134         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /*
3139  * 'mcspi' class
3140  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3141  * bus
3142  */
3143
3144 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3145         .rev_offs       = 0x0000,
3146         .sysc_offs      = 0x0010,
3147         .syss_offs      = 0x0014,
3148         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3149                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3150                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3152         .sysc_fields    = &omap_hwmod_sysc_type1,
3153 };
3154
3155 static struct omap_hwmod_class omap34xx_mcspi_class = {
3156         .name = "mcspi",
3157         .sysc = &omap34xx_mcspi_sysc,
3158         .rev = OMAP3_MCSPI_REV,
3159 };
3160
3161 /* mcspi1 */
3162 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3163         { .name = "irq", .irq = 65 },
3164 };
3165
3166 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3167         { .name = "tx0", .dma_req = 35 },
3168         { .name = "rx0", .dma_req = 36 },
3169         { .name = "tx1", .dma_req = 37 },
3170         { .name = "rx1", .dma_req = 38 },
3171         { .name = "tx2", .dma_req = 39 },
3172         { .name = "rx2", .dma_req = 40 },
3173         { .name = "tx3", .dma_req = 41 },
3174         { .name = "rx3", .dma_req = 42 },
3175 };
3176
3177 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3178         &omap34xx_l4_core__mcspi1,
3179 };
3180
3181 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3182         .num_chipselect = 4,
3183 };
3184
3185 static struct omap_hwmod omap34xx_mcspi1 = {
3186         .name           = "mcspi1",
3187         .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
3188         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3189         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
3190         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3191         .main_clk       = "mcspi1_fck",
3192         .prcm           = {
3193                 .omap2 = {
3194                         .module_offs = CORE_MOD,
3195                         .prcm_reg_id = 1,
3196                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3197                         .idlest_reg_id = 1,
3198                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3199                 },
3200         },
3201         .slaves         = omap34xx_mcspi1_slaves,
3202         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3203         .class          = &omap34xx_mcspi_class,
3204         .dev_attr       = &omap_mcspi1_dev_attr,
3205         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3206 };
3207
3208 /* mcspi2 */
3209 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3210         { .name = "irq", .irq = 66 },
3211 };
3212
3213 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3214         { .name = "tx0", .dma_req = 43 },
3215         { .name = "rx0", .dma_req = 44 },
3216         { .name = "tx1", .dma_req = 45 },
3217         { .name = "rx1", .dma_req = 46 },
3218 };
3219
3220 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3221         &omap34xx_l4_core__mcspi2,
3222 };
3223
3224 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3225         .num_chipselect = 2,
3226 };
3227
3228 static struct omap_hwmod omap34xx_mcspi2 = {
3229         .name           = "mcspi2",
3230         .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
3231         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3232         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
3233         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3234         .main_clk       = "mcspi2_fck",
3235         .prcm           = {
3236                 .omap2 = {
3237                         .module_offs = CORE_MOD,
3238                         .prcm_reg_id = 1,
3239                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3240                         .idlest_reg_id = 1,
3241                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3242                 },
3243         },
3244         .slaves         = omap34xx_mcspi2_slaves,
3245         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3246         .class          = &omap34xx_mcspi_class,
3247         .dev_attr       = &omap_mcspi2_dev_attr,
3248         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3249 };
3250
3251 /* mcspi3 */
3252 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3253         { .name = "irq", .irq = 91 }, /* 91 */
3254 };
3255
3256 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3257         { .name = "tx0", .dma_req = 15 },
3258         { .name = "rx0", .dma_req = 16 },
3259         { .name = "tx1", .dma_req = 23 },
3260         { .name = "rx1", .dma_req = 24 },
3261 };
3262
3263 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3264         &omap34xx_l4_core__mcspi3,
3265 };
3266
3267 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3268         .num_chipselect = 2,
3269 };
3270
3271 static struct omap_hwmod omap34xx_mcspi3 = {
3272         .name           = "mcspi3",
3273         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
3274         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3275         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
3276         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3277         .main_clk       = "mcspi3_fck",
3278         .prcm           = {
3279                 .omap2 = {
3280                         .module_offs = CORE_MOD,
3281                         .prcm_reg_id = 1,
3282                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3283                         .idlest_reg_id = 1,
3284                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3285                 },
3286         },
3287         .slaves         = omap34xx_mcspi3_slaves,
3288         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3289         .class          = &omap34xx_mcspi_class,
3290         .dev_attr       = &omap_mcspi3_dev_attr,
3291         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3292 };
3293
3294 /* SPI4 */
3295 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3296         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3297 };
3298
3299 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3300         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3301         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3302 };
3303
3304 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3305         &omap34xx_l4_core__mcspi4,
3306 };
3307
3308 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3309         .num_chipselect = 1,
3310 };
3311
3312 static struct omap_hwmod omap34xx_mcspi4 = {
3313         .name           = "mcspi4",
3314         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3315         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3316         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3317         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3318         .main_clk       = "mcspi4_fck",
3319         .prcm           = {
3320                 .omap2 = {
3321                         .module_offs = CORE_MOD,
3322                         .prcm_reg_id = 1,
3323                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3324                         .idlest_reg_id = 1,
3325                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3326                 },
3327         },
3328         .slaves         = omap34xx_mcspi4_slaves,
3329         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3330         .class          = &omap34xx_mcspi_class,
3331         .dev_attr       = &omap_mcspi4_dev_attr,
3332         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3333 };
3334
3335 /*
3336  * usbhsotg
3337  */
3338 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3339         .rev_offs       = 0x0400,
3340         .sysc_offs      = 0x0404,
3341         .syss_offs      = 0x0408,
3342         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3343                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3344                           SYSC_HAS_AUTOIDLE),
3345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3346                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3347         .sysc_fields    = &omap_hwmod_sysc_type1,
3348 };
3349
3350 static struct omap_hwmod_class usbotg_class = {
3351         .name = "usbotg",
3352         .sysc = &omap3xxx_usbhsotg_sysc,
3353 };
3354 /* usb_otg_hs */
3355 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3356
3357         { .name = "mc", .irq = 92 },
3358         { .name = "dma", .irq = 93 },
3359 };
3360
3361 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3362         .name           = "usb_otg_hs",
3363         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3364         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3365         .main_clk       = "hsotgusb_ick",
3366         .prcm           = {
3367                 .omap2 = {
3368                         .prcm_reg_id = 1,
3369                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3370                         .module_offs = CORE_MOD,
3371                         .idlest_reg_id = 1,
3372                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3373                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3374                 },
3375         },
3376         .masters        = omap3xxx_usbhsotg_masters,
3377         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3378         .slaves         = omap3xxx_usbhsotg_slaves,
3379         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3380         .class          = &usbotg_class,
3381
3382         /*
3383          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3384          * broken when autoidle is enabled
3385          * workaround is to disable the autoidle bit at module level.
3386          */
3387         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3388                                 | HWMOD_SWSUP_MSTANDBY,
3389         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3390 };
3391
3392 /* usb_otg_hs */
3393 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3394
3395         { .name = "mc", .irq = 71 },
3396 };
3397
3398 static struct omap_hwmod_class am35xx_usbotg_class = {
3399         .name = "am35xx_usbotg",
3400         .sysc = NULL,
3401 };
3402
3403 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3404         .name           = "am35x_otg_hs",
3405         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3406         .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3407         .main_clk       = NULL,
3408         .prcm = {
3409                 .omap2 = {
3410                 },
3411         },
3412         .masters        = am35xx_usbhsotg_masters,
3413         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3414         .slaves         = am35xx_usbhsotg_slaves,
3415         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3416         .class          = &am35xx_usbotg_class,
3417         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3418 };
3419
3420 /* MMC/SD/SDIO common */
3421
3422 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3423         .rev_offs       = 0x1fc,
3424         .sysc_offs      = 0x10,
3425         .syss_offs      = 0x14,
3426         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3427                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3428                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3429         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3430         .sysc_fields    = &omap_hwmod_sysc_type1,
3431 };
3432
3433 static struct omap_hwmod_class omap34xx_mmc_class = {
3434         .name = "mmc",
3435         .sysc = &omap34xx_mmc_sysc,
3436 };
3437
3438 /* MMC/SD/SDIO1 */
3439
3440 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3441         { .irq = 83, },
3442 };
3443
3444 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3445         { .name = "tx", .dma_req = 61, },
3446         { .name = "rx", .dma_req = 62, },
3447 };
3448
3449 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3450         { .role = "dbck", .clk = "omap_32k_fck", },
3451 };
3452
3453 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3454         &omap3xxx_l4_core__mmc1,
3455 };
3456
3457 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3458         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3459 };
3460
3461 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3462         .name           = "mmc1",
3463         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3464         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3465         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3466         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3467         .opt_clks       = omap34xx_mmc1_opt_clks,
3468         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3469         .main_clk       = "mmchs1_fck",
3470         .prcm           = {
3471                 .omap2 = {
3472                         .module_offs = CORE_MOD,
3473                         .prcm_reg_id = 1,
3474                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3475                         .idlest_reg_id = 1,
3476                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3477                 },
3478         },
3479         .dev_attr       = &mmc1_dev_attr,
3480         .slaves         = omap3xxx_mmc1_slaves,
3481         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3482         .class          = &omap34xx_mmc_class,
3483         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3484 };
3485
3486 /* MMC/SD/SDIO2 */
3487
3488 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3489         { .irq = INT_24XX_MMC2_IRQ, },
3490 };
3491
3492 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3493         { .name = "tx", .dma_req = 47, },
3494         { .name = "rx", .dma_req = 48, },
3495 };
3496
3497 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3498         { .role = "dbck", .clk = "omap_32k_fck", },
3499 };
3500
3501 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3502         &omap3xxx_l4_core__mmc2,
3503 };
3504
3505 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3506         .name           = "mmc2",
3507         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3508         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3509         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3510         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3511         .opt_clks       = omap34xx_mmc2_opt_clks,
3512         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3513         .main_clk       = "mmchs2_fck",
3514         .prcm           = {
3515                 .omap2 = {
3516                         .module_offs = CORE_MOD,
3517                         .prcm_reg_id = 1,
3518                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3519                         .idlest_reg_id = 1,
3520                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3521                 },
3522         },
3523         .slaves         = omap3xxx_mmc2_slaves,
3524         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3525         .class          = &omap34xx_mmc_class,
3526         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3527 };
3528
3529 /* MMC/SD/SDIO3 */
3530
3531 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3532         { .irq = 94, },
3533 };
3534
3535 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3536         { .name = "tx", .dma_req = 77, },
3537         { .name = "rx", .dma_req = 78, },
3538 };
3539
3540 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3541         { .role = "dbck", .clk = "omap_32k_fck", },
3542 };
3543
3544 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3545         &omap3xxx_l4_core__mmc3,
3546 };
3547
3548 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3549         .name           = "mmc3",
3550         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3551         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3552         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3553         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3554         .opt_clks       = omap34xx_mmc3_opt_clks,
3555         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3556         .main_clk       = "mmchs3_fck",
3557         .prcm           = {
3558                 .omap2 = {
3559                         .prcm_reg_id = 1,
3560                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3561                         .idlest_reg_id = 1,
3562                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3563                 },
3564         },
3565         .slaves         = omap3xxx_mmc3_slaves,
3566         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3567         .class          = &omap34xx_mmc_class,
3568         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3569 };
3570
3571 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3572         &omap3xxx_l3_main_hwmod,
3573         &omap3xxx_l4_core_hwmod,
3574         &omap3xxx_l4_per_hwmod,
3575         &omap3xxx_l4_wkup_hwmod,
3576         &omap3xxx_mmc1_hwmod,
3577         &omap3xxx_mmc2_hwmod,
3578         &omap3xxx_mmc3_hwmod,
3579         &omap3xxx_mpu_hwmod,
3580         &omap3xxx_iva_hwmod,
3581
3582         &omap3xxx_timer1_hwmod,
3583         &omap3xxx_timer2_hwmod,
3584         &omap3xxx_timer3_hwmod,
3585         &omap3xxx_timer4_hwmod,
3586         &omap3xxx_timer5_hwmod,
3587         &omap3xxx_timer6_hwmod,
3588         &omap3xxx_timer7_hwmod,
3589         &omap3xxx_timer8_hwmod,
3590         &omap3xxx_timer9_hwmod,
3591         &omap3xxx_timer10_hwmod,
3592         &omap3xxx_timer11_hwmod,
3593         &omap3xxx_timer12_hwmod,
3594
3595         &omap3xxx_wd_timer2_hwmod,
3596         &omap3xxx_uart1_hwmod,
3597         &omap3xxx_uart2_hwmod,
3598         &omap3xxx_uart3_hwmod,
3599         &omap3xxx_uart4_hwmod,
3600         /* dss class */
3601         &omap3430es1_dss_core_hwmod,
3602         &omap3xxx_dss_core_hwmod,
3603         &omap3xxx_dss_dispc_hwmod,
3604         &omap3xxx_dss_dsi1_hwmod,
3605         &omap3xxx_dss_rfbi_hwmod,
3606         &omap3xxx_dss_venc_hwmod,
3607
3608         /* i2c class */
3609         &omap3xxx_i2c1_hwmod,
3610         &omap3xxx_i2c2_hwmod,
3611         &omap3xxx_i2c3_hwmod,
3612         &omap34xx_sr1_hwmod,
3613         &omap34xx_sr2_hwmod,
3614         &omap36xx_sr1_hwmod,
3615         &omap36xx_sr2_hwmod,
3616
3617
3618         /* gpio class */
3619         &omap3xxx_gpio1_hwmod,
3620         &omap3xxx_gpio2_hwmod,
3621         &omap3xxx_gpio3_hwmod,
3622         &omap3xxx_gpio4_hwmod,
3623         &omap3xxx_gpio5_hwmod,
3624         &omap3xxx_gpio6_hwmod,
3625
3626         /* dma_system class*/
3627         &omap3xxx_dma_system_hwmod,
3628
3629         /* mcbsp class */
3630         &omap3xxx_mcbsp1_hwmod,
3631         &omap3xxx_mcbsp2_hwmod,
3632         &omap3xxx_mcbsp3_hwmod,
3633         &omap3xxx_mcbsp4_hwmod,
3634         &omap3xxx_mcbsp5_hwmod,
3635         &omap3xxx_mcbsp2_sidetone_hwmod,
3636         &omap3xxx_mcbsp3_sidetone_hwmod,
3637
3638         /* mailbox class */
3639         &omap3xxx_mailbox_hwmod,
3640
3641         /* mcspi class */
3642         &omap34xx_mcspi1,
3643         &omap34xx_mcspi2,
3644         &omap34xx_mcspi3,
3645         &omap34xx_mcspi4,
3646
3647         /* usbotg class */
3648         &omap3xxx_usbhsotg_hwmod,
3649
3650         /* usbotg for am35x */
3651         &am35xx_usbhsotg_hwmod,
3652
3653         NULL,
3654 };
3655
3656 int __init omap3xxx_hwmod_init(void)
3657 {
3658         return omap_hwmod_register(omap3xxx_hwmods);
3659 }