Merge branch 'prcm_scm_misc_fixes_3.2' of git://git.pwsan.com/linux-2.6 into fixes
[pandora-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
1 /*
2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Paul Walmsley
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * The data in this file should be completely autogeneratable from
12  * the TI hardware database or other technical documentation.
13  *
14  * XXX these should be marked initdata for multi-OMAP kernels
15  */
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
18 #include <plat/cpu.h>
19 #include <plat/dma.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
23 #include <plat/i2c.h>
24 #include <plat/gpio.h>
25 #include <plat/mmc.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
29
30 #include "omap_hwmod_common_data.h"
31
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
34 #include "wd_timer.h"
35 #include <mach/am35xx.h>
36
37 /*
38  * OMAP3xxx hardware module integration data
39  *
40  * ALl of the data in this section should be autogeneratable from the
41  * TI hardware database or other technical documentation.  Data that
42  * is driver-specific or driver-kernel integration-specific belongs
43  * elsewhere.
44  */
45
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
77
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
79
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
87
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90         .master = &omap3xxx_l3_main_hwmod,
91         .slave  = &omap3xxx_l4_core_hwmod,
92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
93 };
94
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97         .master = &omap3xxx_l3_main_hwmod,
98         .slave  = &omap3xxx_l4_per_hwmod,
99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
100 };
101
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104         { .irq = INT_34XX_L3_DBG_IRQ },
105         { .irq = INT_34XX_L3_APP_IRQ },
106         { .irq = -1 }
107 };
108
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
110         {
111                 .pa_start       = 0x68000000,
112                 .pa_end         = 0x6800ffff,
113                 .flags          = ADDR_TYPE_RT,
114         },
115         { }
116 };
117
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120         .master   = &omap3xxx_mpu_hwmod,
121         .slave    = &omap3xxx_l3_main_hwmod,
122         .addr     = omap3xxx_l3_main_addrs,
123         .user   = OCP_USER_MPU,
124 };
125
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128         &omap3xxx_mpu__l3_main,
129 };
130
131 /* DSS -> l3 */
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133         .master         = &omap3xxx_dss_core_hwmod,
134         .slave          = &omap3xxx_l3_main_hwmod,
135         .fw = {
136                 .omap2 = {
137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138                         .flags  = OMAP_FIREWALL_L3,
139                 }
140         },
141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
142 };
143
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146         &omap3xxx_l3_main__l4_core,
147         &omap3xxx_l3_main__l4_per,
148 };
149
150 /* L3 */
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
152         .name           = "l3_main",
153         .class          = &l3_hwmod_class,
154         .mpu_irqs       = omap3xxx_l3_main_irqs,
155         .masters        = omap3xxx_l3_main_masters,
156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
157         .slaves         = omap3xxx_l3_main_slaves,
158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159         .flags          = HWMOD_NO_IDLEST,
160 };
161
162 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
163 static struct omap_hwmod omap3xxx_uart1_hwmod;
164 static struct omap_hwmod omap3xxx_uart2_hwmod;
165 static struct omap_hwmod omap3xxx_uart3_hwmod;
166 static struct omap_hwmod omap3xxx_uart4_hwmod;
167 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
168
169 /* l3_core -> usbhsotg interface */
170 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
171         .master         = &omap3xxx_usbhsotg_hwmod,
172         .slave          = &omap3xxx_l3_main_hwmod,
173         .clk            = "core_l3_ick",
174         .user           = OCP_USER_MPU,
175 };
176
177 /* l3_core -> am35xx_usbhsotg interface */
178 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
179         .master         = &am35xx_usbhsotg_hwmod,
180         .slave          = &omap3xxx_l3_main_hwmod,
181         .clk            = "core_l3_ick",
182         .user           = OCP_USER_MPU,
183 };
184 /* L4_CORE -> L4_WKUP interface */
185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
186         .master = &omap3xxx_l4_core_hwmod,
187         .slave  = &omap3xxx_l4_wkup_hwmod,
188         .user   = OCP_USER_MPU | OCP_USER_SDMA,
189 };
190
191 /* L4 CORE -> MMC1 interface */
192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
193         .master         = &omap3xxx_l4_core_hwmod,
194         .slave          = &omap3xxx_mmc1_hwmod,
195         .clk            = "mmchs1_ick",
196         .addr           = omap2430_mmc1_addr_space,
197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
198         .flags          = OMAP_FIREWALL_L4
199 };
200
201 /* L4 CORE -> MMC2 interface */
202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
203         .master         = &omap3xxx_l4_core_hwmod,
204         .slave          = &omap3xxx_mmc2_hwmod,
205         .clk            = "mmchs2_ick",
206         .addr           = omap2430_mmc2_addr_space,
207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
208         .flags          = OMAP_FIREWALL_L4
209 };
210
211 /* L4 CORE -> MMC3 interface */
212 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
213         {
214                 .pa_start       = 0x480ad000,
215                 .pa_end         = 0x480ad1ff,
216                 .flags          = ADDR_TYPE_RT,
217         },
218         { }
219 };
220
221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
222         .master         = &omap3xxx_l4_core_hwmod,
223         .slave          = &omap3xxx_mmc3_hwmod,
224         .clk            = "mmchs3_ick",
225         .addr           = omap3xxx_mmc3_addr_space,
226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
227         .flags          = OMAP_FIREWALL_L4
228 };
229
230 /* L4 CORE -> UART1 interface */
231 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
232         {
233                 .pa_start       = OMAP3_UART1_BASE,
234                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
235                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
236         },
237         { }
238 };
239
240 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
241         .master         = &omap3xxx_l4_core_hwmod,
242         .slave          = &omap3xxx_uart1_hwmod,
243         .clk            = "uart1_ick",
244         .addr           = omap3xxx_uart1_addr_space,
245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
246 };
247
248 /* L4 CORE -> UART2 interface */
249 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
250         {
251                 .pa_start       = OMAP3_UART2_BASE,
252                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
253                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
254         },
255         { }
256 };
257
258 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
259         .master         = &omap3xxx_l4_core_hwmod,
260         .slave          = &omap3xxx_uart2_hwmod,
261         .clk            = "uart2_ick",
262         .addr           = omap3xxx_uart2_addr_space,
263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
264 };
265
266 /* L4 PER -> UART3 interface */
267 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
268         {
269                 .pa_start       = OMAP3_UART3_BASE,
270                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
271                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
272         },
273         { }
274 };
275
276 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
277         .master         = &omap3xxx_l4_per_hwmod,
278         .slave          = &omap3xxx_uart3_hwmod,
279         .clk            = "uart3_ick",
280         .addr           = omap3xxx_uart3_addr_space,
281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
282 };
283
284 /* L4 PER -> UART4 interface */
285 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
286         {
287                 .pa_start       = OMAP3_UART4_BASE,
288                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
289                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
290         },
291         { }
292 };
293
294 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
295         .master         = &omap3xxx_l4_per_hwmod,
296         .slave          = &omap3xxx_uart4_hwmod,
297         .clk            = "uart4_ick",
298         .addr           = omap3xxx_uart4_addr_space,
299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
300 };
301
302 /* L4 CORE -> I2C1 interface */
303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
304         .master         = &omap3xxx_l4_core_hwmod,
305         .slave          = &omap3xxx_i2c1_hwmod,
306         .clk            = "i2c1_ick",
307         .addr           = omap2_i2c1_addr_space,
308         .fw = {
309                 .omap2 = {
310                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
311                         .l4_prot_group = 7,
312                         .flags  = OMAP_FIREWALL_L4,
313                 }
314         },
315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
316 };
317
318 /* L4 CORE -> I2C2 interface */
319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
320         .master         = &omap3xxx_l4_core_hwmod,
321         .slave          = &omap3xxx_i2c2_hwmod,
322         .clk            = "i2c2_ick",
323         .addr           = omap2_i2c2_addr_space,
324         .fw = {
325                 .omap2 = {
326                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
327                         .l4_prot_group = 7,
328                         .flags = OMAP_FIREWALL_L4,
329                 }
330         },
331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
332 };
333
334 /* L4 CORE -> I2C3 interface */
335 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
336         {
337                 .pa_start       = 0x48060000,
338                 .pa_end         = 0x48060000 + SZ_128 - 1,
339                 .flags          = ADDR_TYPE_RT,
340         },
341         { }
342 };
343
344 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
345         .master         = &omap3xxx_l4_core_hwmod,
346         .slave          = &omap3xxx_i2c3_hwmod,
347         .clk            = "i2c3_ick",
348         .addr           = omap3xxx_i2c3_addr_space,
349         .fw = {
350                 .omap2 = {
351                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
352                         .l4_prot_group = 7,
353                         .flags = OMAP_FIREWALL_L4,
354                 }
355         },
356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
357 };
358
359 /* L4 CORE -> SR1 interface */
360 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
361         {
362                 .pa_start       = OMAP34XX_SR1_BASE,
363                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
364                 .flags          = ADDR_TYPE_RT,
365         },
366         { }
367 };
368
369 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
370         .master         = &omap3xxx_l4_core_hwmod,
371         .slave          = &omap34xx_sr1_hwmod,
372         .clk            = "sr_l4_ick",
373         .addr           = omap3_sr1_addr_space,
374         .user           = OCP_USER_MPU,
375 };
376
377 /* L4 CORE -> SR1 interface */
378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
379         {
380                 .pa_start       = OMAP34XX_SR2_BASE,
381                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
382                 .flags          = ADDR_TYPE_RT,
383         },
384         { }
385 };
386
387 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
388         .master         = &omap3xxx_l4_core_hwmod,
389         .slave          = &omap34xx_sr2_hwmod,
390         .clk            = "sr_l4_ick",
391         .addr           = omap3_sr2_addr_space,
392         .user           = OCP_USER_MPU,
393 };
394
395 /*
396 * usbhsotg interface data
397 */
398
399 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
400         {
401                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
402                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
403                 .flags          = ADDR_TYPE_RT
404         },
405         { }
406 };
407
408 /* l4_core -> usbhsotg  */
409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
410         .master         = &omap3xxx_l4_core_hwmod,
411         .slave          = &omap3xxx_usbhsotg_hwmod,
412         .clk            = "l4_ick",
413         .addr           = omap3xxx_usbhsotg_addrs,
414         .user           = OCP_USER_MPU,
415 };
416
417 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
418         &omap3xxx_usbhsotg__l3,
419 };
420
421 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
422         &omap3xxx_l4_core__usbhsotg,
423 };
424
425 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
426         {
427                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
428                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
429                 .flags          = ADDR_TYPE_RT
430         },
431         { }
432 };
433
434 /* l4_core -> usbhsotg  */
435 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
436         .master         = &omap3xxx_l4_core_hwmod,
437         .slave          = &am35xx_usbhsotg_hwmod,
438         .clk            = "l4_ick",
439         .addr           = am35xx_usbhsotg_addrs,
440         .user           = OCP_USER_MPU,
441 };
442
443 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
444         &am35xx_usbhsotg__l3,
445 };
446
447 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
448         &am35xx_l4_core__usbhsotg,
449 };
450 /* Slave interfaces on the L4_CORE interconnect */
451 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
452         &omap3xxx_l3_main__l4_core,
453 };
454
455 /* L4 CORE */
456 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
457         .name           = "l4_core",
458         .class          = &l4_hwmod_class,
459         .slaves         = omap3xxx_l4_core_slaves,
460         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
461         .flags          = HWMOD_NO_IDLEST,
462 };
463
464 /* Slave interfaces on the L4_PER interconnect */
465 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
466         &omap3xxx_l3_main__l4_per,
467 };
468
469 /* L4 PER */
470 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
471         .name           = "l4_per",
472         .class          = &l4_hwmod_class,
473         .slaves         = omap3xxx_l4_per_slaves,
474         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
475         .flags          = HWMOD_NO_IDLEST,
476 };
477
478 /* Slave interfaces on the L4_WKUP interconnect */
479 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
480         &omap3xxx_l4_core__l4_wkup,
481 };
482
483 /* L4 WKUP */
484 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
485         .name           = "l4_wkup",
486         .class          = &l4_hwmod_class,
487         .slaves         = omap3xxx_l4_wkup_slaves,
488         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
489         .flags          = HWMOD_NO_IDLEST,
490 };
491
492 /* Master interfaces on the MPU device */
493 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
494         &omap3xxx_mpu__l3_main,
495 };
496
497 /* MPU */
498 static struct omap_hwmod omap3xxx_mpu_hwmod = {
499         .name           = "mpu",
500         .class          = &mpu_hwmod_class,
501         .main_clk       = "arm_fck",
502         .masters        = omap3xxx_mpu_masters,
503         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
504 };
505
506 /*
507  * IVA2_2 interface data
508  */
509
510 /* IVA2 <- L3 interface */
511 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
512         .master         = &omap3xxx_l3_main_hwmod,
513         .slave          = &omap3xxx_iva_hwmod,
514         .clk            = "iva2_ck",
515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
516 };
517
518 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
519         &omap3xxx_l3__iva,
520 };
521
522 /*
523  * IVA2 (IVA2)
524  */
525
526 static struct omap_hwmod omap3xxx_iva_hwmod = {
527         .name           = "iva",
528         .class          = &iva_hwmod_class,
529         .masters        = omap3xxx_iva_masters,
530         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
531 };
532
533 /* timer class */
534 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
535         .rev_offs       = 0x0000,
536         .sysc_offs      = 0x0010,
537         .syss_offs      = 0x0014,
538         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
539                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
540                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
542         .sysc_fields    = &omap_hwmod_sysc_type1,
543 };
544
545 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
546         .name = "timer",
547         .sysc = &omap3xxx_timer_1ms_sysc,
548         .rev = OMAP_TIMER_IP_VERSION_1,
549 };
550
551 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
552         .rev_offs       = 0x0000,
553         .sysc_offs      = 0x0010,
554         .syss_offs      = 0x0014,
555         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
556                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
557         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
558         .sysc_fields    = &omap_hwmod_sysc_type1,
559 };
560
561 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
562         .name = "timer",
563         .sysc = &omap3xxx_timer_sysc,
564         .rev =  OMAP_TIMER_IP_VERSION_1,
565 };
566
567 /* secure timers dev attribute */
568 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
569         .timer_capability       = OMAP_TIMER_SECURE,
570 };
571
572 /* always-on timers dev attribute */
573 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
574         .timer_capability       = OMAP_TIMER_ALWON,
575 };
576
577 /* pwm timers dev attribute */
578 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
579         .timer_capability       = OMAP_TIMER_HAS_PWM,
580 };
581
582 /* timer1 */
583 static struct omap_hwmod omap3xxx_timer1_hwmod;
584
585 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
586         {
587                 .pa_start       = 0x48318000,
588                 .pa_end         = 0x48318000 + SZ_1K - 1,
589                 .flags          = ADDR_TYPE_RT
590         },
591         { }
592 };
593
594 /* l4_wkup -> timer1 */
595 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
596         .master         = &omap3xxx_l4_wkup_hwmod,
597         .slave          = &omap3xxx_timer1_hwmod,
598         .clk            = "gpt1_ick",
599         .addr           = omap3xxx_timer1_addrs,
600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
601 };
602
603 /* timer1 slave port */
604 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
605         &omap3xxx_l4_wkup__timer1,
606 };
607
608 /* timer1 hwmod */
609 static struct omap_hwmod omap3xxx_timer1_hwmod = {
610         .name           = "timer1",
611         .mpu_irqs       = omap2_timer1_mpu_irqs,
612         .main_clk       = "gpt1_fck",
613         .prcm           = {
614                 .omap2 = {
615                         .prcm_reg_id = 1,
616                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
617                         .module_offs = WKUP_MOD,
618                         .idlest_reg_id = 1,
619                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
620                 },
621         },
622         .dev_attr       = &capability_alwon_dev_attr,
623         .slaves         = omap3xxx_timer1_slaves,
624         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
625         .class          = &omap3xxx_timer_1ms_hwmod_class,
626 };
627
628 /* timer2 */
629 static struct omap_hwmod omap3xxx_timer2_hwmod;
630
631 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
632         {
633                 .pa_start       = 0x49032000,
634                 .pa_end         = 0x49032000 + SZ_1K - 1,
635                 .flags          = ADDR_TYPE_RT
636         },
637         { }
638 };
639
640 /* l4_per -> timer2 */
641 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
642         .master         = &omap3xxx_l4_per_hwmod,
643         .slave          = &omap3xxx_timer2_hwmod,
644         .clk            = "gpt2_ick",
645         .addr           = omap3xxx_timer2_addrs,
646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
647 };
648
649 /* timer2 slave port */
650 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
651         &omap3xxx_l4_per__timer2,
652 };
653
654 /* timer2 hwmod */
655 static struct omap_hwmod omap3xxx_timer2_hwmod = {
656         .name           = "timer2",
657         .mpu_irqs       = omap2_timer2_mpu_irqs,
658         .main_clk       = "gpt2_fck",
659         .prcm           = {
660                 .omap2 = {
661                         .prcm_reg_id = 1,
662                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
663                         .module_offs = OMAP3430_PER_MOD,
664                         .idlest_reg_id = 1,
665                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
666                 },
667         },
668         .dev_attr       = &capability_alwon_dev_attr,
669         .slaves         = omap3xxx_timer2_slaves,
670         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
671         .class          = &omap3xxx_timer_1ms_hwmod_class,
672 };
673
674 /* timer3 */
675 static struct omap_hwmod omap3xxx_timer3_hwmod;
676
677 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
678         {
679                 .pa_start       = 0x49034000,
680                 .pa_end         = 0x49034000 + SZ_1K - 1,
681                 .flags          = ADDR_TYPE_RT
682         },
683         { }
684 };
685
686 /* l4_per -> timer3 */
687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
688         .master         = &omap3xxx_l4_per_hwmod,
689         .slave          = &omap3xxx_timer3_hwmod,
690         .clk            = "gpt3_ick",
691         .addr           = omap3xxx_timer3_addrs,
692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
693 };
694
695 /* timer3 slave port */
696 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
697         &omap3xxx_l4_per__timer3,
698 };
699
700 /* timer3 hwmod */
701 static struct omap_hwmod omap3xxx_timer3_hwmod = {
702         .name           = "timer3",
703         .mpu_irqs       = omap2_timer3_mpu_irqs,
704         .main_clk       = "gpt3_fck",
705         .prcm           = {
706                 .omap2 = {
707                         .prcm_reg_id = 1,
708                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
709                         .module_offs = OMAP3430_PER_MOD,
710                         .idlest_reg_id = 1,
711                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
712                 },
713         },
714         .dev_attr       = &capability_alwon_dev_attr,
715         .slaves         = omap3xxx_timer3_slaves,
716         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
717         .class          = &omap3xxx_timer_hwmod_class,
718 };
719
720 /* timer4 */
721 static struct omap_hwmod omap3xxx_timer4_hwmod;
722
723 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
724         {
725                 .pa_start       = 0x49036000,
726                 .pa_end         = 0x49036000 + SZ_1K - 1,
727                 .flags          = ADDR_TYPE_RT
728         },
729         { }
730 };
731
732 /* l4_per -> timer4 */
733 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
734         .master         = &omap3xxx_l4_per_hwmod,
735         .slave          = &omap3xxx_timer4_hwmod,
736         .clk            = "gpt4_ick",
737         .addr           = omap3xxx_timer4_addrs,
738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
739 };
740
741 /* timer4 slave port */
742 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
743         &omap3xxx_l4_per__timer4,
744 };
745
746 /* timer4 hwmod */
747 static struct omap_hwmod omap3xxx_timer4_hwmod = {
748         .name           = "timer4",
749         .mpu_irqs       = omap2_timer4_mpu_irqs,
750         .main_clk       = "gpt4_fck",
751         .prcm           = {
752                 .omap2 = {
753                         .prcm_reg_id = 1,
754                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
755                         .module_offs = OMAP3430_PER_MOD,
756                         .idlest_reg_id = 1,
757                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
758                 },
759         },
760         .dev_attr       = &capability_alwon_dev_attr,
761         .slaves         = omap3xxx_timer4_slaves,
762         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
763         .class          = &omap3xxx_timer_hwmod_class,
764 };
765
766 /* timer5 */
767 static struct omap_hwmod omap3xxx_timer5_hwmod;
768
769 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
770         {
771                 .pa_start       = 0x49038000,
772                 .pa_end         = 0x49038000 + SZ_1K - 1,
773                 .flags          = ADDR_TYPE_RT
774         },
775         { }
776 };
777
778 /* l4_per -> timer5 */
779 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
780         .master         = &omap3xxx_l4_per_hwmod,
781         .slave          = &omap3xxx_timer5_hwmod,
782         .clk            = "gpt5_ick",
783         .addr           = omap3xxx_timer5_addrs,
784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
785 };
786
787 /* timer5 slave port */
788 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
789         &omap3xxx_l4_per__timer5,
790 };
791
792 /* timer5 hwmod */
793 static struct omap_hwmod omap3xxx_timer5_hwmod = {
794         .name           = "timer5",
795         .mpu_irqs       = omap2_timer5_mpu_irqs,
796         .main_clk       = "gpt5_fck",
797         .prcm           = {
798                 .omap2 = {
799                         .prcm_reg_id = 1,
800                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
801                         .module_offs = OMAP3430_PER_MOD,
802                         .idlest_reg_id = 1,
803                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
804                 },
805         },
806         .dev_attr       = &capability_alwon_dev_attr,
807         .slaves         = omap3xxx_timer5_slaves,
808         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
809         .class          = &omap3xxx_timer_hwmod_class,
810 };
811
812 /* timer6 */
813 static struct omap_hwmod omap3xxx_timer6_hwmod;
814
815 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
816         {
817                 .pa_start       = 0x4903A000,
818                 .pa_end         = 0x4903A000 + SZ_1K - 1,
819                 .flags          = ADDR_TYPE_RT
820         },
821         { }
822 };
823
824 /* l4_per -> timer6 */
825 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
826         .master         = &omap3xxx_l4_per_hwmod,
827         .slave          = &omap3xxx_timer6_hwmod,
828         .clk            = "gpt6_ick",
829         .addr           = omap3xxx_timer6_addrs,
830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
831 };
832
833 /* timer6 slave port */
834 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
835         &omap3xxx_l4_per__timer6,
836 };
837
838 /* timer6 hwmod */
839 static struct omap_hwmod omap3xxx_timer6_hwmod = {
840         .name           = "timer6",
841         .mpu_irqs       = omap2_timer6_mpu_irqs,
842         .main_clk       = "gpt6_fck",
843         .prcm           = {
844                 .omap2 = {
845                         .prcm_reg_id = 1,
846                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
847                         .module_offs = OMAP3430_PER_MOD,
848                         .idlest_reg_id = 1,
849                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
850                 },
851         },
852         .dev_attr       = &capability_alwon_dev_attr,
853         .slaves         = omap3xxx_timer6_slaves,
854         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
855         .class          = &omap3xxx_timer_hwmod_class,
856 };
857
858 /* timer7 */
859 static struct omap_hwmod omap3xxx_timer7_hwmod;
860
861 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
862         {
863                 .pa_start       = 0x4903C000,
864                 .pa_end         = 0x4903C000 + SZ_1K - 1,
865                 .flags          = ADDR_TYPE_RT
866         },
867         { }
868 };
869
870 /* l4_per -> timer7 */
871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
872         .master         = &omap3xxx_l4_per_hwmod,
873         .slave          = &omap3xxx_timer7_hwmod,
874         .clk            = "gpt7_ick",
875         .addr           = omap3xxx_timer7_addrs,
876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
877 };
878
879 /* timer7 slave port */
880 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
881         &omap3xxx_l4_per__timer7,
882 };
883
884 /* timer7 hwmod */
885 static struct omap_hwmod omap3xxx_timer7_hwmod = {
886         .name           = "timer7",
887         .mpu_irqs       = omap2_timer7_mpu_irqs,
888         .main_clk       = "gpt7_fck",
889         .prcm           = {
890                 .omap2 = {
891                         .prcm_reg_id = 1,
892                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
893                         .module_offs = OMAP3430_PER_MOD,
894                         .idlest_reg_id = 1,
895                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
896                 },
897         },
898         .dev_attr       = &capability_alwon_dev_attr,
899         .slaves         = omap3xxx_timer7_slaves,
900         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
901         .class          = &omap3xxx_timer_hwmod_class,
902 };
903
904 /* timer8 */
905 static struct omap_hwmod omap3xxx_timer8_hwmod;
906
907 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
908         {
909                 .pa_start       = 0x4903E000,
910                 .pa_end         = 0x4903E000 + SZ_1K - 1,
911                 .flags          = ADDR_TYPE_RT
912         },
913         { }
914 };
915
916 /* l4_per -> timer8 */
917 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
918         .master         = &omap3xxx_l4_per_hwmod,
919         .slave          = &omap3xxx_timer8_hwmod,
920         .clk            = "gpt8_ick",
921         .addr           = omap3xxx_timer8_addrs,
922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
923 };
924
925 /* timer8 slave port */
926 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
927         &omap3xxx_l4_per__timer8,
928 };
929
930 /* timer8 hwmod */
931 static struct omap_hwmod omap3xxx_timer8_hwmod = {
932         .name           = "timer8",
933         .mpu_irqs       = omap2_timer8_mpu_irqs,
934         .main_clk       = "gpt8_fck",
935         .prcm           = {
936                 .omap2 = {
937                         .prcm_reg_id = 1,
938                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
939                         .module_offs = OMAP3430_PER_MOD,
940                         .idlest_reg_id = 1,
941                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
942                 },
943         },
944         .dev_attr       = &capability_pwm_dev_attr,
945         .slaves         = omap3xxx_timer8_slaves,
946         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
947         .class          = &omap3xxx_timer_hwmod_class,
948 };
949
950 /* timer9 */
951 static struct omap_hwmod omap3xxx_timer9_hwmod;
952
953 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
954         {
955                 .pa_start       = 0x49040000,
956                 .pa_end         = 0x49040000 + SZ_1K - 1,
957                 .flags          = ADDR_TYPE_RT
958         },
959         { }
960 };
961
962 /* l4_per -> timer9 */
963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
964         .master         = &omap3xxx_l4_per_hwmod,
965         .slave          = &omap3xxx_timer9_hwmod,
966         .clk            = "gpt9_ick",
967         .addr           = omap3xxx_timer9_addrs,
968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
969 };
970
971 /* timer9 slave port */
972 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
973         &omap3xxx_l4_per__timer9,
974 };
975
976 /* timer9 hwmod */
977 static struct omap_hwmod omap3xxx_timer9_hwmod = {
978         .name           = "timer9",
979         .mpu_irqs       = omap2_timer9_mpu_irqs,
980         .main_clk       = "gpt9_fck",
981         .prcm           = {
982                 .omap2 = {
983                         .prcm_reg_id = 1,
984                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
985                         .module_offs = OMAP3430_PER_MOD,
986                         .idlest_reg_id = 1,
987                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
988                 },
989         },
990         .dev_attr       = &capability_pwm_dev_attr,
991         .slaves         = omap3xxx_timer9_slaves,
992         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
993         .class          = &omap3xxx_timer_hwmod_class,
994 };
995
996 /* timer10 */
997 static struct omap_hwmod omap3xxx_timer10_hwmod;
998
999 /* l4_core -> timer10 */
1000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1001         .master         = &omap3xxx_l4_core_hwmod,
1002         .slave          = &omap3xxx_timer10_hwmod,
1003         .clk            = "gpt10_ick",
1004         .addr           = omap2_timer10_addrs,
1005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1006 };
1007
1008 /* timer10 slave port */
1009 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1010         &omap3xxx_l4_core__timer10,
1011 };
1012
1013 /* timer10 hwmod */
1014 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1015         .name           = "timer10",
1016         .mpu_irqs       = omap2_timer10_mpu_irqs,
1017         .main_clk       = "gpt10_fck",
1018         .prcm           = {
1019                 .omap2 = {
1020                         .prcm_reg_id = 1,
1021                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1022                         .module_offs = CORE_MOD,
1023                         .idlest_reg_id = 1,
1024                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1025                 },
1026         },
1027         .dev_attr       = &capability_pwm_dev_attr,
1028         .slaves         = omap3xxx_timer10_slaves,
1029         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1030         .class          = &omap3xxx_timer_1ms_hwmod_class,
1031 };
1032
1033 /* timer11 */
1034 static struct omap_hwmod omap3xxx_timer11_hwmod;
1035
1036 /* l4_core -> timer11 */
1037 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1038         .master         = &omap3xxx_l4_core_hwmod,
1039         .slave          = &omap3xxx_timer11_hwmod,
1040         .clk            = "gpt11_ick",
1041         .addr           = omap2_timer11_addrs,
1042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1043 };
1044
1045 /* timer11 slave port */
1046 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1047         &omap3xxx_l4_core__timer11,
1048 };
1049
1050 /* timer11 hwmod */
1051 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1052         .name           = "timer11",
1053         .mpu_irqs       = omap2_timer11_mpu_irqs,
1054         .main_clk       = "gpt11_fck",
1055         .prcm           = {
1056                 .omap2 = {
1057                         .prcm_reg_id = 1,
1058                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1059                         .module_offs = CORE_MOD,
1060                         .idlest_reg_id = 1,
1061                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1062                 },
1063         },
1064         .dev_attr       = &capability_pwm_dev_attr,
1065         .slaves         = omap3xxx_timer11_slaves,
1066         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1067         .class          = &omap3xxx_timer_hwmod_class,
1068 };
1069
1070 /* timer12*/
1071 static struct omap_hwmod omap3xxx_timer12_hwmod;
1072 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1073         { .irq = 95, },
1074         { .irq = -1 }
1075 };
1076
1077 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1078         {
1079                 .pa_start       = 0x48304000,
1080                 .pa_end         = 0x48304000 + SZ_1K - 1,
1081                 .flags          = ADDR_TYPE_RT
1082         },
1083         { }
1084 };
1085
1086 /* l4_core -> timer12 */
1087 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1088         .master         = &omap3xxx_l4_core_hwmod,
1089         .slave          = &omap3xxx_timer12_hwmod,
1090         .clk            = "gpt12_ick",
1091         .addr           = omap3xxx_timer12_addrs,
1092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1093 };
1094
1095 /* timer12 slave port */
1096 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1097         &omap3xxx_l4_core__timer12,
1098 };
1099
1100 /* timer12 hwmod */
1101 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1102         .name           = "timer12",
1103         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1104         .main_clk       = "gpt12_fck",
1105         .prcm           = {
1106                 .omap2 = {
1107                         .prcm_reg_id = 1,
1108                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1109                         .module_offs = WKUP_MOD,
1110                         .idlest_reg_id = 1,
1111                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1112                 },
1113         },
1114         .dev_attr       = &capability_secure_dev_attr,
1115         .slaves         = omap3xxx_timer12_slaves,
1116         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1117         .class          = &omap3xxx_timer_hwmod_class,
1118 };
1119
1120 /* l4_wkup -> wd_timer2 */
1121 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1122         {
1123                 .pa_start       = 0x48314000,
1124                 .pa_end         = 0x4831407f,
1125                 .flags          = ADDR_TYPE_RT
1126         },
1127         { }
1128 };
1129
1130 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1131         .master         = &omap3xxx_l4_wkup_hwmod,
1132         .slave          = &omap3xxx_wd_timer2_hwmod,
1133         .clk            = "wdt2_ick",
1134         .addr           = omap3xxx_wd_timer2_addrs,
1135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1136 };
1137
1138 /*
1139  * 'wd_timer' class
1140  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1141  * overflow condition
1142  */
1143
1144 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1145         .rev_offs       = 0x0000,
1146         .sysc_offs      = 0x0010,
1147         .syss_offs      = 0x0014,
1148         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1149                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1150                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1151                            SYSS_HAS_RESET_STATUS),
1152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1153         .sysc_fields    = &omap_hwmod_sysc_type1,
1154 };
1155
1156 /* I2C common */
1157 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1158         .rev_offs       = 0x00,
1159         .sysc_offs      = 0x20,
1160         .syss_offs      = 0x10,
1161         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1162                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1163                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1165         .sysc_fields    = &omap_hwmod_sysc_type1,
1166 };
1167
1168 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1169         .name           = "wd_timer",
1170         .sysc           = &omap3xxx_wd_timer_sysc,
1171         .pre_shutdown   = &omap2_wd_timer_disable
1172 };
1173
1174 /* wd_timer2 */
1175 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1176         &omap3xxx_l4_wkup__wd_timer2,
1177 };
1178
1179 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1180         .name           = "wd_timer2",
1181         .class          = &omap3xxx_wd_timer_hwmod_class,
1182         .main_clk       = "wdt2_fck",
1183         .prcm           = {
1184                 .omap2 = {
1185                         .prcm_reg_id = 1,
1186                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1187                         .module_offs = WKUP_MOD,
1188                         .idlest_reg_id = 1,
1189                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1190                 },
1191         },
1192         .slaves         = omap3xxx_wd_timer2_slaves,
1193         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1194         /*
1195          * XXX: Use software supervised mode, HW supervised smartidle seems to
1196          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1197          */
1198         .flags          = HWMOD_SWSUP_SIDLE,
1199 };
1200
1201 /* UART1 */
1202
1203 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1204         &omap3_l4_core__uart1,
1205 };
1206
1207 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1208         .name           = "uart1",
1209         .mpu_irqs       = omap2_uart1_mpu_irqs,
1210         .sdma_reqs      = omap2_uart1_sdma_reqs,
1211         .main_clk       = "uart1_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .module_offs = CORE_MOD,
1215                         .prcm_reg_id = 1,
1216                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_uart1_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1223         .class          = &omap2_uart_class,
1224 };
1225
1226 /* UART2 */
1227
1228 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1229         &omap3_l4_core__uart2,
1230 };
1231
1232 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1233         .name           = "uart2",
1234         .mpu_irqs       = omap2_uart2_mpu_irqs,
1235         .sdma_reqs      = omap2_uart2_sdma_reqs,
1236         .main_clk       = "uart2_fck",
1237         .prcm           = {
1238                 .omap2 = {
1239                         .module_offs = CORE_MOD,
1240                         .prcm_reg_id = 1,
1241                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1242                         .idlest_reg_id = 1,
1243                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1244                 },
1245         },
1246         .slaves         = omap3xxx_uart2_slaves,
1247         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1248         .class          = &omap2_uart_class,
1249 };
1250
1251 /* UART3 */
1252
1253 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1254         &omap3_l4_per__uart3,
1255 };
1256
1257 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1258         .name           = "uart3",
1259         .mpu_irqs       = omap2_uart3_mpu_irqs,
1260         .sdma_reqs      = omap2_uart3_sdma_reqs,
1261         .main_clk       = "uart3_fck",
1262         .prcm           = {
1263                 .omap2 = {
1264                         .module_offs = OMAP3430_PER_MOD,
1265                         .prcm_reg_id = 1,
1266                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1267                         .idlest_reg_id = 1,
1268                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1269                 },
1270         },
1271         .slaves         = omap3xxx_uart3_slaves,
1272         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1273         .class          = &omap2_uart_class,
1274 };
1275
1276 /* UART4 */
1277
1278 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1279         { .irq = INT_36XX_UART4_IRQ, },
1280         { .irq = -1 }
1281 };
1282
1283 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1284         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1285         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1286         { .dma_req = -1 }
1287 };
1288
1289 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1290         &omap3_l4_per__uart4,
1291 };
1292
1293 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1294         .name           = "uart4",
1295         .mpu_irqs       = uart4_mpu_irqs,
1296         .sdma_reqs      = uart4_sdma_reqs,
1297         .main_clk       = "uart4_fck",
1298         .prcm           = {
1299                 .omap2 = {
1300                         .module_offs = OMAP3430_PER_MOD,
1301                         .prcm_reg_id = 1,
1302                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1303                         .idlest_reg_id = 1,
1304                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1305                 },
1306         },
1307         .slaves         = omap3xxx_uart4_slaves,
1308         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1309         .class          = &omap2_uart_class,
1310 };
1311
1312 static struct omap_hwmod_class i2c_class = {
1313         .name   = "i2c",
1314         .sysc   = &i2c_sysc,
1315         .rev    = OMAP_I2C_IP_VERSION_1,
1316         .reset  = &omap_i2c_reset,
1317 };
1318
1319 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1320         { .name = "dispc", .dma_req = 5 },
1321         { .name = "dsi1", .dma_req = 74 },
1322         { .dma_req = -1 }
1323 };
1324
1325 /* dss */
1326 /* dss master ports */
1327 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1328         &omap3xxx_dss__l3,
1329 };
1330
1331 /* l4_core -> dss */
1332 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1333         .master         = &omap3xxx_l4_core_hwmod,
1334         .slave          = &omap3430es1_dss_core_hwmod,
1335         .clk            = "dss_ick",
1336         .addr           = omap2_dss_addrs,
1337         .fw = {
1338                 .omap2 = {
1339                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1340                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1341                         .flags  = OMAP_FIREWALL_L4,
1342                 }
1343         },
1344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1345 };
1346
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1348         .master         = &omap3xxx_l4_core_hwmod,
1349         .slave          = &omap3xxx_dss_core_hwmod,
1350         .clk            = "dss_ick",
1351         .addr           = omap2_dss_addrs,
1352         .fw = {
1353                 .omap2 = {
1354                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1355                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1356                         .flags  = OMAP_FIREWALL_L4,
1357                 }
1358         },
1359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1360 };
1361
1362 /* dss slave ports */
1363 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1364         &omap3430es1_l4_core__dss,
1365 };
1366
1367 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1368         &omap3xxx_l4_core__dss,
1369 };
1370
1371 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372         { .role = "tv_clk", .clk = "dss_tv_fck" },
1373         { .role = "video_clk", .clk = "dss_96m_fck" },
1374         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1375 };
1376
1377 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1378         .name           = "dss_core",
1379         .class          = &omap2_dss_hwmod_class,
1380         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1381         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1382         .prcm           = {
1383                 .omap2 = {
1384                         .prcm_reg_id = 1,
1385                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1386                         .module_offs = OMAP3430_DSS_MOD,
1387                         .idlest_reg_id = 1,
1388                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1389                 },
1390         },
1391         .opt_clks       = dss_opt_clks,
1392         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1393         .slaves         = omap3430es1_dss_slaves,
1394         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1395         .masters        = omap3xxx_dss_masters,
1396         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1397         .flags          = HWMOD_NO_IDLEST,
1398 };
1399
1400 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1401         .name           = "dss_core",
1402         .class          = &omap2_dss_hwmod_class,
1403         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1404         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1405         .prcm           = {
1406                 .omap2 = {
1407                         .prcm_reg_id = 1,
1408                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1409                         .module_offs = OMAP3430_DSS_MOD,
1410                         .idlest_reg_id = 1,
1411                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1412                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1413                 },
1414         },
1415         .opt_clks       = dss_opt_clks,
1416         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1417         .slaves         = omap3xxx_dss_slaves,
1418         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1419         .masters        = omap3xxx_dss_masters,
1420         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1421 };
1422
1423 /* l4_core -> dss_dispc */
1424 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1425         .master         = &omap3xxx_l4_core_hwmod,
1426         .slave          = &omap3xxx_dss_dispc_hwmod,
1427         .clk            = "dss_ick",
1428         .addr           = omap2_dss_dispc_addrs,
1429         .fw = {
1430                 .omap2 = {
1431                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1432                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1433                         .flags  = OMAP_FIREWALL_L4,
1434                 }
1435         },
1436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1437 };
1438
1439 /* dss_dispc slave ports */
1440 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1441         &omap3xxx_l4_core__dss_dispc,
1442 };
1443
1444 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1445         .name           = "dss_dispc",
1446         .class          = &omap2_dispc_hwmod_class,
1447         .mpu_irqs       = omap2_dispc_irqs,
1448         .main_clk       = "dss1_alwon_fck",
1449         .prcm           = {
1450                 .omap2 = {
1451                         .prcm_reg_id = 1,
1452                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1453                         .module_offs = OMAP3430_DSS_MOD,
1454                 },
1455         },
1456         .slaves         = omap3xxx_dss_dispc_slaves,
1457         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1458         .flags          = HWMOD_NO_IDLEST,
1459 };
1460
1461 /*
1462  * 'dsi' class
1463  * display serial interface controller
1464  */
1465
1466 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1467         .name = "dsi",
1468 };
1469
1470 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1471         { .irq = 25 },
1472         { .irq = -1 }
1473 };
1474
1475 /* dss_dsi1 */
1476 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1477         {
1478                 .pa_start       = 0x4804FC00,
1479                 .pa_end         = 0x4804FFFF,
1480                 .flags          = ADDR_TYPE_RT
1481         },
1482         { }
1483 };
1484
1485 /* l4_core -> dss_dsi1 */
1486 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1487         .master         = &omap3xxx_l4_core_hwmod,
1488         .slave          = &omap3xxx_dss_dsi1_hwmod,
1489         .addr           = omap3xxx_dss_dsi1_addrs,
1490         .fw = {
1491                 .omap2 = {
1492                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1493                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1494                         .flags  = OMAP_FIREWALL_L4,
1495                 }
1496         },
1497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1498 };
1499
1500 /* dss_dsi1 slave ports */
1501 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1502         &omap3xxx_l4_core__dss_dsi1,
1503 };
1504
1505 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1506         .name           = "dss_dsi1",
1507         .class          = &omap3xxx_dsi_hwmod_class,
1508         .mpu_irqs       = omap3xxx_dsi1_irqs,
1509         .main_clk       = "dss1_alwon_fck",
1510         .prcm           = {
1511                 .omap2 = {
1512                         .prcm_reg_id = 1,
1513                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1514                         .module_offs = OMAP3430_DSS_MOD,
1515                 },
1516         },
1517         .slaves         = omap3xxx_dss_dsi1_slaves,
1518         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1519         .flags          = HWMOD_NO_IDLEST,
1520 };
1521
1522 /* l4_core -> dss_rfbi */
1523 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1524         .master         = &omap3xxx_l4_core_hwmod,
1525         .slave          = &omap3xxx_dss_rfbi_hwmod,
1526         .clk            = "dss_ick",
1527         .addr           = omap2_dss_rfbi_addrs,
1528         .fw = {
1529                 .omap2 = {
1530                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1531                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1532                         .flags  = OMAP_FIREWALL_L4,
1533                 }
1534         },
1535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1536 };
1537
1538 /* dss_rfbi slave ports */
1539 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1540         &omap3xxx_l4_core__dss_rfbi,
1541 };
1542
1543 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1544         .name           = "dss_rfbi",
1545         .class          = &omap2_rfbi_hwmod_class,
1546         .main_clk       = "dss1_alwon_fck",
1547         .prcm           = {
1548                 .omap2 = {
1549                         .prcm_reg_id = 1,
1550                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1551                         .module_offs = OMAP3430_DSS_MOD,
1552                 },
1553         },
1554         .slaves         = omap3xxx_dss_rfbi_slaves,
1555         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1556         .flags          = HWMOD_NO_IDLEST,
1557 };
1558
1559 /* l4_core -> dss_venc */
1560 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1561         .master         = &omap3xxx_l4_core_hwmod,
1562         .slave          = &omap3xxx_dss_venc_hwmod,
1563         .clk            = "dss_tv_fck",
1564         .addr           = omap2_dss_venc_addrs,
1565         .fw = {
1566                 .omap2 = {
1567                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1568                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1569                         .flags  = OMAP_FIREWALL_L4,
1570                 }
1571         },
1572         .flags          = OCPIF_SWSUP_IDLE,
1573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1574 };
1575
1576 /* dss_venc slave ports */
1577 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1578         &omap3xxx_l4_core__dss_venc,
1579 };
1580
1581 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1582         .name           = "dss_venc",
1583         .class          = &omap2_venc_hwmod_class,
1584         .main_clk       = "dss1_alwon_fck",
1585         .prcm           = {
1586                 .omap2 = {
1587                         .prcm_reg_id = 1,
1588                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1589                         .module_offs = OMAP3430_DSS_MOD,
1590                 },
1591         },
1592         .slaves         = omap3xxx_dss_venc_slaves,
1593         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1594         .flags          = HWMOD_NO_IDLEST,
1595 };
1596
1597 /* I2C1 */
1598
1599 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1600         .fifo_depth     = 8, /* bytes */
1601         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1602                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1603                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1604 };
1605
1606 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1607         &omap3_l4_core__i2c1,
1608 };
1609
1610 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1611         .name           = "i2c1",
1612         .flags          = HWMOD_16BIT_REG,
1613         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1614         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1615         .main_clk       = "i2c1_fck",
1616         .prcm           = {
1617                 .omap2 = {
1618                         .module_offs = CORE_MOD,
1619                         .prcm_reg_id = 1,
1620                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1621                         .idlest_reg_id = 1,
1622                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1623                 },
1624         },
1625         .slaves         = omap3xxx_i2c1_slaves,
1626         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1627         .class          = &i2c_class,
1628         .dev_attr       = &i2c1_dev_attr,
1629 };
1630
1631 /* I2C2 */
1632
1633 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1634         .fifo_depth     = 8, /* bytes */
1635         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1636                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1637                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1638 };
1639
1640 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1641         &omap3_l4_core__i2c2,
1642 };
1643
1644 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1645         .name           = "i2c2",
1646         .flags          = HWMOD_16BIT_REG,
1647         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1648         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1649         .main_clk       = "i2c2_fck",
1650         .prcm           = {
1651                 .omap2 = {
1652                         .module_offs = CORE_MOD,
1653                         .prcm_reg_id = 1,
1654                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1655                         .idlest_reg_id = 1,
1656                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1657                 },
1658         },
1659         .slaves         = omap3xxx_i2c2_slaves,
1660         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1661         .class          = &i2c_class,
1662         .dev_attr       = &i2c2_dev_attr,
1663 };
1664
1665 /* I2C3 */
1666
1667 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1668         .fifo_depth     = 64, /* bytes */
1669         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1670                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1671                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1672 };
1673
1674 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1675         { .irq = INT_34XX_I2C3_IRQ, },
1676         { .irq = -1 }
1677 };
1678
1679 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1680         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1681         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1682         { .dma_req = -1 }
1683 };
1684
1685 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1686         &omap3_l4_core__i2c3,
1687 };
1688
1689 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1690         .name           = "i2c3",
1691         .flags          = HWMOD_16BIT_REG,
1692         .mpu_irqs       = i2c3_mpu_irqs,
1693         .sdma_reqs      = i2c3_sdma_reqs,
1694         .main_clk       = "i2c3_fck",
1695         .prcm           = {
1696                 .omap2 = {
1697                         .module_offs = CORE_MOD,
1698                         .prcm_reg_id = 1,
1699                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1700                         .idlest_reg_id = 1,
1701                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1702                 },
1703         },
1704         .slaves         = omap3xxx_i2c3_slaves,
1705         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1706         .class          = &i2c_class,
1707         .dev_attr       = &i2c3_dev_attr,
1708 };
1709
1710 /* l4_wkup -> gpio1 */
1711 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1712         {
1713                 .pa_start       = 0x48310000,
1714                 .pa_end         = 0x483101ff,
1715                 .flags          = ADDR_TYPE_RT
1716         },
1717         { }
1718 };
1719
1720 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1721         .master         = &omap3xxx_l4_wkup_hwmod,
1722         .slave          = &omap3xxx_gpio1_hwmod,
1723         .addr           = omap3xxx_gpio1_addrs,
1724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1725 };
1726
1727 /* l4_per -> gpio2 */
1728 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1729         {
1730                 .pa_start       = 0x49050000,
1731                 .pa_end         = 0x490501ff,
1732                 .flags          = ADDR_TYPE_RT
1733         },
1734         { }
1735 };
1736
1737 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1738         .master         = &omap3xxx_l4_per_hwmod,
1739         .slave          = &omap3xxx_gpio2_hwmod,
1740         .addr           = omap3xxx_gpio2_addrs,
1741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1742 };
1743
1744 /* l4_per -> gpio3 */
1745 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1746         {
1747                 .pa_start       = 0x49052000,
1748                 .pa_end         = 0x490521ff,
1749                 .flags          = ADDR_TYPE_RT
1750         },
1751         { }
1752 };
1753
1754 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1755         .master         = &omap3xxx_l4_per_hwmod,
1756         .slave          = &omap3xxx_gpio3_hwmod,
1757         .addr           = omap3xxx_gpio3_addrs,
1758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1759 };
1760
1761 /* l4_per -> gpio4 */
1762 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1763         {
1764                 .pa_start       = 0x49054000,
1765                 .pa_end         = 0x490541ff,
1766                 .flags          = ADDR_TYPE_RT
1767         },
1768         { }
1769 };
1770
1771 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1772         .master         = &omap3xxx_l4_per_hwmod,
1773         .slave          = &omap3xxx_gpio4_hwmod,
1774         .addr           = omap3xxx_gpio4_addrs,
1775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1776 };
1777
1778 /* l4_per -> gpio5 */
1779 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1780         {
1781                 .pa_start       = 0x49056000,
1782                 .pa_end         = 0x490561ff,
1783                 .flags          = ADDR_TYPE_RT
1784         },
1785         { }
1786 };
1787
1788 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1789         .master         = &omap3xxx_l4_per_hwmod,
1790         .slave          = &omap3xxx_gpio5_hwmod,
1791         .addr           = omap3xxx_gpio5_addrs,
1792         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1793 };
1794
1795 /* l4_per -> gpio6 */
1796 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1797         {
1798                 .pa_start       = 0x49058000,
1799                 .pa_end         = 0x490581ff,
1800                 .flags          = ADDR_TYPE_RT
1801         },
1802         { }
1803 };
1804
1805 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1806         .master         = &omap3xxx_l4_per_hwmod,
1807         .slave          = &omap3xxx_gpio6_hwmod,
1808         .addr           = omap3xxx_gpio6_addrs,
1809         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1810 };
1811
1812 /*
1813  * 'gpio' class
1814  * general purpose io module
1815  */
1816
1817 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1818         .rev_offs       = 0x0000,
1819         .sysc_offs      = 0x0010,
1820         .syss_offs      = 0x0014,
1821         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1822                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1823                            SYSS_HAS_RESET_STATUS),
1824         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1825         .sysc_fields    = &omap_hwmod_sysc_type1,
1826 };
1827
1828 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1829         .name = "gpio",
1830         .sysc = &omap3xxx_gpio_sysc,
1831         .rev = 1,
1832 };
1833
1834 /* gpio_dev_attr*/
1835 static struct omap_gpio_dev_attr gpio_dev_attr = {
1836         .bank_width = 32,
1837         .dbck_flag = true,
1838 };
1839
1840 /* gpio1 */
1841 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1842         { .role = "dbclk", .clk = "gpio1_dbck", },
1843 };
1844
1845 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1846         &omap3xxx_l4_wkup__gpio1,
1847 };
1848
1849 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1850         .name           = "gpio1",
1851         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1852         .mpu_irqs       = omap2_gpio1_irqs,
1853         .main_clk       = "gpio1_ick",
1854         .opt_clks       = gpio1_opt_clks,
1855         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1856         .prcm           = {
1857                 .omap2 = {
1858                         .prcm_reg_id = 1,
1859                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1860                         .module_offs = WKUP_MOD,
1861                         .idlest_reg_id = 1,
1862                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1863                 },
1864         },
1865         .slaves         = omap3xxx_gpio1_slaves,
1866         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1867         .class          = &omap3xxx_gpio_hwmod_class,
1868         .dev_attr       = &gpio_dev_attr,
1869 };
1870
1871 /* gpio2 */
1872 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1873         { .role = "dbclk", .clk = "gpio2_dbck", },
1874 };
1875
1876 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1877         &omap3xxx_l4_per__gpio2,
1878 };
1879
1880 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1881         .name           = "gpio2",
1882         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1883         .mpu_irqs       = omap2_gpio2_irqs,
1884         .main_clk       = "gpio2_ick",
1885         .opt_clks       = gpio2_opt_clks,
1886         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1887         .prcm           = {
1888                 .omap2 = {
1889                         .prcm_reg_id = 1,
1890                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1891                         .module_offs = OMAP3430_PER_MOD,
1892                         .idlest_reg_id = 1,
1893                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1894                 },
1895         },
1896         .slaves         = omap3xxx_gpio2_slaves,
1897         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1898         .class          = &omap3xxx_gpio_hwmod_class,
1899         .dev_attr       = &gpio_dev_attr,
1900 };
1901
1902 /* gpio3 */
1903 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1904         { .role = "dbclk", .clk = "gpio3_dbck", },
1905 };
1906
1907 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1908         &omap3xxx_l4_per__gpio3,
1909 };
1910
1911 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1912         .name           = "gpio3",
1913         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1914         .mpu_irqs       = omap2_gpio3_irqs,
1915         .main_clk       = "gpio3_ick",
1916         .opt_clks       = gpio3_opt_clks,
1917         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1918         .prcm           = {
1919                 .omap2 = {
1920                         .prcm_reg_id = 1,
1921                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1922                         .module_offs = OMAP3430_PER_MOD,
1923                         .idlest_reg_id = 1,
1924                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1925                 },
1926         },
1927         .slaves         = omap3xxx_gpio3_slaves,
1928         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1929         .class          = &omap3xxx_gpio_hwmod_class,
1930         .dev_attr       = &gpio_dev_attr,
1931 };
1932
1933 /* gpio4 */
1934 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1935         { .role = "dbclk", .clk = "gpio4_dbck", },
1936 };
1937
1938 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1939         &omap3xxx_l4_per__gpio4,
1940 };
1941
1942 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1943         .name           = "gpio4",
1944         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1945         .mpu_irqs       = omap2_gpio4_irqs,
1946         .main_clk       = "gpio4_ick",
1947         .opt_clks       = gpio4_opt_clks,
1948         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1949         .prcm           = {
1950                 .omap2 = {
1951                         .prcm_reg_id = 1,
1952                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1953                         .module_offs = OMAP3430_PER_MOD,
1954                         .idlest_reg_id = 1,
1955                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1956                 },
1957         },
1958         .slaves         = omap3xxx_gpio4_slaves,
1959         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1960         .class          = &omap3xxx_gpio_hwmod_class,
1961         .dev_attr       = &gpio_dev_attr,
1962 };
1963
1964 /* gpio5 */
1965 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1966         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1967         { .irq = -1 }
1968 };
1969
1970 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1971         { .role = "dbclk", .clk = "gpio5_dbck", },
1972 };
1973
1974 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1975         &omap3xxx_l4_per__gpio5,
1976 };
1977
1978 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1979         .name           = "gpio5",
1980         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1981         .mpu_irqs       = omap3xxx_gpio5_irqs,
1982         .main_clk       = "gpio5_ick",
1983         .opt_clks       = gpio5_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1985         .prcm           = {
1986                 .omap2 = {
1987                         .prcm_reg_id = 1,
1988                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1989                         .module_offs = OMAP3430_PER_MOD,
1990                         .idlest_reg_id = 1,
1991                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1992                 },
1993         },
1994         .slaves         = omap3xxx_gpio5_slaves,
1995         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1996         .class          = &omap3xxx_gpio_hwmod_class,
1997         .dev_attr       = &gpio_dev_attr,
1998 };
1999
2000 /* gpio6 */
2001 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2002         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2003         { .irq = -1 }
2004 };
2005
2006 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2007         { .role = "dbclk", .clk = "gpio6_dbck", },
2008 };
2009
2010 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2011         &omap3xxx_l4_per__gpio6,
2012 };
2013
2014 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2015         .name           = "gpio6",
2016         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2017         .mpu_irqs       = omap3xxx_gpio6_irqs,
2018         .main_clk       = "gpio6_ick",
2019         .opt_clks       = gpio6_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2021         .prcm           = {
2022                 .omap2 = {
2023                         .prcm_reg_id = 1,
2024                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2025                         .module_offs = OMAP3430_PER_MOD,
2026                         .idlest_reg_id = 1,
2027                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2028                 },
2029         },
2030         .slaves         = omap3xxx_gpio6_slaves,
2031         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2032         .class          = &omap3xxx_gpio_hwmod_class,
2033         .dev_attr       = &gpio_dev_attr,
2034 };
2035
2036 /* dma_system -> L3 */
2037 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2038         .master         = &omap3xxx_dma_system_hwmod,
2039         .slave          = &omap3xxx_l3_main_hwmod,
2040         .clk            = "core_l3_ick",
2041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2042 };
2043
2044 /* dma attributes */
2045 static struct omap_dma_dev_attr dma_dev_attr = {
2046         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2047                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2048         .lch_count = 32,
2049 };
2050
2051 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2052         .rev_offs       = 0x0000,
2053         .sysc_offs      = 0x002c,
2054         .syss_offs      = 0x0028,
2055         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2056                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2057                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2058                            SYSS_HAS_RESET_STATUS),
2059         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2060                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2061         .sysc_fields    = &omap_hwmod_sysc_type1,
2062 };
2063
2064 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2065         .name = "dma",
2066         .sysc = &omap3xxx_dma_sysc,
2067 };
2068
2069 /* dma_system */
2070 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2071         {
2072                 .pa_start       = 0x48056000,
2073                 .pa_end         = 0x48056fff,
2074                 .flags          = ADDR_TYPE_RT
2075         },
2076         { }
2077 };
2078
2079 /* dma_system master ports */
2080 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2081         &omap3xxx_dma_system__l3,
2082 };
2083
2084 /* l4_cfg -> dma_system */
2085 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2086         .master         = &omap3xxx_l4_core_hwmod,
2087         .slave          = &omap3xxx_dma_system_hwmod,
2088         .clk            = "core_l4_ick",
2089         .addr           = omap3xxx_dma_system_addrs,
2090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2091 };
2092
2093 /* dma_system slave ports */
2094 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2095         &omap3xxx_l4_core__dma_system,
2096 };
2097
2098 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2099         .name           = "dma",
2100         .class          = &omap3xxx_dma_hwmod_class,
2101         .mpu_irqs       = omap2_dma_system_irqs,
2102         .main_clk       = "core_l3_ick",
2103         .prcm = {
2104                 .omap2 = {
2105                         .module_offs            = CORE_MOD,
2106                         .prcm_reg_id            = 1,
2107                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2108                         .idlest_reg_id          = 1,
2109                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2110                 },
2111         },
2112         .slaves         = omap3xxx_dma_system_slaves,
2113         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2114         .masters        = omap3xxx_dma_system_masters,
2115         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2116         .dev_attr       = &dma_dev_attr,
2117         .flags          = HWMOD_NO_IDLEST,
2118 };
2119
2120 /*
2121  * 'mcbsp' class
2122  * multi channel buffered serial port controller
2123  */
2124
2125 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2126         .sysc_offs      = 0x008c,
2127         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2128                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2129         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2130         .sysc_fields    = &omap_hwmod_sysc_type1,
2131         .clockact       = 0x2,
2132 };
2133
2134 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2135         .name = "mcbsp",
2136         .sysc = &omap3xxx_mcbsp_sysc,
2137         .rev  = MCBSP_CONFIG_TYPE3,
2138 };
2139
2140 /* mcbsp1 */
2141 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2142         { .name = "irq", .irq = 16 },
2143         { .name = "tx", .irq = 59 },
2144         { .name = "rx", .irq = 60 },
2145         { .irq = -1 }
2146 };
2147
2148 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2149         {
2150                 .name           = "mpu",
2151                 .pa_start       = 0x48074000,
2152                 .pa_end         = 0x480740ff,
2153                 .flags          = ADDR_TYPE_RT
2154         },
2155         { }
2156 };
2157
2158 /* l4_core -> mcbsp1 */
2159 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2160         .master         = &omap3xxx_l4_core_hwmod,
2161         .slave          = &omap3xxx_mcbsp1_hwmod,
2162         .clk            = "mcbsp1_ick",
2163         .addr           = omap3xxx_mcbsp1_addrs,
2164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2165 };
2166
2167 /* mcbsp1 slave ports */
2168 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2169         &omap3xxx_l4_core__mcbsp1,
2170 };
2171
2172 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2173         .name           = "mcbsp1",
2174         .class          = &omap3xxx_mcbsp_hwmod_class,
2175         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2176         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2177         .main_clk       = "mcbsp1_fck",
2178         .prcm           = {
2179                 .omap2 = {
2180                         .prcm_reg_id = 1,
2181                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2182                         .module_offs = CORE_MOD,
2183                         .idlest_reg_id = 1,
2184                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2185                 },
2186         },
2187         .slaves         = omap3xxx_mcbsp1_slaves,
2188         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2189 };
2190
2191 /* mcbsp2 */
2192 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2193         { .name = "irq", .irq = 17 },
2194         { .name = "tx", .irq = 62 },
2195         { .name = "rx", .irq = 63 },
2196         { .irq = -1 }
2197 };
2198
2199 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2200         {
2201                 .name           = "mpu",
2202                 .pa_start       = 0x49022000,
2203                 .pa_end         = 0x490220ff,
2204                 .flags          = ADDR_TYPE_RT
2205         },
2206         { }
2207 };
2208
2209 /* l4_per -> mcbsp2 */
2210 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2211         .master         = &omap3xxx_l4_per_hwmod,
2212         .slave          = &omap3xxx_mcbsp2_hwmod,
2213         .clk            = "mcbsp2_ick",
2214         .addr           = omap3xxx_mcbsp2_addrs,
2215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2216 };
2217
2218 /* mcbsp2 slave ports */
2219 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2220         &omap3xxx_l4_per__mcbsp2,
2221 };
2222
2223 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2224         .sidetone       = "mcbsp2_sidetone",
2225 };
2226
2227 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2228         .name           = "mcbsp2",
2229         .class          = &omap3xxx_mcbsp_hwmod_class,
2230         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2231         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2232         .main_clk       = "mcbsp2_fck",
2233         .prcm           = {
2234                 .omap2 = {
2235                         .prcm_reg_id = 1,
2236                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2237                         .module_offs = OMAP3430_PER_MOD,
2238                         .idlest_reg_id = 1,
2239                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2240                 },
2241         },
2242         .slaves         = omap3xxx_mcbsp2_slaves,
2243         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2244         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2245 };
2246
2247 /* mcbsp3 */
2248 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2249         { .name = "irq", .irq = 22 },
2250         { .name = "tx", .irq = 89 },
2251         { .name = "rx", .irq = 90 },
2252         { .irq = -1 }
2253 };
2254
2255 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2256         {
2257                 .name           = "mpu",
2258                 .pa_start       = 0x49024000,
2259                 .pa_end         = 0x490240ff,
2260                 .flags          = ADDR_TYPE_RT
2261         },
2262         { }
2263 };
2264
2265 /* l4_per -> mcbsp3 */
2266 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2267         .master         = &omap3xxx_l4_per_hwmod,
2268         .slave          = &omap3xxx_mcbsp3_hwmod,
2269         .clk            = "mcbsp3_ick",
2270         .addr           = omap3xxx_mcbsp3_addrs,
2271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2272 };
2273
2274 /* mcbsp3 slave ports */
2275 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2276         &omap3xxx_l4_per__mcbsp3,
2277 };
2278
2279 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2280         .sidetone       = "mcbsp3_sidetone",
2281 };
2282
2283 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2284         .name           = "mcbsp3",
2285         .class          = &omap3xxx_mcbsp_hwmod_class,
2286         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2287         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2288         .main_clk       = "mcbsp3_fck",
2289         .prcm           = {
2290                 .omap2 = {
2291                         .prcm_reg_id = 1,
2292                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2293                         .module_offs = OMAP3430_PER_MOD,
2294                         .idlest_reg_id = 1,
2295                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2296                 },
2297         },
2298         .slaves         = omap3xxx_mcbsp3_slaves,
2299         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2300         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2301 };
2302
2303 /* mcbsp4 */
2304 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2305         { .name = "irq", .irq = 23 },
2306         { .name = "tx", .irq = 54 },
2307         { .name = "rx", .irq = 55 },
2308         { .irq = -1 }
2309 };
2310
2311 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2312         { .name = "rx", .dma_req = 20 },
2313         { .name = "tx", .dma_req = 19 },
2314         { .dma_req = -1 }
2315 };
2316
2317 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2318         {
2319                 .name           = "mpu",
2320                 .pa_start       = 0x49026000,
2321                 .pa_end         = 0x490260ff,
2322                 .flags          = ADDR_TYPE_RT
2323         },
2324         { }
2325 };
2326
2327 /* l4_per -> mcbsp4 */
2328 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2329         .master         = &omap3xxx_l4_per_hwmod,
2330         .slave          = &omap3xxx_mcbsp4_hwmod,
2331         .clk            = "mcbsp4_ick",
2332         .addr           = omap3xxx_mcbsp4_addrs,
2333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2334 };
2335
2336 /* mcbsp4 slave ports */
2337 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2338         &omap3xxx_l4_per__mcbsp4,
2339 };
2340
2341 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2342         .name           = "mcbsp4",
2343         .class          = &omap3xxx_mcbsp_hwmod_class,
2344         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2345         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2346         .main_clk       = "mcbsp4_fck",
2347         .prcm           = {
2348                 .omap2 = {
2349                         .prcm_reg_id = 1,
2350                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2351                         .module_offs = OMAP3430_PER_MOD,
2352                         .idlest_reg_id = 1,
2353                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2354                 },
2355         },
2356         .slaves         = omap3xxx_mcbsp4_slaves,
2357         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2358 };
2359
2360 /* mcbsp5 */
2361 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2362         { .name = "irq", .irq = 27 },
2363         { .name = "tx", .irq = 81 },
2364         { .name = "rx", .irq = 82 },
2365         { .irq = -1 }
2366 };
2367
2368 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2369         { .name = "rx", .dma_req = 22 },
2370         { .name = "tx", .dma_req = 21 },
2371         { .dma_req = -1 }
2372 };
2373
2374 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2375         {
2376                 .name           = "mpu",
2377                 .pa_start       = 0x48096000,
2378                 .pa_end         = 0x480960ff,
2379                 .flags          = ADDR_TYPE_RT
2380         },
2381         { }
2382 };
2383
2384 /* l4_core -> mcbsp5 */
2385 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2386         .master         = &omap3xxx_l4_core_hwmod,
2387         .slave          = &omap3xxx_mcbsp5_hwmod,
2388         .clk            = "mcbsp5_ick",
2389         .addr           = omap3xxx_mcbsp5_addrs,
2390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2391 };
2392
2393 /* mcbsp5 slave ports */
2394 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2395         &omap3xxx_l4_core__mcbsp5,
2396 };
2397
2398 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2399         .name           = "mcbsp5",
2400         .class          = &omap3xxx_mcbsp_hwmod_class,
2401         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2402         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2403         .main_clk       = "mcbsp5_fck",
2404         .prcm           = {
2405                 .omap2 = {
2406                         .prcm_reg_id = 1,
2407                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2408                         .module_offs = CORE_MOD,
2409                         .idlest_reg_id = 1,
2410                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2411                 },
2412         },
2413         .slaves         = omap3xxx_mcbsp5_slaves,
2414         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2415 };
2416 /* 'mcbsp sidetone' class */
2417
2418 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2419         .sysc_offs      = 0x0010,
2420         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2421         .sysc_fields    = &omap_hwmod_sysc_type1,
2422 };
2423
2424 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2425         .name = "mcbsp_sidetone",
2426         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2427 };
2428
2429 /* mcbsp2_sidetone */
2430 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2431         { .name = "irq", .irq = 4 },
2432         { .irq = -1 }
2433 };
2434
2435 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2436         {
2437                 .name           = "sidetone",
2438                 .pa_start       = 0x49028000,
2439                 .pa_end         = 0x490280ff,
2440                 .flags          = ADDR_TYPE_RT
2441         },
2442         { }
2443 };
2444
2445 /* l4_per -> mcbsp2_sidetone */
2446 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2447         .master         = &omap3xxx_l4_per_hwmod,
2448         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2449         .clk            = "mcbsp2_ick",
2450         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2451         .user           = OCP_USER_MPU,
2452 };
2453
2454 /* mcbsp2_sidetone slave ports */
2455 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2456         &omap3xxx_l4_per__mcbsp2_sidetone,
2457 };
2458
2459 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2460         .name           = "mcbsp2_sidetone",
2461         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2462         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2463         .main_clk       = "mcbsp2_fck",
2464         .prcm           = {
2465                 .omap2 = {
2466                         .prcm_reg_id = 1,
2467                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2468                         .module_offs = OMAP3430_PER_MOD,
2469                         .idlest_reg_id = 1,
2470                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2471                 },
2472         },
2473         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2474         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2475 };
2476
2477 /* mcbsp3_sidetone */
2478 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2479         { .name = "irq", .irq = 5 },
2480         { .irq = -1 }
2481 };
2482
2483 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2484         {
2485                 .name           = "sidetone",
2486                 .pa_start       = 0x4902A000,
2487                 .pa_end         = 0x4902A0ff,
2488                 .flags          = ADDR_TYPE_RT
2489         },
2490         { }
2491 };
2492
2493 /* l4_per -> mcbsp3_sidetone */
2494 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2495         .master         = &omap3xxx_l4_per_hwmod,
2496         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2497         .clk            = "mcbsp3_ick",
2498         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2499         .user           = OCP_USER_MPU,
2500 };
2501
2502 /* mcbsp3_sidetone slave ports */
2503 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2504         &omap3xxx_l4_per__mcbsp3_sidetone,
2505 };
2506
2507 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2508         .name           = "mcbsp3_sidetone",
2509         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2510         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2511         .main_clk       = "mcbsp3_fck",
2512         .prcm           = {
2513                 .omap2 = {
2514                         .prcm_reg_id = 1,
2515                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2516                         .module_offs = OMAP3430_PER_MOD,
2517                         .idlest_reg_id = 1,
2518                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2519                 },
2520         },
2521         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2522         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2523 };
2524
2525
2526 /* SR common */
2527 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2528         .clkact_shift   = 20,
2529 };
2530
2531 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2532         .sysc_offs      = 0x24,
2533         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2534         .clockact       = CLOCKACT_TEST_ICLK,
2535         .sysc_fields    = &omap34xx_sr_sysc_fields,
2536 };
2537
2538 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2539         .name = "smartreflex",
2540         .sysc = &omap34xx_sr_sysc,
2541         .rev  = 1,
2542 };
2543
2544 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2545         .sidle_shift    = 24,
2546         .enwkup_shift   = 26
2547 };
2548
2549 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2550         .sysc_offs      = 0x38,
2551         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2552         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2553                         SYSC_NO_CACHE),
2554         .sysc_fields    = &omap36xx_sr_sysc_fields,
2555 };
2556
2557 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2558         .name = "smartreflex",
2559         .sysc = &omap36xx_sr_sysc,
2560         .rev  = 2,
2561 };
2562
2563 /* SR1 */
2564 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2565         &omap3_l4_core__sr1,
2566 };
2567
2568 static struct omap_hwmod omap34xx_sr1_hwmod = {
2569         .name           = "sr1_hwmod",
2570         .class          = &omap34xx_smartreflex_hwmod_class,
2571         .main_clk       = "sr1_fck",
2572         .vdd_name       = "mpu_iva",
2573         .prcm           = {
2574                 .omap2 = {
2575                         .prcm_reg_id = 1,
2576                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2577                         .module_offs = WKUP_MOD,
2578                         .idlest_reg_id = 1,
2579                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2580                 },
2581         },
2582         .slaves         = omap3_sr1_slaves,
2583         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2584         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2585 };
2586
2587 static struct omap_hwmod omap36xx_sr1_hwmod = {
2588         .name           = "sr1_hwmod",
2589         .class          = &omap36xx_smartreflex_hwmod_class,
2590         .main_clk       = "sr1_fck",
2591         .vdd_name       = "mpu_iva",
2592         .prcm           = {
2593                 .omap2 = {
2594                         .prcm_reg_id = 1,
2595                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2596                         .module_offs = WKUP_MOD,
2597                         .idlest_reg_id = 1,
2598                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2599                 },
2600         },
2601         .slaves         = omap3_sr1_slaves,
2602         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2603 };
2604
2605 /* SR2 */
2606 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2607         &omap3_l4_core__sr2,
2608 };
2609
2610 static struct omap_hwmod omap34xx_sr2_hwmod = {
2611         .name           = "sr2_hwmod",
2612         .class          = &omap34xx_smartreflex_hwmod_class,
2613         .main_clk       = "sr2_fck",
2614         .vdd_name       = "core",
2615         .prcm           = {
2616                 .omap2 = {
2617                         .prcm_reg_id = 1,
2618                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2619                         .module_offs = WKUP_MOD,
2620                         .idlest_reg_id = 1,
2621                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2622                 },
2623         },
2624         .slaves         = omap3_sr2_slaves,
2625         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2626         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2627 };
2628
2629 static struct omap_hwmod omap36xx_sr2_hwmod = {
2630         .name           = "sr2_hwmod",
2631         .class          = &omap36xx_smartreflex_hwmod_class,
2632         .main_clk       = "sr2_fck",
2633         .vdd_name       = "core",
2634         .prcm           = {
2635                 .omap2 = {
2636                         .prcm_reg_id = 1,
2637                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2638                         .module_offs = WKUP_MOD,
2639                         .idlest_reg_id = 1,
2640                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2641                 },
2642         },
2643         .slaves         = omap3_sr2_slaves,
2644         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2645 };
2646
2647 /*
2648  * 'mailbox' class
2649  * mailbox module allowing communication between the on-chip processors
2650  * using a queued mailbox-interrupt mechanism.
2651  */
2652
2653 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2654         .rev_offs       = 0x000,
2655         .sysc_offs      = 0x010,
2656         .syss_offs      = 0x014,
2657         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2658                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2659         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2660         .sysc_fields    = &omap_hwmod_sysc_type1,
2661 };
2662
2663 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2664         .name = "mailbox",
2665         .sysc = &omap3xxx_mailbox_sysc,
2666 };
2667
2668 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2669 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2670         { .irq = 26 },
2671         { .irq = -1 }
2672 };
2673
2674 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2675         {
2676                 .pa_start       = 0x48094000,
2677                 .pa_end         = 0x480941ff,
2678                 .flags          = ADDR_TYPE_RT,
2679         },
2680         { }
2681 };
2682
2683 /* l4_core -> mailbox */
2684 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2685         .master         = &omap3xxx_l4_core_hwmod,
2686         .slave          = &omap3xxx_mailbox_hwmod,
2687         .addr           = omap3xxx_mailbox_addrs,
2688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2689 };
2690
2691 /* mailbox slave ports */
2692 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2693         &omap3xxx_l4_core__mailbox,
2694 };
2695
2696 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2697         .name           = "mailbox",
2698         .class          = &omap3xxx_mailbox_hwmod_class,
2699         .mpu_irqs       = omap3xxx_mailbox_irqs,
2700         .main_clk       = "mailboxes_ick",
2701         .prcm           = {
2702                 .omap2 = {
2703                         .prcm_reg_id = 1,
2704                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2705                         .module_offs = CORE_MOD,
2706                         .idlest_reg_id = 1,
2707                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2708                 },
2709         },
2710         .slaves         = omap3xxx_mailbox_slaves,
2711         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2712 };
2713
2714 /* l4 core -> mcspi1 interface */
2715 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2716         .master         = &omap3xxx_l4_core_hwmod,
2717         .slave          = &omap34xx_mcspi1,
2718         .clk            = "mcspi1_ick",
2719         .addr           = omap2_mcspi1_addr_space,
2720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2721 };
2722
2723 /* l4 core -> mcspi2 interface */
2724 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2725         .master         = &omap3xxx_l4_core_hwmod,
2726         .slave          = &omap34xx_mcspi2,
2727         .clk            = "mcspi2_ick",
2728         .addr           = omap2_mcspi2_addr_space,
2729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2730 };
2731
2732 /* l4 core -> mcspi3 interface */
2733 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2734         .master         = &omap3xxx_l4_core_hwmod,
2735         .slave          = &omap34xx_mcspi3,
2736         .clk            = "mcspi3_ick",
2737         .addr           = omap2430_mcspi3_addr_space,
2738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2739 };
2740
2741 /* l4 core -> mcspi4 interface */
2742 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2743         {
2744                 .pa_start       = 0x480ba000,
2745                 .pa_end         = 0x480ba0ff,
2746                 .flags          = ADDR_TYPE_RT,
2747         },
2748         { }
2749 };
2750
2751 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2752         .master         = &omap3xxx_l4_core_hwmod,
2753         .slave          = &omap34xx_mcspi4,
2754         .clk            = "mcspi4_ick",
2755         .addr           = omap34xx_mcspi4_addr_space,
2756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2757 };
2758
2759 /*
2760  * 'mcspi' class
2761  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2762  * bus
2763  */
2764
2765 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2766         .rev_offs       = 0x0000,
2767         .sysc_offs      = 0x0010,
2768         .syss_offs      = 0x0014,
2769         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2770                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2771                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2773         .sysc_fields    = &omap_hwmod_sysc_type1,
2774 };
2775
2776 static struct omap_hwmod_class omap34xx_mcspi_class = {
2777         .name = "mcspi",
2778         .sysc = &omap34xx_mcspi_sysc,
2779         .rev = OMAP3_MCSPI_REV,
2780 };
2781
2782 /* mcspi1 */
2783 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2784         &omap34xx_l4_core__mcspi1,
2785 };
2786
2787 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2788         .num_chipselect = 4,
2789 };
2790
2791 static struct omap_hwmod omap34xx_mcspi1 = {
2792         .name           = "mcspi1",
2793         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2794         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2795         .main_clk       = "mcspi1_fck",
2796         .prcm           = {
2797                 .omap2 = {
2798                         .module_offs = CORE_MOD,
2799                         .prcm_reg_id = 1,
2800                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2801                         .idlest_reg_id = 1,
2802                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2803                 },
2804         },
2805         .slaves         = omap34xx_mcspi1_slaves,
2806         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2807         .class          = &omap34xx_mcspi_class,
2808         .dev_attr       = &omap_mcspi1_dev_attr,
2809 };
2810
2811 /* mcspi2 */
2812 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2813         &omap34xx_l4_core__mcspi2,
2814 };
2815
2816 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2817         .num_chipselect = 2,
2818 };
2819
2820 static struct omap_hwmod omap34xx_mcspi2 = {
2821         .name           = "mcspi2",
2822         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2823         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2824         .main_clk       = "mcspi2_fck",
2825         .prcm           = {
2826                 .omap2 = {
2827                         .module_offs = CORE_MOD,
2828                         .prcm_reg_id = 1,
2829                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2830                         .idlest_reg_id = 1,
2831                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2832                 },
2833         },
2834         .slaves         = omap34xx_mcspi2_slaves,
2835         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2836         .class          = &omap34xx_mcspi_class,
2837         .dev_attr       = &omap_mcspi2_dev_attr,
2838 };
2839
2840 /* mcspi3 */
2841 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2842         { .name = "irq", .irq = 91 }, /* 91 */
2843         { .irq = -1 }
2844 };
2845
2846 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2847         { .name = "tx0", .dma_req = 15 },
2848         { .name = "rx0", .dma_req = 16 },
2849         { .name = "tx1", .dma_req = 23 },
2850         { .name = "rx1", .dma_req = 24 },
2851         { .dma_req = -1 }
2852 };
2853
2854 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2855         &omap34xx_l4_core__mcspi3,
2856 };
2857
2858 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2859         .num_chipselect = 2,
2860 };
2861
2862 static struct omap_hwmod omap34xx_mcspi3 = {
2863         .name           = "mcspi3",
2864         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2865         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2866         .main_clk       = "mcspi3_fck",
2867         .prcm           = {
2868                 .omap2 = {
2869                         .module_offs = CORE_MOD,
2870                         .prcm_reg_id = 1,
2871                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2872                         .idlest_reg_id = 1,
2873                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2874                 },
2875         },
2876         .slaves         = omap34xx_mcspi3_slaves,
2877         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2878         .class          = &omap34xx_mcspi_class,
2879         .dev_attr       = &omap_mcspi3_dev_attr,
2880 };
2881
2882 /* SPI4 */
2883 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2884         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2885         { .irq = -1 }
2886 };
2887
2888 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2889         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2890         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2891         { .dma_req = -1 }
2892 };
2893
2894 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2895         &omap34xx_l4_core__mcspi4,
2896 };
2897
2898 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2899         .num_chipselect = 1,
2900 };
2901
2902 static struct omap_hwmod omap34xx_mcspi4 = {
2903         .name           = "mcspi4",
2904         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2905         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2906         .main_clk       = "mcspi4_fck",
2907         .prcm           = {
2908                 .omap2 = {
2909                         .module_offs = CORE_MOD,
2910                         .prcm_reg_id = 1,
2911                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2912                         .idlest_reg_id = 1,
2913                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2914                 },
2915         },
2916         .slaves         = omap34xx_mcspi4_slaves,
2917         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2918         .class          = &omap34xx_mcspi_class,
2919         .dev_attr       = &omap_mcspi4_dev_attr,
2920 };
2921
2922 /*
2923  * usbhsotg
2924  */
2925 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2926         .rev_offs       = 0x0400,
2927         .sysc_offs      = 0x0404,
2928         .syss_offs      = 0x0408,
2929         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2930                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2931                           SYSC_HAS_AUTOIDLE),
2932         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2933                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2934         .sysc_fields    = &omap_hwmod_sysc_type1,
2935 };
2936
2937 static struct omap_hwmod_class usbotg_class = {
2938         .name = "usbotg",
2939         .sysc = &omap3xxx_usbhsotg_sysc,
2940 };
2941 /* usb_otg_hs */
2942 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2943
2944         { .name = "mc", .irq = 92 },
2945         { .name = "dma", .irq = 93 },
2946         { .irq = -1 }
2947 };
2948
2949 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2950         .name           = "usb_otg_hs",
2951         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2952         .main_clk       = "hsotgusb_ick",
2953         .prcm           = {
2954                 .omap2 = {
2955                         .prcm_reg_id = 1,
2956                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2957                         .module_offs = CORE_MOD,
2958                         .idlest_reg_id = 1,
2959                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2960                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2961                 },
2962         },
2963         .masters        = omap3xxx_usbhsotg_masters,
2964         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2965         .slaves         = omap3xxx_usbhsotg_slaves,
2966         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2967         .class          = &usbotg_class,
2968
2969         /*
2970          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2971          * broken when autoidle is enabled
2972          * workaround is to disable the autoidle bit at module level.
2973          */
2974         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2975                                 | HWMOD_SWSUP_MSTANDBY,
2976 };
2977
2978 /* usb_otg_hs */
2979 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2980
2981         { .name = "mc", .irq = 71 },
2982         { .irq = -1 }
2983 };
2984
2985 static struct omap_hwmod_class am35xx_usbotg_class = {
2986         .name = "am35xx_usbotg",
2987         .sysc = NULL,
2988 };
2989
2990 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2991         .name           = "am35x_otg_hs",
2992         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
2993         .main_clk       = NULL,
2994         .prcm = {
2995                 .omap2 = {
2996                 },
2997         },
2998         .masters        = am35xx_usbhsotg_masters,
2999         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3000         .slaves         = am35xx_usbhsotg_slaves,
3001         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3002         .class          = &am35xx_usbotg_class,
3003 };
3004
3005 /* MMC/SD/SDIO common */
3006
3007 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3008         .rev_offs       = 0x1fc,
3009         .sysc_offs      = 0x10,
3010         .syss_offs      = 0x14