arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/smartreflex.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28
  29 #include "omap_hwmod_common_data.h"
  30
  31 #include "prm-regbits-34xx.h"
  32 #include "cm-regbits-34xx.h"
  33 #include "wd_timer.h"
  34 #include <mach/am35xx.h>
  35
  36 /*
  37  * OMAP3xxx hardware module integration data
  38  *
  39  * ALl of the data in this section should be autogeneratable from the
  40  * TI hardware database or other technical documentation.  Data that
  41  * is driver-specific or driver-kernel integration-specific belongs
  42  * elsewhere.
  43  */
  44
  45 static struct omap_hwmod omap3xxx_mpu_hwmod;
  46 static struct omap_hwmod omap3xxx_iva_hwmod;
  47 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  48 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  50 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  51 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  52 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  57 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  60 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  66 static struct omap_hwmod omap34xx_sr1_hwmod;
  67 static struct omap_hwmod omap34xx_sr2_hwmod;
  68 static struct omap_hwmod omap34xx_mcspi1;
  69 static struct omap_hwmod omap34xx_mcspi2;
  70 static struct omap_hwmod omap34xx_mcspi3;
  71 static struct omap_hwmod omap34xx_mcspi4;
  72 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  73
  74 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  75
  76 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  77 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  78 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  79 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  80 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  83
  84 /* L3 -> L4_CORE interface */
  85 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  86         .master = &omap3xxx_l3_main_hwmod,
  87         .slave  = &omap3xxx_l4_core_hwmod,
  88         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  89 };
  90
  91 /* L3 -> L4_PER interface */
  92 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  93         .master = &omap3xxx_l3_main_hwmod,
  94         .slave  = &omap3xxx_l4_per_hwmod,
  95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  96 };
  97
  98 /* MPU -> L3 interface */
  99 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 100         .master = &omap3xxx_mpu_hwmod,
 101         .slave  = &omap3xxx_l3_main_hwmod,
 102         .user   = OCP_USER_MPU,
 103 };
 104
 105 /* Slave interfaces on the L3 interconnect */
 106 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 107         &omap3xxx_mpu__l3_main,
 108 };
 109
 110 /* DSS -> l3 */
 111 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 112         .master         = &omap3xxx_dss_core_hwmod,
 113         .slave          = &omap3xxx_l3_main_hwmod,
 114         .fw = {
 115                 .omap2 = {
 116                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 117                         .flags  = OMAP_FIREWALL_L3,
 118                 }
 119         },
 120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 121 };
 122
 123 /* Master interfaces on the L3 interconnect */
 124 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 125         &omap3xxx_l3_main__l4_core,
 126         &omap3xxx_l3_main__l4_per,
 127 };
 128
 129 /* L3 */
 130 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 131         .name           = "l3_main",
 132         .class          = &l3_hwmod_class,
 133         .masters        = omap3xxx_l3_main_masters,
 134         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 135         .slaves         = omap3xxx_l3_main_slaves,
 136         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 137         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 138         .flags          = HWMOD_NO_IDLEST,
 139 };
 140
 141 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 142 static struct omap_hwmod omap3xxx_uart1_hwmod;
 143 static struct omap_hwmod omap3xxx_uart2_hwmod;
 144 static struct omap_hwmod omap3xxx_uart3_hwmod;
 145 static struct omap_hwmod omap3xxx_uart4_hwmod;
 146 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 147
 148 /* l3_core -> usbhsotg interface */
 149 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 150         .master         = &omap3xxx_usbhsotg_hwmod,
 151         .slave          = &omap3xxx_l3_main_hwmod,
 152         .clk            = "core_l3_ick",
 153         .user           = OCP_USER_MPU,
 154 };
 155
 156 /* l3_core -> am35xx_usbhsotg interface */
 157 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 158         .master         = &am35xx_usbhsotg_hwmod,
 159         .slave          = &omap3xxx_l3_main_hwmod,
 160         .clk            = "core_l3_ick",
 161         .user           = OCP_USER_MPU,
 162 };
 163 /* L4_CORE -> L4_WKUP interface */
 164 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 165         .master = &omap3xxx_l4_core_hwmod,
 166         .slave  = &omap3xxx_l4_wkup_hwmod,
 167         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 168 };
 169
 170 /* L4 CORE -> UART1 interface */
 171 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 172         {
 173                 .pa_start       = OMAP3_UART1_BASE,
 174                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 175                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 176         },
 177 };
 178
 179 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 180         .master         = &omap3xxx_l4_core_hwmod,
 181         .slave          = &omap3xxx_uart1_hwmod,
 182         .clk            = "uart1_ick",
 183         .addr           = omap3xxx_uart1_addr_space,
 184         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 186 };
 187
 188 /* L4 CORE -> UART2 interface */
 189 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 190         {
 191                 .pa_start       = OMAP3_UART2_BASE,
 192                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 193                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 194         },
 195 };
 196
 197 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 198         .master         = &omap3xxx_l4_core_hwmod,
 199         .slave          = &omap3xxx_uart2_hwmod,
 200         .clk            = "uart2_ick",
 201         .addr           = omap3xxx_uart2_addr_space,
 202         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 204 };
 205
 206 /* L4 PER -> UART3 interface */
 207 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 208         {
 209                 .pa_start       = OMAP3_UART3_BASE,
 210                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 211                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 212         },
 213 };
 214
 215 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 216         .master         = &omap3xxx_l4_per_hwmod,
 217         .slave          = &omap3xxx_uart3_hwmod,
 218         .clk            = "uart3_ick",
 219         .addr           = omap3xxx_uart3_addr_space,
 220         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 222 };
 223
 224 /* L4 PER -> UART4 interface */
 225 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 226         {
 227                 .pa_start       = OMAP3_UART4_BASE,
 228                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 229                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 230         },
 231 };
 232
 233 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 234         .master         = &omap3xxx_l4_per_hwmod,
 235         .slave          = &omap3xxx_uart4_hwmod,
 236         .clk            = "uart4_ick",
 237         .addr           = omap3xxx_uart4_addr_space,
 238         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 240 };
 241
 242 /* I2C IP block address space length (in bytes) */
 243 #define OMAP2_I2C_AS_LEN                128
 244
 245 /* L4 CORE -> I2C1 interface */
 246 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 247         {
 248                 .pa_start       = 0x48070000,
 249                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 250                 .flags          = ADDR_TYPE_RT,
 251         },
 252 };
 253
 254 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 255         .master         = &omap3xxx_l4_core_hwmod,
 256         .slave          = &omap3xxx_i2c1_hwmod,
 257         .clk            = "i2c1_ick",
 258         .addr           = omap3xxx_i2c1_addr_space,
 259         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
 260         .fw = {
 261                 .omap2 = {
 262                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 263                         .l4_prot_group = 7,
 264                         .flags  = OMAP_FIREWALL_L4,
 265                 }
 266         },
 267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 268 };
 269
 270 /* L4 CORE -> I2C2 interface */
 271 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 272         {
 273                 .pa_start       = 0x48072000,
 274                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 275                 .flags          = ADDR_TYPE_RT,
 276         },
 277 };
 278
 279 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 280         .master         = &omap3xxx_l4_core_hwmod,
 281         .slave          = &omap3xxx_i2c2_hwmod,
 282         .clk            = "i2c2_ick",
 283         .addr           = omap3xxx_i2c2_addr_space,
 284         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
 285         .fw = {
 286                 .omap2 = {
 287                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 288                         .l4_prot_group = 7,
 289                         .flags = OMAP_FIREWALL_L4,
 290                 }
 291         },
 292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 293 };
 294
 295 /* L4 CORE -> I2C3 interface */
 296 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 297         {
 298                 .pa_start       = 0x48060000,
 299                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 300                 .flags          = ADDR_TYPE_RT,
 301         },
 302 };
 303
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c3_hwmod,
 307         .clk            = "i2c3_ick",
 308         .addr           = omap3xxx_i2c3_addr_space,
 309         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
 310         .fw = {
 311                 .omap2 = {
 312                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 313                         .l4_prot_group = 7,
 314                         .flags = OMAP_FIREWALL_L4,
 315                 }
 316         },
 317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 318 };
 319
 320 /* L4 CORE -> SR1 interface */
 321 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 322         {
 323                 .pa_start       = OMAP34XX_SR1_BASE,
 324                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 325                 .flags          = ADDR_TYPE_RT,
 326         },
 327 };
 328
 329 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 330         .master         = &omap3xxx_l4_core_hwmod,
 331         .slave          = &omap34xx_sr1_hwmod,
 332         .clk            = "sr_l4_ick",
 333         .addr           = omap3_sr1_addr_space,
 334         .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
 335         .user           = OCP_USER_MPU,
 336 };
 337
 338 /* L4 CORE -> SR1 interface */
 339 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 340         {
 341                 .pa_start       = OMAP34XX_SR2_BASE,
 342                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 343                 .flags          = ADDR_TYPE_RT,
 344         },
 345 };
 346
 347 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 348         .master         = &omap3xxx_l4_core_hwmod,
 349         .slave          = &omap34xx_sr2_hwmod,
 350         .clk            = "sr_l4_ick",
 351         .addr           = omap3_sr2_addr_space,
 352         .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
 353         .user           = OCP_USER_MPU,
 354 };
 355
 356 /*
 357 * usbhsotg interface data
 358 */
 359
 360 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 361         {
 362                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 363                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 364                 .flags          = ADDR_TYPE_RT
 365         },
 366 };
 367
 368 /* l4_core -> usbhsotg  */
 369 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 370         .master         = &omap3xxx_l4_core_hwmod,
 371         .slave          = &omap3xxx_usbhsotg_hwmod,
 372         .clk            = "l4_ick",
 373         .addr           = omap3xxx_usbhsotg_addrs,
 374         .addr_cnt       = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 379         &omap3xxx_usbhsotg__l3,
 380 };
 381
 382 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 383         &omap3xxx_l4_core__usbhsotg,
 384 };
 385
 386 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 387         {
 388                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 389                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 390                 .flags          = ADDR_TYPE_RT
 391         },
 392 };
 393
 394 /* l4_core -> usbhsotg  */
 395 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 396         .master         = &omap3xxx_l4_core_hwmod,
 397         .slave          = &am35xx_usbhsotg_hwmod,
 398         .clk            = "l4_ick",
 399         .addr           = am35xx_usbhsotg_addrs,
 400         .addr_cnt       = ARRAY_SIZE(am35xx_usbhsotg_addrs),
 401         .user           = OCP_USER_MPU,
 402 };
 403
 404 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 405         &am35xx_usbhsotg__l3,
 406 };
 407
 408 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 409         &am35xx_l4_core__usbhsotg,
 410 };
 411 /* Slave interfaces on the L4_CORE interconnect */
 412 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 413         &omap3xxx_l3_main__l4_core,
 414         &omap3_l4_core__sr1,
 415         &omap3_l4_core__sr2,
 416 };
 417
 418 /* Master interfaces on the L4_CORE interconnect */
 419 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 420         &omap3xxx_l4_core__l4_wkup,
 421         &omap3_l4_core__uart1,
 422         &omap3_l4_core__uart2,
 423         &omap3_l4_core__i2c1,
 424         &omap3_l4_core__i2c2,
 425         &omap3_l4_core__i2c3,
 426 };
 427
 428 /* L4 CORE */
 429 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 430         .name           = "l4_core",
 431         .class          = &l4_hwmod_class,
 432         .masters        = omap3xxx_l4_core_masters,
 433         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
 434         .slaves         = omap3xxx_l4_core_slaves,
 435         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 436         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 437         .flags          = HWMOD_NO_IDLEST,
 438 };
 439
 440 /* Slave interfaces on the L4_PER interconnect */
 441 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 442         &omap3xxx_l3_main__l4_per,
 443 };
 444
 445 /* Master interfaces on the L4_PER interconnect */
 446 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 447         &omap3_l4_per__uart3,
 448         &omap3_l4_per__uart4,
 449 };
 450
 451 /* L4 PER */
 452 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 453         .name           = "l4_per",
 454         .class          = &l4_hwmod_class,
 455         .masters        = omap3xxx_l4_per_masters,
 456         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
 457         .slaves         = omap3xxx_l4_per_slaves,
 458         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 459         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 460         .flags          = HWMOD_NO_IDLEST,
 461 };
 462
 463 /* Slave interfaces on the L4_WKUP interconnect */
 464 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 465         &omap3xxx_l4_core__l4_wkup,
 466 };
 467
 468 /* Master interfaces on the L4_WKUP interconnect */
 469 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 470 };
 471
 472 /* L4 WKUP */
 473 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 474         .name           = "l4_wkup",
 475         .class          = &l4_hwmod_class,
 476         .masters        = omap3xxx_l4_wkup_masters,
 477         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
 478         .slaves         = omap3xxx_l4_wkup_slaves,
 479         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 480         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 481         .flags          = HWMOD_NO_IDLEST,
 482 };
 483
 484 /* Master interfaces on the MPU device */
 485 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 486         &omap3xxx_mpu__l3_main,
 487 };
 488
 489 /* MPU */
 490 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 491         .name           = "mpu",
 492         .class          = &mpu_hwmod_class,
 493         .main_clk       = "arm_fck",
 494         .masters        = omap3xxx_mpu_masters,
 495         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 496         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 497 };
 498
 499 /*
 500  * IVA2_2 interface data
 501  */
 502
 503 /* IVA2 <- L3 interface */
 504 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 505         .master         = &omap3xxx_l3_main_hwmod,
 506         .slave          = &omap3xxx_iva_hwmod,
 507         .clk            = "iva2_ck",
 508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 509 };
 510
 511 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 512         &omap3xxx_l3__iva,
 513 };
 514
 515 /*
 516  * IVA2 (IVA2)
 517  */
 518
 519 static struct omap_hwmod omap3xxx_iva_hwmod = {
 520         .name           = "iva",
 521         .class          = &iva_hwmod_class,
 522         .masters        = omap3xxx_iva_masters,
 523         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 525 };
 526
 527 /* l4_wkup -> wd_timer2 */
 528 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 529         {
 530                 .pa_start       = 0x48314000,
 531                 .pa_end         = 0x4831407f,
 532                 .flags          = ADDR_TYPE_RT
 533         },
 534 };
 535
 536 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 537         .master         = &omap3xxx_l4_wkup_hwmod,
 538         .slave          = &omap3xxx_wd_timer2_hwmod,
 539         .clk            = "wdt2_ick",
 540         .addr           = omap3xxx_wd_timer2_addrs,
 541         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 543 };
 544
 545 /*
 546  * 'wd_timer' class
 547  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 548  * overflow condition
 549  */
 550
 551 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 556                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 557                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 558         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 559         .sysc_fields    = &omap_hwmod_sysc_type1,
 560 };
 561
 562 /* I2C common */
 563 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 564         .rev_offs       = 0x00,
 565         .sysc_offs      = 0x20,
 566         .syss_offs      = 0x10,
 567         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 568                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 569                            SYSC_HAS_AUTOIDLE),
 570         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 571         .sysc_fields    = &omap_hwmod_sysc_type1,
 572 };
 573
 574 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 575         .name           = "wd_timer",
 576         .sysc           = &omap3xxx_wd_timer_sysc,
 577         .pre_shutdown   = &omap2_wd_timer_disable
 578 };
 579
 580 /* wd_timer2 */
 581 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 582         &omap3xxx_l4_wkup__wd_timer2,
 583 };
 584
 585 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 586         .name           = "wd_timer2",
 587         .class          = &omap3xxx_wd_timer_hwmod_class,
 588         .main_clk       = "wdt2_fck",
 589         .prcm           = {
 590                 .omap2 = {
 591                         .prcm_reg_id = 1,
 592                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 593                         .module_offs = WKUP_MOD,
 594                         .idlest_reg_id = 1,
 595                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 596                 },
 597         },
 598         .slaves         = omap3xxx_wd_timer2_slaves,
 599         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 600         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 601 };
 602
 603 /* UART common */
 604
 605 static struct omap_hwmod_class_sysconfig uart_sysc = {
 606         .rev_offs       = 0x50,
 607         .sysc_offs      = 0x54,
 608         .syss_offs      = 0x58,
 609         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 610                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 611                            SYSC_HAS_AUTOIDLE),
 612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 613         .sysc_fields    = &omap_hwmod_sysc_type1,
 614 };
 615
 616 static struct omap_hwmod_class uart_class = {
 617         .name = "uart",
 618         .sysc = &uart_sysc,
 619 };
 620
 621 /* UART1 */
 622
 623 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 624         { .irq = INT_24XX_UART1_IRQ, },
 625 };
 626
 627 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 628         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 629         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 630 };
 631
 632 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 633         &omap3_l4_core__uart1,
 634 };
 635
 636 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 637         .name           = "uart1",
 638         .mpu_irqs       = uart1_mpu_irqs,
 639         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 640         .sdma_reqs      = uart1_sdma_reqs,
 641         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 642         .main_clk       = "uart1_fck",
 643         .prcm           = {
 644                 .omap2 = {
 645                         .module_offs = CORE_MOD,
 646                         .prcm_reg_id = 1,
 647                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 648                         .idlest_reg_id = 1,
 649                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 650                 },
 651         },
 652         .slaves         = omap3xxx_uart1_slaves,
 653         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 654         .class          = &uart_class,
 655         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 656 };
 657
 658 /* UART2 */
 659
 660 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 661         { .irq = INT_24XX_UART2_IRQ, },
 662 };
 663
 664 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 665         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 666         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 667 };
 668
 669 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 670         &omap3_l4_core__uart2,
 671 };
 672
 673 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 674         .name           = "uart2",
 675         .mpu_irqs       = uart2_mpu_irqs,
 676         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 677         .sdma_reqs      = uart2_sdma_reqs,
 678         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 679         .main_clk       = "uart2_fck",
 680         .prcm           = {
 681                 .omap2 = {
 682                         .module_offs = CORE_MOD,
 683                         .prcm_reg_id = 1,
 684                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 685                         .idlest_reg_id = 1,
 686                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 687                 },
 688         },
 689         .slaves         = omap3xxx_uart2_slaves,
 690         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 691         .class          = &uart_class,
 692         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 693 };
 694
 695 /* UART3 */
 696
 697 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 698         { .irq = INT_24XX_UART3_IRQ, },
 699 };
 700
 701 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 702         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 703         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 704 };
 705
 706 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 707         &omap3_l4_per__uart3,
 708 };
 709
 710 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 711         .name           = "uart3",
 712         .mpu_irqs       = uart3_mpu_irqs,
 713         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 714         .sdma_reqs      = uart3_sdma_reqs,
 715         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 716         .main_clk       = "uart3_fck",
 717         .prcm           = {
 718                 .omap2 = {
 719                         .module_offs = OMAP3430_PER_MOD,
 720                         .prcm_reg_id = 1,
 721                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 722                         .idlest_reg_id = 1,
 723                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 724                 },
 725         },
 726         .slaves         = omap3xxx_uart3_slaves,
 727         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 728         .class          = &uart_class,
 729         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 730 };
 731
 732 /* UART4 */
 733
 734 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 735         { .irq = INT_36XX_UART4_IRQ, },
 736 };
 737
 738 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 739         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 740         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 741 };
 742
 743 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 744         &omap3_l4_per__uart4,
 745 };
 746
 747 static struct omap_hwmod omap3xxx_uart4_hwmod = {
 748         .name           = "uart4",
 749         .mpu_irqs       = uart4_mpu_irqs,
 750         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 751         .sdma_reqs      = uart4_sdma_reqs,
 752         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 753         .main_clk       = "uart4_fck",
 754         .prcm           = {
 755                 .omap2 = {
 756                         .module_offs = OMAP3430_PER_MOD,
 757                         .prcm_reg_id = 1,
 758                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 759                         .idlest_reg_id = 1,
 760                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 761                 },
 762         },
 763         .slaves         = omap3xxx_uart4_slaves,
 764         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 765         .class          = &uart_class,
 766         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 767 };
 768
 769 static struct omap_hwmod_class i2c_class = {
 770         .name = "i2c",
 771         .sysc = &i2c_sysc,
 772 };
 773
 774 /*
 775  * 'dss' class
 776  * display sub-system
 777  */
 778
 779 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
 780         .rev_offs       = 0x0000,
 781         .sysc_offs      = 0x0010,
 782         .syss_offs      = 0x0014,
 783         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 784         .sysc_fields    = &omap_hwmod_sysc_type1,
 785 };
 786
 787 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
 788         .name = "dss",
 789         .sysc = &omap3xxx_dss_sysc,
 790 };
 791
 792 /* dss */
 793 static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = {
 794         { .irq = 25 },
 795 };
 796
 797 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 798         { .name = "dispc", .dma_req = 5 },
 799         { .name = "dsi1", .dma_req = 74 },
 800 };
 801
 802 /* dss */
 803 /* dss master ports */
 804 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
 805         &omap3xxx_dss__l3,
 806 };
 807
 808 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
 809         {
 810                 .pa_start       = 0x48050000,
 811                 .pa_end         = 0x480503FF,
 812                 .flags          = ADDR_TYPE_RT
 813         },
 814 };
 815
 816 /* l4_core -> dss */
 817 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
 818         .master         = &omap3xxx_l4_core_hwmod,
 819         .slave          = &omap3430es1_dss_core_hwmod,
 820         .clk            = "dss_ick",
 821         .addr           = omap3xxx_dss_addrs,
 822         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 823         .fw = {
 824                 .omap2 = {
 825                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
 826                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 827                         .flags  = OMAP_FIREWALL_L4,
 828                 }
 829         },
 830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 831 };
 832
 833 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
 834         .master         = &omap3xxx_l4_core_hwmod,
 835         .slave          = &omap3xxx_dss_core_hwmod,
 836         .clk            = "dss_ick",
 837         .addr           = omap3xxx_dss_addrs,
 838         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_addrs),
 839         .fw = {
 840                 .omap2 = {
 841                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
 842                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 843                         .flags  = OMAP_FIREWALL_L4,
 844                 }
 845         },
 846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 847 };
 848
 849 /* dss slave ports */
 850 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
 851         &omap3430es1_l4_core__dss,
 852 };
 853
 854 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
 855         &omap3xxx_l4_core__dss,
 856 };
 857
 858 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 859         { .role = "tv_clk", .clk = "dss_tv_fck" },
 860         { .role = "dssclk", .clk = "dss_96m_fck" },
 861         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 862 };
 863
 864 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 865         .name           = "dss_core",
 866         .class          = &omap3xxx_dss_hwmod_class,
 867         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 868         .mpu_irqs       = omap3xxx_dss_irqs,
 869         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 870         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 871         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 872
 873         .prcm           = {
 874                 .omap2 = {
 875                         .prcm_reg_id = 1,
 876                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 877                         .module_offs = OMAP3430_DSS_MOD,
 878                         .idlest_reg_id = 1,
 879                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 880                 },
 881         },
 882         .opt_clks       = dss_opt_clks,
 883         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 884         .slaves         = omap3430es1_dss_slaves,
 885         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
 886         .masters        = omap3xxx_dss_masters,
 887         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 888         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 889         .flags          = HWMOD_NO_IDLEST,
 890 };
 891
 892 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 893         .name           = "dss_core",
 894         .class          = &omap3xxx_dss_hwmod_class,
 895         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 896         .mpu_irqs       = omap3xxx_dss_irqs,
 897         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dss_irqs),
 898         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 899         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
 900
 901         .prcm           = {
 902                 .omap2 = {
 903                         .prcm_reg_id = 1,
 904                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 905                         .module_offs = OMAP3430_DSS_MOD,
 906                         .idlest_reg_id = 1,
 907                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 908                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 909                 },
 910         },
 911         .opt_clks       = dss_opt_clks,
 912         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 913         .slaves         = omap3xxx_dss_slaves,
 914         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
 915         .masters        = omap3xxx_dss_masters,
 916         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 917         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
 918                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
 919 };
 920
 921 /*
 922  * 'dispc' class
 923  * display controller
 924  */
 925
 926 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
 927         .rev_offs       = 0x0000,
 928         .sysc_offs      = 0x0010,
 929         .syss_offs      = 0x0014,
 930         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 931                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
 932                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 933         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 934                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 935         .sysc_fields    = &omap_hwmod_sysc_type1,
 936 };
 937
 938 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
 939         .name = "dispc",
 940         .sysc = &omap3xxx_dispc_sysc,
 941 };
 942
 943 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
 944         {
 945                 .pa_start       = 0x48050400,
 946                 .pa_end         = 0x480507FF,
 947                 .flags          = ADDR_TYPE_RT
 948         },
 949 };
 950
 951 /* l4_core -> dss_dispc */
 952 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
 953         .master         = &omap3xxx_l4_core_hwmod,
 954         .slave          = &omap3xxx_dss_dispc_hwmod,
 955         .clk            = "dss_ick",
 956         .addr           = omap3xxx_dss_dispc_addrs,
 957         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
 958         .fw = {
 959                 .omap2 = {
 960                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
 961                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
 962                         .flags  = OMAP_FIREWALL_L4,
 963                 }
 964         },
 965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 966 };
 967
 968 /* dss_dispc slave ports */
 969 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
 970         &omap3xxx_l4_core__dss_dispc,
 971 };
 972
 973 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 974         .name           = "dss_dispc",
 975         .class          = &omap3xxx_dispc_hwmod_class,
 976         .main_clk       = "dss1_alwon_fck",
 977         .prcm           = {
 978                 .omap2 = {
 979                         .prcm_reg_id = 1,
 980                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 981                         .module_offs = OMAP3430_DSS_MOD,
 982                 },
 983         },
 984         .slaves         = omap3xxx_dss_dispc_slaves,
 985         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
 986         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 987                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
 988                                 CHIP_GE_OMAP3630ES1_1),
 989         .flags          = HWMOD_NO_IDLEST,
 990 };
 991
 992 /*
 993  * 'dsi' class
 994  * display serial interface controller
 995  */
 996
 997 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 998         .name = "dsi",
 999 };
1000
1001 /* dss_dsi1 */
1002 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1003         {
1004                 .pa_start       = 0x4804FC00,
1005                 .pa_end         = 0x4804FFFF,
1006                 .flags          = ADDR_TYPE_RT
1007         },
1008 };
1009
1010 /* l4_core -> dss_dsi1 */
1011 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1012         .master         = &omap3xxx_l4_core_hwmod,
1013         .slave          = &omap3xxx_dss_dsi1_hwmod,
1014         .addr           = omap3xxx_dss_dsi1_addrs,
1015         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1016         .fw = {
1017                 .omap2 = {
1018                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1019                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1020                         .flags  = OMAP_FIREWALL_L4,
1021                 }
1022         },
1023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1024 };
1025
1026 /* dss_dsi1 slave ports */
1027 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1028         &omap3xxx_l4_core__dss_dsi1,
1029 };
1030
1031 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1032         .name           = "dss_dsi1",
1033         .class          = &omap3xxx_dsi_hwmod_class,
1034         .main_clk       = "dss1_alwon_fck",
1035         .prcm           = {
1036                 .omap2 = {
1037                         .prcm_reg_id = 1,
1038                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1039                         .module_offs = OMAP3430_DSS_MOD,
1040                 },
1041         },
1042         .slaves         = omap3xxx_dss_dsi1_slaves,
1043         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1044         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1045                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1046                                 CHIP_GE_OMAP3630ES1_1),
1047         .flags          = HWMOD_NO_IDLEST,
1048 };
1049
1050 /*
1051  * 'rfbi' class
1052  * remote frame buffer interface
1053  */
1054
1055 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1056         .rev_offs       = 0x0000,
1057         .sysc_offs      = 0x0010,
1058         .syss_offs      = 0x0014,
1059         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1060                            SYSC_HAS_AUTOIDLE),
1061         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1062         .sysc_fields    = &omap_hwmod_sysc_type1,
1063 };
1064
1065 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1066         .name = "rfbi",
1067         .sysc = &omap3xxx_rfbi_sysc,
1068 };
1069
1070 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1071         {
1072                 .pa_start       = 0x48050800,
1073                 .pa_end         = 0x48050BFF,
1074                 .flags          = ADDR_TYPE_RT
1075         },
1076 };
1077
1078 /* l4_core -> dss_rfbi */
1079 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1080         .master         = &omap3xxx_l4_core_hwmod,
1081         .slave          = &omap3xxx_dss_rfbi_hwmod,
1082         .clk            = "dss_ick",
1083         .addr           = omap3xxx_dss_rfbi_addrs,
1084         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1085         .fw = {
1086                 .omap2 = {
1087                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1088                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1089                         .flags  = OMAP_FIREWALL_L4,
1090                 }
1091         },
1092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1093 };
1094
1095 /* dss_rfbi slave ports */
1096 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1097         &omap3xxx_l4_core__dss_rfbi,
1098 };
1099
1100 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1101         .name           = "dss_rfbi",
1102         .class          = &omap3xxx_rfbi_hwmod_class,
1103         .main_clk       = "dss1_alwon_fck",
1104         .prcm           = {
1105                 .omap2 = {
1106                         .prcm_reg_id = 1,
1107                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1108                         .module_offs = OMAP3430_DSS_MOD,
1109                 },
1110         },
1111         .slaves         = omap3xxx_dss_rfbi_slaves,
1112         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1113         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1114                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1115                                 CHIP_GE_OMAP3630ES1_1),
1116         .flags          = HWMOD_NO_IDLEST,
1117 };
1118
1119 /*
1120  * 'venc' class
1121  * video encoder
1122  */
1123
1124 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1125         .name = "venc",
1126 };
1127
1128 /* dss_venc */
1129 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1130         {
1131                 .pa_start       = 0x48050C00,
1132                 .pa_end         = 0x48050FFF,
1133                 .flags          = ADDR_TYPE_RT
1134         },
1135 };
1136
1137 /* l4_core -> dss_venc */
1138 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1139         .master         = &omap3xxx_l4_core_hwmod,
1140         .slave          = &omap3xxx_dss_venc_hwmod,
1141         .clk            = "dss_tv_fck",
1142         .addr           = omap3xxx_dss_venc_addrs,
1143         .addr_cnt       = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1144         .fw = {
1145                 .omap2 = {
1146                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1147                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1148                         .flags  = OMAP_FIREWALL_L4,
1149                 }
1150         },
1151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1152 };
1153
1154 /* dss_venc slave ports */
1155 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1156         &omap3xxx_l4_core__dss_venc,
1157 };
1158
1159 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1160         .name           = "dss_venc",
1161         .class          = &omap3xxx_venc_hwmod_class,
1162         .main_clk       = "dss1_alwon_fck",
1163         .prcm           = {
1164                 .omap2 = {
1165                         .prcm_reg_id = 1,
1166                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1167                         .module_offs = OMAP3430_DSS_MOD,
1168                 },
1169         },
1170         .slaves         = omap3xxx_dss_venc_slaves,
1171         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1172         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1173                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1174                                 CHIP_GE_OMAP3630ES1_1),
1175         .flags          = HWMOD_NO_IDLEST,
1176 };
1177
1178 /* I2C1 */
1179
1180 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1181         .fifo_depth     = 8, /* bytes */
1182 };
1183
1184 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1185         { .irq = INT_24XX_I2C1_IRQ, },
1186 };
1187
1188 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1189         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1190         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1191 };
1192
1193 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1194         &omap3_l4_core__i2c1,
1195 };
1196
1197 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1198         .name           = "i2c1",
1199         .mpu_irqs       = i2c1_mpu_irqs,
1200         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1201         .sdma_reqs      = i2c1_sdma_reqs,
1202         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1203         .main_clk       = "i2c1_fck",
1204         .prcm           = {
1205                 .omap2 = {
1206                         .module_offs = CORE_MOD,
1207                         .prcm_reg_id = 1,
1208                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1209                         .idlest_reg_id = 1,
1210                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1211                 },
1212         },
1213         .slaves         = omap3xxx_i2c1_slaves,
1214         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1215         .class          = &i2c_class,
1216         .dev_attr       = &i2c1_dev_attr,
1217         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1218 };
1219
1220 /* I2C2 */
1221
1222 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1223         .fifo_depth     = 8, /* bytes */
1224 };
1225
1226 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1227         { .irq = INT_24XX_I2C2_IRQ, },
1228 };
1229
1230 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1231         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1232         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1233 };
1234
1235 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1236         &omap3_l4_core__i2c2,
1237 };
1238
1239 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1240         .name           = "i2c2",
1241         .mpu_irqs       = i2c2_mpu_irqs,
1242         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1243         .sdma_reqs      = i2c2_sdma_reqs,
1244         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1245         .main_clk       = "i2c2_fck",
1246         .prcm           = {
1247                 .omap2 = {
1248                         .module_offs = CORE_MOD,
1249                         .prcm_reg_id = 1,
1250                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1251                         .idlest_reg_id = 1,
1252                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1253                 },
1254         },
1255         .slaves         = omap3xxx_i2c2_slaves,
1256         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1257         .class          = &i2c_class,
1258         .dev_attr       = &i2c2_dev_attr,
1259         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1260 };
1261
1262 /* I2C3 */
1263
1264 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1265         .fifo_depth     = 64, /* bytes */
1266 };
1267
1268 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1269         { .irq = INT_34XX_I2C3_IRQ, },
1270 };
1271
1272 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1273         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1274         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1275 };
1276
1277 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1278         &omap3_l4_core__i2c3,
1279 };
1280
1281 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1282         .name           = "i2c3",
1283         .mpu_irqs       = i2c3_mpu_irqs,
1284         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
1285         .sdma_reqs      = i2c3_sdma_reqs,
1286         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1287         .main_clk       = "i2c3_fck",
1288         .prcm           = {
1289                 .omap2 = {
1290                         .module_offs = CORE_MOD,
1291                         .prcm_reg_id = 1,
1292                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1293                         .idlest_reg_id = 1,
1294                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1295                 },
1296         },
1297         .slaves         = omap3xxx_i2c3_slaves,
1298         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1299         .class          = &i2c_class,
1300         .dev_attr       = &i2c3_dev_attr,
1301         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1302 };
1303
1304 /* l4_wkup -> gpio1 */
1305 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1306         {
1307                 .pa_start       = 0x48310000,
1308                 .pa_end         = 0x483101ff,
1309                 .flags          = ADDR_TYPE_RT
1310         },
1311 };
1312
1313 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1314         .master         = &omap3xxx_l4_wkup_hwmod,
1315         .slave          = &omap3xxx_gpio1_hwmod,
1316         .addr           = omap3xxx_gpio1_addrs,
1317         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
1318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1319 };
1320
1321 /* l4_per -> gpio2 */
1322 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1323         {
1324                 .pa_start       = 0x49050000,
1325                 .pa_end         = 0x490501ff,
1326                 .flags          = ADDR_TYPE_RT
1327         },
1328 };
1329
1330 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1331         .master         = &omap3xxx_l4_per_hwmod,
1332         .slave          = &omap3xxx_gpio2_hwmod,
1333         .addr           = omap3xxx_gpio2_addrs,
1334         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
1335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1336 };
1337
1338 /* l4_per -> gpio3 */
1339 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1340         {
1341                 .pa_start       = 0x49052000,
1342                 .pa_end         = 0x490521ff,
1343                 .flags          = ADDR_TYPE_RT
1344         },
1345 };
1346
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1348         .master         = &omap3xxx_l4_per_hwmod,
1349         .slave          = &omap3xxx_gpio3_hwmod,
1350         .addr           = omap3xxx_gpio3_addrs,
1351         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
1352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1353 };
1354
1355 /* l4_per -> gpio4 */
1356 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1357         {
1358                 .pa_start       = 0x49054000,
1359                 .pa_end         = 0x490541ff,
1360                 .flags          = ADDR_TYPE_RT
1361         },
1362 };
1363
1364 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1365         .master         = &omap3xxx_l4_per_hwmod,
1366         .slave          = &omap3xxx_gpio4_hwmod,
1367         .addr           = omap3xxx_gpio4_addrs,
1368         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
1369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1370 };
1371
1372 /* l4_per -> gpio5 */
1373 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1374         {
1375                 .pa_start       = 0x49056000,
1376                 .pa_end         = 0x490561ff,
1377                 .flags          = ADDR_TYPE_RT
1378         },
1379 };
1380
1381 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1382         .master         = &omap3xxx_l4_per_hwmod,
1383         .slave          = &omap3xxx_gpio5_hwmod,
1384         .addr           = omap3xxx_gpio5_addrs,
1385         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
1386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1387 };
1388
1389 /* l4_per -> gpio6 */
1390 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1391         {
1392                 .pa_start       = 0x49058000,
1393                 .pa_end         = 0x490581ff,
1394                 .flags          = ADDR_TYPE_RT
1395         },
1396 };
1397
1398 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1399         .master         = &omap3xxx_l4_per_hwmod,
1400         .slave          = &omap3xxx_gpio6_hwmod,
1401         .addr           = omap3xxx_gpio6_addrs,
1402         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
1403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1404 };
1405
1406 /*
1407  * 'gpio' class
1408  * general purpose io module
1409  */
1410
1411 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1412         .rev_offs       = 0x0000,
1413         .sysc_offs      = 0x0010,
1414         .syss_offs      = 0x0014,
1415         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1416                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1417         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1418         .sysc_fields    = &omap_hwmod_sysc_type1,
1419 };
1420
1421 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1422         .name = "gpio",
1423         .sysc = &omap3xxx_gpio_sysc,
1424         .rev = 1,
1425 };
1426
1427 /* gpio_dev_attr*/
1428 static struct omap_gpio_dev_attr gpio_dev_attr = {
1429         .bank_width = 32,
1430         .dbck_flag = true,
1431 };
1432
1433 /* gpio1 */
1434 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
1435         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
1436 };
1437
1438 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1439         { .role = "dbclk", .clk = "gpio1_dbck", },
1440 };
1441
1442 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1443         &omap3xxx_l4_wkup__gpio1,
1444 };
1445
1446 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1447         .name           = "gpio1",
1448         .mpu_irqs       = omap3xxx_gpio1_irqs,
1449         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
1450         .main_clk       = "gpio1_ick",
1451         .opt_clks       = gpio1_opt_clks,
1452         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1453         .prcm           = {
1454                 .omap2 = {
1455                         .prcm_reg_id = 1,
1456                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1457                         .module_offs = WKUP_MOD,
1458                         .idlest_reg_id = 1,
1459                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1460                 },
1461         },
1462         .slaves         = omap3xxx_gpio1_slaves,
1463         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1464         .class          = &omap3xxx_gpio_hwmod_class,
1465         .dev_attr       = &gpio_dev_attr,
1466         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1467 };
1468
1469 /* gpio2 */
1470 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
1471         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
1472 };
1473
1474 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1475         { .role = "dbclk", .clk = "gpio2_dbck", },
1476 };
1477
1478 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1479         &omap3xxx_l4_per__gpio2,
1480 };
1481
1482 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1483         .name           = "gpio2",
1484         .mpu_irqs       = omap3xxx_gpio2_irqs,
1485         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
1486         .main_clk       = "gpio2_ick",
1487         .opt_clks       = gpio2_opt_clks,
1488         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1489         .prcm           = {
1490                 .omap2 = {
1491                         .prcm_reg_id = 1,
1492                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1493                         .module_offs = OMAP3430_PER_MOD,
1494                         .idlest_reg_id = 1,
1495                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1496                 },
1497         },
1498         .slaves         = omap3xxx_gpio2_slaves,
1499         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1500         .class          = &omap3xxx_gpio_hwmod_class,
1501         .dev_attr       = &gpio_dev_attr,
1502         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1503 };
1504
1505 /* gpio3 */
1506 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
1507         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
1508 };
1509
1510 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1511         { .role = "dbclk", .clk = "gpio3_dbck", },
1512 };
1513
1514 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1515         &omap3xxx_l4_per__gpio3,
1516 };
1517
1518 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1519         .name           = "gpio3",
1520         .mpu_irqs       = omap3xxx_gpio3_irqs,
1521         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
1522         .main_clk       = "gpio3_ick",
1523         .opt_clks       = gpio3_opt_clks,
1524         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1525         .prcm           = {
1526                 .omap2 = {
1527                         .prcm_reg_id = 1,
1528                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1529                         .module_offs = OMAP3430_PER_MOD,
1530                         .idlest_reg_id = 1,
1531                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1532                 },
1533         },
1534         .slaves         = omap3xxx_gpio3_slaves,
1535         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1536         .class          = &omap3xxx_gpio_hwmod_class,
1537         .dev_attr       = &gpio_dev_attr,
1538         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1539 };
1540
1541 /* gpio4 */
1542 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
1543         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
1544 };
1545
1546 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1547         { .role = "dbclk", .clk = "gpio4_dbck", },
1548 };
1549
1550 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1551         &omap3xxx_l4_per__gpio4,
1552 };
1553
1554 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1555         .name           = "gpio4",
1556         .mpu_irqs       = omap3xxx_gpio4_irqs,
1557         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1558         .main_clk       = "gpio4_ick",
1559         .opt_clks       = gpio4_opt_clks,
1560         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1561         .prcm           = {
1562                 .omap2 = {
1563                         .prcm_reg_id = 1,
1564                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1565                         .module_offs = OMAP3430_PER_MOD,
1566                         .idlest_reg_id = 1,
1567                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1568                 },
1569         },
1570         .slaves         = omap3xxx_gpio4_slaves,
1571         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1572         .class          = &omap3xxx_gpio_hwmod_class,
1573         .dev_attr       = &gpio_dev_attr,
1574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1575 };
1576
1577 /* gpio5 */
1578 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1579         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1580 };
1581
1582 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1583         { .role = "dbclk", .clk = "gpio5_dbck", },
1584 };
1585
1586 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1587         &omap3xxx_l4_per__gpio5,
1588 };
1589
1590 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1591         .name           = "gpio5",
1592         .mpu_irqs       = omap3xxx_gpio5_irqs,
1593         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1594         .main_clk       = "gpio5_ick",
1595         .opt_clks       = gpio5_opt_clks,
1596         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1597         .prcm           = {
1598                 .omap2 = {
1599                         .prcm_reg_id = 1,
1600                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1601                         .module_offs = OMAP3430_PER_MOD,
1602                         .idlest_reg_id = 1,
1603                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1604                 },
1605         },
1606         .slaves         = omap3xxx_gpio5_slaves,
1607         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1608         .class          = &omap3xxx_gpio_hwmod_class,
1609         .dev_attr       = &gpio_dev_attr,
1610         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1611 };
1612
1613 /* gpio6 */
1614 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1615         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1616 };
1617
1618 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1619         { .role = "dbclk", .clk = "gpio6_dbck", },
1620 };
1621
1622 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1623         &omap3xxx_l4_per__gpio6,
1624 };
1625
1626 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1627         .name           = "gpio6",
1628         .mpu_irqs       = omap3xxx_gpio6_irqs,
1629         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1630         .main_clk       = "gpio6_ick",
1631         .opt_clks       = gpio6_opt_clks,
1632         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1633         .prcm           = {
1634                 .omap2 = {
1635                         .prcm_reg_id = 1,
1636                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1637                         .module_offs = OMAP3430_PER_MOD,
1638                         .idlest_reg_id = 1,
1639                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1640                 },
1641         },
1642         .slaves         = omap3xxx_gpio6_slaves,
1643         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1644         .class          = &omap3xxx_gpio_hwmod_class,
1645         .dev_attr       = &gpio_dev_attr,
1646         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1647 };
1648
1649 /* dma_system -> L3 */
1650 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1651         .master         = &omap3xxx_dma_system_hwmod,
1652         .slave          = &omap3xxx_l3_main_hwmod,
1653         .clk            = "core_l3_ick",
1654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1655 };
1656
1657 /* dma attributes */
1658 static struct omap_dma_dev_attr dma_dev_attr = {
1659         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1660                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1661         .lch_count = 32,
1662 };
1663
1664 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1665         .rev_offs       = 0x0000,
1666         .sysc_offs      = 0x002c,
1667         .syss_offs      = 0x0028,
1668         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1669                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1670                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1672                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1673         .sysc_fields    = &omap_hwmod_sysc_type1,
1674 };
1675
1676 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1677         .name = "dma",
1678         .sysc = &omap3xxx_dma_sysc,
1679 };
1680
1681 /* dma_system */
1682 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1683         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1684         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1685         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1686         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1687 };
1688
1689 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1690         {
1691                 .pa_start       = 0x48056000,
1692                 .pa_end         = 0x4a0560ff,
1693                 .flags          = ADDR_TYPE_RT
1694         },
1695 };
1696
1697 /* dma_system master ports */
1698 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1699         &omap3xxx_dma_system__l3,
1700 };
1701
1702 /* l4_cfg -> dma_system */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1704         .master         = &omap3xxx_l4_core_hwmod,
1705         .slave          = &omap3xxx_dma_system_hwmod,
1706         .clk            = "core_l4_ick",
1707         .addr           = omap3xxx_dma_system_addrs,
1708         .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1710 };
1711
1712 /* dma_system slave ports */
1713 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1714         &omap3xxx_l4_core__dma_system,
1715 };
1716
1717 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1718         .name           = "dma",
1719         .class          = &omap3xxx_dma_hwmod_class,
1720         .mpu_irqs       = omap3xxx_dma_system_irqs,
1721         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1722         .main_clk       = "core_l3_ick",
1723         .prcm = {
1724                 .omap2 = {
1725                         .module_offs            = CORE_MOD,
1726                         .prcm_reg_id            = 1,
1727                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1728                         .idlest_reg_id          = 1,
1729                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1730                 },
1731         },
1732         .slaves         = omap3xxx_dma_system_slaves,
1733         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1734         .masters        = omap3xxx_dma_system_masters,
1735         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
1736         .dev_attr       = &dma_dev_attr,
1737         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1738         .flags          = HWMOD_NO_IDLEST,
1739 };
1740
1741 /*
1742  * 'mcbsp' class
1743  * multi channel buffered serial port controller
1744  */
1745
1746 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1747         .sysc_offs      = 0x008c,
1748         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1749                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1750         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1751         .sysc_fields    = &omap_hwmod_sysc_type1,
1752         .clockact       = 0x2,
1753 };
1754
1755 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1756         .name = "mcbsp",
1757         .sysc = &omap3xxx_mcbsp_sysc,
1758         .rev  = MCBSP_CONFIG_TYPE3,
1759 };
1760
1761 /* mcbsp1 */
1762 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1763         { .name = "irq", .irq = 16 },
1764         { .name = "tx", .irq = 59 },
1765         { .name = "rx", .irq = 60 },
1766 };
1767
1768 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
1769         { .name = "rx", .dma_req = 32 },
1770         { .name = "tx", .dma_req = 31 },
1771 };
1772
1773 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
1774         {
1775                 .name           = "mpu",
1776                 .pa_start       = 0x48074000,
1777                 .pa_end         = 0x480740ff,
1778                 .flags          = ADDR_TYPE_RT
1779         },
1780 };
1781
1782 /* l4_core -> mcbsp1 */
1783 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
1784         .master         = &omap3xxx_l4_core_hwmod,
1785         .slave          = &omap3xxx_mcbsp1_hwmod,
1786         .clk            = "mcbsp1_ick",
1787         .addr           = omap3xxx_mcbsp1_addrs,
1788         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
1789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1790 };
1791
1792 /* mcbsp1 slave ports */
1793 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
1794         &omap3xxx_l4_core__mcbsp1,
1795 };
1796
1797 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1798         .name           = "mcbsp1",
1799         .class          = &omap3xxx_mcbsp_hwmod_class,
1800         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1801         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
1802         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
1803         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
1804         .main_clk       = "mcbsp1_fck",
1805         .prcm           = {
1806                 .omap2 = {
1807                         .prcm_reg_id = 1,
1808                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1809                         .module_offs = CORE_MOD,
1810                         .idlest_reg_id = 1,
1811                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1812                 },
1813         },
1814         .slaves         = omap3xxx_mcbsp1_slaves,
1815         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
1816         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1817 };
1818
1819 /* mcbsp2 */
1820 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1821         { .name = "irq", .irq = 17 },
1822         { .name = "tx", .irq = 62 },
1823         { .name = "rx", .irq = 63 },
1824 };
1825
1826 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
1827         { .name = "rx", .dma_req = 34 },
1828         { .name = "tx", .dma_req = 33 },
1829 };
1830
1831 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
1832         {
1833                 .name           = "mpu",
1834                 .pa_start       = 0x49022000,
1835                 .pa_end         = 0x490220ff,
1836                 .flags          = ADDR_TYPE_RT
1837         },
1838 };
1839
1840 /* l4_per -> mcbsp2 */
1841 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
1842         .master         = &omap3xxx_l4_per_hwmod,
1843         .slave          = &omap3xxx_mcbsp2_hwmod,
1844         .clk            = "mcbsp2_ick",
1845         .addr           = omap3xxx_mcbsp2_addrs,
1846         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
1847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1848 };
1849
1850 /* mcbsp2 slave ports */
1851 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
1852         &omap3xxx_l4_per__mcbsp2,
1853 };
1854
1855 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1856         .sidetone       = "mcbsp2_sidetone",
1857 };
1858
1859 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1860         .name           = "mcbsp2",
1861         .class          = &omap3xxx_mcbsp_hwmod_class,
1862         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1863         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
1864         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
1865         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
1866         .main_clk       = "mcbsp2_fck",
1867         .prcm           = {
1868                 .omap2 = {
1869                         .prcm_reg_id = 1,
1870                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1871                         .module_offs = OMAP3430_PER_MOD,
1872                         .idlest_reg_id = 1,
1873                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1874                 },
1875         },
1876         .slaves         = omap3xxx_mcbsp2_slaves,
1877         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
1878         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1879         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1880 };
1881
1882 /* mcbsp3 */
1883 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1884         { .name = "irq", .irq = 22 },
1885         { .name = "tx", .irq = 89 },
1886         { .name = "rx", .irq = 90 },
1887 };
1888
1889 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
1890         { .name = "rx", .dma_req = 18 },
1891         { .name = "tx", .dma_req = 17 },
1892 };
1893
1894 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
1895         {
1896                 .name           = "mpu",
1897                 .pa_start       = 0x49024000,
1898                 .pa_end         = 0x490240ff,
1899                 .flags          = ADDR_TYPE_RT
1900         },
1901 };
1902
1903 /* l4_per -> mcbsp3 */
1904 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
1905         .master         = &omap3xxx_l4_per_hwmod,
1906         .slave          = &omap3xxx_mcbsp3_hwmod,
1907         .clk            = "mcbsp3_ick",
1908         .addr           = omap3xxx_mcbsp3_addrs,
1909         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
1910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1911 };
1912
1913 /* mcbsp3 slave ports */
1914 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
1915         &omap3xxx_l4_per__mcbsp3,
1916 };
1917
1918 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1919         .sidetone       = "mcbsp3_sidetone",
1920 };
1921
1922 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1923         .name           = "mcbsp3",
1924         .class          = &omap3xxx_mcbsp_hwmod_class,
1925         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1926         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
1927         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
1928         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
1929         .main_clk       = "mcbsp3_fck",
1930         .prcm           = {
1931                 .omap2 = {
1932                         .prcm_reg_id = 1,
1933                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1934                         .module_offs = OMAP3430_PER_MOD,
1935                         .idlest_reg_id = 1,
1936                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1937                 },
1938         },
1939         .slaves         = omap3xxx_mcbsp3_slaves,
1940         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
1941         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1942         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1943 };
1944
1945 /* mcbsp4 */
1946 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1947         { .name = "irq", .irq = 23 },
1948         { .name = "tx", .irq = 54 },
1949         { .name = "rx", .irq = 55 },
1950 };
1951
1952 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1953         { .name = "rx", .dma_req = 20 },
1954         { .name = "tx", .dma_req = 19 },
1955 };
1956
1957 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
1958         {
1959                 .name           = "mpu",
1960                 .pa_start       = 0x49026000,
1961                 .pa_end         = 0x490260ff,
1962                 .flags          = ADDR_TYPE_RT
1963         },
1964 };
1965
1966 /* l4_per -> mcbsp4 */
1967 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
1968         .master         = &omap3xxx_l4_per_hwmod,
1969         .slave          = &omap3xxx_mcbsp4_hwmod,
1970         .clk            = "mcbsp4_ick",
1971         .addr           = omap3xxx_mcbsp4_addrs,
1972         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
1973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1974 };
1975
1976 /* mcbsp4 slave ports */
1977 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
1978         &omap3xxx_l4_per__mcbsp4,
1979 };
1980
1981 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1982         .name           = "mcbsp4",
1983         .class          = &omap3xxx_mcbsp_hwmod_class,
1984         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1985         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
1986         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1987         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
1988         .main_clk       = "mcbsp4_fck",
1989         .prcm           = {
1990                 .omap2 = {
1991                         .prcm_reg_id = 1,
1992                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1993                         .module_offs = OMAP3430_PER_MOD,
1994                         .idlest_reg_id = 1,
1995                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1996                 },
1997         },
1998         .slaves         = omap3xxx_mcbsp4_slaves,
1999         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2000         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2001 };
2002
2003 /* mcbsp5 */
2004 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2005         { .name = "irq", .irq = 27 },
2006         { .name = "tx", .irq = 81 },
2007         { .name = "rx", .irq = 82 },
2008 };
2009
2010 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2011         { .name = "rx", .dma_req = 22 },
2012         { .name = "tx", .dma_req = 21 },
2013 };
2014
2015 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2016         {
2017                 .name           = "mpu",
2018                 .pa_start       = 0x48096000,
2019                 .pa_end         = 0x480960ff,
2020                 .flags          = ADDR_TYPE_RT
2021         },
2022 };
2023
2024 /* l4_core -> mcbsp5 */
2025 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2026         .master         = &omap3xxx_l4_core_hwmod,
2027         .slave          = &omap3xxx_mcbsp5_hwmod,
2028         .clk            = "mcbsp5_ick",
2029         .addr           = omap3xxx_mcbsp5_addrs,
2030         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2032 };
2033
2034 /* mcbsp5 slave ports */
2035 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2036         &omap3xxx_l4_core__mcbsp5,
2037 };
2038
2039 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2040         .name           = "mcbsp5",
2041         .class          = &omap3xxx_mcbsp_hwmod_class,
2042         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2043         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2044         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2045         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2046         .main_clk       = "mcbsp5_fck",
2047         .prcm           = {
2048                 .omap2 = {
2049                         .prcm_reg_id = 1,
2050                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2051                         .module_offs = CORE_MOD,
2052                         .idlest_reg_id = 1,
2053                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2054                 },
2055         },
2056         .slaves         = omap3xxx_mcbsp5_slaves,
2057         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2059 };
2060 /* 'mcbsp sidetone' class */
2061
2062 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2063         .sysc_offs      = 0x0010,
2064         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2065         .sysc_fields    = &omap_hwmod_sysc_type1,
2066 };
2067
2068 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2069         .name = "mcbsp_sidetone",
2070         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2071 };
2072
2073 /* mcbsp2_sidetone */
2074 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2075         { .name = "irq", .irq = 4 },
2076 };
2077
2078 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2079         {
2080                 .name           = "sidetone",
2081                 .pa_start       = 0x49028000,
2082                 .pa_end         = 0x490280ff,
2083                 .flags          = ADDR_TYPE_RT
2084         },
2085 };
2086
2087 /* l4_per -> mcbsp2_sidetone */
2088 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2089         .master         = &omap3xxx_l4_per_hwmod,
2090         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2091         .clk            = "mcbsp2_ick",
2092         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2093         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2094         .user           = OCP_USER_MPU,
2095 };
2096
2097 /* mcbsp2_sidetone slave ports */
2098 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2099         &omap3xxx_l4_per__mcbsp2_sidetone,
2100 };
2101
2102 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2103         .name           = "mcbsp2_sidetone",
2104         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2105         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2106         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2107         .main_clk       = "mcbsp2_fck",
2108         .prcm           = {
2109                 .omap2 = {
2110                         .prcm_reg_id = 1,
2111                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2112                         .module_offs = OMAP3430_PER_MOD,
2113                         .idlest_reg_id = 1,
2114                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2115                 },
2116         },
2117         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2118         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2119         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2120 };
2121
2122 /* mcbsp3_sidetone */
2123 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2124         { .name = "irq", .irq = 5 },
2125 };
2126
2127 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2128         {
2129                 .name           = "sidetone",
2130                 .pa_start       = 0x4902A000,
2131                 .pa_end         = 0x4902A0ff,
2132                 .flags          = ADDR_TYPE_RT
2133         },
2134 };
2135
2136 /* l4_per -> mcbsp3_sidetone */
2137 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2138         .master         = &omap3xxx_l4_per_hwmod,
2139         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2140         .clk            = "mcbsp3_ick",
2141         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2142         .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2143         .user           = OCP_USER_MPU,
2144 };
2145
2146 /* mcbsp3_sidetone slave ports */
2147 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2148         &omap3xxx_l4_per__mcbsp3_sidetone,
2149 };
2150
2151 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2152         .name           = "mcbsp3_sidetone",
2153         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2154         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2155         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2156         .main_clk       = "mcbsp3_fck",
2157         .prcm           = {
2158                 .omap2 = {
2159                         .prcm_reg_id = 1,
2160                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2161                         .module_offs = OMAP3430_PER_MOD,
2162                         .idlest_reg_id = 1,
2163                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2164                 },
2165         },
2166         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2167         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2168         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2169 };
2170
2171
2172 /* SR common */
2173 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2174         .clkact_shift   = 20,
2175 };
2176
2177 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2178         .sysc_offs      = 0x24,
2179         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2180         .clockact       = CLOCKACT_TEST_ICLK,
2181         .sysc_fields    = &omap34xx_sr_sysc_fields,
2182 };
2183
2184 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2185         .name = "smartreflex",
2186         .sysc = &omap34xx_sr_sysc,
2187         .rev  = 1,
2188 };
2189
2190 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2191         .sidle_shift    = 24,
2192         .enwkup_shift   = 26
2193 };
2194
2195 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2196         .sysc_offs      = 0x38,
2197         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2198         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2199                         SYSC_NO_CACHE),
2200         .sysc_fields    = &omap36xx_sr_sysc_fields,
2201 };
2202
2203 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2204         .name = "smartreflex",
2205         .sysc = &omap36xx_sr_sysc,
2206         .rev  = 2,
2207 };
2208
2209 /* SR1 */
2210 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2211         &omap3_l4_core__sr1,
2212 };
2213
2214 static struct omap_hwmod omap34xx_sr1_hwmod = {
2215         .name           = "sr1_hwmod",
2216         .class          = &omap34xx_smartreflex_hwmod_class,
2217         .main_clk       = "sr1_fck",
2218         .vdd_name       = "mpu",
2219         .prcm           = {
2220                 .omap2 = {
2221                         .prcm_reg_id = 1,
2222                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2223                         .module_offs = WKUP_MOD,
2224                         .idlest_reg_id = 1,
2225                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2226                 },
2227         },
2228         .slaves         = omap3_sr1_slaves,
2229         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2231                                         CHIP_IS_OMAP3430ES3_0 |
2232                                         CHIP_IS_OMAP3430ES3_1),
2233         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2234 };
2235
2236 static struct omap_hwmod omap36xx_sr1_hwmod = {
2237         .name           = "sr1_hwmod",
2238         .class          = &omap36xx_smartreflex_hwmod_class,
2239         .main_clk       = "sr1_fck",
2240         .vdd_name       = "mpu",
2241         .prcm           = {
2242                 .omap2 = {
2243                         .prcm_reg_id = 1,
2244                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2245                         .module_offs = WKUP_MOD,
2246                         .idlest_reg_id = 1,
2247                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2248                 },
2249         },
2250         .slaves         = omap3_sr1_slaves,
2251         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2252         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2253 };
2254
2255 /* SR2 */
2256 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2257         &omap3_l4_core__sr2,
2258 };
2259
2260 static struct omap_hwmod omap34xx_sr2_hwmod = {
2261         .name           = "sr2_hwmod",
2262         .class          = &omap34xx_smartreflex_hwmod_class,
2263         .main_clk       = "sr2_fck",
2264         .vdd_name       = "core",
2265         .prcm           = {
2266                 .omap2 = {
2267                         .prcm_reg_id = 1,
2268                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2269                         .module_offs = WKUP_MOD,
2270                         .idlest_reg_id = 1,
2271                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2272                 },
2273         },
2274         .slaves         = omap3_sr2_slaves,
2275         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2276         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2277                                         CHIP_IS_OMAP3430ES3_0 |
2278                                         CHIP_IS_OMAP3430ES3_1),
2279         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2280 };
2281
2282 static struct omap_hwmod omap36xx_sr2_hwmod = {
2283         .name           = "sr2_hwmod",
2284         .class          = &omap36xx_smartreflex_hwmod_class,
2285         .main_clk       = "sr2_fck",
2286         .vdd_name       = "core",
2287         .prcm           = {
2288                 .omap2 = {
2289                         .prcm_reg_id = 1,
2290                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2291                         .module_offs = WKUP_MOD,
2292                         .idlest_reg_id = 1,
2293                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2294                 },
2295         },
2296         .slaves         = omap3_sr2_slaves,
2297         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2298         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2299 };
2300
2301 /*
2302  * 'mailbox' class
2303  * mailbox module allowing communication between the on-chip processors
2304  * using a queued mailbox-interrupt mechanism.
2305  */
2306
2307 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2308         .rev_offs       = 0x000,
2309         .sysc_offs      = 0x010,
2310         .syss_offs      = 0x014,
2311         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2312                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2313         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2314         .sysc_fields    = &omap_hwmod_sysc_type1,
2315 };
2316
2317 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2318         .name = "mailbox",
2319         .sysc = &omap3xxx_mailbox_sysc,
2320 };
2321
2322 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2323 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2324         { .irq = 26 },
2325 };
2326
2327 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2328         {
2329                 .pa_start       = 0x48094000,
2330                 .pa_end         = 0x480941ff,
2331                 .flags          = ADDR_TYPE_RT,
2332         },
2333 };
2334
2335 /* l4_core -> mailbox */
2336 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2337         .master         = &omap3xxx_l4_core_hwmod,
2338         .slave          = &omap3xxx_mailbox_hwmod,
2339         .addr           = omap3xxx_mailbox_addrs,
2340         .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
2341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2342 };
2343
2344 /* mailbox slave ports */
2345 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2346         &omap3xxx_l4_core__mailbox,
2347 };
2348
2349 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2350         .name           = "mailbox",
2351         .class          = &omap3xxx_mailbox_hwmod_class,
2352         .mpu_irqs       = omap3xxx_mailbox_irqs,
2353         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
2354         .main_clk       = "mailboxes_ick",
2355         .prcm           = {
2356                 .omap2 = {
2357                         .prcm_reg_id = 1,
2358                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2359                         .module_offs = CORE_MOD,
2360                         .idlest_reg_id = 1,
2361                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2362                 },
2363         },
2364         .slaves         = omap3xxx_mailbox_slaves,
2365         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2366         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2367 };
2368
2369 /* l4 core -> mcspi1 interface */
2370 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
2371         {
2372                 .pa_start       = 0x48098000,
2373                 .pa_end         = 0x480980ff,
2374                 .flags          = ADDR_TYPE_RT,
2375         },
2376 };
2377
2378 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2379         .master         = &omap3xxx_l4_core_hwmod,
2380         .slave          = &omap34xx_mcspi1,
2381         .clk            = "mcspi1_ick",
2382         .addr           = omap34xx_mcspi1_addr_space,
2383         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
2384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2385 };
2386
2387 /* l4 core -> mcspi2 interface */
2388 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
2389         {
2390                 .pa_start       = 0x4809a000,
2391                 .pa_end         = 0x4809a0ff,
2392                 .flags          = ADDR_TYPE_RT,
2393         },
2394 };
2395
2396 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2397         .master         = &omap3xxx_l4_core_hwmod,
2398         .slave          = &omap34xx_mcspi2,
2399         .clk            = "mcspi2_ick",
2400         .addr           = omap34xx_mcspi2_addr_space,
2401         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* l4 core -> mcspi3 interface */
2406 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
2407         {
2408                 .pa_start       = 0x480b8000,
2409                 .pa_end         = 0x480b80ff,
2410                 .flags          = ADDR_TYPE_RT,
2411         },
2412 };
2413
2414 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2415         .master         = &omap3xxx_l4_core_hwmod,
2416         .slave          = &omap34xx_mcspi3,
2417         .clk            = "mcspi3_ick",
2418         .addr           = omap34xx_mcspi3_addr_space,
2419         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
2420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2421 };
2422
2423 /* l4 core -> mcspi4 interface */
2424 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2425         {
2426                 .pa_start       = 0x480ba000,
2427                 .pa_end         = 0x480ba0ff,
2428                 .flags          = ADDR_TYPE_RT,
2429         },
2430 };
2431
2432 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2433         .master         = &omap3xxx_l4_core_hwmod,
2434         .slave          = &omap34xx_mcspi4,
2435         .clk            = "mcspi4_ick",
2436         .addr           = omap34xx_mcspi4_addr_space,
2437         .addr_cnt       = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
2438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2439 };
2440
2441 /*
2442  * 'mcspi' class
2443  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2444  * bus
2445  */
2446
2447 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2448         .rev_offs       = 0x0000,
2449         .sysc_offs      = 0x0010,
2450         .syss_offs      = 0x0014,
2451         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2452                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2453                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2454         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2455         .sysc_fields    = &omap_hwmod_sysc_type1,
2456 };
2457
2458 static struct omap_hwmod_class omap34xx_mcspi_class = {
2459         .name = "mcspi",
2460         .sysc = &omap34xx_mcspi_sysc,
2461         .rev = OMAP3_MCSPI_REV,
2462 };
2463
2464 /* mcspi1 */
2465 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
2466         { .name = "irq", .irq = 65 },
2467 };
2468
2469 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2470         { .name = "tx0", .dma_req = 35 },
2471         { .name = "rx0", .dma_req = 36 },
2472         { .name = "tx1", .dma_req = 37 },
2473         { .name = "rx1", .dma_req = 38 },
2474         { .name = "tx2", .dma_req = 39 },
2475         { .name = "rx2", .dma_req = 40 },
2476         { .name = "tx3", .dma_req = 41 },
2477         { .name = "rx3", .dma_req = 42 },
2478 };
2479
2480 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2481         &omap34xx_l4_core__mcspi1,
2482 };
2483
2484 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2485         .num_chipselect = 4,
2486 };
2487
2488 static struct omap_hwmod omap34xx_mcspi1 = {
2489         .name           = "mcspi1",
2490         .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
2491         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
2492         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
2493         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
2494         .main_clk       = "mcspi1_fck",
2495         .prcm           = {
2496                 .omap2 = {
2497                         .module_offs = CORE_MOD,
2498                         .prcm_reg_id = 1,
2499                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2500                         .idlest_reg_id = 1,
2501                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2502                 },
2503         },
2504         .slaves         = omap34xx_mcspi1_slaves,
2505         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2506         .class          = &omap34xx_mcspi_class,
2507         .dev_attr       = &omap_mcspi1_dev_attr,
2508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2509 };
2510
2511 /* mcspi2 */
2512 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
2513         { .name = "irq", .irq = 66 },
2514 };
2515
2516 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2517         { .name = "tx0", .dma_req = 43 },
2518         { .name = "rx0", .dma_req = 44 },
2519         { .name = "tx1", .dma_req = 45 },
2520         { .name = "rx1", .dma_req = 46 },
2521 };
2522
2523 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2524         &omap34xx_l4_core__mcspi2,
2525 };
2526
2527 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2528         .num_chipselect = 2,
2529 };
2530
2531 static struct omap_hwmod omap34xx_mcspi2 = {
2532         .name           = "mcspi2",
2533         .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
2534         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
2535         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
2536         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
2537         .main_clk       = "mcspi2_fck",
2538         .prcm           = {
2539                 .omap2 = {
2540                         .module_offs = CORE_MOD,
2541                         .prcm_reg_id = 1,
2542                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2543                         .idlest_reg_id = 1,
2544                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2545                 },
2546         },
2547         .slaves         = omap34xx_mcspi2_slaves,
2548         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2549         .class          = &omap34xx_mcspi_class,
2550         .dev_attr       = &omap_mcspi2_dev_attr,
2551         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2552 };
2553
2554 /* mcspi3 */
2555 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2556         { .name = "irq", .irq = 91 }, /* 91 */
2557 };
2558
2559 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2560         { .name = "tx0", .dma_req = 15 },
2561         { .name = "rx0", .dma_req = 16 },
2562         { .name = "tx1", .dma_req = 23 },
2563         { .name = "rx1", .dma_req = 24 },
2564 };
2565
2566 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2567         &omap34xx_l4_core__mcspi3,
2568 };
2569
2570 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2571         .num_chipselect = 2,
2572 };
2573
2574 static struct omap_hwmod omap34xx_mcspi3 = {
2575         .name           = "mcspi3",
2576         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2577         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
2578         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2579         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
2580         .main_clk       = "mcspi3_fck",
2581         .prcm           = {
2582                 .omap2 = {
2583                         .module_offs = CORE_MOD,
2584                         .prcm_reg_id = 1,
2585                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2586                         .idlest_reg_id = 1,
2587                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2588                 },
2589         },
2590         .slaves         = omap34xx_mcspi3_slaves,
2591         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2592         .class          = &omap34xx_mcspi_class,
2593         .dev_attr       = &omap_mcspi3_dev_attr,
2594         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2595 };
2596
2597 /* SPI4 */
2598 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2599         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2600 };
2601
2602 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2603         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2604         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2605 };
2606
2607 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2608         &omap34xx_l4_core__mcspi4,
2609 };
2610
2611 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2612         .num_chipselect = 1,
2613 };
2614
2615 static struct omap_hwmod omap34xx_mcspi4 = {
2616         .name           = "mcspi4",
2617         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2618         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
2619         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2620         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
2621         .main_clk       = "mcspi4_fck",
2622         .prcm           = {
2623                 .omap2 = {
2624                         .module_offs = CORE_MOD,
2625                         .prcm_reg_id = 1,
2626                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2627                         .idlest_reg_id = 1,
2628                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2629                 },
2630         },
2631         .slaves         = omap34xx_mcspi4_slaves,
2632         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2633         .class          = &omap34xx_mcspi_class,
2634         .dev_attr       = &omap_mcspi4_dev_attr,
2635         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2636 };
2637
2638 /*
2639  * usbhsotg
2640  */
2641 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2642         .rev_offs       = 0x0400,
2643         .sysc_offs      = 0x0404,
2644         .syss_offs      = 0x0408,
2645         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2646                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2647                           SYSC_HAS_AUTOIDLE),
2648         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2649                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2650         .sysc_fields    = &omap_hwmod_sysc_type1,
2651 };
2652
2653 static struct omap_hwmod_class usbotg_class = {
2654         .name = "usbotg",
2655         .sysc = &omap3xxx_usbhsotg_sysc,
2656 };
2657 /* usb_otg_hs */
2658 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2659
2660         { .name = "mc", .irq = 92 },
2661         { .name = "dma", .irq = 93 },
2662 };
2663
2664 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2665         .name           = "usb_otg_hs",
2666         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2667         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
2668         .main_clk       = "hsotgusb_ick",
2669         .prcm           = {
2670                 .omap2 = {
2671                         .prcm_reg_id = 1,
2672                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2673                         .module_offs = CORE_MOD,
2674                         .idlest_reg_id = 1,
2675                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2676                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2677                 },
2678         },
2679         .masters        = omap3xxx_usbhsotg_masters,
2680         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2681         .slaves         = omap3xxx_usbhsotg_slaves,
2682         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2683         .class          = &usbotg_class,
2684
2685         /*
2686          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
2687          * broken when autoidle is enabled
2688          * workaround is to disable the autoidle bit at module level.
2689          */
2690         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2691                                 | HWMOD_SWSUP_MSTANDBY,
2692         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
2693 };
2694
2695 /* usb_otg_hs */
2696 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
2697
2698         { .name = "mc", .irq = 71 },
2699 };
2700
2701 static struct omap_hwmod_class am35xx_usbotg_class = {
2702         .name = "am35xx_usbotg",
2703         .sysc = NULL,
2704 };
2705
2706 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2707         .name           = "am35x_otg_hs",
2708         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
2709         .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
2710         .main_clk       = NULL,
2711         .prcm = {
2712                 .omap2 = {
2713                 },
2714         },
2715         .masters        = am35xx_usbhsotg_masters,
2716         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
2717         .slaves         = am35xx_usbhsotg_slaves,
2718         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
2719         .class          = &am35xx_usbotg_class,
2720         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2721 };
2722
2723 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2724         &omap3xxx_l3_main_hwmod,
2725         &omap3xxx_l4_core_hwmod,
2726         &omap3xxx_l4_per_hwmod,
2727         &omap3xxx_l4_wkup_hwmod,
2728         &omap3xxx_mpu_hwmod,
2729         &omap3xxx_iva_hwmod,
2730         &omap3xxx_wd_timer2_hwmod,
2731         &omap3xxx_uart1_hwmod,
2732         &omap3xxx_uart2_hwmod,
2733         &omap3xxx_uart3_hwmod,
2734         &omap3xxx_uart4_hwmod,
2735         /* dss class */
2736         &omap3430es1_dss_core_hwmod,
2737         &omap3xxx_dss_core_hwmod,
2738         &omap3xxx_dss_dispc_hwmod,
2739         &omap3xxx_dss_dsi1_hwmod,
2740         &omap3xxx_dss_rfbi_hwmod,
2741         &omap3xxx_dss_venc_hwmod,
2742
2743         /* i2c class */
2744         &omap3xxx_i2c1_hwmod,
2745         &omap3xxx_i2c2_hwmod,
2746         &omap3xxx_i2c3_hwmod,
2747         &omap34xx_sr1_hwmod,
2748         &omap34xx_sr2_hwmod,
2749         &omap36xx_sr1_hwmod,
2750         &omap36xx_sr2_hwmod,
2751
2752
2753         /* gpio class */
2754         &omap3xxx_gpio1_hwmod,
2755         &omap3xxx_gpio2_hwmod,
2756         &omap3xxx_gpio3_hwmod,
2757         &omap3xxx_gpio4_hwmod,
2758         &omap3xxx_gpio5_hwmod,
2759         &omap3xxx_gpio6_hwmod,
2760
2761         /* dma_system class*/
2762         &omap3xxx_dma_system_hwmod,
2763
2764         /* mcbsp class */
2765         &omap3xxx_mcbsp1_hwmod,
2766         &omap3xxx_mcbsp2_hwmod,
2767         &omap3xxx_mcbsp3_hwmod,
2768         &omap3xxx_mcbsp4_hwmod,
2769         &omap3xxx_mcbsp5_hwmod,
2770         &omap3xxx_mcbsp2_sidetone_hwmod,
2771         &omap3xxx_mcbsp3_sidetone_hwmod,
2772
2773         /* mailbox class */
2774         &omap3xxx_mailbox_hwmod,
2775
2776         /* mcspi class */
2777         &omap34xx_mcspi1,
2778         &omap34xx_mcspi2,
2779         &omap34xx_mcspi3,
2780         &omap34xx_mcspi4,
2781
2782         /* usbotg class */
2783         &omap3xxx_usbhsotg_hwmod,
2784
2785         /* usbotg for am35x */
2786         &am35xx_usbhsotg_hwmod,
2787
2788         NULL,
2789 };
2790
2791 int __init omap3xxx_hwmod_init(void)
2792 {
2793         return omap_hwmod_init(omap3xxx_hwmods);
2794 }