arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <plat/omap_hwmod.h>
  12 #include <plat/serial.h>
  13 #include <plat/gpio.h>
  14 #include <plat/dma.h>
  15 #include <plat/dmtimer.h>
  16 #include <plat/mcspi.h>
  17
  18 #include <mach/irqs.h>
  19
  20 #include "omap_hwmod_common_data.h"
  21 #include "cm-regbits-24xx.h"
  22 #include "prm-regbits-24xx.h"
  23 #include "wd_timer.h"
  24
  25 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
  26         { .irq = 48, },
  27         { .irq = -1 }
  28 };
  29
  30 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  31         { .name = "dispc", .dma_req = 5 },
  32         { .dma_req = -1 }
  33 };
  34
  35 /*
  36  * 'dispc' class
  37  * display controller
  38  */
  39
  40 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  41         .rev_offs       = 0x0000,
  42         .sysc_offs      = 0x0010,
  43         .syss_offs      = 0x0014,
  44         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  45                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  46         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  47                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  48         .sysc_fields    = &omap_hwmod_sysc_type1,
  49 };
  50
  51 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  52         .name   = "dispc",
  53         .sysc   = &omap2_dispc_sysc,
  54 };
  55
  56 /* OMAP2xxx Timer Common */
  57 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  58         .rev_offs       = 0x0000,
  59         .sysc_offs      = 0x0010,
  60         .syss_offs      = 0x0014,
  61         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  62                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  63                            SYSC_HAS_AUTOIDLE),
  64         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  65         .sysc_fields    = &omap_hwmod_sysc_type1,
  66 };
  67
  68 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  69         .name   = "timer",
  70         .sysc   = &omap2xxx_timer_sysc,
  71         .rev    = OMAP_TIMER_IP_VERSION_1,
  72 };
  73
  74 /*
  75  * 'wd_timer' class
  76  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  77  * overflow condition
  78  */
  79
  80 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  81         .rev_offs       = 0x0000,
  82         .sysc_offs      = 0x0010,
  83         .syss_offs      = 0x0014,
  84         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  85                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  86         .sysc_fields    = &omap_hwmod_sysc_type1,
  87 };
  88
  89 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  90         .name           = "wd_timer",
  91         .sysc           = &omap2xxx_wd_timer_sysc,
  92         .pre_shutdown   = &omap2_wd_timer_disable
  93 };
  94
  95 /*
  96  * 'gpio' class
  97  * general purpose io module
  98  */
  99 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
 100         .rev_offs       = 0x0000,
 101         .sysc_offs      = 0x0010,
 102         .syss_offs      = 0x0014,
 103         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 104                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 105                            SYSS_HAS_RESET_STATUS),
 106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 107         .sysc_fields    = &omap_hwmod_sysc_type1,
 108 };
 109
 110 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
 111         .name = "gpio",
 112         .sysc = &omap2xxx_gpio_sysc,
 113         .rev = 0,
 114 };
 115
 116 /* system dma */
 117 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 118         .rev_offs       = 0x0000,
 119         .sysc_offs      = 0x002c,
 120         .syss_offs      = 0x0028,
 121         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 122                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 123                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 124         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 125         .sysc_fields    = &omap_hwmod_sysc_type1,
 126 };
 127
 128 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 129         .name   = "dma",
 130         .sysc   = &omap2xxx_dma_sysc,
 131 };
 132
 133 /*
 134  * 'mailbox' class
 135  * mailbox module allowing communication between the on-chip processors
 136  * using a queued mailbox-interrupt mechanism.
 137  */
 138
 139 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 140         .rev_offs       = 0x000,
 141         .sysc_offs      = 0x010,
 142         .syss_offs      = 0x014,
 143         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 144                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 145         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 146         .sysc_fields    = &omap_hwmod_sysc_type1,
 147 };
 148
 149 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 150         .name   = "mailbox",
 151         .sysc   = &omap2xxx_mailbox_sysc,
 152 };
 153
 154 /*
 155  * 'mcspi' class
 156  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 157  * bus
 158  */
 159
 160 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 161         .rev_offs       = 0x0000,
 162         .sysc_offs      = 0x0010,
 163         .syss_offs      = 0x0014,
 164         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 165                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 166                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 167         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 168         .sysc_fields    = &omap_hwmod_sysc_type1,
 169 };
 170
 171 struct omap_hwmod_class omap2xxx_mcspi_class = {
 172         .name   = "mcspi",
 173         .sysc   = &omap2xxx_mcspi_sysc,
 174         .rev    = OMAP2_MCSPI_REV,
 175 };
 176
 177 /*
 178  * IP blocks
 179  */
 180
 181 /* L3 */
 182 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 183         .name           = "l3_main",
 184         .class          = &l3_hwmod_class,
 185         .flags          = HWMOD_NO_IDLEST,
 186 };
 187
 188 /* L4 CORE */
 189 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 190         .name           = "l4_core",
 191         .class          = &l4_hwmod_class,
 192         .flags          = HWMOD_NO_IDLEST,
 193 };
 194
 195 /* L4 WKUP */
 196 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 197         .name           = "l4_wkup",
 198         .class          = &l4_hwmod_class,
 199         .flags          = HWMOD_NO_IDLEST,
 200 };
 201
 202 /* MPU */
 203 struct omap_hwmod omap2xxx_mpu_hwmod = {
 204         .name           = "mpu",
 205         .class          = &mpu_hwmod_class,
 206         .main_clk       = "mpu_ck",
 207 };
 208
 209 /* IVA2 */
 210 struct omap_hwmod omap2xxx_iva_hwmod = {
 211         .name           = "iva",
 212         .class          = &iva_hwmod_class,
 213 };
 214
 215 /* always-on timers dev attribute */
 216 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 217         .timer_capability       = OMAP_TIMER_ALWON,
 218 };
 219
 220 /* pwm timers dev attribute */
 221 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 222         .timer_capability       = OMAP_TIMER_HAS_PWM,
 223 };
 224
 225 /* timer1 */
 226
 227 struct omap_hwmod omap2xxx_timer1_hwmod = {
 228         .name           = "timer1",
 229         .mpu_irqs       = omap2_timer1_mpu_irqs,
 230         .main_clk       = "gpt1_fck",
 231         .prcm           = {
 232                 .omap2 = {
 233                         .prcm_reg_id = 1,
 234                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 235                         .module_offs = WKUP_MOD,
 236                         .idlest_reg_id = 1,
 237                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 238                 },
 239         },
 240         .dev_attr       = &capability_alwon_dev_attr,
 241         .class          = &omap2xxx_timer_hwmod_class,
 242 };
 243
 244 /* timer2 */
 245
 246 struct omap_hwmod omap2xxx_timer2_hwmod = {
 247         .name           = "timer2",
 248         .mpu_irqs       = omap2_timer2_mpu_irqs,
 249         .main_clk       = "gpt2_fck",
 250         .prcm           = {
 251                 .omap2 = {
 252                         .prcm_reg_id = 1,
 253                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 254                         .module_offs = CORE_MOD,
 255                         .idlest_reg_id = 1,
 256                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 257                 },
 258         },
 259         .dev_attr       = &capability_alwon_dev_attr,
 260         .class          = &omap2xxx_timer_hwmod_class,
 261 };
 262
 263 /* timer3 */
 264
 265 struct omap_hwmod omap2xxx_timer3_hwmod = {
 266         .name           = "timer3",
 267         .mpu_irqs       = omap2_timer3_mpu_irqs,
 268         .main_clk       = "gpt3_fck",
 269         .prcm           = {
 270                 .omap2 = {
 271                         .prcm_reg_id = 1,
 272                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 273                         .module_offs = CORE_MOD,
 274                         .idlest_reg_id = 1,
 275                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 276                 },
 277         },
 278         .dev_attr       = &capability_alwon_dev_attr,
 279         .class          = &omap2xxx_timer_hwmod_class,
 280 };
 281
 282 /* timer4 */
 283
 284 struct omap_hwmod omap2xxx_timer4_hwmod = {
 285         .name           = "timer4",
 286         .mpu_irqs       = omap2_timer4_mpu_irqs,
 287         .main_clk       = "gpt4_fck",
 288         .prcm           = {
 289                 .omap2 = {
 290                         .prcm_reg_id = 1,
 291                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 292                         .module_offs = CORE_MOD,
 293                         .idlest_reg_id = 1,
 294                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 295                 },
 296         },
 297         .dev_attr       = &capability_alwon_dev_attr,
 298         .class          = &omap2xxx_timer_hwmod_class,
 299 };
 300
 301 /* timer5 */
 302
 303 struct omap_hwmod omap2xxx_timer5_hwmod = {
 304         .name           = "timer5",
 305         .mpu_irqs       = omap2_timer5_mpu_irqs,
 306         .main_clk       = "gpt5_fck",
 307         .prcm           = {
 308                 .omap2 = {
 309                         .prcm_reg_id = 1,
 310                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 311                         .module_offs = CORE_MOD,
 312                         .idlest_reg_id = 1,
 313                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 314                 },
 315         },
 316         .dev_attr       = &capability_alwon_dev_attr,
 317         .class          = &omap2xxx_timer_hwmod_class,
 318 };
 319
 320 /* timer6 */
 321
 322 struct omap_hwmod omap2xxx_timer6_hwmod = {
 323         .name           = "timer6",
 324         .mpu_irqs       = omap2_timer6_mpu_irqs,
 325         .main_clk       = "gpt6_fck",
 326         .prcm           = {
 327                 .omap2 = {
 328                         .prcm_reg_id = 1,
 329                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 330                         .module_offs = CORE_MOD,
 331                         .idlest_reg_id = 1,
 332                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 333                 },
 334         },
 335         .dev_attr       = &capability_alwon_dev_attr,
 336         .class          = &omap2xxx_timer_hwmod_class,
 337 };
 338
 339 /* timer7 */
 340
 341 struct omap_hwmod omap2xxx_timer7_hwmod = {
 342         .name           = "timer7",
 343         .mpu_irqs       = omap2_timer7_mpu_irqs,
 344         .main_clk       = "gpt7_fck",
 345         .prcm           = {
 346                 .omap2 = {
 347                         .prcm_reg_id = 1,
 348                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 349                         .module_offs = CORE_MOD,
 350                         .idlest_reg_id = 1,
 351                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 352                 },
 353         },
 354         .dev_attr       = &capability_alwon_dev_attr,
 355         .class          = &omap2xxx_timer_hwmod_class,
 356 };
 357
 358 /* timer8 */
 359
 360 struct omap_hwmod omap2xxx_timer8_hwmod = {
 361         .name           = "timer8",
 362         .mpu_irqs       = omap2_timer8_mpu_irqs,
 363         .main_clk       = "gpt8_fck",
 364         .prcm           = {
 365                 .omap2 = {
 366                         .prcm_reg_id = 1,
 367                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 368                         .module_offs = CORE_MOD,
 369                         .idlest_reg_id = 1,
 370                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 371                 },
 372         },
 373         .dev_attr       = &capability_alwon_dev_attr,
 374         .class          = &omap2xxx_timer_hwmod_class,
 375 };
 376
 377 /* timer9 */
 378
 379 struct omap_hwmod omap2xxx_timer9_hwmod = {
 380         .name           = "timer9",
 381         .mpu_irqs       = omap2_timer9_mpu_irqs,
 382         .main_clk       = "gpt9_fck",
 383         .prcm           = {
 384                 .omap2 = {
 385                         .prcm_reg_id = 1,
 386                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 387                         .module_offs = CORE_MOD,
 388                         .idlest_reg_id = 1,
 389                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 390                 },
 391         },
 392         .dev_attr       = &capability_pwm_dev_attr,
 393         .class          = &omap2xxx_timer_hwmod_class,
 394 };
 395
 396 /* timer10 */
 397
 398 struct omap_hwmod omap2xxx_timer10_hwmod = {
 399         .name           = "timer10",
 400         .mpu_irqs       = omap2_timer10_mpu_irqs,
 401         .main_clk       = "gpt10_fck",
 402         .prcm           = {
 403                 .omap2 = {
 404                         .prcm_reg_id = 1,
 405                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 406                         .module_offs = CORE_MOD,
 407                         .idlest_reg_id = 1,
 408                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 409                 },
 410         },
 411         .dev_attr       = &capability_pwm_dev_attr,
 412         .class          = &omap2xxx_timer_hwmod_class,
 413 };
 414
 415 /* timer11 */
 416
 417 struct omap_hwmod omap2xxx_timer11_hwmod = {
 418         .name           = "timer11",
 419         .mpu_irqs       = omap2_timer11_mpu_irqs,
 420         .main_clk       = "gpt11_fck",
 421         .prcm           = {
 422                 .omap2 = {
 423                         .prcm_reg_id = 1,
 424                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 425                         .module_offs = CORE_MOD,
 426                         .idlest_reg_id = 1,
 427                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 428                 },
 429         },
 430         .dev_attr       = &capability_pwm_dev_attr,
 431         .class          = &omap2xxx_timer_hwmod_class,
 432 };
 433
 434 /* timer12 */
 435
 436 struct omap_hwmod omap2xxx_timer12_hwmod = {
 437         .name           = "timer12",
 438         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 439         .main_clk       = "gpt12_fck",
 440         .prcm           = {
 441                 .omap2 = {
 442                         .prcm_reg_id = 1,
 443                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 444                         .module_offs = CORE_MOD,
 445                         .idlest_reg_id = 1,
 446                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 447                 },
 448         },
 449         .dev_attr       = &capability_pwm_dev_attr,
 450         .class          = &omap2xxx_timer_hwmod_class,
 451 };
 452
 453 /* wd_timer2 */
 454 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 455         .name           = "wd_timer2",
 456         .class          = &omap2xxx_wd_timer_hwmod_class,
 457         .main_clk       = "mpu_wdt_fck",
 458         .prcm           = {
 459                 .omap2 = {
 460                         .prcm_reg_id = 1,
 461                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 462                         .module_offs = WKUP_MOD,
 463                         .idlest_reg_id = 1,
 464                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 465                 },
 466         },
 467 };
 468
 469 /* UART1 */
 470
 471 struct omap_hwmod omap2xxx_uart1_hwmod = {
 472         .name           = "uart1",
 473         .mpu_irqs       = omap2_uart1_mpu_irqs,
 474         .sdma_reqs      = omap2_uart1_sdma_reqs,
 475         .main_clk       = "uart1_fck",
 476         .prcm           = {
 477                 .omap2 = {
 478                         .module_offs = CORE_MOD,
 479                         .prcm_reg_id = 1,
 480                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 481                         .idlest_reg_id = 1,
 482                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 483                 },
 484         },
 485         .class          = &omap2_uart_class,
 486 };
 487
 488 /* UART2 */
 489
 490 struct omap_hwmod omap2xxx_uart2_hwmod = {
 491         .name           = "uart2",
 492         .mpu_irqs       = omap2_uart2_mpu_irqs,
 493         .sdma_reqs      = omap2_uart2_sdma_reqs,
 494         .main_clk       = "uart2_fck",
 495         .prcm           = {
 496                 .omap2 = {
 497                         .module_offs = CORE_MOD,
 498                         .prcm_reg_id = 1,
 499                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 500                         .idlest_reg_id = 1,
 501                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 502                 },
 503         },
 504         .class          = &omap2_uart_class,
 505 };
 506
 507 /* UART3 */
 508
 509 struct omap_hwmod omap2xxx_uart3_hwmod = {
 510         .name           = "uart3",
 511         .mpu_irqs       = omap2_uart3_mpu_irqs,
 512         .sdma_reqs      = omap2_uart3_sdma_reqs,
 513         .main_clk       = "uart3_fck",
 514         .prcm           = {
 515                 .omap2 = {
 516                         .module_offs = CORE_MOD,
 517                         .prcm_reg_id = 2,
 518                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 519                         .idlest_reg_id = 2,
 520                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 521                 },
 522         },
 523         .class          = &omap2_uart_class,
 524 };
 525
 526 /* dss */
 527
 528 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 529         /*
 530          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 531          * driver does not use these clocks.
 532          */
 533         { .role = "tv_clk", .clk = "dss_54m_fck" },
 534         { .role = "sys_clk", .clk = "dss2_fck" },
 535 };
 536
 537 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 538         .name           = "dss_core",
 539         .class          = &omap2_dss_hwmod_class,
 540         .main_clk       = "dss1_fck", /* instead of dss_fck */
 541         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 542         .prcm           = {
 543                 .omap2 = {
 544                         .prcm_reg_id = 1,
 545                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 546                         .module_offs = CORE_MOD,
 547                         .idlest_reg_id = 1,
 548                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 549                 },
 550         },
 551         .opt_clks       = dss_opt_clks,
 552         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 553         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 554 };
 555
 556 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 557         .name           = "dss_dispc",
 558         .class          = &omap2_dispc_hwmod_class,
 559         .mpu_irqs       = omap2_dispc_irqs,
 560         .main_clk       = "dss1_fck",
 561         .prcm           = {
 562                 .omap2 = {
 563                         .prcm_reg_id = 1,
 564                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 565                         .module_offs = CORE_MOD,
 566                         .idlest_reg_id = 1,
 567                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 568                 },
 569         },
 570         .flags          = HWMOD_NO_IDLEST,
 571         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 572 };
 573
 574 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 575         { .role = "ick", .clk = "dss_ick" },
 576 };
 577
 578 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 579         .name           = "dss_rfbi",
 580         .class          = &omap2_rfbi_hwmod_class,
 581         .main_clk       = "dss1_fck",
 582         .prcm           = {
 583                 .omap2 = {
 584                         .prcm_reg_id = 1,
 585                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 586                         .module_offs = CORE_MOD,
 587                 },
 588         },
 589         .opt_clks       = dss_rfbi_opt_clks,
 590         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 591         .flags          = HWMOD_NO_IDLEST,
 592 };
 593
 594 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 595         .name           = "dss_venc",
 596         .class          = &omap2_venc_hwmod_class,
 597         .main_clk       = "dss_54m_fck",
 598         .prcm           = {
 599                 .omap2 = {
 600                         .prcm_reg_id = 1,
 601                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 602                         .module_offs = CORE_MOD,
 603                 },
 604         },
 605         .flags          = HWMOD_NO_IDLEST,
 606 };
 607
 608 /* gpio dev_attr */
 609 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 610         .bank_width = 32,
 611         .dbck_flag = false,
 612 };
 613
 614 /* gpio1 */
 615 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 616         .name           = "gpio1",
 617         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 618         .mpu_irqs       = omap2_gpio1_irqs,
 619         .main_clk       = "gpios_fck",
 620         .prcm           = {
 621                 .omap2 = {
 622                         .prcm_reg_id = 1,
 623                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 624                         .module_offs = WKUP_MOD,
 625                         .idlest_reg_id = 1,
 626                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 627                 },
 628         },
 629         .class          = &omap2xxx_gpio_hwmod_class,
 630         .dev_attr       = &omap2xxx_gpio_dev_attr,
 631 };
 632
 633 /* gpio2 */
 634 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 635         .name           = "gpio2",
 636         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 637         .mpu_irqs       = omap2_gpio2_irqs,
 638         .main_clk       = "gpios_fck",
 639         .prcm           = {
 640                 .omap2 = {
 641                         .prcm_reg_id = 1,
 642                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 643                         .module_offs = WKUP_MOD,
 644                         .idlest_reg_id = 1,
 645                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 646                 },
 647         },
 648         .class          = &omap2xxx_gpio_hwmod_class,
 649         .dev_attr       = &omap2xxx_gpio_dev_attr,
 650 };
 651
 652 /* gpio3 */
 653 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 654         .name           = "gpio3",
 655         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 656         .mpu_irqs       = omap2_gpio3_irqs,
 657         .main_clk       = "gpios_fck",
 658         .prcm           = {
 659                 .omap2 = {
 660                         .prcm_reg_id = 1,
 661                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 662                         .module_offs = WKUP_MOD,
 663                         .idlest_reg_id = 1,
 664                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 665                 },
 666         },
 667         .class          = &omap2xxx_gpio_hwmod_class,
 668         .dev_attr       = &omap2xxx_gpio_dev_attr,
 669 };
 670
 671 /* gpio4 */
 672 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 673         .name           = "gpio4",
 674         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 675         .mpu_irqs       = omap2_gpio4_irqs,
 676         .main_clk       = "gpios_fck",
 677         .prcm           = {
 678                 .omap2 = {
 679                         .prcm_reg_id = 1,
 680                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 681                         .module_offs = WKUP_MOD,
 682                         .idlest_reg_id = 1,
 683                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 684                 },
 685         },
 686         .class          = &omap2xxx_gpio_hwmod_class,
 687         .dev_attr       = &omap2xxx_gpio_dev_attr,
 688 };
 689
 690 /* mcspi1 */
 691 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 692         .num_chipselect = 4,
 693 };
 694
 695 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 696         .name           = "mcspi1",
 697         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
 698         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
 699         .main_clk       = "mcspi1_fck",
 700         .prcm           = {
 701                 .omap2 = {
 702                         .module_offs = CORE_MOD,
 703                         .prcm_reg_id = 1,
 704                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 705                         .idlest_reg_id = 1,
 706                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 707                 },
 708         },
 709         .class          = &omap2xxx_mcspi_class,
 710         .dev_attr       = &omap_mcspi1_dev_attr,
 711 };
 712
 713 /* mcspi2 */
 714 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 715         .num_chipselect = 2,
 716 };
 717
 718 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 719         .name           = "mcspi2",
 720         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
 721         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
 722         .main_clk       = "mcspi2_fck",
 723         .prcm           = {
 724                 .omap2 = {
 725                         .module_offs = CORE_MOD,
 726                         .prcm_reg_id = 1,
 727                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 728                         .idlest_reg_id = 1,
 729                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 730                 },
 731         },
 732         .class          = &omap2xxx_mcspi_class,
 733         .dev_attr       = &omap_mcspi2_dev_attr,
 734 };
 735
 736
 737 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 738         .name   = "counter",
 739 };
 740
 741 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 742         .name           = "counter_32k",
 743         .main_clk       = "func_32k_ck",
 744         .prcm           = {
 745                 .omap2  = {
 746                         .module_offs = WKUP_MOD,
 747                         .prcm_reg_id = 1,
 748                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 749                         .idlest_reg_id = 1,
 750                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 751                 },
 752         },
 753         .class          = &omap2xxx_counter_hwmod_class,
 754 };