arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/mmc.h>
  25 #include <plat/l3_2xxx.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "prm-regbits-24xx.h"
  30 #include "cm-regbits-24xx.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * ALl of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 static struct omap_hwmod omap2430_mpu_hwmod;
  43 static struct omap_hwmod omap2430_iva_hwmod;
  44 static struct omap_hwmod omap2430_l3_main_hwmod;
  45 static struct omap_hwmod omap2430_l4_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_core_hwmod;
  47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  49 static struct omap_hwmod omap2430_dss_venc_hwmod;
  50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  51 static struct omap_hwmod omap2430_gpio1_hwmod;
  52 static struct omap_hwmod omap2430_gpio2_hwmod;
  53 static struct omap_hwmod omap2430_gpio3_hwmod;
  54 static struct omap_hwmod omap2430_gpio4_hwmod;
  55 static struct omap_hwmod omap2430_gpio5_hwmod;
  56 static struct omap_hwmod omap2430_dma_system_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  62 static struct omap_hwmod omap2430_mcspi1_hwmod;
  63 static struct omap_hwmod omap2430_mcspi2_hwmod;
  64 static struct omap_hwmod omap2430_mcspi3_hwmod;
  65 static struct omap_hwmod omap2430_mmc1_hwmod;
  66 static struct omap_hwmod omap2430_mmc2_hwmod;
  67
  68 /* L3 -> L4_CORE interface */
  69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  70         .master = &omap2430_l3_main_hwmod,
  71         .slave  = &omap2430_l4_core_hwmod,
  72         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  73 };
  74
  75 /* MPU -> L3 interface */
  76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  77         .master = &omap2430_mpu_hwmod,
  78         .slave  = &omap2430_l3_main_hwmod,
  79         .user   = OCP_USER_MPU,
  80 };
  81
  82 /* Slave interfaces on the L3 interconnect */
  83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  84         &omap2430_mpu__l3_main,
  85 };
  86
  87 /* DSS -> l3 */
  88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  89         .master         = &omap2430_dss_core_hwmod,
  90         .slave          = &omap2430_l3_main_hwmod,
  91         .fw = {
  92                 .omap2 = {
  93                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  94                         .flags  = OMAP_FIREWALL_L3,
  95                 }
  96         },
  97         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  98 };
  99
 100 /* Master interfaces on the L3 interconnect */
 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
 102         &omap2430_l3_main__l4_core,
 103 };
 104
 105 /* L3 */
 106 static struct omap_hwmod omap2430_l3_main_hwmod = {
 107         .name           = "l3_main",
 108         .class          = &l3_hwmod_class,
 109         .masters        = omap2430_l3_main_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 111         .slaves         = omap2430_l3_main_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 113         .flags          = HWMOD_NO_IDLEST,
 114 };
 115
 116 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 117 static struct omap_hwmod omap2430_uart1_hwmod;
 118 static struct omap_hwmod omap2430_uart2_hwmod;
 119 static struct omap_hwmod omap2430_uart3_hwmod;
 120 static struct omap_hwmod omap2430_i2c1_hwmod;
 121 static struct omap_hwmod omap2430_i2c2_hwmod;
 122
 123 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 124
 125 /* l3_core -> usbhsotg  interface */
 126 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 127         .master         = &omap2430_usbhsotg_hwmod,
 128         .slave          = &omap2430_l3_main_hwmod,
 129         .clk            = "core_l3_ck",
 130         .user           = OCP_USER_MPU,
 131 };
 132
 133 /* L4 CORE -> I2C1 interface */
 134 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 135         .master         = &omap2430_l4_core_hwmod,
 136         .slave          = &omap2430_i2c1_hwmod,
 137         .clk            = "i2c1_ick",
 138         .addr           = omap2_i2c1_addr_space,
 139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 140 };
 141
 142 /* L4 CORE -> I2C2 interface */
 143 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 144         .master         = &omap2430_l4_core_hwmod,
 145         .slave          = &omap2430_i2c2_hwmod,
 146         .clk            = "i2c2_ick",
 147         .addr           = omap2_i2c2_addr_space,
 148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 149 };
 150
 151 /* L4_CORE -> L4_WKUP interface */
 152 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 153         .master = &omap2430_l4_core_hwmod,
 154         .slave  = &omap2430_l4_wkup_hwmod,
 155         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 /* L4 CORE -> UART1 interface */
 159 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 160         .master         = &omap2430_l4_core_hwmod,
 161         .slave          = &omap2430_uart1_hwmod,
 162         .clk            = "uart1_ick",
 163         .addr           = omap2xxx_uart1_addr_space,
 164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 165 };
 166
 167 /* L4 CORE -> UART2 interface */
 168 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 169         .master         = &omap2430_l4_core_hwmod,
 170         .slave          = &omap2430_uart2_hwmod,
 171         .clk            = "uart2_ick",
 172         .addr           = omap2xxx_uart2_addr_space,
 173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 174 };
 175
 176 /* L4 PER -> UART3 interface */
 177 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 178         .master         = &omap2430_l4_core_hwmod,
 179         .slave          = &omap2430_uart3_hwmod,
 180         .clk            = "uart3_ick",
 181         .addr           = omap2xxx_uart3_addr_space,
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /*
 186 * usbhsotg interface data
 187 */
 188 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 189         {
 190                 .pa_start       = OMAP243X_HS_BASE,
 191                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 192                 .flags          = ADDR_TYPE_RT
 193         },
 194         { }
 195 };
 196
 197 /*  l4_core ->usbhsotg  interface */
 198 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 199         .master         = &omap2430_l4_core_hwmod,
 200         .slave          = &omap2430_usbhsotg_hwmod,
 201         .clk            = "usb_l4_ick",
 202         .addr           = omap2430_usbhsotg_addrs,
 203         .user           = OCP_USER_MPU,
 204 };
 205
 206 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 207         &omap2430_usbhsotg__l3,
 208 };
 209
 210 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 211         &omap2430_l4_core__usbhsotg,
 212 };
 213
 214 /* L4 CORE -> MMC1 interface */
 215 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 216         .master         = &omap2430_l4_core_hwmod,
 217         .slave          = &omap2430_mmc1_hwmod,
 218         .clk            = "mmchs1_ick",
 219         .addr           = omap2430_mmc1_addr_space,
 220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 221 };
 222
 223 /* L4 CORE -> MMC2 interface */
 224 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 225         .master         = &omap2430_l4_core_hwmod,
 226         .slave          = &omap2430_mmc2_hwmod,
 227         .clk            = "mmchs2_ick",
 228         .addr           = omap2430_mmc2_addr_space,
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* Slave interfaces on the L4_CORE interconnect */
 233 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 234         &omap2430_l3_main__l4_core,
 235 };
 236
 237 /* Master interfaces on the L4_CORE interconnect */
 238 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 239         &omap2430_l4_core__l4_wkup,
 240         &omap2430_l4_core__mmc1,
 241         &omap2430_l4_core__mmc2,
 242 };
 243
 244 /* L4 CORE */
 245 static struct omap_hwmod omap2430_l4_core_hwmod = {
 246         .name           = "l4_core",
 247         .class          = &l4_hwmod_class,
 248         .masters        = omap2430_l4_core_masters,
 249         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 250         .slaves         = omap2430_l4_core_slaves,
 251         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 252         .flags          = HWMOD_NO_IDLEST,
 253 };
 254
 255 /* Slave interfaces on the L4_WKUP interconnect */
 256 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 257         &omap2430_l4_core__l4_wkup,
 258         &omap2_l4_core__uart1,
 259         &omap2_l4_core__uart2,
 260         &omap2_l4_core__uart3,
 261 };
 262
 263 /* Master interfaces on the L4_WKUP interconnect */
 264 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 265 };
 266
 267 /* l4 core -> mcspi1 interface */
 268 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 269         .master         = &omap2430_l4_core_hwmod,
 270         .slave          = &omap2430_mcspi1_hwmod,
 271         .clk            = "mcspi1_ick",
 272         .addr           = omap2_mcspi1_addr_space,
 273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 274 };
 275
 276 /* l4 core -> mcspi2 interface */
 277 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 278         .master         = &omap2430_l4_core_hwmod,
 279         .slave          = &omap2430_mcspi2_hwmod,
 280         .clk            = "mcspi2_ick",
 281         .addr           = omap2_mcspi2_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* l4 core -> mcspi3 interface */
 286 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 287         .master         = &omap2430_l4_core_hwmod,
 288         .slave          = &omap2430_mcspi3_hwmod,
 289         .clk            = "mcspi3_ick",
 290         .addr           = omap2430_mcspi3_addr_space,
 291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 292 };
 293
 294 /* L4 WKUP */
 295 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 296         .name           = "l4_wkup",
 297         .class          = &l4_hwmod_class,
 298         .masters        = omap2430_l4_wkup_masters,
 299         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 300         .slaves         = omap2430_l4_wkup_slaves,
 301         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 302         .flags          = HWMOD_NO_IDLEST,
 303 };
 304
 305 /* Master interfaces on the MPU device */
 306 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 307         &omap2430_mpu__l3_main,
 308 };
 309
 310 /* MPU */
 311 static struct omap_hwmod omap2430_mpu_hwmod = {
 312         .name           = "mpu",
 313         .class          = &mpu_hwmod_class,
 314         .main_clk       = "mpu_ck",
 315         .masters        = omap2430_mpu_masters,
 316         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 317 };
 318
 319 /*
 320  * IVA2_1 interface data
 321  */
 322
 323 /* IVA2 <- L3 interface */
 324 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 325         .master         = &omap2430_l3_main_hwmod,
 326         .slave          = &omap2430_iva_hwmod,
 327         .clk            = "dsp_fck",
 328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 329 };
 330
 331 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 332         &omap2430_l3__iva,
 333 };
 334
 335 /*
 336  * IVA2 (IVA2)
 337  */
 338
 339 static struct omap_hwmod omap2430_iva_hwmod = {
 340         .name           = "iva",
 341         .class          = &iva_hwmod_class,
 342         .masters        = omap2430_iva_masters,
 343         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 344 };
 345
 346 /* timer1 */
 347 static struct omap_hwmod omap2430_timer1_hwmod;
 348
 349 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 350         {
 351                 .pa_start       = 0x49018000,
 352                 .pa_end         = 0x49018000 + SZ_1K - 1,
 353                 .flags          = ADDR_TYPE_RT
 354         },
 355         { }
 356 };
 357
 358 /* l4_wkup -> timer1 */
 359 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 360         .master         = &omap2430_l4_wkup_hwmod,
 361         .slave          = &omap2430_timer1_hwmod,
 362         .clk            = "gpt1_ick",
 363         .addr           = omap2430_timer1_addrs,
 364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 365 };
 366
 367 /* timer1 slave port */
 368 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 369         &omap2430_l4_wkup__timer1,
 370 };
 371
 372 /* timer1 hwmod */
 373 static struct omap_hwmod omap2430_timer1_hwmod = {
 374         .name           = "timer1",
 375         .mpu_irqs       = omap2_timer1_mpu_irqs,
 376         .main_clk       = "gpt1_fck",
 377         .prcm           = {
 378                 .omap2 = {
 379                         .prcm_reg_id = 1,
 380                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 381                         .module_offs = WKUP_MOD,
 382                         .idlest_reg_id = 1,
 383                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 384                 },
 385         },
 386         .slaves         = omap2430_timer1_slaves,
 387         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 388         .class          = &omap2xxx_timer_hwmod_class,
 389 };
 390
 391 /* timer2 */
 392 static struct omap_hwmod omap2430_timer2_hwmod;
 393
 394 /* l4_core -> timer2 */
 395 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 396         .master         = &omap2430_l4_core_hwmod,
 397         .slave          = &omap2430_timer2_hwmod,
 398         .clk            = "gpt2_ick",
 399         .addr           = omap2xxx_timer2_addrs,
 400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 401 };
 402
 403 /* timer2 slave port */
 404 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 405         &omap2430_l4_core__timer2,
 406 };
 407
 408 /* timer2 hwmod */
 409 static struct omap_hwmod omap2430_timer2_hwmod = {
 410         .name           = "timer2",
 411         .mpu_irqs       = omap2_timer2_mpu_irqs,
 412         .main_clk       = "gpt2_fck",
 413         .prcm           = {
 414                 .omap2 = {
 415                         .prcm_reg_id = 1,
 416                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 417                         .module_offs = CORE_MOD,
 418                         .idlest_reg_id = 1,
 419                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 420                 },
 421         },
 422         .slaves         = omap2430_timer2_slaves,
 423         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 424         .class          = &omap2xxx_timer_hwmod_class,
 425 };
 426
 427 /* timer3 */
 428 static struct omap_hwmod omap2430_timer3_hwmod;
 429
 430 /* l4_core -> timer3 */
 431 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 432         .master         = &omap2430_l4_core_hwmod,
 433         .slave          = &omap2430_timer3_hwmod,
 434         .clk            = "gpt3_ick",
 435         .addr           = omap2xxx_timer3_addrs,
 436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 437 };
 438
 439 /* timer3 slave port */
 440 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 441         &omap2430_l4_core__timer3,
 442 };
 443
 444 /* timer3 hwmod */
 445 static struct omap_hwmod omap2430_timer3_hwmod = {
 446         .name           = "timer3",
 447         .mpu_irqs       = omap2_timer3_mpu_irqs,
 448         .main_clk       = "gpt3_fck",
 449         .prcm           = {
 450                 .omap2 = {
 451                         .prcm_reg_id = 1,
 452                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 453                         .module_offs = CORE_MOD,
 454                         .idlest_reg_id = 1,
 455                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 456                 },
 457         },
 458         .slaves         = omap2430_timer3_slaves,
 459         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 460         .class          = &omap2xxx_timer_hwmod_class,
 461 };
 462
 463 /* timer4 */
 464 static struct omap_hwmod omap2430_timer4_hwmod;
 465
 466 /* l4_core -> timer4 */
 467 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 468         .master         = &omap2430_l4_core_hwmod,
 469         .slave          = &omap2430_timer4_hwmod,
 470         .clk            = "gpt4_ick",
 471         .addr           = omap2xxx_timer4_addrs,
 472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 473 };
 474
 475 /* timer4 slave port */
 476 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 477         &omap2430_l4_core__timer4,
 478 };
 479
 480 /* timer4 hwmod */
 481 static struct omap_hwmod omap2430_timer4_hwmod = {
 482         .name           = "timer4",
 483         .mpu_irqs       = omap2_timer4_mpu_irqs,
 484         .main_clk       = "gpt4_fck",
 485         .prcm           = {
 486                 .omap2 = {
 487                         .prcm_reg_id = 1,
 488                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 489                         .module_offs = CORE_MOD,
 490                         .idlest_reg_id = 1,
 491                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 492                 },
 493         },
 494         .slaves         = omap2430_timer4_slaves,
 495         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 496         .class          = &omap2xxx_timer_hwmod_class,
 497 };
 498
 499 /* timer5 */
 500 static struct omap_hwmod omap2430_timer5_hwmod;
 501
 502 /* l4_core -> timer5 */
 503 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 504         .master         = &omap2430_l4_core_hwmod,
 505         .slave          = &omap2430_timer5_hwmod,
 506         .clk            = "gpt5_ick",
 507         .addr           = omap2xxx_timer5_addrs,
 508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 509 };
 510
 511 /* timer5 slave port */
 512 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 513         &omap2430_l4_core__timer5,
 514 };
 515
 516 /* timer5 hwmod */
 517 static struct omap_hwmod omap2430_timer5_hwmod = {
 518         .name           = "timer5",
 519         .mpu_irqs       = omap2_timer5_mpu_irqs,
 520         .main_clk       = "gpt5_fck",
 521         .prcm           = {
 522                 .omap2 = {
 523                         .prcm_reg_id = 1,
 524                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 525                         .module_offs = CORE_MOD,
 526                         .idlest_reg_id = 1,
 527                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 528                 },
 529         },
 530         .slaves         = omap2430_timer5_slaves,
 531         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 532         .class          = &omap2xxx_timer_hwmod_class,
 533 };
 534
 535 /* timer6 */
 536 static struct omap_hwmod omap2430_timer6_hwmod;
 537
 538 /* l4_core -> timer6 */
 539 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 540         .master         = &omap2430_l4_core_hwmod,
 541         .slave          = &omap2430_timer6_hwmod,
 542         .clk            = "gpt6_ick",
 543         .addr           = omap2xxx_timer6_addrs,
 544         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 545 };
 546
 547 /* timer6 slave port */
 548 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 549         &omap2430_l4_core__timer6,
 550 };
 551
 552 /* timer6 hwmod */
 553 static struct omap_hwmod omap2430_timer6_hwmod = {
 554         .name           = "timer6",
 555         .mpu_irqs       = omap2_timer6_mpu_irqs,
 556         .main_clk       = "gpt6_fck",
 557         .prcm           = {
 558                 .omap2 = {
 559                         .prcm_reg_id = 1,
 560                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 561                         .module_offs = CORE_MOD,
 562                         .idlest_reg_id = 1,
 563                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 564                 },
 565         },
 566         .slaves         = omap2430_timer6_slaves,
 567         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 568         .class          = &omap2xxx_timer_hwmod_class,
 569 };
 570
 571 /* timer7 */
 572 static struct omap_hwmod omap2430_timer7_hwmod;
 573
 574 /* l4_core -> timer7 */
 575 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 576         .master         = &omap2430_l4_core_hwmod,
 577         .slave          = &omap2430_timer7_hwmod,
 578         .clk            = "gpt7_ick",
 579         .addr           = omap2xxx_timer7_addrs,
 580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 581 };
 582
 583 /* timer7 slave port */
 584 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 585         &omap2430_l4_core__timer7,
 586 };
 587
 588 /* timer7 hwmod */
 589 static struct omap_hwmod omap2430_timer7_hwmod = {
 590         .name           = "timer7",
 591         .mpu_irqs       = omap2_timer7_mpu_irqs,
 592         .main_clk       = "gpt7_fck",
 593         .prcm           = {
 594                 .omap2 = {
 595                         .prcm_reg_id = 1,
 596                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 597                         .module_offs = CORE_MOD,
 598                         .idlest_reg_id = 1,
 599                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 600                 },
 601         },
 602         .slaves         = omap2430_timer7_slaves,
 603         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 604         .class          = &omap2xxx_timer_hwmod_class,
 605 };
 606
 607 /* timer8 */
 608 static struct omap_hwmod omap2430_timer8_hwmod;
 609
 610 /* l4_core -> timer8 */
 611 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 612         .master         = &omap2430_l4_core_hwmod,
 613         .slave          = &omap2430_timer8_hwmod,
 614         .clk            = "gpt8_ick",
 615         .addr           = omap2xxx_timer8_addrs,
 616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 617 };
 618
 619 /* timer8 slave port */
 620 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 621         &omap2430_l4_core__timer8,
 622 };
 623
 624 /* timer8 hwmod */
 625 static struct omap_hwmod omap2430_timer8_hwmod = {
 626         .name           = "timer8",
 627         .mpu_irqs       = omap2_timer8_mpu_irqs,
 628         .main_clk       = "gpt8_fck",
 629         .prcm           = {
 630                 .omap2 = {
 631                         .prcm_reg_id = 1,
 632                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 633                         .module_offs = CORE_MOD,
 634                         .idlest_reg_id = 1,
 635                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 636                 },
 637         },
 638         .slaves         = omap2430_timer8_slaves,
 639         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 640         .class          = &omap2xxx_timer_hwmod_class,
 641 };
 642
 643 /* timer9 */
 644 static struct omap_hwmod omap2430_timer9_hwmod;
 645
 646 /* l4_core -> timer9 */
 647 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 648         .master         = &omap2430_l4_core_hwmod,
 649         .slave          = &omap2430_timer9_hwmod,
 650         .clk            = "gpt9_ick",
 651         .addr           = omap2xxx_timer9_addrs,
 652         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 653 };
 654
 655 /* timer9 slave port */
 656 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 657         &omap2430_l4_core__timer9,
 658 };
 659
 660 /* timer9 hwmod */
 661 static struct omap_hwmod omap2430_timer9_hwmod = {
 662         .name           = "timer9",
 663         .mpu_irqs       = omap2_timer9_mpu_irqs,
 664         .main_clk       = "gpt9_fck",
 665         .prcm           = {
 666                 .omap2 = {
 667                         .prcm_reg_id = 1,
 668                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 669                         .module_offs = CORE_MOD,
 670                         .idlest_reg_id = 1,
 671                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 672                 },
 673         },
 674         .slaves         = omap2430_timer9_slaves,
 675         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 676         .class          = &omap2xxx_timer_hwmod_class,
 677 };
 678
 679 /* timer10 */
 680 static struct omap_hwmod omap2430_timer10_hwmod;
 681
 682 /* l4_core -> timer10 */
 683 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 684         .master         = &omap2430_l4_core_hwmod,
 685         .slave          = &omap2430_timer10_hwmod,
 686         .clk            = "gpt10_ick",
 687         .addr           = omap2_timer10_addrs,
 688         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 689 };
 690
 691 /* timer10 slave port */
 692 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 693         &omap2430_l4_core__timer10,
 694 };
 695
 696 /* timer10 hwmod */
 697 static struct omap_hwmod omap2430_timer10_hwmod = {
 698         .name           = "timer10",
 699         .mpu_irqs       = omap2_timer10_mpu_irqs,
 700         .main_clk       = "gpt10_fck",
 701         .prcm           = {
 702                 .omap2 = {
 703                         .prcm_reg_id = 1,
 704                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 705                         .module_offs = CORE_MOD,
 706                         .idlest_reg_id = 1,
 707                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 708                 },
 709         },
 710         .slaves         = omap2430_timer10_slaves,
 711         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 712         .class          = &omap2xxx_timer_hwmod_class,
 713 };
 714
 715 /* timer11 */
 716 static struct omap_hwmod omap2430_timer11_hwmod;
 717
 718 /* l4_core -> timer11 */
 719 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 720         .master         = &omap2430_l4_core_hwmod,
 721         .slave          = &omap2430_timer11_hwmod,
 722         .clk            = "gpt11_ick",
 723         .addr           = omap2_timer11_addrs,
 724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 725 };
 726
 727 /* timer11 slave port */
 728 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 729         &omap2430_l4_core__timer11,
 730 };
 731
 732 /* timer11 hwmod */
 733 static struct omap_hwmod omap2430_timer11_hwmod = {
 734         .name           = "timer11",
 735         .mpu_irqs       = omap2_timer11_mpu_irqs,
 736         .main_clk       = "gpt11_fck",
 737         .prcm           = {
 738                 .omap2 = {
 739                         .prcm_reg_id = 1,
 740                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 741                         .module_offs = CORE_MOD,
 742                         .idlest_reg_id = 1,
 743                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 744                 },
 745         },
 746         .slaves         = omap2430_timer11_slaves,
 747         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
 748         .class          = &omap2xxx_timer_hwmod_class,
 749 };
 750
 751 /* timer12 */
 752 static struct omap_hwmod omap2430_timer12_hwmod;
 753
 754 /* l4_core -> timer12 */
 755 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
 756         .master         = &omap2430_l4_core_hwmod,
 757         .slave          = &omap2430_timer12_hwmod,
 758         .clk            = "gpt12_ick",
 759         .addr           = omap2xxx_timer12_addrs,
 760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 761 };
 762
 763 /* timer12 slave port */
 764 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 765         &omap2430_l4_core__timer12,
 766 };
 767
 768 /* timer12 hwmod */
 769 static struct omap_hwmod omap2430_timer12_hwmod = {
 770         .name           = "timer12",
 771         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 772         .main_clk       = "gpt12_fck",
 773         .prcm           = {
 774                 .omap2 = {
 775                         .prcm_reg_id = 1,
 776                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 777                         .module_offs = CORE_MOD,
 778                         .idlest_reg_id = 1,
 779                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 780                 },
 781         },
 782         .slaves         = omap2430_timer12_slaves,
 783         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
 784         .class          = &omap2xxx_timer_hwmod_class,
 785 };
 786
 787 /* l4_wkup -> wd_timer2 */
 788 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 789         {
 790                 .pa_start       = 0x49016000,
 791                 .pa_end         = 0x4901607f,
 792                 .flags          = ADDR_TYPE_RT
 793         },
 794         { }
 795 };
 796
 797 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 798         .master         = &omap2430_l4_wkup_hwmod,
 799         .slave          = &omap2430_wd_timer2_hwmod,
 800         .clk            = "mpu_wdt_ick",
 801         .addr           = omap2430_wd_timer2_addrs,
 802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 803 };
 804
 805 /* wd_timer2 */
 806 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 807         &omap2430_l4_wkup__wd_timer2,
 808 };
 809
 810 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 811         .name           = "wd_timer2",
 812         .class          = &omap2xxx_wd_timer_hwmod_class,
 813         .main_clk       = "mpu_wdt_fck",
 814         .prcm           = {
 815                 .omap2 = {
 816                         .prcm_reg_id = 1,
 817                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 818                         .module_offs = WKUP_MOD,
 819                         .idlest_reg_id = 1,
 820                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 821                 },
 822         },
 823         .slaves         = omap2430_wd_timer2_slaves,
 824         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
 825 };
 826
 827 /* UART1 */
 828
 829 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
 830         &omap2_l4_core__uart1,
 831 };
 832
 833 static struct omap_hwmod omap2430_uart1_hwmod = {
 834         .name           = "uart1",
 835         .mpu_irqs       = omap2_uart1_mpu_irqs,
 836         .sdma_reqs      = omap2_uart1_sdma_reqs,
 837         .main_clk       = "uart1_fck",
 838         .prcm           = {
 839                 .omap2 = {
 840                         .module_offs = CORE_MOD,
 841                         .prcm_reg_id = 1,
 842                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 843                         .idlest_reg_id = 1,
 844                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 845                 },
 846         },
 847         .slaves         = omap2430_uart1_slaves,
 848         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
 849         .class          = &omap2_uart_class,
 850 };
 851
 852 /* UART2 */
 853
 854 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
 855         &omap2_l4_core__uart2,
 856 };
 857
 858 static struct omap_hwmod omap2430_uart2_hwmod = {
 859         .name           = "uart2",
 860         .mpu_irqs       = omap2_uart2_mpu_irqs,
 861         .sdma_reqs      = omap2_uart2_sdma_reqs,
 862         .main_clk       = "uart2_fck",
 863         .prcm           = {
 864                 .omap2 = {
 865                         .module_offs = CORE_MOD,
 866                         .prcm_reg_id = 1,
 867                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 868                         .idlest_reg_id = 1,
 869                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 870                 },
 871         },
 872         .slaves         = omap2430_uart2_slaves,
 873         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
 874         .class          = &omap2_uart_class,
 875 };
 876
 877 /* UART3 */
 878
 879 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
 880         &omap2_l4_core__uart3,
 881 };
 882
 883 static struct omap_hwmod omap2430_uart3_hwmod = {
 884         .name           = "uart3",
 885         .mpu_irqs       = omap2_uart3_mpu_irqs,
 886         .sdma_reqs      = omap2_uart3_sdma_reqs,
 887         .main_clk       = "uart3_fck",
 888         .prcm           = {
 889                 .omap2 = {
 890                         .module_offs = CORE_MOD,
 891                         .prcm_reg_id = 2,
 892                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 893                         .idlest_reg_id = 2,
 894                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 895                 },
 896         },
 897         .slaves         = omap2430_uart3_slaves,
 898         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
 899         .class          = &omap2_uart_class,
 900 };
 901
 902 /* dss */
 903 /* dss master ports */
 904 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
 905         &omap2430_dss__l3,
 906 };
 907
 908 /* l4_core -> dss */
 909 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
 910         .master         = &omap2430_l4_core_hwmod,
 911         .slave          = &omap2430_dss_core_hwmod,
 912         .clk            = "dss_ick",
 913         .addr           = omap2_dss_addrs,
 914         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 915 };
 916
 917 /* dss slave ports */
 918 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 919         &omap2430_l4_core__dss,
 920 };
 921
 922 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 923         { .role = "tv_clk", .clk = "dss_54m_fck" },
 924         { .role = "sys_clk", .clk = "dss2_fck" },
 925 };
 926
 927 static struct omap_hwmod omap2430_dss_core_hwmod = {
 928         .name           = "dss_core",
 929         .class          = &omap2_dss_hwmod_class,
 930         .main_clk       = "dss1_fck", /* instead of dss_fck */
 931         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 932         .prcm           = {
 933                 .omap2 = {
 934                         .prcm_reg_id = 1,
 935                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 936                         .module_offs = CORE_MOD,
 937                         .idlest_reg_id = 1,
 938                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 939                 },
 940         },
 941         .opt_clks       = dss_opt_clks,
 942         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 943         .slaves         = omap2430_dss_slaves,
 944         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
 945         .masters        = omap2430_dss_masters,
 946         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
 947         .flags          = HWMOD_NO_IDLEST,
 948 };
 949
 950 /* l4_core -> dss_dispc */
 951 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
 952         .master         = &omap2430_l4_core_hwmod,
 953         .slave          = &omap2430_dss_dispc_hwmod,
 954         .clk            = "dss_ick",
 955         .addr           = omap2_dss_dispc_addrs,
 956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 957 };
 958
 959 /* dss_dispc slave ports */
 960 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
 961         &omap2430_l4_core__dss_dispc,
 962 };
 963
 964 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
 965         .name           = "dss_dispc",
 966         .class          = &omap2_dispc_hwmod_class,
 967         .mpu_irqs       = omap2_dispc_irqs,
 968         .main_clk       = "dss1_fck",
 969         .prcm           = {
 970                 .omap2 = {
 971                         .prcm_reg_id = 1,
 972                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 973                         .module_offs = CORE_MOD,
 974                         .idlest_reg_id = 1,
 975                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 976                 },
 977         },
 978         .slaves         = omap2430_dss_dispc_slaves,
 979         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
 980         .flags          = HWMOD_NO_IDLEST,
 981 };
 982
 983 /* l4_core -> dss_rfbi */
 984 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
 985         .master         = &omap2430_l4_core_hwmod,
 986         .slave          = &omap2430_dss_rfbi_hwmod,
 987         .clk            = "dss_ick",
 988         .addr           = omap2_dss_rfbi_addrs,
 989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 990 };
 991
 992 /* dss_rfbi slave ports */
 993 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
 994         &omap2430_l4_core__dss_rfbi,
 995 };
 996
 997 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
 998         .name           = "dss_rfbi",
 999         .class          = &omap2_rfbi_hwmod_class,
1000         .main_clk       = "dss1_fck",
1001         .prcm           = {
1002                 .omap2 = {
1003                         .prcm_reg_id = 1,
1004                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1005                         .module_offs = CORE_MOD,
1006                 },
1007         },
1008         .slaves         = omap2430_dss_rfbi_slaves,
1009         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1010         .flags          = HWMOD_NO_IDLEST,
1011 };
1012
1013 /* l4_core -> dss_venc */
1014 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1015         .master         = &omap2430_l4_core_hwmod,
1016         .slave          = &omap2430_dss_venc_hwmod,
1017         .clk            = "dss_54m_fck",
1018         .addr           = omap2_dss_venc_addrs,
1019         .flags          = OCPIF_SWSUP_IDLE,
1020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1021 };
1022
1023 /* dss_venc slave ports */
1024 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1025         &omap2430_l4_core__dss_venc,
1026 };
1027
1028 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1029         .name           = "dss_venc",
1030         .class          = &omap2_venc_hwmod_class,
1031         .main_clk       = "dss1_fck",
1032         .prcm           = {
1033                 .omap2 = {
1034                         .prcm_reg_id = 1,
1035                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1036                         .module_offs = CORE_MOD,
1037                 },
1038         },
1039         .slaves         = omap2430_dss_venc_slaves,
1040         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1041         .flags          = HWMOD_NO_IDLEST,
1042 };
1043
1044 /* I2C common */
1045 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1046         .rev_offs       = 0x00,
1047         .sysc_offs      = 0x20,
1048         .syss_offs      = 0x10,
1049         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1050                            SYSS_HAS_RESET_STATUS),
1051         .sysc_fields    = &omap_hwmod_sysc_type1,
1052 };
1053
1054 static struct omap_hwmod_class i2c_class = {
1055         .name           = "i2c",
1056         .sysc           = &i2c_sysc,
1057         .rev            = OMAP_I2C_IP_VERSION_1,
1058         .reset          = &omap_i2c_reset,
1059 };
1060
1061 static struct omap_i2c_dev_attr i2c_dev_attr = {
1062         .fifo_depth     = 8, /* bytes */
1063         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1064                           OMAP_I2C_FLAG_BUS_SHIFT_2 |
1065                           OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1066 };
1067
1068 /* I2C1 */
1069
1070 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1071         &omap2430_l4_core__i2c1,
1072 };
1073
1074 static struct omap_hwmod omap2430_i2c1_hwmod = {
1075         .name           = "i2c1",
1076         .flags          = HWMOD_16BIT_REG,
1077         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1078         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1079         .main_clk       = "i2chs1_fck",
1080         .prcm           = {
1081                 .omap2 = {
1082                         /*
1083                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1084                          * I2CHS IP's do not follow the usual pattern.
1085                          * prcm_reg_id alone cannot be used to program
1086                          * the iclk and fclk. Needs to be handled using
1087                          * additional flags when clk handling is moved
1088                          * to hwmod framework.
1089                          */
1090                         .module_offs = CORE_MOD,
1091                         .prcm_reg_id = 1,
1092                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1093                         .idlest_reg_id = 1,
1094                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1095                 },
1096         },
1097         .slaves         = omap2430_i2c1_slaves,
1098         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1099         .class          = &i2c_class,
1100         .dev_attr       = &i2c_dev_attr,
1101 };
1102
1103 /* I2C2 */
1104
1105 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1106         &omap2430_l4_core__i2c2,
1107 };
1108
1109 static struct omap_hwmod omap2430_i2c2_hwmod = {
1110         .name           = "i2c2",
1111         .flags          = HWMOD_16BIT_REG,
1112         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1113         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1114         .main_clk       = "i2chs2_fck",
1115         .prcm           = {
1116                 .omap2 = {
1117                         .module_offs = CORE_MOD,
1118                         .prcm_reg_id = 1,
1119                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1120                         .idlest_reg_id = 1,
1121                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1122                 },
1123         },
1124         .slaves         = omap2430_i2c2_slaves,
1125         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1126         .class          = &i2c_class,
1127         .dev_attr       = &i2c_dev_attr,
1128 };
1129
1130 /* l4_wkup -> gpio1 */
1131 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1132         {
1133                 .pa_start       = 0x4900C000,
1134                 .pa_end         = 0x4900C1ff,
1135                 .flags          = ADDR_TYPE_RT
1136         },
1137         { }
1138 };
1139
1140 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1141         .master         = &omap2430_l4_wkup_hwmod,
1142         .slave          = &omap2430_gpio1_hwmod,
1143         .clk            = "gpios_ick",
1144         .addr           = omap2430_gpio1_addr_space,
1145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1146 };
1147
1148 /* l4_wkup -> gpio2 */
1149 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1150         {
1151                 .pa_start       = 0x4900E000,
1152                 .pa_end         = 0x4900E1ff,
1153                 .flags          = ADDR_TYPE_RT
1154         },
1155         { }
1156 };
1157
1158 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1159         .master         = &omap2430_l4_wkup_hwmod,
1160         .slave          = &omap2430_gpio2_hwmod,
1161         .clk            = "gpios_ick",
1162         .addr           = omap2430_gpio2_addr_space,
1163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1164 };
1165
1166 /* l4_wkup -> gpio3 */
1167 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1168         {
1169                 .pa_start       = 0x49010000,
1170                 .pa_end         = 0x490101ff,
1171                 .flags          = ADDR_TYPE_RT
1172         },
1173         { }
1174 };
1175
1176 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1177         .master         = &omap2430_l4_wkup_hwmod,
1178         .slave          = &omap2430_gpio3_hwmod,
1179         .clk            = "gpios_ick",
1180         .addr           = omap2430_gpio3_addr_space,
1181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1182 };
1183
1184 /* l4_wkup -> gpio4 */
1185 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1186         {
1187                 .pa_start       = 0x49012000,
1188                 .pa_end         = 0x490121ff,
1189                 .flags          = ADDR_TYPE_RT
1190         },
1191         { }
1192 };
1193
1194 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1195         .master         = &omap2430_l4_wkup_hwmod,
1196         .slave          = &omap2430_gpio4_hwmod,
1197         .clk            = "gpios_ick",
1198         .addr           = omap2430_gpio4_addr_space,
1199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1200 };
1201
1202 /* l4_core -> gpio5 */
1203 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1204         {
1205                 .pa_start       = 0x480B6000,
1206                 .pa_end         = 0x480B61ff,
1207                 .flags          = ADDR_TYPE_RT
1208         },
1209         { }
1210 };
1211
1212 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1213         .master         = &omap2430_l4_core_hwmod,
1214         .slave          = &omap2430_gpio5_hwmod,
1215         .clk            = "gpio5_ick",
1216         .addr           = omap2430_gpio5_addr_space,
1217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1218 };
1219
1220 /* gpio dev_attr */
1221 static struct omap_gpio_dev_attr gpio_dev_attr = {
1222         .bank_width = 32,
1223         .dbck_flag = false,
1224 };
1225
1226 /* gpio1 */
1227 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1228         &omap2430_l4_wkup__gpio1,
1229 };
1230
1231 static struct omap_hwmod omap2430_gpio1_hwmod = {
1232         .name           = "gpio1",
1233         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1234         .mpu_irqs       = omap2_gpio1_irqs,
1235         .main_clk       = "gpios_fck",
1236         .prcm           = {
1237                 .omap2 = {
1238                         .prcm_reg_id = 1,
1239                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1240                         .module_offs = WKUP_MOD,
1241                         .idlest_reg_id = 1,
1242                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1243                 },
1244         },
1245         .slaves         = omap2430_gpio1_slaves,
1246         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1247         .class          = &omap2xxx_gpio_hwmod_class,
1248         .dev_attr       = &gpio_dev_attr,
1249 };
1250
1251 /* gpio2 */
1252 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1253         &omap2430_l4_wkup__gpio2,
1254 };
1255
1256 static struct omap_hwmod omap2430_gpio2_hwmod = {
1257         .name           = "gpio2",
1258         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1259         .mpu_irqs       = omap2_gpio2_irqs,
1260         .main_clk       = "gpios_fck",
1261         .prcm           = {
1262                 .omap2 = {
1263                         .prcm_reg_id = 1,
1264                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1265                         .module_offs = WKUP_MOD,
1266                         .idlest_reg_id = 1,
1267                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1268                 },
1269         },
1270         .slaves         = omap2430_gpio2_slaves,
1271         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1272         .class          = &omap2xxx_gpio_hwmod_class,
1273         .dev_attr       = &gpio_dev_attr,
1274 };
1275
1276 /* gpio3 */
1277 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1278         &omap2430_l4_wkup__gpio3,
1279 };
1280
1281 static struct omap_hwmod omap2430_gpio3_hwmod = {
1282         .name           = "gpio3",
1283         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1284         .mpu_irqs       = omap2_gpio3_irqs,
1285         .main_clk       = "gpios_fck",
1286         .prcm           = {
1287                 .omap2 = {
1288                         .prcm_reg_id = 1,
1289                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1290                         .module_offs = WKUP_MOD,
1291                         .idlest_reg_id = 1,
1292                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1293                 },
1294         },
1295         .slaves         = omap2430_gpio3_slaves,
1296         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1297         .class          = &omap2xxx_gpio_hwmod_class,
1298         .dev_attr       = &gpio_dev_attr,
1299 };
1300
1301 /* gpio4 */
1302 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1303         &omap2430_l4_wkup__gpio4,
1304 };
1305
1306 static struct omap_hwmod omap2430_gpio4_hwmod = {
1307         .name           = "gpio4",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap2_gpio4_irqs,
1310         .main_clk       = "gpios_fck",
1311         .prcm           = {
1312                 .omap2 = {
1313                         .prcm_reg_id = 1,
1314                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1315                         .module_offs = WKUP_MOD,
1316                         .idlest_reg_id = 1,
1317                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1318                 },
1319         },
1320         .slaves         = omap2430_gpio4_slaves,
1321         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1322         .class          = &omap2xxx_gpio_hwmod_class,
1323         .dev_attr       = &gpio_dev_attr,
1324 };
1325
1326 /* gpio5 */
1327 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1328         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1329         { .irq = -1 }
1330 };
1331
1332 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1333         &omap2430_l4_core__gpio5,
1334 };
1335
1336 static struct omap_hwmod omap2430_gpio5_hwmod = {
1337         .name           = "gpio5",
1338         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1339         .mpu_irqs       = omap243x_gpio5_irqs,
1340         .main_clk       = "gpio5_fck",
1341         .prcm           = {
1342                 .omap2 = {
1343                         .prcm_reg_id = 2,
1344                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1345                         .module_offs = CORE_MOD,
1346                         .idlest_reg_id = 2,
1347                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1348                 },
1349         },
1350         .slaves         = omap2430_gpio5_slaves,
1351         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1352         .class          = &omap2xxx_gpio_hwmod_class,
1353         .dev_attr       = &gpio_dev_attr,
1354 };
1355
1356 /* dma attributes */
1357 static struct omap_dma_dev_attr dma_dev_attr = {
1358         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1359                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1360         .lch_count = 32,
1361 };
1362
1363 /* dma_system -> L3 */
1364 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1365         .master         = &omap2430_dma_system_hwmod,
1366         .slave          = &omap2430_l3_main_hwmod,
1367         .clk            = "core_l3_ck",
1368         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1369 };
1370
1371 /* dma_system master ports */
1372 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1373         &omap2430_dma_system__l3,
1374 };
1375
1376 /* l4_core -> dma_system */
1377 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1378         .master         = &omap2430_l4_core_hwmod,
1379         .slave          = &omap2430_dma_system_hwmod,
1380         .clk            = "sdma_ick",
1381         .addr           = omap2_dma_system_addrs,
1382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1383 };
1384
1385 /* dma_system slave ports */
1386 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1387         &omap2430_l4_core__dma_system,
1388 };
1389
1390 static struct omap_hwmod omap2430_dma_system_hwmod = {
1391         .name           = "dma",
1392         .class          = &omap2xxx_dma_hwmod_class,
1393         .mpu_irqs       = omap2_dma_system_irqs,
1394         .main_clk       = "core_l3_ck",
1395         .slaves         = omap2430_dma_system_slaves,
1396         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1397         .masters        = omap2430_dma_system_masters,
1398         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1399         .dev_attr       = &dma_dev_attr,
1400         .flags          = HWMOD_NO_IDLEST,
1401 };
1402
1403 /* mailbox */
1404 static struct omap_hwmod omap2430_mailbox_hwmod;
1405 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1406         { .irq = 26 },
1407         { .irq = -1 }
1408 };
1409
1410 /* l4_core -> mailbox */
1411 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1412         .master         = &omap2430_l4_core_hwmod,
1413         .slave          = &omap2430_mailbox_hwmod,
1414         .addr           = omap2_mailbox_addrs,
1415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1416 };
1417
1418 /* mailbox slave ports */
1419 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1420         &omap2430_l4_core__mailbox,
1421 };
1422
1423 static struct omap_hwmod omap2430_mailbox_hwmod = {
1424         .name           = "mailbox",
1425         .class          = &omap2xxx_mailbox_hwmod_class,
1426         .mpu_irqs       = omap2430_mailbox_irqs,
1427         .main_clk       = "mailboxes_ick",
1428         .prcm           = {
1429                 .omap2 = {
1430                         .prcm_reg_id = 1,
1431                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1432                         .module_offs = CORE_MOD,
1433                         .idlest_reg_id = 1,
1434                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1435                 },
1436         },
1437         .slaves         = omap2430_mailbox_slaves,
1438         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
1439 };
1440
1441 /* mcspi1 */
1442 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1443         &omap2430_l4_core__mcspi1,
1444 };
1445
1446 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1447         .num_chipselect = 4,
1448 };
1449
1450 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1451         .name           = "mcspi1_hwmod",
1452         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1453         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1454         .main_clk       = "mcspi1_fck",
1455         .prcm           = {
1456                 .omap2 = {
1457                         .module_offs = CORE_MOD,
1458                         .prcm_reg_id = 1,
1459                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1460                         .idlest_reg_id = 1,
1461                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1462                 },
1463         },
1464         .slaves         = omap2430_mcspi1_slaves,
1465         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
1466         .class          = &omap2xxx_mcspi_class,
1467         .dev_attr       = &omap_mcspi1_dev_attr,
1468 };
1469
1470 /* mcspi2 */
1471 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1472         &omap2430_l4_core__mcspi2,
1473 };
1474
1475 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1476         .num_chipselect = 2,
1477 };
1478
1479 static struct omap_hwmod omap2430_mcspi2_hwmod = {
1480         .name           = "mcspi2_hwmod",
1481         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1482         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1483         .main_clk       = "mcspi2_fck",
1484         .prcm           = {
1485                 .omap2 = {
1486                         .module_offs = CORE_MOD,
1487                         .prcm_reg_id = 1,
1488                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1489                         .idlest_reg_id = 1,
1490                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1491                 },
1492         },
1493         .slaves         = omap2430_mcspi2_slaves,
1494         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
1495         .class          = &omap2xxx_mcspi_class,
1496         .dev_attr       = &omap_mcspi2_dev_attr,
1497 };
1498
1499 /* mcspi3 */
1500 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1501         { .irq = 91 },
1502         { .irq = -1 }
1503 };
1504
1505 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1506         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1507         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1508         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1509         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1510         { .dma_req = -1 }
1511 };
1512
1513 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1514         &omap2430_l4_core__mcspi3,
1515 };
1516
1517 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1518         .num_chipselect = 2,
1519 };
1520
1521 static struct omap_hwmod omap2430_mcspi3_hwmod = {
1522         .name           = "mcspi3_hwmod",
1523         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
1524         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
1525         .main_clk       = "mcspi3_fck",
1526         .prcm           = {
1527                 .omap2 = {
1528                         .module_offs = CORE_MOD,
1529                         .prcm_reg_id = 2,
1530                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1531                         .idlest_reg_id = 2,
1532                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1533                 },
1534         },
1535         .slaves         = omap2430_mcspi3_slaves,
1536         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
1537         .class          = &omap2xxx_mcspi_class,
1538         .dev_attr       = &omap_mcspi3_dev_attr,
1539 };
1540
1541 /*
1542  * usbhsotg
1543  */
1544 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1545         .rev_offs       = 0x0400,
1546         .sysc_offs      = 0x0404,
1547         .syss_offs      = 0x0408,
1548         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1549                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1550                           SYSC_HAS_AUTOIDLE),
1551         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1552                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1553         .sysc_fields    = &omap_hwmod_sysc_type1,
1554 };
1555
1556 static struct omap_hwmod_class usbotg_class = {
1557         .name = "usbotg",
1558         .sysc = &omap2430_usbhsotg_sysc,
1559 };
1560
1561 /* usb_otg_hs */
1562 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1563
1564         { .name = "mc", .irq = 92 },
1565         { .name = "dma", .irq = 93 },
1566         { .irq = -1 }
1567 };
1568
1569 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1570         .name           = "usb_otg_hs",
1571         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
1572         .main_clk       = "usbhs_ick",
1573         .prcm           = {
1574                 .omap2 = {
1575                         .prcm_reg_id = 1,
1576                         .module_bit = OMAP2430_EN_USBHS_MASK,
1577                         .module_offs = CORE_MOD,
1578                         .idlest_reg_id = 1,
1579                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1580                 },
1581         },
1582         .masters        = omap2430_usbhsotg_masters,
1583         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
1584         .slaves         = omap2430_usbhsotg_slaves,
1585         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1586         .class          = &usbotg_class,
1587         /*
1588          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1589          * broken when autoidle is enabled
1590          * workaround is to disable the autoidle bit at module level.
1591          */
1592         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1593                                 | HWMOD_SWSUP_MSTANDBY,
1594 };
1595
1596 /*
1597  * 'mcbsp' class
1598  * multi channel buffered serial port controller
1599  */
1600
1601 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
1602         .rev_offs       = 0x007C,
1603         .sysc_offs      = 0x008C,
1604         .sysc_flags     = (SYSC_HAS_SOFTRESET),
1605         .sysc_fields    = &omap_hwmod_sysc_type1,
1606 };
1607
1608 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
1609         .name = "mcbsp",
1610         .sysc = &omap2430_mcbsp_sysc,
1611         .rev  = MCBSP_CONFIG_TYPE2,
1612 };
1613
1614 /* mcbsp1 */
1615 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1616         { .name = "tx",         .irq = 59 },
1617         { .name = "rx",         .irq = 60 },
1618         { .name = "ovr",        .irq = 61 },
1619         { .name = "common",     .irq = 64 },
1620         { .irq = -1 }
1621 };
1622
1623 /* l4_core -> mcbsp1 */
1624 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1625         .master         = &omap2430_l4_core_hwmod,
1626         .slave          = &omap2430_mcbsp1_hwmod,
1627         .clk            = "mcbsp1_ick",
1628         .addr           = omap2_mcbsp1_addrs,
1629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1630 };
1631
1632 /* mcbsp1 slave ports */
1633 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1634         &omap2430_l4_core__mcbsp1,
1635 };
1636
1637 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1638         .name           = "mcbsp1",
1639         .class          = &omap2430_mcbsp_hwmod_class,
1640         .mpu_irqs       = omap2430_mcbsp1_irqs,
1641         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1642         .main_clk       = "mcbsp1_fck",
1643         .prcm           = {
1644                 .omap2 = {
1645                         .prcm_reg_id = 1,
1646                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1647                         .module_offs = CORE_MOD,
1648                         .idlest_reg_id = 1,
1649                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1650                 },
1651         },
1652         .slaves         = omap2430_mcbsp1_slaves,
1653         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1654 };
1655
1656 /* mcbsp2 */
1657 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1658         { .name = "tx",         .irq = 62 },
1659         { .name = "rx",         .irq = 63 },
1660         { .name = "common",     .irq = 16 },
1661         { .irq = -1 }
1662 };
1663
1664 /* l4_core -> mcbsp2 */
1665 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1666         .master         = &omap2430_l4_core_hwmod,
1667         .slave          = &omap2430_mcbsp2_hwmod,
1668         .clk            = "mcbsp2_ick",
1669         .addr           = omap2xxx_mcbsp2_addrs,
1670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1671 };
1672
1673 /* mcbsp2 slave ports */
1674 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1675         &omap2430_l4_core__mcbsp2,
1676 };
1677
1678 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1679         .name           = "mcbsp2",
1680         .class          = &omap2430_mcbsp_hwmod_class,
1681         .mpu_irqs       = omap2430_mcbsp2_irqs,
1682         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1683         .main_clk       = "mcbsp2_fck",
1684         .prcm           = {
1685                 .omap2 = {
1686                         .prcm_reg_id = 1,
1687                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1688                         .module_offs = CORE_MOD,
1689                         .idlest_reg_id = 1,
1690                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1691                 },
1692         },
1693         .slaves         = omap2430_mcbsp2_slaves,
1694         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1695 };
1696
1697 /* mcbsp3 */
1698 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1699         { .name = "tx",         .irq = 89 },
1700         { .name = "rx",         .irq = 90 },
1701         { .name = "common",     .irq = 17 },
1702         { .irq = -1 }
1703 };
1704
1705 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1706         {
1707                 .name           = "mpu",
1708                 .pa_start       = 0x4808C000,
1709                 .pa_end         = 0x4808C0ff,
1710                 .flags          = ADDR_TYPE_RT
1711         },
1712         { }
1713 };
1714
1715 /* l4_core -> mcbsp3 */
1716 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1717         .master         = &omap2430_l4_core_hwmod,
1718         .slave          = &omap2430_mcbsp3_hwmod,
1719         .clk            = "mcbsp3_ick",
1720         .addr           = omap2430_mcbsp3_addrs,
1721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1722 };
1723
1724 /* mcbsp3 slave ports */
1725 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1726         &omap2430_l4_core__mcbsp3,
1727 };
1728
1729 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1730         .name           = "mcbsp3",
1731         .class          = &omap2430_mcbsp_hwmod_class,
1732         .mpu_irqs       = omap2430_mcbsp3_irqs,
1733         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1734         .main_clk       = "mcbsp3_fck",
1735         .prcm           = {
1736                 .omap2 = {
1737                         .prcm_reg_id = 1,
1738                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
1739                         .module_offs = CORE_MOD,
1740                         .idlest_reg_id = 2,
1741                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1742                 },
1743         },
1744         .slaves         = omap2430_mcbsp3_slaves,
1745         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1746 };
1747
1748 /* mcbsp4 */
1749 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
1750         { .name = "tx",         .irq = 54 },
1751         { .name = "rx",         .irq = 55 },
1752         { .name = "common",     .irq = 18 },
1753         { .irq = -1 }
1754 };
1755
1756 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1757         { .name = "rx", .dma_req = 20 },
1758         { .name = "tx", .dma_req = 19 },
1759         { .dma_req = -1 }
1760 };
1761
1762 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1763         {
1764                 .name           = "mpu",
1765                 .pa_start       = 0x4808E000,
1766                 .pa_end         = 0x4808E0ff,
1767                 .flags          = ADDR_TYPE_RT
1768         },
1769         { }
1770 };
1771
1772 /* l4_core -> mcbsp4 */
1773 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1774         .master         = &omap2430_l4_core_hwmod,
1775         .slave          = &omap2430_mcbsp4_hwmod,
1776         .clk            = "mcbsp4_ick",
1777         .addr           = omap2430_mcbsp4_addrs,
1778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1779 };
1780
1781 /* mcbsp4 slave ports */
1782 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1783         &omap2430_l4_core__mcbsp4,
1784 };
1785
1786 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1787         .name           = "mcbsp4",
1788         .class          = &omap2430_mcbsp_hwmod_class,
1789         .mpu_irqs       = omap2430_mcbsp4_irqs,
1790         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
1791         .main_clk       = "mcbsp4_fck",
1792         .prcm           = {
1793                 .omap2 = {
1794                         .prcm_reg_id = 1,
1795                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
1796                         .module_offs = CORE_MOD,
1797                         .idlest_reg_id = 2,
1798                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1799                 },
1800         },
1801         .slaves         = omap2430_mcbsp4_slaves,
1802         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1803 };
1804
1805 /* mcbsp5 */
1806 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
1807         { .name = "tx",         .irq = 81 },
1808         { .name = "rx",         .irq = 82 },
1809         { .name = "common",     .irq = 19 },
1810         { .irq = -1 }
1811 };
1812
1813 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1814         { .name = "rx", .dma_req = 22 },
1815         { .name = "tx", .dma_req = 21 },
1816         { .dma_req = -1 }
1817 };
1818
1819 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1820         {
1821                 .name           = "mpu",
1822                 .pa_start       = 0x48096000,
1823                 .pa_end         = 0x480960ff,
1824                 .flags          = ADDR_TYPE_RT
1825         },
1826         { }
1827 };
1828
1829 /* l4_core -> mcbsp5 */
1830 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1831         .master         = &omap2430_l4_core_hwmod,
1832         .slave          = &omap2430_mcbsp5_hwmod,
1833         .clk            = "mcbsp5_ick",
1834         .addr           = omap2430_mcbsp5_addrs,
1835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1836 };
1837
1838 /* mcbsp5 slave ports */
1839 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1840         &omap2430_l4_core__mcbsp5,
1841 };
1842
1843 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1844         .name           = "mcbsp5",
1845         .class          = &omap2430_mcbsp_hwmod_class,
1846         .mpu_irqs       = omap2430_mcbsp5_irqs,
1847         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
1848         .main_clk       = "mcbsp5_fck",
1849         .prcm           = {
1850                 .omap2 = {
1851                         .prcm_reg_id = 1,
1852                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
1853                         .module_offs = CORE_MOD,
1854                         .idlest_reg_id = 2,
1855                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1856                 },
1857         },
1858         .slaves         = omap2430_mcbsp5_slaves,
1859         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1860 };
1861
1862 /* MMC/SD/SDIO common */
1863
1864 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1865         .rev_offs       = 0x1fc,
1866         .sysc_offs      = 0x10,
1867         .syss_offs      = 0x14,
1868         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1869                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1870                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1872         .sysc_fields    = &omap_hwmod_sysc_type1,
1873 };
1874
1875 static struct omap_hwmod_class omap2430_mmc_class = {
1876         .name = "mmc",
1877         .sysc = &omap2430_mmc_sysc,
1878 };
1879
1880 /* MMC/SD/SDIO1 */
1881
1882 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1883         { .irq = 83 },
1884         { .irq = -1 }
1885 };
1886
1887 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
1888         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
1889         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1890         { .dma_req = -1 }
1891 };
1892
1893 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1894         { .role = "dbck", .clk = "mmchsdb1_fck" },
1895 };
1896
1897 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1898         &omap2430_l4_core__mmc1,
1899 };
1900
1901 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1902         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1903 };
1904
1905 static struct omap_hwmod omap2430_mmc1_hwmod = {
1906         .name           = "mmc1",
1907         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1908         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
1909         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
1910         .opt_clks       = omap2430_mmc1_opt_clks,
1911         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
1912         .main_clk       = "mmchs1_fck",
1913         .prcm           = {
1914                 .omap2 = {
1915                         .module_offs = CORE_MOD,
1916                         .prcm_reg_id = 2,
1917                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
1918                         .idlest_reg_id = 2,
1919                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
1920                 },
1921         },
1922         .dev_attr       = &mmc1_dev_attr,
1923         .slaves         = omap2430_mmc1_slaves,
1924         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
1925         .class          = &omap2430_mmc_class,
1926 };
1927
1928 /* MMC/SD/SDIO2 */
1929
1930 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1931         { .irq = 86 },
1932         { .irq = -1 }
1933 };
1934
1935 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
1936         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
1937         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1938         { .dma_req = -1 }
1939 };
1940
1941 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1942         { .role = "dbck", .clk = "mmchsdb2_fck" },
1943 };
1944
1945 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1946         &omap2430_l4_core__mmc2,
1947 };
1948
1949 static struct omap_hwmod omap2430_mmc2_hwmod = {
1950         .name           = "mmc2",
1951         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1952         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
1953         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
1954         .opt_clks       = omap2430_mmc2_opt_clks,
1955         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
1956         .main_clk       = "mmchs2_fck",
1957         .prcm           = {
1958                 .omap2 = {
1959                         .module_offs = CORE_MOD,
1960                         .prcm_reg_id = 2,
1961                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
1962                         .idlest_reg_id = 2,
1963                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
1964                 },
1965         },
1966         .slaves         = omap2430_mmc2_slaves,
1967         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
1968         .class          = &omap2430_mmc_class,
1969 };
1970
1971 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1972         &omap2430_l3_main_hwmod,
1973         &omap2430_l4_core_hwmod,
1974         &omap2430_l4_wkup_hwmod,
1975         &omap2430_mpu_hwmod,
1976         &omap2430_iva_hwmod,
1977
1978         &omap2430_timer1_hwmod,
1979         &omap2430_timer2_hwmod,
1980         &omap2430_timer3_hwmod,
1981         &omap2430_timer4_hwmod,
1982         &omap2430_timer5_hwmod,
1983         &omap2430_timer6_hwmod,
1984         &omap2430_timer7_hwmod,
1985         &omap2430_timer8_hwmod,
1986         &omap2430_timer9_hwmod,
1987         &omap2430_timer10_hwmod,
1988         &omap2430_timer11_hwmod,
1989         &omap2430_timer12_hwmod,
1990
1991         &omap2430_wd_timer2_hwmod,
1992         &omap2430_uart1_hwmod,
1993         &omap2430_uart2_hwmod,
1994         &omap2430_uart3_hwmod,
1995         /* dss class */
1996         &omap2430_dss_core_hwmod,
1997         &omap2430_dss_dispc_hwmod,
1998         &omap2430_dss_rfbi_hwmod,
1999         &omap2430_dss_venc_hwmod,
2000         /* i2c class */
2001         &omap2430_i2c1_hwmod,
2002         &omap2430_i2c2_hwmod,
2003         &omap2430_mmc1_hwmod,
2004         &omap2430_mmc2_hwmod,
2005
2006         /* gpio class */
2007         &omap2430_gpio1_hwmod,
2008         &omap2430_gpio2_hwmod,
2009         &omap2430_gpio3_hwmod,
2010         &omap2430_gpio4_hwmod,
2011         &omap2430_gpio5_hwmod,
2012
2013         /* dma_system class*/
2014         &omap2430_dma_system_hwmod,
2015
2016         /* mcbsp class */
2017         &omap2430_mcbsp1_hwmod,
2018         &omap2430_mcbsp2_hwmod,
2019         &omap2430_mcbsp3_hwmod,
2020         &omap2430_mcbsp4_hwmod,
2021         &omap2430_mcbsp5_hwmod,
2022
2023         /* mailbox class */
2024         &omap2430_mailbox_hwmod,
2025
2026         /* mcspi class */
2027         &omap2430_mcspi1_hwmod,
2028         &omap2430_mcspi2_hwmod,
2029         &omap2430_mcspi3_hwmod,
2030
2031         /* usbotg class*/
2032         &omap2430_usbhsotg_hwmod,
2033
2034         NULL,
2035 };
2036
2037 int __init omap2430_hwmod_init(void)
2038 {
2039         return omap_hwmod_register(omap2430_hwmods);
2040 }