arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcbsp.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/mmc.h>
  25 #include <plat/l3_2xxx.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "prm-regbits-24xx.h"
  30 #include "cm-regbits-24xx.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * ALl of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 static struct omap_hwmod omap2430_mpu_hwmod;
  43 static struct omap_hwmod omap2430_iva_hwmod;
  44 static struct omap_hwmod omap2430_l3_main_hwmod;
  45 static struct omap_hwmod omap2430_l4_core_hwmod;
  46 static struct omap_hwmod omap2430_dss_core_hwmod;
  47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
  48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
  49 static struct omap_hwmod omap2430_dss_venc_hwmod;
  50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
  51 static struct omap_hwmod omap2430_gpio1_hwmod;
  52 static struct omap_hwmod omap2430_gpio2_hwmod;
  53 static struct omap_hwmod omap2430_gpio3_hwmod;
  54 static struct omap_hwmod omap2430_gpio4_hwmod;
  55 static struct omap_hwmod omap2430_gpio5_hwmod;
  56 static struct omap_hwmod omap2430_dma_system_hwmod;
  57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
  58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
  59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
  60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
  61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
  62 static struct omap_hwmod omap2430_mcspi1_hwmod;
  63 static struct omap_hwmod omap2430_mcspi2_hwmod;
  64 static struct omap_hwmod omap2430_mcspi3_hwmod;
  65 static struct omap_hwmod omap2430_mmc1_hwmod;
  66 static struct omap_hwmod omap2430_mmc2_hwmod;
  67
  68 /* L3 -> L4_CORE interface */
  69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
  70         .master = &omap2430_l3_main_hwmod,
  71         .slave  = &omap2430_l4_core_hwmod,
  72         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  73 };
  74
  75 /* MPU -> L3 interface */
  76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
  77         .master = &omap2430_mpu_hwmod,
  78         .slave  = &omap2430_l3_main_hwmod,
  79         .user   = OCP_USER_MPU,
  80 };
  81
  82 /* Slave interfaces on the L3 interconnect */
  83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
  84         &omap2430_mpu__l3_main,
  85 };
  86
  87 /* DSS -> l3 */
  88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
  89         .master         = &omap2430_dss_core_hwmod,
  90         .slave          = &omap2430_l3_main_hwmod,
  91         .fw = {
  92                 .omap2 = {
  93                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  94                         .flags  = OMAP_FIREWALL_L3,
  95                 }
  96         },
  97         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  98 };
  99
 100 /* Master interfaces on the L3 interconnect */
 101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
 102         &omap2430_l3_main__l4_core,
 103 };
 104
 105 /* L3 */
 106 static struct omap_hwmod omap2430_l3_main_hwmod = {
 107         .name           = "l3_main",
 108         .class          = &l3_hwmod_class,
 109         .masters        = omap2430_l3_main_masters,
 110         .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
 111         .slaves         = omap2430_l3_main_slaves,
 112         .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
 113         .flags          = HWMOD_NO_IDLEST,
 114 };
 115
 116 static struct omap_hwmod omap2430_l4_wkup_hwmod;
 117 static struct omap_hwmod omap2430_uart1_hwmod;
 118 static struct omap_hwmod omap2430_uart2_hwmod;
 119 static struct omap_hwmod omap2430_uart3_hwmod;
 120 static struct omap_hwmod omap2430_i2c1_hwmod;
 121 static struct omap_hwmod omap2430_i2c2_hwmod;
 122
 123 static struct omap_hwmod omap2430_usbhsotg_hwmod;
 124
 125 /* l3_core -> usbhsotg  interface */
 126 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 127         .master         = &omap2430_usbhsotg_hwmod,
 128         .slave          = &omap2430_l3_main_hwmod,
 129         .clk            = "core_l3_ck",
 130         .user           = OCP_USER_MPU,
 131 };
 132
 133 /* L4 CORE -> I2C1 interface */
 134 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 135         .master         = &omap2430_l4_core_hwmod,
 136         .slave          = &omap2430_i2c1_hwmod,
 137         .clk            = "i2c1_ick",
 138         .addr           = omap2_i2c1_addr_space,
 139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 140 };
 141
 142 /* L4 CORE -> I2C2 interface */
 143 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 144         .master         = &omap2430_l4_core_hwmod,
 145         .slave          = &omap2430_i2c2_hwmod,
 146         .clk            = "i2c2_ick",
 147         .addr           = omap2_i2c2_addr_space,
 148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 149 };
 150
 151 /* L4_CORE -> L4_WKUP interface */
 152 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
 153         .master = &omap2430_l4_core_hwmod,
 154         .slave  = &omap2430_l4_wkup_hwmod,
 155         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 /* L4 CORE -> UART1 interface */
 159 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 160         .master         = &omap2430_l4_core_hwmod,
 161         .slave          = &omap2430_uart1_hwmod,
 162         .clk            = "uart1_ick",
 163         .addr           = omap2xxx_uart1_addr_space,
 164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 165 };
 166
 167 /* L4 CORE -> UART2 interface */
 168 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 169         .master         = &omap2430_l4_core_hwmod,
 170         .slave          = &omap2430_uart2_hwmod,
 171         .clk            = "uart2_ick",
 172         .addr           = omap2xxx_uart2_addr_space,
 173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 174 };
 175
 176 /* L4 PER -> UART3 interface */
 177 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 178         .master         = &omap2430_l4_core_hwmod,
 179         .slave          = &omap2430_uart3_hwmod,
 180         .clk            = "uart3_ick",
 181         .addr           = omap2xxx_uart3_addr_space,
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /*
 186 * usbhsotg interface data
 187 */
 188 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 189         {
 190                 .pa_start       = OMAP243X_HS_BASE,
 191                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 192                 .flags          = ADDR_TYPE_RT
 193         },
 194         { }
 195 };
 196
 197 /*  l4_core ->usbhsotg  interface */
 198 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 199         .master         = &omap2430_l4_core_hwmod,
 200         .slave          = &omap2430_usbhsotg_hwmod,
 201         .clk            = "usb_l4_ick",
 202         .addr           = omap2430_usbhsotg_addrs,
 203         .user           = OCP_USER_MPU,
 204 };
 205
 206 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
 207         &omap2430_usbhsotg__l3,
 208 };
 209
 210 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
 211         &omap2430_l4_core__usbhsotg,
 212 };
 213
 214 /* L4 CORE -> MMC1 interface */
 215 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 216         .master         = &omap2430_l4_core_hwmod,
 217         .slave          = &omap2430_mmc1_hwmod,
 218         .clk            = "mmchs1_ick",
 219         .addr           = omap2430_mmc1_addr_space,
 220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 221 };
 222
 223 /* L4 CORE -> MMC2 interface */
 224 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 225         .master         = &omap2430_l4_core_hwmod,
 226         .slave          = &omap2430_mmc2_hwmod,
 227         .clk            = "mmchs2_ick",
 228         .addr           = omap2430_mmc2_addr_space,
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* Slave interfaces on the L4_CORE interconnect */
 233 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 234         &omap2430_l3_main__l4_core,
 235 };
 236
 237 /* Master interfaces on the L4_CORE interconnect */
 238 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
 239         &omap2430_l4_core__l4_wkup,
 240         &omap2430_l4_core__mmc1,
 241         &omap2430_l4_core__mmc2,
 242 };
 243
 244 /* L4 CORE */
 245 static struct omap_hwmod omap2430_l4_core_hwmod = {
 246         .name           = "l4_core",
 247         .class          = &l4_hwmod_class,
 248         .masters        = omap2430_l4_core_masters,
 249         .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
 250         .slaves         = omap2430_l4_core_slaves,
 251         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
 252         .flags          = HWMOD_NO_IDLEST,
 253 };
 254
 255 /* Slave interfaces on the L4_WKUP interconnect */
 256 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 257         &omap2430_l4_core__l4_wkup,
 258         &omap2_l4_core__uart1,
 259         &omap2_l4_core__uart2,
 260         &omap2_l4_core__uart3,
 261 };
 262
 263 /* Master interfaces on the L4_WKUP interconnect */
 264 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 265 };
 266
 267 /* l4 core -> mcspi1 interface */
 268 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 269         .master         = &omap2430_l4_core_hwmod,
 270         .slave          = &omap2430_mcspi1_hwmod,
 271         .clk            = "mcspi1_ick",
 272         .addr           = omap2_mcspi1_addr_space,
 273         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 274 };
 275
 276 /* l4 core -> mcspi2 interface */
 277 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 278         .master         = &omap2430_l4_core_hwmod,
 279         .slave          = &omap2430_mcspi2_hwmod,
 280         .clk            = "mcspi2_ick",
 281         .addr           = omap2_mcspi2_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* l4 core -> mcspi3 interface */
 286 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 287         .master         = &omap2430_l4_core_hwmod,
 288         .slave          = &omap2430_mcspi3_hwmod,
 289         .clk            = "mcspi3_ick",
 290         .addr           = omap2430_mcspi3_addr_space,
 291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 292 };
 293
 294 /* L4 WKUP */
 295 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 296         .name           = "l4_wkup",
 297         .class          = &l4_hwmod_class,
 298         .masters        = omap2430_l4_wkup_masters,
 299         .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
 300         .slaves         = omap2430_l4_wkup_slaves,
 301         .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
 302         .flags          = HWMOD_NO_IDLEST,
 303 };
 304
 305 /* Master interfaces on the MPU device */
 306 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
 307         &omap2430_mpu__l3_main,
 308 };
 309
 310 /* MPU */
 311 static struct omap_hwmod omap2430_mpu_hwmod = {
 312         .name           = "mpu",
 313         .class          = &mpu_hwmod_class,
 314         .main_clk       = "mpu_ck",
 315         .masters        = omap2430_mpu_masters,
 316         .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
 317 };
 318
 319 /*
 320  * IVA2_1 interface data
 321  */
 322
 323 /* IVA2 <- L3 interface */
 324 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 325         .master         = &omap2430_l3_main_hwmod,
 326         .slave          = &omap2430_iva_hwmod,
 327         .clk            = "dsp_fck",
 328         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 329 };
 330
 331 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
 332         &omap2430_l3__iva,
 333 };
 334
 335 /*
 336  * IVA2 (IVA2)
 337  */
 338
 339 static struct omap_hwmod omap2430_iva_hwmod = {
 340         .name           = "iva",
 341         .class          = &iva_hwmod_class,
 342         .masters        = omap2430_iva_masters,
 343         .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
 344 };
 345
 346 /* always-on timers dev attribute */
 347 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 348         .timer_capability       = OMAP_TIMER_ALWON,
 349 };
 350
 351 /* pwm timers dev attribute */
 352 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 353         .timer_capability       = OMAP_TIMER_HAS_PWM,
 354 };
 355
 356 /* timer1 */
 357 static struct omap_hwmod omap2430_timer1_hwmod;
 358
 359 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 360         {
 361                 .pa_start       = 0x49018000,
 362                 .pa_end         = 0x49018000 + SZ_1K - 1,
 363                 .flags          = ADDR_TYPE_RT
 364         },
 365         { }
 366 };
 367
 368 /* l4_wkup -> timer1 */
 369 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 370         .master         = &omap2430_l4_wkup_hwmod,
 371         .slave          = &omap2430_timer1_hwmod,
 372         .clk            = "gpt1_ick",
 373         .addr           = omap2430_timer1_addrs,
 374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 375 };
 376
 377 /* timer1 slave port */
 378 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
 379         &omap2430_l4_wkup__timer1,
 380 };
 381
 382 /* timer1 hwmod */
 383 static struct omap_hwmod omap2430_timer1_hwmod = {
 384         .name           = "timer1",
 385         .mpu_irqs       = omap2_timer1_mpu_irqs,
 386         .main_clk       = "gpt1_fck",
 387         .prcm           = {
 388                 .omap2 = {
 389                         .prcm_reg_id = 1,
 390                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 391                         .module_offs = WKUP_MOD,
 392                         .idlest_reg_id = 1,
 393                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 394                 },
 395         },
 396         .dev_attr       = &capability_alwon_dev_attr,
 397         .slaves         = omap2430_timer1_slaves,
 398         .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
 399         .class          = &omap2xxx_timer_hwmod_class,
 400 };
 401
 402 /* timer2 */
 403 static struct omap_hwmod omap2430_timer2_hwmod;
 404
 405 /* l4_core -> timer2 */
 406 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 407         .master         = &omap2430_l4_core_hwmod,
 408         .slave          = &omap2430_timer2_hwmod,
 409         .clk            = "gpt2_ick",
 410         .addr           = omap2xxx_timer2_addrs,
 411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 412 };
 413
 414 /* timer2 slave port */
 415 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
 416         &omap2430_l4_core__timer2,
 417 };
 418
 419 /* timer2 hwmod */
 420 static struct omap_hwmod omap2430_timer2_hwmod = {
 421         .name           = "timer2",
 422         .mpu_irqs       = omap2_timer2_mpu_irqs,
 423         .main_clk       = "gpt2_fck",
 424         .prcm           = {
 425                 .omap2 = {
 426                         .prcm_reg_id = 1,
 427                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 428                         .module_offs = CORE_MOD,
 429                         .idlest_reg_id = 1,
 430                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 431                 },
 432         },
 433         .dev_attr       = &capability_alwon_dev_attr,
 434         .slaves         = omap2430_timer2_slaves,
 435         .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
 436         .class          = &omap2xxx_timer_hwmod_class,
 437 };
 438
 439 /* timer3 */
 440 static struct omap_hwmod omap2430_timer3_hwmod;
 441
 442 /* l4_core -> timer3 */
 443 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 444         .master         = &omap2430_l4_core_hwmod,
 445         .slave          = &omap2430_timer3_hwmod,
 446         .clk            = "gpt3_ick",
 447         .addr           = omap2xxx_timer3_addrs,
 448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 449 };
 450
 451 /* timer3 slave port */
 452 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
 453         &omap2430_l4_core__timer3,
 454 };
 455
 456 /* timer3 hwmod */
 457 static struct omap_hwmod omap2430_timer3_hwmod = {
 458         .name           = "timer3",
 459         .mpu_irqs       = omap2_timer3_mpu_irqs,
 460         .main_clk       = "gpt3_fck",
 461         .prcm           = {
 462                 .omap2 = {
 463                         .prcm_reg_id = 1,
 464                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 465                         .module_offs = CORE_MOD,
 466                         .idlest_reg_id = 1,
 467                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 468                 },
 469         },
 470         .dev_attr       = &capability_alwon_dev_attr,
 471         .slaves         = omap2430_timer3_slaves,
 472         .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
 473         .class          = &omap2xxx_timer_hwmod_class,
 474 };
 475
 476 /* timer4 */
 477 static struct omap_hwmod omap2430_timer4_hwmod;
 478
 479 /* l4_core -> timer4 */
 480 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 481         .master         = &omap2430_l4_core_hwmod,
 482         .slave          = &omap2430_timer4_hwmod,
 483         .clk            = "gpt4_ick",
 484         .addr           = omap2xxx_timer4_addrs,
 485         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 486 };
 487
 488 /* timer4 slave port */
 489 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
 490         &omap2430_l4_core__timer4,
 491 };
 492
 493 /* timer4 hwmod */
 494 static struct omap_hwmod omap2430_timer4_hwmod = {
 495         .name           = "timer4",
 496         .mpu_irqs       = omap2_timer4_mpu_irqs,
 497         .main_clk       = "gpt4_fck",
 498         .prcm           = {
 499                 .omap2 = {
 500                         .prcm_reg_id = 1,
 501                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 502                         .module_offs = CORE_MOD,
 503                         .idlest_reg_id = 1,
 504                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 505                 },
 506         },
 507         .dev_attr       = &capability_alwon_dev_attr,
 508         .slaves         = omap2430_timer4_slaves,
 509         .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
 510         .class          = &omap2xxx_timer_hwmod_class,
 511 };
 512
 513 /* timer5 */
 514 static struct omap_hwmod omap2430_timer5_hwmod;
 515
 516 /* l4_core -> timer5 */
 517 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 518         .master         = &omap2430_l4_core_hwmod,
 519         .slave          = &omap2430_timer5_hwmod,
 520         .clk            = "gpt5_ick",
 521         .addr           = omap2xxx_timer5_addrs,
 522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 523 };
 524
 525 /* timer5 slave port */
 526 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
 527         &omap2430_l4_core__timer5,
 528 };
 529
 530 /* timer5 hwmod */
 531 static struct omap_hwmod omap2430_timer5_hwmod = {
 532         .name           = "timer5",
 533         .mpu_irqs       = omap2_timer5_mpu_irqs,
 534         .main_clk       = "gpt5_fck",
 535         .prcm           = {
 536                 .omap2 = {
 537                         .prcm_reg_id = 1,
 538                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 539                         .module_offs = CORE_MOD,
 540                         .idlest_reg_id = 1,
 541                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 542                 },
 543         },
 544         .dev_attr       = &capability_alwon_dev_attr,
 545         .slaves         = omap2430_timer5_slaves,
 546         .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
 547         .class          = &omap2xxx_timer_hwmod_class,
 548 };
 549
 550 /* timer6 */
 551 static struct omap_hwmod omap2430_timer6_hwmod;
 552
 553 /* l4_core -> timer6 */
 554 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 555         .master         = &omap2430_l4_core_hwmod,
 556         .slave          = &omap2430_timer6_hwmod,
 557         .clk            = "gpt6_ick",
 558         .addr           = omap2xxx_timer6_addrs,
 559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 560 };
 561
 562 /* timer6 slave port */
 563 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
 564         &omap2430_l4_core__timer6,
 565 };
 566
 567 /* timer6 hwmod */
 568 static struct omap_hwmod omap2430_timer6_hwmod = {
 569         .name           = "timer6",
 570         .mpu_irqs       = omap2_timer6_mpu_irqs,
 571         .main_clk       = "gpt6_fck",
 572         .prcm           = {
 573                 .omap2 = {
 574                         .prcm_reg_id = 1,
 575                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 576                         .module_offs = CORE_MOD,
 577                         .idlest_reg_id = 1,
 578                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 579                 },
 580         },
 581         .dev_attr       = &capability_alwon_dev_attr,
 582         .slaves         = omap2430_timer6_slaves,
 583         .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
 584         .class          = &omap2xxx_timer_hwmod_class,
 585 };
 586
 587 /* timer7 */
 588 static struct omap_hwmod omap2430_timer7_hwmod;
 589
 590 /* l4_core -> timer7 */
 591 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 592         .master         = &omap2430_l4_core_hwmod,
 593         .slave          = &omap2430_timer7_hwmod,
 594         .clk            = "gpt7_ick",
 595         .addr           = omap2xxx_timer7_addrs,
 596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 597 };
 598
 599 /* timer7 slave port */
 600 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
 601         &omap2430_l4_core__timer7,
 602 };
 603
 604 /* timer7 hwmod */
 605 static struct omap_hwmod omap2430_timer7_hwmod = {
 606         .name           = "timer7",
 607         .mpu_irqs       = omap2_timer7_mpu_irqs,
 608         .main_clk       = "gpt7_fck",
 609         .prcm           = {
 610                 .omap2 = {
 611                         .prcm_reg_id = 1,
 612                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 613                         .module_offs = CORE_MOD,
 614                         .idlest_reg_id = 1,
 615                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 616                 },
 617         },
 618         .dev_attr       = &capability_alwon_dev_attr,
 619         .slaves         = omap2430_timer7_slaves,
 620         .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
 621         .class          = &omap2xxx_timer_hwmod_class,
 622 };
 623
 624 /* timer8 */
 625 static struct omap_hwmod omap2430_timer8_hwmod;
 626
 627 /* l4_core -> timer8 */
 628 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 629         .master         = &omap2430_l4_core_hwmod,
 630         .slave          = &omap2430_timer8_hwmod,
 631         .clk            = "gpt8_ick",
 632         .addr           = omap2xxx_timer8_addrs,
 633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 634 };
 635
 636 /* timer8 slave port */
 637 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
 638         &omap2430_l4_core__timer8,
 639 };
 640
 641 /* timer8 hwmod */
 642 static struct omap_hwmod omap2430_timer8_hwmod = {
 643         .name           = "timer8",
 644         .mpu_irqs       = omap2_timer8_mpu_irqs,
 645         .main_clk       = "gpt8_fck",
 646         .prcm           = {
 647                 .omap2 = {
 648                         .prcm_reg_id = 1,
 649                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 650                         .module_offs = CORE_MOD,
 651                         .idlest_reg_id = 1,
 652                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 653                 },
 654         },
 655         .dev_attr       = &capability_alwon_dev_attr,
 656         .slaves         = omap2430_timer8_slaves,
 657         .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
 658         .class          = &omap2xxx_timer_hwmod_class,
 659 };
 660
 661 /* timer9 */
 662 static struct omap_hwmod omap2430_timer9_hwmod;
 663
 664 /* l4_core -> timer9 */
 665 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 666         .master         = &omap2430_l4_core_hwmod,
 667         .slave          = &omap2430_timer9_hwmod,
 668         .clk            = "gpt9_ick",
 669         .addr           = omap2xxx_timer9_addrs,
 670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 671 };
 672
 673 /* timer9 slave port */
 674 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
 675         &omap2430_l4_core__timer9,
 676 };
 677
 678 /* timer9 hwmod */
 679 static struct omap_hwmod omap2430_timer9_hwmod = {
 680         .name           = "timer9",
 681         .mpu_irqs       = omap2_timer9_mpu_irqs,
 682         .main_clk       = "gpt9_fck",
 683         .prcm           = {
 684                 .omap2 = {
 685                         .prcm_reg_id = 1,
 686                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 687                         .module_offs = CORE_MOD,
 688                         .idlest_reg_id = 1,
 689                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 690                 },
 691         },
 692         .dev_attr       = &capability_pwm_dev_attr,
 693         .slaves         = omap2430_timer9_slaves,
 694         .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
 695         .class          = &omap2xxx_timer_hwmod_class,
 696 };
 697
 698 /* timer10 */
 699 static struct omap_hwmod omap2430_timer10_hwmod;
 700
 701 /* l4_core -> timer10 */
 702 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 703         .master         = &omap2430_l4_core_hwmod,
 704         .slave          = &omap2430_timer10_hwmod,
 705         .clk            = "gpt10_ick",
 706         .addr           = omap2_timer10_addrs,
 707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 708 };
 709
 710 /* timer10 slave port */
 711 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
 712         &omap2430_l4_core__timer10,
 713 };
 714
 715 /* timer10 hwmod */
 716 static struct omap_hwmod omap2430_timer10_hwmod = {
 717         .name           = "timer10",
 718         .mpu_irqs       = omap2_timer10_mpu_irqs,
 719         .main_clk       = "gpt10_fck",
 720         .prcm           = {
 721                 .omap2 = {
 722                         .prcm_reg_id = 1,
 723                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 724                         .module_offs = CORE_MOD,
 725                         .idlest_reg_id = 1,
 726                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 727                 },
 728         },
 729         .dev_attr       = &capability_pwm_dev_attr,
 730         .slaves         = omap2430_timer10_slaves,
 731         .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
 732         .class          = &omap2xxx_timer_hwmod_class,
 733 };
 734
 735 /* timer11 */
 736 static struct omap_hwmod omap2430_timer11_hwmod;
 737
 738 /* l4_core -> timer11 */
 739 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 740         .master         = &omap2430_l4_core_hwmod,
 741         .slave          = &omap2430_timer11_hwmod,
 742         .clk            = "gpt11_ick",
 743         .addr           = omap2_timer11_addrs,
 744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 745 };
 746
 747 /* timer11 slave port */
 748 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
 749         &omap2430_l4_core__timer11,
 750 };
 751
 752 /* timer11 hwmod */
 753 static struct omap_hwmod omap2430_timer11_hwmod = {
 754         .name           = "timer11",
 755         .mpu_irqs       = omap2_timer11_mpu_irqs,
 756         .main_clk       = "gpt11_fck",
 757         .prcm           = {
 758                 .omap2 = {
 759                         .prcm_reg_id = 1,
 760                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 761                         .module_offs = CORE_MOD,
 762                         .idlest_reg_id = 1,
 763                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 764                 },
 765         },
 766         .dev_attr       = &capability_pwm_dev_attr,
 767         .slaves         = omap2430_timer11_slaves,
 768         .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
 769         .class          = &omap2xxx_timer_hwmod_class,
 770 };
 771
 772 /* timer12 */
 773 static struct omap_hwmod omap2430_timer12_hwmod;
 774
 775 /* l4_core -> timer12 */
 776 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
 777         .master         = &omap2430_l4_core_hwmod,
 778         .slave          = &omap2430_timer12_hwmod,
 779         .clk            = "gpt12_ick",
 780         .addr           = omap2xxx_timer12_addrs,
 781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 782 };
 783
 784 /* timer12 slave port */
 785 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
 786         &omap2430_l4_core__timer12,
 787 };
 788
 789 /* timer12 hwmod */
 790 static struct omap_hwmod omap2430_timer12_hwmod = {
 791         .name           = "timer12",
 792         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 793         .main_clk       = "gpt12_fck",
 794         .prcm           = {
 795                 .omap2 = {
 796                         .prcm_reg_id = 1,
 797                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 798                         .module_offs = CORE_MOD,
 799                         .idlest_reg_id = 1,
 800                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 801                 },
 802         },
 803         .dev_attr       = &capability_pwm_dev_attr,
 804         .slaves         = omap2430_timer12_slaves,
 805         .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
 806         .class          = &omap2xxx_timer_hwmod_class,
 807 };
 808
 809 /* l4_wkup -> wd_timer2 */
 810 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 811         {
 812                 .pa_start       = 0x49016000,
 813                 .pa_end         = 0x4901607f,
 814                 .flags          = ADDR_TYPE_RT
 815         },
 816         { }
 817 };
 818
 819 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 820         .master         = &omap2430_l4_wkup_hwmod,
 821         .slave          = &omap2430_wd_timer2_hwmod,
 822         .clk            = "mpu_wdt_ick",
 823         .addr           = omap2430_wd_timer2_addrs,
 824         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 825 };
 826
 827 /* wd_timer2 */
 828 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
 829         &omap2430_l4_wkup__wd_timer2,
 830 };
 831
 832 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
 833         .name           = "wd_timer2",
 834         .class          = &omap2xxx_wd_timer_hwmod_class,
 835         .main_clk       = "mpu_wdt_fck",
 836         .prcm           = {
 837                 .omap2 = {
 838                         .prcm_reg_id = 1,
 839                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 840                         .module_offs = WKUP_MOD,
 841                         .idlest_reg_id = 1,
 842                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 843                 },
 844         },
 845         .slaves         = omap2430_wd_timer2_slaves,
 846         .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
 847 };
 848
 849 /* UART1 */
 850
 851 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
 852         &omap2_l4_core__uart1,
 853 };
 854
 855 static struct omap_hwmod omap2430_uart1_hwmod = {
 856         .name           = "uart1",
 857         .mpu_irqs       = omap2_uart1_mpu_irqs,
 858         .sdma_reqs      = omap2_uart1_sdma_reqs,
 859         .main_clk       = "uart1_fck",
 860         .prcm           = {
 861                 .omap2 = {
 862                         .module_offs = CORE_MOD,
 863                         .prcm_reg_id = 1,
 864                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 865                         .idlest_reg_id = 1,
 866                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 867                 },
 868         },
 869         .slaves         = omap2430_uart1_slaves,
 870         .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
 871         .class          = &omap2_uart_class,
 872 };
 873
 874 /* UART2 */
 875
 876 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
 877         &omap2_l4_core__uart2,
 878 };
 879
 880 static struct omap_hwmod omap2430_uart2_hwmod = {
 881         .name           = "uart2",
 882         .mpu_irqs       = omap2_uart2_mpu_irqs,
 883         .sdma_reqs      = omap2_uart2_sdma_reqs,
 884         .main_clk       = "uart2_fck",
 885         .prcm           = {
 886                 .omap2 = {
 887                         .module_offs = CORE_MOD,
 888                         .prcm_reg_id = 1,
 889                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 890                         .idlest_reg_id = 1,
 891                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 892                 },
 893         },
 894         .slaves         = omap2430_uart2_slaves,
 895         .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
 896         .class          = &omap2_uart_class,
 897 };
 898
 899 /* UART3 */
 900
 901 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
 902         &omap2_l4_core__uart3,
 903 };
 904
 905 static struct omap_hwmod omap2430_uart3_hwmod = {
 906         .name           = "uart3",
 907         .mpu_irqs       = omap2_uart3_mpu_irqs,
 908         .sdma_reqs      = omap2_uart3_sdma_reqs,
 909         .main_clk       = "uart3_fck",
 910         .prcm           = {
 911                 .omap2 = {
 912                         .module_offs = CORE_MOD,
 913                         .prcm_reg_id = 2,
 914                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 915                         .idlest_reg_id = 2,
 916                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 917                 },
 918         },
 919         .slaves         = omap2430_uart3_slaves,
 920         .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
 921         .class          = &omap2_uart_class,
 922 };
 923
 924 /* dss */
 925 /* dss master ports */
 926 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
 927         &omap2430_dss__l3,
 928 };
 929
 930 /* l4_core -> dss */
 931 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
 932         .master         = &omap2430_l4_core_hwmod,
 933         .slave          = &omap2430_dss_core_hwmod,
 934         .clk            = "dss_ick",
 935         .addr           = omap2_dss_addrs,
 936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 937 };
 938
 939 /* dss slave ports */
 940 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
 941         &omap2430_l4_core__dss,
 942 };
 943
 944 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 945         /*
 946          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 947          * driver does not use these clocks.
 948          */
 949         { .role = "tv_clk", .clk = "dss_54m_fck" },
 950         { .role = "sys_clk", .clk = "dss2_fck" },
 951 };
 952
 953 static struct omap_hwmod omap2430_dss_core_hwmod = {
 954         .name           = "dss_core",
 955         .class          = &omap2_dss_hwmod_class,
 956         .main_clk       = "dss1_fck", /* instead of dss_fck */
 957         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 958         .prcm           = {
 959                 .omap2 = {
 960                         .prcm_reg_id = 1,
 961                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 962                         .module_offs = CORE_MOD,
 963                         .idlest_reg_id = 1,
 964                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 965                 },
 966         },
 967         .opt_clks       = dss_opt_clks,
 968         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 969         .slaves         = omap2430_dss_slaves,
 970         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
 971         .masters        = omap2430_dss_masters,
 972         .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
 973         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 974 };
 975
 976 /* l4_core -> dss_dispc */
 977 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
 978         .master         = &omap2430_l4_core_hwmod,
 979         .slave          = &omap2430_dss_dispc_hwmod,
 980         .clk            = "dss_ick",
 981         .addr           = omap2_dss_dispc_addrs,
 982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 983 };
 984
 985 /* dss_dispc slave ports */
 986 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
 987         &omap2430_l4_core__dss_dispc,
 988 };
 989
 990 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
 991         .name           = "dss_dispc",
 992         .class          = &omap2_dispc_hwmod_class,
 993         .mpu_irqs       = omap2_dispc_irqs,
 994         .main_clk       = "dss1_fck",
 995         .prcm           = {
 996                 .omap2 = {
 997                         .prcm_reg_id = 1,
 998                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 999                         .module_offs = CORE_MOD,
1000                         .idlest_reg_id = 1,
1001                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1002                 },
1003         },
1004         .slaves         = omap2430_dss_dispc_slaves,
1005         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1006         .flags          = HWMOD_NO_IDLEST,
1007         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1008 };
1009
1010 /* l4_core -> dss_rfbi */
1011 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1012         .master         = &omap2430_l4_core_hwmod,
1013         .slave          = &omap2430_dss_rfbi_hwmod,
1014         .clk            = "dss_ick",
1015         .addr           = omap2_dss_rfbi_addrs,
1016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1017 };
1018
1019 /* dss_rfbi slave ports */
1020 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1021         &omap2430_l4_core__dss_rfbi,
1022 };
1023
1024 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025         { .role = "ick", .clk = "dss_ick" },
1026 };
1027
1028 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1029         .name           = "dss_rfbi",
1030         .class          = &omap2_rfbi_hwmod_class,
1031         .main_clk       = "dss1_fck",
1032         .prcm           = {
1033                 .omap2 = {
1034                         .prcm_reg_id = 1,
1035                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1036                         .module_offs = CORE_MOD,
1037                 },
1038         },
1039         .opt_clks       = dss_rfbi_opt_clks,
1040         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1041         .slaves         = omap2430_dss_rfbi_slaves,
1042         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1043         .flags          = HWMOD_NO_IDLEST,
1044 };
1045
1046 /* l4_core -> dss_venc */
1047 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1048         .master         = &omap2430_l4_core_hwmod,
1049         .slave          = &omap2430_dss_venc_hwmod,
1050         .clk            = "dss_ick",
1051         .addr           = omap2_dss_venc_addrs,
1052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1053 };
1054
1055 /* dss_venc slave ports */
1056 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1057         &omap2430_l4_core__dss_venc,
1058 };
1059
1060 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1061         .name           = "dss_venc",
1062         .class          = &omap2_venc_hwmod_class,
1063         .main_clk       = "dss_54m_fck",
1064         .prcm           = {
1065                 .omap2 = {
1066                         .prcm_reg_id = 1,
1067                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1068                         .module_offs = CORE_MOD,
1069                 },
1070         },
1071         .slaves         = omap2430_dss_venc_slaves,
1072         .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
1073         .flags          = HWMOD_NO_IDLEST,
1074 };
1075
1076 /* I2C common */
1077 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1078         .rev_offs       = 0x00,
1079         .sysc_offs      = 0x20,
1080         .syss_offs      = 0x10,
1081         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1082                            SYSS_HAS_RESET_STATUS),
1083         .sysc_fields    = &omap_hwmod_sysc_type1,
1084 };
1085
1086 static struct omap_hwmod_class i2c_class = {
1087         .name           = "i2c",
1088         .sysc           = &i2c_sysc,
1089         .rev            = OMAP_I2C_IP_VERSION_1,
1090         .reset          = &omap_i2c_reset,
1091 };
1092
1093 static struct omap_i2c_dev_attr i2c_dev_attr = {
1094         .fifo_depth     = 8, /* bytes */
1095         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1096                           OMAP_I2C_FLAG_BUS_SHIFT_2 |
1097                           OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1098 };
1099
1100 /* I2C1 */
1101
1102 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1103         &omap2430_l4_core__i2c1,
1104 };
1105
1106 static struct omap_hwmod omap2430_i2c1_hwmod = {
1107         .name           = "i2c1",
1108         .flags          = HWMOD_16BIT_REG,
1109         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1110         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1111         .main_clk       = "i2chs1_fck",
1112         .prcm           = {
1113                 .omap2 = {
1114                         /*
1115                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1116                          * I2CHS IP's do not follow the usual pattern.
1117                          * prcm_reg_id alone cannot be used to program
1118                          * the iclk and fclk. Needs to be handled using
1119                          * additional flags when clk handling is moved
1120                          * to hwmod framework.
1121                          */
1122                         .module_offs = CORE_MOD,
1123                         .prcm_reg_id = 1,
1124                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1125                         .idlest_reg_id = 1,
1126                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1127                 },
1128         },
1129         .slaves         = omap2430_i2c1_slaves,
1130         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
1131         .class          = &i2c_class,
1132         .dev_attr       = &i2c_dev_attr,
1133 };
1134
1135 /* I2C2 */
1136
1137 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1138         &omap2430_l4_core__i2c2,
1139 };
1140
1141 static struct omap_hwmod omap2430_i2c2_hwmod = {
1142         .name           = "i2c2",
1143         .flags          = HWMOD_16BIT_REG,
1144         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1145         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1146         .main_clk       = "i2chs2_fck",
1147         .prcm           = {
1148                 .omap2 = {
1149                         .module_offs = CORE_MOD,
1150                         .prcm_reg_id = 1,
1151                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1152                         .idlest_reg_id = 1,
1153                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1154                 },
1155         },
1156         .slaves         = omap2430_i2c2_slaves,
1157         .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
1158         .class          = &i2c_class,
1159         .dev_attr       = &i2c_dev_attr,
1160 };
1161
1162 /* l4_wkup -> gpio1 */
1163 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1164         {
1165                 .pa_start       = 0x4900C000,
1166                 .pa_end         = 0x4900C1ff,
1167                 .flags          = ADDR_TYPE_RT
1168         },
1169         { }
1170 };
1171
1172 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1173         .master         = &omap2430_l4_wkup_hwmod,
1174         .slave          = &omap2430_gpio1_hwmod,
1175         .clk            = "gpios_ick",
1176         .addr           = omap2430_gpio1_addr_space,
1177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1178 };
1179
1180 /* l4_wkup -> gpio2 */
1181 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1182         {
1183                 .pa_start       = 0x4900E000,
1184                 .pa_end         = 0x4900E1ff,
1185                 .flags          = ADDR_TYPE_RT
1186         },
1187         { }
1188 };
1189
1190 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1191         .master         = &omap2430_l4_wkup_hwmod,
1192         .slave          = &omap2430_gpio2_hwmod,
1193         .clk            = "gpios_ick",
1194         .addr           = omap2430_gpio2_addr_space,
1195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1196 };
1197
1198 /* l4_wkup -> gpio3 */
1199 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1200         {
1201                 .pa_start       = 0x49010000,
1202                 .pa_end         = 0x490101ff,
1203                 .flags          = ADDR_TYPE_RT
1204         },
1205         { }
1206 };
1207
1208 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1209         .master         = &omap2430_l4_wkup_hwmod,
1210         .slave          = &omap2430_gpio3_hwmod,
1211         .clk            = "gpios_ick",
1212         .addr           = omap2430_gpio3_addr_space,
1213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1214 };
1215
1216 /* l4_wkup -> gpio4 */
1217 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1218         {
1219                 .pa_start       = 0x49012000,
1220                 .pa_end         = 0x490121ff,
1221                 .flags          = ADDR_TYPE_RT
1222         },
1223         { }
1224 };
1225
1226 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1227         .master         = &omap2430_l4_wkup_hwmod,
1228         .slave          = &omap2430_gpio4_hwmod,
1229         .clk            = "gpios_ick",
1230         .addr           = omap2430_gpio4_addr_space,
1231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1232 };
1233
1234 /* l4_core -> gpio5 */
1235 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1236         {
1237                 .pa_start       = 0x480B6000,
1238                 .pa_end         = 0x480B61ff,
1239                 .flags          = ADDR_TYPE_RT
1240         },
1241         { }
1242 };
1243
1244 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1245         .master         = &omap2430_l4_core_hwmod,
1246         .slave          = &omap2430_gpio5_hwmod,
1247         .clk            = "gpio5_ick",
1248         .addr           = omap2430_gpio5_addr_space,
1249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1250 };
1251
1252 /* gpio dev_attr */
1253 static struct omap_gpio_dev_attr gpio_dev_attr = {
1254         .bank_width = 32,
1255         .dbck_flag = false,
1256 };
1257
1258 /* gpio1 */
1259 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1260         &omap2430_l4_wkup__gpio1,
1261 };
1262
1263 static struct omap_hwmod omap2430_gpio1_hwmod = {
1264         .name           = "gpio1",
1265         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1266         .mpu_irqs       = omap2_gpio1_irqs,
1267         .main_clk       = "gpios_fck",
1268         .prcm           = {
1269                 .omap2 = {
1270                         .prcm_reg_id = 1,
1271                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1272                         .module_offs = WKUP_MOD,
1273                         .idlest_reg_id = 1,
1274                         .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1275                 },
1276         },
1277         .slaves         = omap2430_gpio1_slaves,
1278         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
1279         .class          = &omap2xxx_gpio_hwmod_class,
1280         .dev_attr       = &gpio_dev_attr,
1281 };
1282
1283 /* gpio2 */
1284 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1285         &omap2430_l4_wkup__gpio2,
1286 };
1287
1288 static struct omap_hwmod omap2430_gpio2_hwmod = {
1289         .name           = "gpio2",
1290         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1291         .mpu_irqs       = omap2_gpio2_irqs,
1292         .main_clk       = "gpios_fck",
1293         .prcm           = {
1294                 .omap2 = {
1295                         .prcm_reg_id = 1,
1296                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1297                         .module_offs = WKUP_MOD,
1298                         .idlest_reg_id = 1,
1299                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1300                 },
1301         },
1302         .slaves         = omap2430_gpio2_slaves,
1303         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
1304         .class          = &omap2xxx_gpio_hwmod_class,
1305         .dev_attr       = &gpio_dev_attr,
1306 };
1307
1308 /* gpio3 */
1309 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1310         &omap2430_l4_wkup__gpio3,
1311 };
1312
1313 static struct omap_hwmod omap2430_gpio3_hwmod = {
1314         .name           = "gpio3",
1315         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1316         .mpu_irqs       = omap2_gpio3_irqs,
1317         .main_clk       = "gpios_fck",
1318         .prcm           = {
1319                 .omap2 = {
1320                         .prcm_reg_id = 1,
1321                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1322                         .module_offs = WKUP_MOD,
1323                         .idlest_reg_id = 1,
1324                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1325                 },
1326         },
1327         .slaves         = omap2430_gpio3_slaves,
1328         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
1329         .class          = &omap2xxx_gpio_hwmod_class,
1330         .dev_attr       = &gpio_dev_attr,
1331 };
1332
1333 /* gpio4 */
1334 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1335         &omap2430_l4_wkup__gpio4,
1336 };
1337
1338 static struct omap_hwmod omap2430_gpio4_hwmod = {
1339         .name           = "gpio4",
1340         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1341         .mpu_irqs       = omap2_gpio4_irqs,
1342         .main_clk       = "gpios_fck",
1343         .prcm           = {
1344                 .omap2 = {
1345                         .prcm_reg_id = 1,
1346                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1347                         .module_offs = WKUP_MOD,
1348                         .idlest_reg_id = 1,
1349                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1350                 },
1351         },
1352         .slaves         = omap2430_gpio4_slaves,
1353         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
1354         .class          = &omap2xxx_gpio_hwmod_class,
1355         .dev_attr       = &gpio_dev_attr,
1356 };
1357
1358 /* gpio5 */
1359 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1360         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1361         { .irq = -1 }
1362 };
1363
1364 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1365         &omap2430_l4_core__gpio5,
1366 };
1367
1368 static struct omap_hwmod omap2430_gpio5_hwmod = {
1369         .name           = "gpio5",
1370         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1371         .mpu_irqs       = omap243x_gpio5_irqs,
1372         .main_clk       = "gpio5_fck",
1373         .prcm           = {
1374                 .omap2 = {
1375                         .prcm_reg_id = 2,
1376                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1377                         .module_offs = CORE_MOD,
1378                         .idlest_reg_id = 2,
1379                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1380                 },
1381         },
1382         .slaves         = omap2430_gpio5_slaves,
1383         .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
1384         .class          = &omap2xxx_gpio_hwmod_class,
1385         .dev_attr       = &gpio_dev_attr,
1386 };
1387
1388 /* dma attributes */
1389 static struct omap_dma_dev_attr dma_dev_attr = {
1390         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1391                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1392         .lch_count = 32,
1393 };
1394
1395 /* dma_system -> L3 */
1396 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1397         .master         = &omap2430_dma_system_hwmod,
1398         .slave          = &omap2430_l3_main_hwmod,
1399         .clk            = "core_l3_ck",
1400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1401 };
1402
1403 /* dma_system master ports */
1404 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1405         &omap2430_dma_system__l3,
1406 };
1407
1408 /* l4_core -> dma_system */
1409 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1410         .master         = &omap2430_l4_core_hwmod,
1411         .slave          = &omap2430_dma_system_hwmod,
1412         .clk            = "sdma_ick",
1413         .addr           = omap2_dma_system_addrs,
1414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1415 };
1416
1417 /* dma_system slave ports */
1418 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1419         &omap2430_l4_core__dma_system,
1420 };
1421
1422 static struct omap_hwmod omap2430_dma_system_hwmod = {
1423         .name           = "dma",
1424         .class          = &omap2xxx_dma_hwmod_class,
1425         .mpu_irqs       = omap2_dma_system_irqs,
1426         .main_clk       = "core_l3_ck",
1427         .slaves         = omap2430_dma_system_slaves,
1428         .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
1429         .masters        = omap2430_dma_system_masters,
1430         .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
1431         .dev_attr       = &dma_dev_attr,
1432         .flags          = HWMOD_NO_IDLEST,
1433 };
1434
1435 /* mailbox */
1436 static struct omap_hwmod omap2430_mailbox_hwmod;
1437 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1438         { .irq = 26 },
1439         { .irq = -1 }
1440 };
1441
1442 /* l4_core -> mailbox */
1443 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1444         .master         = &omap2430_l4_core_hwmod,
1445         .slave          = &omap2430_mailbox_hwmod,
1446         .addr           = omap2_mailbox_addrs,
1447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1448 };
1449
1450 /* mailbox slave ports */
1451 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1452         &omap2430_l4_core__mailbox,
1453 };
1454
1455 static struct omap_hwmod omap2430_mailbox_hwmod = {
1456         .name           = "mailbox",
1457         .class          = &omap2xxx_mailbox_hwmod_class,
1458         .mpu_irqs       = omap2430_mailbox_irqs,
1459         .main_clk       = "mailboxes_ick",
1460         .prcm           = {
1461                 .omap2 = {
1462                         .prcm_reg_id = 1,
1463                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1464                         .module_offs = CORE_MOD,
1465                         .idlest_reg_id = 1,
1466                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1467                 },
1468         },
1469         .slaves         = omap2430_mailbox_slaves,
1470         .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
1471 };
1472
1473 /* mcspi1 */
1474 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1475         &omap2430_l4_core__mcspi1,
1476 };
1477
1478 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1479         .num_chipselect = 4,
1480 };
1481
1482 static struct omap_hwmod omap2430_mcspi1_hwmod = {
1483         .name           = "mcspi1_hwmod",
1484         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1485         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1486         .main_clk       = "mcspi1_fck",
1487         .prcm           = {
1488                 .omap2 = {
1489                         .module_offs = CORE_MOD,
1490                         .prcm_reg_id = 1,
1491                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1492                         .idlest_reg_id = 1,
1493                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1494                 },
1495         },
1496         .slaves         = omap2430_mcspi1_slaves,
1497         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
1498         .class          = &omap2xxx_mcspi_class,
1499         .dev_attr       = &omap_mcspi1_dev_attr,
1500 };
1501
1502 /* mcspi2 */
1503 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1504         &omap2430_l4_core__mcspi2,
1505 };
1506
1507 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1508         .num_chipselect = 2,
1509 };
1510
1511 static struct omap_hwmod omap2430_mcspi2_hwmod = {
1512         .name           = "mcspi2_hwmod",
1513         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1514         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1515         .main_clk       = "mcspi2_fck",
1516         .prcm           = {
1517                 .omap2 = {
1518                         .module_offs = CORE_MOD,
1519                         .prcm_reg_id = 1,
1520                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1521                         .idlest_reg_id = 1,
1522                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1523                 },
1524         },
1525         .slaves         = omap2430_mcspi2_slaves,
1526         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
1527         .class          = &omap2xxx_mcspi_class,
1528         .dev_attr       = &omap_mcspi2_dev_attr,
1529 };
1530
1531 /* mcspi3 */
1532 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
1533         { .irq = 91 },
1534         { .irq = -1 }
1535 };
1536
1537 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1538         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
1539         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
1540         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
1541         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1542         { .dma_req = -1 }
1543 };
1544
1545 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1546         &omap2430_l4_core__mcspi3,
1547 };
1548
1549 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1550         .num_chipselect = 2,
1551 };
1552
1553 static struct omap_hwmod omap2430_mcspi3_hwmod = {
1554         .name           = "mcspi3_hwmod",
1555         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
1556         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
1557         .main_clk       = "mcspi3_fck",
1558         .prcm           = {
1559                 .omap2 = {
1560                         .module_offs = CORE_MOD,
1561                         .prcm_reg_id = 2,
1562                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
1563                         .idlest_reg_id = 2,
1564                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1565                 },
1566         },
1567         .slaves         = omap2430_mcspi3_slaves,
1568         .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
1569         .class          = &omap2xxx_mcspi_class,
1570         .dev_attr       = &omap_mcspi3_dev_attr,
1571 };
1572
1573 /*
1574  * usbhsotg
1575  */
1576 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1577         .rev_offs       = 0x0400,
1578         .sysc_offs      = 0x0404,
1579         .syss_offs      = 0x0408,
1580         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1581                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1582                           SYSC_HAS_AUTOIDLE),
1583         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1584                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1585         .sysc_fields    = &omap_hwmod_sysc_type1,
1586 };
1587
1588 static struct omap_hwmod_class usbotg_class = {
1589         .name = "usbotg",
1590         .sysc = &omap2430_usbhsotg_sysc,
1591 };
1592
1593 /* usb_otg_hs */
1594 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
1595
1596         { .name = "mc", .irq = 92 },
1597         { .name = "dma", .irq = 93 },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1602         .name           = "usb_otg_hs",
1603         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
1604         .main_clk       = "usbhs_ick",
1605         .prcm           = {
1606                 .omap2 = {
1607                         .prcm_reg_id = 1,
1608                         .module_bit = OMAP2430_EN_USBHS_MASK,
1609                         .module_offs = CORE_MOD,
1610                         .idlest_reg_id = 1,
1611                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1612                 },
1613         },
1614         .masters        = omap2430_usbhsotg_masters,
1615         .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
1616         .slaves         = omap2430_usbhsotg_slaves,
1617         .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1618         .class          = &usbotg_class,
1619         /*
1620          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1621          * broken when autoidle is enabled
1622          * workaround is to disable the autoidle bit at module level.
1623          */
1624         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1625                                 | HWMOD_SWSUP_MSTANDBY,
1626 };
1627
1628 /*
1629  * 'mcbsp' class
1630  * multi channel buffered serial port controller
1631  */
1632
1633 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
1634         .rev_offs       = 0x007C,
1635         .sysc_offs      = 0x008C,
1636         .sysc_flags     = (SYSC_HAS_SOFTRESET),
1637         .sysc_fields    = &omap_hwmod_sysc_type1,
1638 };
1639
1640 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
1641         .name = "mcbsp",
1642         .sysc = &omap2430_mcbsp_sysc,
1643         .rev  = MCBSP_CONFIG_TYPE2,
1644 };
1645
1646 /* mcbsp1 */
1647 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1648         { .name = "tx",         .irq = 59 },
1649         { .name = "rx",         .irq = 60 },
1650         { .name = "ovr",        .irq = 61 },
1651         { .name = "common",     .irq = 64 },
1652         { .irq = -1 }
1653 };
1654
1655 /* l4_core -> mcbsp1 */
1656 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1657         .master         = &omap2430_l4_core_hwmod,
1658         .slave          = &omap2430_mcbsp1_hwmod,
1659         .clk            = "mcbsp1_ick",
1660         .addr           = omap2_mcbsp1_addrs,
1661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1662 };
1663
1664 /* mcbsp1 slave ports */
1665 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1666         &omap2430_l4_core__mcbsp1,
1667 };
1668
1669 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1670         .name           = "mcbsp1",
1671         .class          = &omap2430_mcbsp_hwmod_class,
1672         .mpu_irqs       = omap2430_mcbsp1_irqs,
1673         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1674         .main_clk       = "mcbsp1_fck",
1675         .prcm           = {
1676                 .omap2 = {
1677                         .prcm_reg_id = 1,
1678                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1679                         .module_offs = CORE_MOD,
1680                         .idlest_reg_id = 1,
1681                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1682                 },
1683         },
1684         .slaves         = omap2430_mcbsp1_slaves,
1685         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1686 };
1687
1688 /* mcbsp2 */
1689 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1690         { .name = "tx",         .irq = 62 },
1691         { .name = "rx",         .irq = 63 },
1692         { .name = "common",     .irq = 16 },
1693         { .irq = -1 }
1694 };
1695
1696 /* l4_core -> mcbsp2 */
1697 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1698         .master         = &omap2430_l4_core_hwmod,
1699         .slave          = &omap2430_mcbsp2_hwmod,
1700         .clk            = "mcbsp2_ick",
1701         .addr           = omap2xxx_mcbsp2_addrs,
1702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1703 };
1704
1705 /* mcbsp2 slave ports */
1706 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1707         &omap2430_l4_core__mcbsp2,
1708 };
1709
1710 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1711         .name           = "mcbsp2",
1712         .class          = &omap2430_mcbsp_hwmod_class,
1713         .mpu_irqs       = omap2430_mcbsp2_irqs,
1714         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1715         .main_clk       = "mcbsp2_fck",
1716         .prcm           = {
1717                 .omap2 = {
1718                         .prcm_reg_id = 1,
1719                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1720                         .module_offs = CORE_MOD,
1721                         .idlest_reg_id = 1,
1722                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1723                 },
1724         },
1725         .slaves         = omap2430_mcbsp2_slaves,
1726         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1727 };
1728
1729 /* mcbsp3 */
1730 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1731         { .name = "tx",         .irq = 89 },
1732         { .name = "rx",         .irq = 90 },
1733         { .name = "common",     .irq = 17 },
1734         { .irq = -1 }
1735 };
1736
1737 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1738         {
1739                 .name           = "mpu",
1740                 .pa_start       = 0x4808C000,
1741                 .pa_end         = 0x4808C0ff,
1742                 .flags          = ADDR_TYPE_RT
1743         },
1744         { }
1745 };
1746
1747 /* l4_core -> mcbsp3 */
1748 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1749         .master         = &omap2430_l4_core_hwmod,
1750         .slave          = &omap2430_mcbsp3_hwmod,
1751         .clk            = "mcbsp3_ick",
1752         .addr           = omap2430_mcbsp3_addrs,
1753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1754 };
1755
1756 /* mcbsp3 slave ports */
1757 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1758         &omap2430_l4_core__mcbsp3,
1759 };
1760
1761 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1762         .name           = "mcbsp3",
1763         .class          = &omap2430_mcbsp_hwmod_class,
1764         .mpu_irqs       = omap2430_mcbsp3_irqs,
1765         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1766         .main_clk       = "mcbsp3_fck",
1767         .prcm           = {
1768                 .omap2 = {
1769                         .prcm_reg_id = 1,
1770                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
1771                         .module_offs = CORE_MOD,
1772                         .idlest_reg_id = 2,
1773                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1774                 },
1775         },
1776         .slaves         = omap2430_mcbsp3_slaves,
1777         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1778 };
1779
1780 /* mcbsp4 */
1781 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
1782         { .name = "tx",         .irq = 54 },
1783         { .name = "rx",         .irq = 55 },
1784         { .name = "common",     .irq = 18 },
1785         { .irq = -1 }
1786 };
1787
1788 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1789         { .name = "rx", .dma_req = 20 },
1790         { .name = "tx", .dma_req = 19 },
1791         { .dma_req = -1 }
1792 };
1793
1794 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1795         {
1796                 .name           = "mpu",
1797                 .pa_start       = 0x4808E000,
1798                 .pa_end         = 0x4808E0ff,
1799                 .flags          = ADDR_TYPE_RT
1800         },
1801         { }
1802 };
1803
1804 /* l4_core -> mcbsp4 */
1805 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1806         .master         = &omap2430_l4_core_hwmod,
1807         .slave          = &omap2430_mcbsp4_hwmod,
1808         .clk            = "mcbsp4_ick",
1809         .addr           = omap2430_mcbsp4_addrs,
1810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1811 };
1812
1813 /* mcbsp4 slave ports */
1814 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1815         &omap2430_l4_core__mcbsp4,
1816 };
1817
1818 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1819         .name           = "mcbsp4",
1820         .class          = &omap2430_mcbsp_hwmod_class,
1821         .mpu_irqs       = omap2430_mcbsp4_irqs,
1822         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
1823         .main_clk       = "mcbsp4_fck",
1824         .prcm           = {
1825                 .omap2 = {
1826                         .prcm_reg_id = 1,
1827                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
1828                         .module_offs = CORE_MOD,
1829                         .idlest_reg_id = 2,
1830                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1831                 },
1832         },
1833         .slaves         = omap2430_mcbsp4_slaves,
1834         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1835 };
1836
1837 /* mcbsp5 */
1838 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
1839         { .name = "tx",         .irq = 81 },
1840         { .name = "rx",         .irq = 82 },
1841         { .name = "common",     .irq = 19 },
1842         { .irq = -1 }
1843 };
1844
1845 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1846         { .name = "rx", .dma_req = 22 },
1847         { .name = "tx", .dma_req = 21 },
1848         { .dma_req = -1 }
1849 };
1850
1851 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1852         {
1853                 .name           = "mpu",
1854                 .pa_start       = 0x48096000,
1855                 .pa_end         = 0x480960ff,
1856                 .flags          = ADDR_TYPE_RT
1857         },
1858         { }
1859 };
1860
1861 /* l4_core -> mcbsp5 */
1862 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1863         .master         = &omap2430_l4_core_hwmod,
1864         .slave          = &omap2430_mcbsp5_hwmod,
1865         .clk            = "mcbsp5_ick",
1866         .addr           = omap2430_mcbsp5_addrs,
1867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1868 };
1869
1870 /* mcbsp5 slave ports */
1871 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1872         &omap2430_l4_core__mcbsp5,
1873 };
1874
1875 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1876         .name           = "mcbsp5",
1877         .class          = &omap2430_mcbsp_hwmod_class,
1878         .mpu_irqs       = omap2430_mcbsp5_irqs,
1879         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
1880         .main_clk       = "mcbsp5_fck",
1881         .prcm           = {
1882                 .omap2 = {
1883                         .prcm_reg_id = 1,
1884                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
1885                         .module_offs = CORE_MOD,
1886                         .idlest_reg_id = 2,
1887                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1888                 },
1889         },
1890         .slaves         = omap2430_mcbsp5_slaves,
1891         .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1892 };
1893
1894 /* MMC/SD/SDIO common */
1895
1896 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1897         .rev_offs       = 0x1fc,
1898         .sysc_offs      = 0x10,
1899         .syss_offs      = 0x14,
1900         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1901                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1902                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1903         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1904         .sysc_fields    = &omap_hwmod_sysc_type1,
1905 };
1906
1907 static struct omap_hwmod_class omap2430_mmc_class = {
1908         .name = "mmc",
1909         .sysc = &omap2430_mmc_sysc,
1910 };
1911
1912 /* MMC/SD/SDIO1 */
1913
1914 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1915         { .irq = 83 },
1916         { .irq = -1 }
1917 };
1918
1919 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
1920         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
1921         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1922         { .dma_req = -1 }
1923 };
1924
1925 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1926         { .role = "dbck", .clk = "mmchsdb1_fck" },
1927 };
1928
1929 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1930         &omap2430_l4_core__mmc1,
1931 };
1932
1933 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1934         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1935 };
1936
1937 static struct omap_hwmod omap2430_mmc1_hwmod = {
1938         .name           = "mmc1",
1939         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1940         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
1941         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
1942         .opt_clks       = omap2430_mmc1_opt_clks,
1943         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
1944         .main_clk       = "mmchs1_fck",
1945         .prcm           = {
1946                 .omap2 = {
1947                         .module_offs = CORE_MOD,
1948                         .prcm_reg_id = 2,
1949                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
1950                         .idlest_reg_id = 2,
1951                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
1952                 },
1953         },
1954         .dev_attr       = &mmc1_dev_attr,
1955         .slaves         = omap2430_mmc1_slaves,
1956         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
1957         .class          = &omap2430_mmc_class,
1958 };
1959
1960 /* MMC/SD/SDIO2 */
1961
1962 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1963         { .irq = 86 },
1964         { .irq = -1 }
1965 };
1966
1967 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
1968         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
1969         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1970         { .dma_req = -1 }
1971 };
1972
1973 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1974         { .role = "dbck", .clk = "mmchsdb2_fck" },
1975 };
1976
1977 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1978         &omap2430_l4_core__mmc2,
1979 };
1980
1981 static struct omap_hwmod omap2430_mmc2_hwmod = {
1982         .name           = "mmc2",
1983         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1984         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
1985         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
1986         .opt_clks       = omap2430_mmc2_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
1988         .main_clk       = "mmchs2_fck",
1989         .prcm           = {
1990                 .omap2 = {
1991                         .module_offs = CORE_MOD,
1992                         .prcm_reg_id = 2,
1993                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
1994                         .idlest_reg_id = 2,
1995                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
1996                 },
1997         },
1998         .slaves         = omap2430_mmc2_slaves,
1999         .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
2000         .class          = &omap2430_mmc_class,
2001 };
2002
2003 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2004         &omap2430_l3_main_hwmod,
2005         &omap2430_l4_core_hwmod,
2006         &omap2430_l4_wkup_hwmod,
2007         &omap2430_mpu_hwmod,
2008         &omap2430_iva_hwmod,
2009
2010         &omap2430_timer1_hwmod,
2011         &omap2430_timer2_hwmod,
2012         &omap2430_timer3_hwmod,
2013         &omap2430_timer4_hwmod,
2014         &omap2430_timer5_hwmod,
2015         &omap2430_timer6_hwmod,
2016         &omap2430_timer7_hwmod,
2017         &omap2430_timer8_hwmod,
2018         &omap2430_timer9_hwmod,
2019         &omap2430_timer10_hwmod,
2020         &omap2430_timer11_hwmod,
2021         &omap2430_timer12_hwmod,
2022
2023         &omap2430_wd_timer2_hwmod,
2024         &omap2430_uart1_hwmod,
2025         &omap2430_uart2_hwmod,
2026         &omap2430_uart3_hwmod,
2027         /* dss class */
2028         &omap2430_dss_core_hwmod,
2029         &omap2430_dss_dispc_hwmod,
2030         &omap2430_dss_rfbi_hwmod,
2031         &omap2430_dss_venc_hwmod,
2032         /* i2c class */
2033         &omap2430_i2c1_hwmod,
2034         &omap2430_i2c2_hwmod,
2035         &omap2430_mmc1_hwmod,
2036         &omap2430_mmc2_hwmod,
2037
2038         /* gpio class */
2039         &omap2430_gpio1_hwmod,
2040         &omap2430_gpio2_hwmod,
2041         &omap2430_gpio3_hwmod,
2042         &omap2430_gpio4_hwmod,
2043         &omap2430_gpio5_hwmod,
2044
2045         /* dma_system class*/
2046         &omap2430_dma_system_hwmod,
2047
2048         /* mcbsp class */
2049         &omap2430_mcbsp1_hwmod,
2050         &omap2430_mcbsp2_hwmod,
2051         &omap2430_mcbsp3_hwmod,
2052         &omap2430_mcbsp4_hwmod,
2053         &omap2430_mcbsp5_hwmod,
2054
2055         /* mailbox class */
2056         &omap2430_mailbox_hwmod,
2057
2058         /* mcspi class */
2059         &omap2430_mcspi1_hwmod,
2060         &omap2430_mcspi2_hwmod,
2061         &omap2430_mcspi3_hwmod,
2062
2063         /* usbotg class*/
2064         &omap2430_usbhsotg_hwmod,
2065
2066         NULL,
2067 };
2068
2069 int __init omap2430_hwmod_init(void)
2070 {
2071         return omap_hwmod_register(omap2430_hwmods);
2072 }