arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21
  22 #include "omap_hwmod_common_data.h"
  23
  24 #include "cm-regbits-24xx.h"
  25 #include "prm-regbits-24xx.h"
  26 #include "wd_timer.h"
  27
  28 /*
  29  * OMAP2420 hardware module integration data
  30  *
  31  * ALl of the data in this section should be autogeneratable from the
  32  * TI hardware database or other technical documentation.  Data that
  33  * is driver-specific or driver-kernel integration-specific belongs
  34  * elsewhere.
  35  */
  36
  37 static struct omap_hwmod omap2420_mpu_hwmod;
  38 static struct omap_hwmod omap2420_iva_hwmod;
  39 static struct omap_hwmod omap2420_l3_main_hwmod;
  40 static struct omap_hwmod omap2420_l4_core_hwmod;
  41 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  42 static struct omap_hwmod omap2420_gpio1_hwmod;
  43 static struct omap_hwmod omap2420_gpio2_hwmod;
  44 static struct omap_hwmod omap2420_gpio3_hwmod;
  45 static struct omap_hwmod omap2420_gpio4_hwmod;
  46 static struct omap_hwmod omap2420_dma_system_hwmod;
  47
  48 /* L3 -> L4_CORE interface */
  49 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  50         .master = &omap2420_l3_main_hwmod,
  51         .slave  = &omap2420_l4_core_hwmod,
  52         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  53 };
  54
  55 /* MPU -> L3 interface */
  56 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  57         .master = &omap2420_mpu_hwmod,
  58         .slave  = &omap2420_l3_main_hwmod,
  59         .user   = OCP_USER_MPU,
  60 };
  61
  62 /* Slave interfaces on the L3 interconnect */
  63 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  64         &omap2420_mpu__l3_main,
  65 };
  66
  67 /* Master interfaces on the L3 interconnect */
  68 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  69         &omap2420_l3_main__l4_core,
  70 };
  71
  72 /* L3 */
  73 static struct omap_hwmod omap2420_l3_main_hwmod = {
  74         .name           = "l3_main",
  75         .class          = &l3_hwmod_class,
  76         .masters        = omap2420_l3_main_masters,
  77         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
  78         .slaves         = omap2420_l3_main_slaves,
  79         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
  80         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
  81         .flags          = HWMOD_NO_IDLEST,
  82 };
  83
  84 static struct omap_hwmod omap2420_l4_wkup_hwmod;
  85 static struct omap_hwmod omap2420_uart1_hwmod;
  86 static struct omap_hwmod omap2420_uart2_hwmod;
  87 static struct omap_hwmod omap2420_uart3_hwmod;
  88 static struct omap_hwmod omap2420_i2c1_hwmod;
  89 static struct omap_hwmod omap2420_i2c2_hwmod;
  90
  91 /* L4_CORE -> L4_WKUP interface */
  92 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
  93         .master = &omap2420_l4_core_hwmod,
  94         .slave  = &omap2420_l4_wkup_hwmod,
  95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  96 };
  97
  98 /* L4 CORE -> UART1 interface */
  99 static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
 100         {
 101                 .pa_start       = OMAP2_UART1_BASE,
 102                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
 103                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 104         },
 105 };
 106
 107 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 108         .master         = &omap2420_l4_core_hwmod,
 109         .slave          = &omap2420_uart1_hwmod,
 110         .clk            = "uart1_ick",
 111         .addr           = omap2420_uart1_addr_space,
 112         .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
 113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 114 };
 115
 116 /* L4 CORE -> UART2 interface */
 117 static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
 118         {
 119                 .pa_start       = OMAP2_UART2_BASE,
 120                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
 121                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 122         },
 123 };
 124
 125 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 126         .master         = &omap2420_l4_core_hwmod,
 127         .slave          = &omap2420_uart2_hwmod,
 128         .clk            = "uart2_ick",
 129         .addr           = omap2420_uart2_addr_space,
 130         .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* L4 PER -> UART3 interface */
 135 static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
 136         {
 137                 .pa_start       = OMAP2_UART3_BASE,
 138                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
 139                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 140         },
 141 };
 142
 143 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 144         .master         = &omap2420_l4_core_hwmod,
 145         .slave          = &omap2420_uart3_hwmod,
 146         .clk            = "uart3_ick",
 147         .addr           = omap2420_uart3_addr_space,
 148         .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
 149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 150 };
 151
 152 /* I2C IP block address space length (in bytes) */
 153 #define OMAP2_I2C_AS_LEN                128
 154
 155 /* L4 CORE -> I2C1 interface */
 156 static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
 157         {
 158                 .pa_start       = 0x48070000,
 159                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 160                 .flags          = ADDR_TYPE_RT,
 161         },
 162 };
 163
 164 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 165         .master         = &omap2420_l4_core_hwmod,
 166         .slave          = &omap2420_i2c1_hwmod,
 167         .clk            = "i2c1_ick",
 168         .addr           = omap2420_i2c1_addr_space,
 169         .addr_cnt       = ARRAY_SIZE(omap2420_i2c1_addr_space),
 170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 171 };
 172
 173 /* L4 CORE -> I2C2 interface */
 174 static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
 175         {
 176                 .pa_start       = 0x48072000,
 177                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 178                 .flags          = ADDR_TYPE_RT,
 179         },
 180 };
 181
 182 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 183         .master         = &omap2420_l4_core_hwmod,
 184         .slave          = &omap2420_i2c2_hwmod,
 185         .clk            = "i2c2_ick",
 186         .addr           = omap2420_i2c2_addr_space,
 187         .addr_cnt       = ARRAY_SIZE(omap2420_i2c2_addr_space),
 188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 189 };
 190
 191 /* Slave interfaces on the L4_CORE interconnect */
 192 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 193         &omap2420_l3_main__l4_core,
 194 };
 195
 196 /* Master interfaces on the L4_CORE interconnect */
 197 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 198         &omap2420_l4_core__l4_wkup,
 199         &omap2_l4_core__uart1,
 200         &omap2_l4_core__uart2,
 201         &omap2_l4_core__uart3,
 202         &omap2420_l4_core__i2c1,
 203         &omap2420_l4_core__i2c2
 204 };
 205
 206 /* L4 CORE */
 207 static struct omap_hwmod omap2420_l4_core_hwmod = {
 208         .name           = "l4_core",
 209         .class          = &l4_hwmod_class,
 210         .masters        = omap2420_l4_core_masters,
 211         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 212         .slaves         = omap2420_l4_core_slaves,
 213         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 214         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 215         .flags          = HWMOD_NO_IDLEST,
 216 };
 217
 218 /* Slave interfaces on the L4_WKUP interconnect */
 219 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 220         &omap2420_l4_core__l4_wkup,
 221 };
 222
 223 /* Master interfaces on the L4_WKUP interconnect */
 224 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 225 };
 226
 227 /* L4 WKUP */
 228 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 229         .name           = "l4_wkup",
 230         .class          = &l4_hwmod_class,
 231         .masters        = omap2420_l4_wkup_masters,
 232         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 233         .slaves         = omap2420_l4_wkup_slaves,
 234         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 235         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 236         .flags          = HWMOD_NO_IDLEST,
 237 };
 238
 239 /* Master interfaces on the MPU device */
 240 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 241         &omap2420_mpu__l3_main,
 242 };
 243
 244 /* MPU */
 245 static struct omap_hwmod omap2420_mpu_hwmod = {
 246         .name           = "mpu",
 247         .class          = &mpu_hwmod_class,
 248         .main_clk       = "mpu_ck",
 249         .masters        = omap2420_mpu_masters,
 250         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 251         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 252 };
 253
 254 /*
 255  * IVA1 interface data
 256  */
 257
 258 /* IVA <- L3 interface */
 259 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 260         .master         = &omap2420_l3_main_hwmod,
 261         .slave          = &omap2420_iva_hwmod,
 262         .clk            = "iva1_ifck",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 267         &omap2420_l3__iva,
 268 };
 269
 270 /*
 271  * IVA2 (IVA2)
 272  */
 273
 274 static struct omap_hwmod omap2420_iva_hwmod = {
 275         .name           = "iva",
 276         .class          = &iva_hwmod_class,
 277         .masters        = omap2420_iva_masters,
 278         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 279         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 280 };
 281
 282 /* l4_wkup -> wd_timer2 */
 283 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 284         {
 285                 .pa_start       = 0x48022000,
 286                 .pa_end         = 0x4802207f,
 287                 .flags          = ADDR_TYPE_RT
 288         },
 289 };
 290
 291 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 292         .master         = &omap2420_l4_wkup_hwmod,
 293         .slave          = &omap2420_wd_timer2_hwmod,
 294         .clk            = "mpu_wdt_ick",
 295         .addr           = omap2420_wd_timer2_addrs,
 296         .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
 297         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 298 };
 299
 300 /*
 301  * 'wd_timer' class
 302  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 303  * overflow condition
 304  */
 305
 306 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 307         .rev_offs       = 0x0000,
 308         .sysc_offs      = 0x0010,
 309         .syss_offs      = 0x0014,
 310         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 311                            SYSC_HAS_AUTOIDLE),
 312         .sysc_fields    = &omap_hwmod_sysc_type1,
 313 };
 314
 315 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 316         .name           = "wd_timer",
 317         .sysc           = &omap2420_wd_timer_sysc,
 318         .pre_shutdown   = &omap2_wd_timer_disable
 319 };
 320
 321 /* wd_timer2 */
 322 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 323         &omap2420_l4_wkup__wd_timer2,
 324 };
 325
 326 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 327         .name           = "wd_timer2",
 328         .class          = &omap2420_wd_timer_hwmod_class,
 329         .main_clk       = "mpu_wdt_fck",
 330         .prcm           = {
 331                 .omap2 = {
 332                         .prcm_reg_id = 1,
 333                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 334                         .module_offs = WKUP_MOD,
 335                         .idlest_reg_id = 1,
 336                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 337                 },
 338         },
 339         .slaves         = omap2420_wd_timer2_slaves,
 340         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 341         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 342 };
 343
 344 /* UART */
 345
 346 static struct omap_hwmod_class_sysconfig uart_sysc = {
 347         .rev_offs       = 0x50,
 348         .sysc_offs      = 0x54,
 349         .syss_offs      = 0x58,
 350         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 351                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 352                            SYSC_HAS_AUTOIDLE),
 353         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 354         .sysc_fields    = &omap_hwmod_sysc_type1,
 355 };
 356
 357 static struct omap_hwmod_class uart_class = {
 358         .name = "uart",
 359         .sysc = &uart_sysc,
 360 };
 361
 362 /* UART1 */
 363
 364 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 365         { .irq = INT_24XX_UART1_IRQ, },
 366 };
 367
 368 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 369         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 370         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 371 };
 372
 373 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 374         &omap2_l4_core__uart1,
 375 };
 376
 377 static struct omap_hwmod omap2420_uart1_hwmod = {
 378         .name           = "uart1",
 379         .mpu_irqs       = uart1_mpu_irqs,
 380         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 381         .sdma_reqs      = uart1_sdma_reqs,
 382         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 383         .main_clk       = "uart1_fck",
 384         .prcm           = {
 385                 .omap2 = {
 386                         .module_offs = CORE_MOD,
 387                         .prcm_reg_id = 1,
 388                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 389                         .idlest_reg_id = 1,
 390                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 391                 },
 392         },
 393         .slaves         = omap2420_uart1_slaves,
 394         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 395         .class          = &uart_class,
 396         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 397 };
 398
 399 /* UART2 */
 400
 401 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 402         { .irq = INT_24XX_UART2_IRQ, },
 403 };
 404
 405 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 406         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 407         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 408 };
 409
 410 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 411         &omap2_l4_core__uart2,
 412 };
 413
 414 static struct omap_hwmod omap2420_uart2_hwmod = {
 415         .name           = "uart2",
 416         .mpu_irqs       = uart2_mpu_irqs,
 417         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 418         .sdma_reqs      = uart2_sdma_reqs,
 419         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 420         .main_clk       = "uart2_fck",
 421         .prcm           = {
 422                 .omap2 = {
 423                         .module_offs = CORE_MOD,
 424                         .prcm_reg_id = 1,
 425                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 426                         .idlest_reg_id = 1,
 427                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 428                 },
 429         },
 430         .slaves         = omap2420_uart2_slaves,
 431         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 432         .class          = &uart_class,
 433         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 434 };
 435
 436 /* UART3 */
 437
 438 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 439         { .irq = INT_24XX_UART3_IRQ, },
 440 };
 441
 442 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 443         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 444         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 445 };
 446
 447 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 448         &omap2_l4_core__uart3,
 449 };
 450
 451 static struct omap_hwmod omap2420_uart3_hwmod = {
 452         .name           = "uart3",
 453         .mpu_irqs       = uart3_mpu_irqs,
 454         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 455         .sdma_reqs      = uart3_sdma_reqs,
 456         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 457         .main_clk       = "uart3_fck",
 458         .prcm           = {
 459                 .omap2 = {
 460                         .module_offs = CORE_MOD,
 461                         .prcm_reg_id = 2,
 462                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 463                         .idlest_reg_id = 2,
 464                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 465                 },
 466         },
 467         .slaves         = omap2420_uart3_slaves,
 468         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 469         .class          = &uart_class,
 470         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 471 };
 472
 473 /* I2C common */
 474 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 475         .rev_offs       = 0x00,
 476         .sysc_offs      = 0x20,
 477         .syss_offs      = 0x10,
 478         .sysc_flags     = SYSC_HAS_SOFTRESET,
 479         .sysc_fields    = &omap_hwmod_sysc_type1,
 480 };
 481
 482 static struct omap_hwmod_class i2c_class = {
 483         .name           = "i2c",
 484         .sysc           = &i2c_sysc,
 485 };
 486
 487 static struct omap_i2c_dev_attr i2c_dev_attr;
 488
 489 /* I2C1 */
 490
 491 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
 492         { .irq = INT_24XX_I2C1_IRQ, },
 493 };
 494
 495 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
 496         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 497         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 498 };
 499
 500 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
 501         &omap2420_l4_core__i2c1,
 502 };
 503
 504 static struct omap_hwmod omap2420_i2c1_hwmod = {
 505         .name           = "i2c1",
 506         .mpu_irqs       = i2c1_mpu_irqs,
 507         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
 508         .sdma_reqs      = i2c1_sdma_reqs,
 509         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
 510         .main_clk       = "i2c1_fck",
 511         .prcm           = {
 512                 .omap2 = {
 513                         .module_offs = CORE_MOD,
 514                         .prcm_reg_id = 1,
 515                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
 516                         .idlest_reg_id = 1,
 517                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 518                 },
 519         },
 520         .slaves         = omap2420_i2c1_slaves,
 521         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
 522         .class          = &i2c_class,
 523         .dev_attr       = &i2c_dev_attr,
 524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 525         .flags          = HWMOD_16BIT_REG,
 526 };
 527
 528 /* I2C2 */
 529
 530 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 531         { .irq = INT_24XX_I2C2_IRQ, },
 532 };
 533
 534 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
 535         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 536         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 537 };
 538
 539 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
 540         &omap2420_l4_core__i2c2,
 541 };
 542
 543 static struct omap_hwmod omap2420_i2c2_hwmod = {
 544         .name           = "i2c2",
 545         .mpu_irqs       = i2c2_mpu_irqs,
 546         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
 547         .sdma_reqs      = i2c2_sdma_reqs,
 548         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
 549         .main_clk       = "i2c2_fck",
 550         .prcm           = {
 551                 .omap2 = {
 552                         .module_offs = CORE_MOD,
 553                         .prcm_reg_id = 1,
 554                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
 555                         .idlest_reg_id = 1,
 556                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 557                 },
 558         },
 559         .slaves         = omap2420_i2c2_slaves,
 560         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
 561         .class          = &i2c_class,
 562         .dev_attr       = &i2c_dev_attr,
 563         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 564         .flags          = HWMOD_16BIT_REG,
 565 };
 566
 567 /* l4_wkup -> gpio1 */
 568 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 569         {
 570                 .pa_start       = 0x48018000,
 571                 .pa_end         = 0x480181ff,
 572                 .flags          = ADDR_TYPE_RT
 573         },
 574 };
 575
 576 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 577         .master         = &omap2420_l4_wkup_hwmod,
 578         .slave          = &omap2420_gpio1_hwmod,
 579         .clk            = "gpios_ick",
 580         .addr           = omap2420_gpio1_addr_space,
 581         .addr_cnt       = ARRAY_SIZE(omap2420_gpio1_addr_space),
 582         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 583 };
 584
 585 /* l4_wkup -> gpio2 */
 586 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 587         {
 588                 .pa_start       = 0x4801a000,
 589                 .pa_end         = 0x4801a1ff,
 590                 .flags          = ADDR_TYPE_RT
 591         },
 592 };
 593
 594 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 595         .master         = &omap2420_l4_wkup_hwmod,
 596         .slave          = &omap2420_gpio2_hwmod,
 597         .clk            = "gpios_ick",
 598         .addr           = omap2420_gpio2_addr_space,
 599         .addr_cnt       = ARRAY_SIZE(omap2420_gpio2_addr_space),
 600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 601 };
 602
 603 /* l4_wkup -> gpio3 */
 604 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 605         {
 606                 .pa_start       = 0x4801c000,
 607                 .pa_end         = 0x4801c1ff,
 608                 .flags          = ADDR_TYPE_RT
 609         },
 610 };
 611
 612 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 613         .master         = &omap2420_l4_wkup_hwmod,
 614         .slave          = &omap2420_gpio3_hwmod,
 615         .clk            = "gpios_ick",
 616         .addr           = omap2420_gpio3_addr_space,
 617         .addr_cnt       = ARRAY_SIZE(omap2420_gpio3_addr_space),
 618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 619 };
 620
 621 /* l4_wkup -> gpio4 */
 622 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 623         {
 624                 .pa_start       = 0x4801e000,
 625                 .pa_end         = 0x4801e1ff,
 626                 .flags          = ADDR_TYPE_RT
 627         },
 628 };
 629
 630 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 631         .master         = &omap2420_l4_wkup_hwmod,
 632         .slave          = &omap2420_gpio4_hwmod,
 633         .clk            = "gpios_ick",
 634         .addr           = omap2420_gpio4_addr_space,
 635         .addr_cnt       = ARRAY_SIZE(omap2420_gpio4_addr_space),
 636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 637 };
 638
 639 /* gpio dev_attr */
 640 static struct omap_gpio_dev_attr gpio_dev_attr = {
 641         .bank_width = 32,
 642         .dbck_flag = false,
 643 };
 644
 645 static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
 646         .rev_offs       = 0x0000,
 647         .sysc_offs      = 0x0010,
 648         .syss_offs      = 0x0014,
 649         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 650                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 651         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 652         .sysc_fields    = &omap_hwmod_sysc_type1,
 653 };
 654
 655 /*
 656  * 'gpio' class
 657  * general purpose io module
 658  */
 659 static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
 660         .name = "gpio",
 661         .sysc = &omap242x_gpio_sysc,
 662         .rev = 0,
 663 };
 664
 665 /* gpio1 */
 666 static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
 667         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
 668 };
 669
 670 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
 671         &omap2420_l4_wkup__gpio1,
 672 };
 673
 674 static struct omap_hwmod omap2420_gpio1_hwmod = {
 675         .name           = "gpio1",
 676         .mpu_irqs       = omap242x_gpio1_irqs,
 677         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
 678         .main_clk       = "gpios_fck",
 679         .prcm           = {
 680                 .omap2 = {
 681                         .prcm_reg_id = 1,
 682                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 683                         .module_offs = WKUP_MOD,
 684                         .idlest_reg_id = 1,
 685                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 686                 },
 687         },
 688         .slaves         = omap2420_gpio1_slaves,
 689         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
 690         .class          = &omap242x_gpio_hwmod_class,
 691         .dev_attr       = &gpio_dev_attr,
 692         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 693 };
 694
 695 /* gpio2 */
 696 static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
 697         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
 698 };
 699
 700 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
 701         &omap2420_l4_wkup__gpio2,
 702 };
 703
 704 static struct omap_hwmod omap2420_gpio2_hwmod = {
 705         .name           = "gpio2",
 706         .mpu_irqs       = omap242x_gpio2_irqs,
 707         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
 708         .main_clk       = "gpios_fck",
 709         .prcm           = {
 710                 .omap2 = {
 711                         .prcm_reg_id = 1,
 712                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 713                         .module_offs = WKUP_MOD,
 714                         .idlest_reg_id = 1,
 715                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 716                 },
 717         },
 718         .slaves         = omap2420_gpio2_slaves,
 719         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
 720         .class          = &omap242x_gpio_hwmod_class,
 721         .dev_attr       = &gpio_dev_attr,
 722         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 723 };
 724
 725 /* gpio3 */
 726 static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
 727         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
 728 };
 729
 730 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
 731         &omap2420_l4_wkup__gpio3,
 732 };
 733
 734 static struct omap_hwmod omap2420_gpio3_hwmod = {
 735         .name           = "gpio3",
 736         .mpu_irqs       = omap242x_gpio3_irqs,
 737         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
 738         .main_clk       = "gpios_fck",
 739         .prcm           = {
 740                 .omap2 = {
 741                         .prcm_reg_id = 1,
 742                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 743                         .module_offs = WKUP_MOD,
 744                         .idlest_reg_id = 1,
 745                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 746                 },
 747         },
 748         .slaves         = omap2420_gpio3_slaves,
 749         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
 750         .class          = &omap242x_gpio_hwmod_class,
 751         .dev_attr       = &gpio_dev_attr,
 752         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 753 };
 754
 755 /* gpio4 */
 756 static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
 757         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
 758 };
 759
 760 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
 761         &omap2420_l4_wkup__gpio4,
 762 };
 763
 764 static struct omap_hwmod omap2420_gpio4_hwmod = {
 765         .name           = "gpio4",
 766         .mpu_irqs       = omap242x_gpio4_irqs,
 767         .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
 768         .main_clk       = "gpios_fck",
 769         .prcm           = {
 770                 .omap2 = {
 771                         .prcm_reg_id = 1,
 772                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 773                         .module_offs = WKUP_MOD,
 774                         .idlest_reg_id = 1,
 775                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 776                 },
 777         },
 778         .slaves         = omap2420_gpio4_slaves,
 779         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
 780         .class          = &omap242x_gpio_hwmod_class,
 781         .dev_attr       = &gpio_dev_attr,
 782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 783 };
 784
 785 /* system dma */
 786 static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
 787         .rev_offs       = 0x0000,
 788         .sysc_offs      = 0x002c,
 789         .syss_offs      = 0x0028,
 790         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 791                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 792                            SYSC_HAS_AUTOIDLE),
 793         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 794         .sysc_fields    = &omap_hwmod_sysc_type1,
 795 };
 796
 797 static struct omap_hwmod_class omap2420_dma_hwmod_class = {
 798         .name = "dma",
 799         .sysc = &omap2420_dma_sysc,
 800 };
 801
 802 /* dma attributes */
 803 static struct omap_dma_dev_attr dma_dev_attr = {
 804         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 805                                                 IS_CSSA_32 | IS_CDSA_32,
 806         .lch_count = 32,
 807 };
 808
 809 static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
 810         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
 811         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
 812         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
 813         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
 814 };
 815
 816 static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
 817         {
 818                 .pa_start       = 0x48056000,
 819                 .pa_end         = 0x4a0560ff,
 820                 .flags          = ADDR_TYPE_RT
 821         },
 822 };
 823
 824 /* dma_system -> L3 */
 825 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 826         .master         = &omap2420_dma_system_hwmod,
 827         .slave          = &omap2420_l3_main_hwmod,
 828         .clk            = "core_l3_ck",
 829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 830 };
 831
 832 /* dma_system master ports */
 833 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
 834         &omap2420_dma_system__l3,
 835 };
 836
 837 /* l4_core -> dma_system */
 838 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 839         .master         = &omap2420_l4_core_hwmod,
 840         .slave          = &omap2420_dma_system_hwmod,
 841         .clk            = "sdma_ick",
 842         .addr           = omap2420_dma_system_addrs,
 843         .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
 844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 845 };
 846
 847 /* dma_system slave ports */
 848 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
 849         &omap2420_l4_core__dma_system,
 850 };
 851
 852 static struct omap_hwmod omap2420_dma_system_hwmod = {
 853         .name           = "dma",
 854         .class          = &omap2420_dma_hwmod_class,
 855         .mpu_irqs       = omap2420_dma_system_irqs,
 856         .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
 857         .main_clk       = "core_l3_ck",
 858         .slaves         = omap2420_dma_system_slaves,
 859         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
 860         .masters        = omap2420_dma_system_masters,
 861         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
 862         .dev_attr       = &dma_dev_attr,
 863         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 864         .flags          = HWMOD_NO_IDLEST,
 865 };
 866
 867 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 868         &omap2420_l3_main_hwmod,
 869         &omap2420_l4_core_hwmod,
 870         &omap2420_l4_wkup_hwmod,
 871         &omap2420_mpu_hwmod,
 872         &omap2420_iva_hwmod,
 873         &omap2420_wd_timer2_hwmod,
 874         &omap2420_uart1_hwmod,
 875         &omap2420_uart2_hwmod,
 876         &omap2420_uart3_hwmod,
 877         &omap2420_i2c1_hwmod,
 878         &omap2420_i2c2_hwmod,
 879
 880         /* gpio class */
 881         &omap2420_gpio1_hwmod,
 882         &omap2420_gpio2_hwmod,
 883         &omap2420_gpio3_hwmod,
 884         &omap2420_gpio4_hwmod,
 885
 886         /* dma_system class*/
 887         &omap2420_dma_system_hwmod,
 888         NULL,
 889 };
 890
 891 int __init omap2420_hwmod_init(void)
 892 {
 893         return omap_hwmod_init(omap2420_hwmods);
 894 }