arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .flags          = HWMOD_NO_IDLEST,
 104 };
 105
 106 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 107 static struct omap_hwmod omap2420_uart1_hwmod;
 108 static struct omap_hwmod omap2420_uart2_hwmod;
 109 static struct omap_hwmod omap2420_uart3_hwmod;
 110 static struct omap_hwmod omap2420_i2c1_hwmod;
 111 static struct omap_hwmod omap2420_i2c2_hwmod;
 112 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 114
 115 /* l4 core -> mcspi1 interface */
 116 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 117         .master         = &omap2420_l4_core_hwmod,
 118         .slave          = &omap2420_mcspi1_hwmod,
 119         .clk            = "mcspi1_ick",
 120         .addr           = omap2_mcspi1_addr_space,
 121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 122 };
 123
 124 /* l4 core -> mcspi2 interface */
 125 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 126         .master         = &omap2420_l4_core_hwmod,
 127         .slave          = &omap2420_mcspi2_hwmod,
 128         .clk            = "mcspi2_ick",
 129         .addr           = omap2_mcspi2_addr_space,
 130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 131 };
 132
 133 /* L4_CORE -> L4_WKUP interface */
 134 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 135         .master = &omap2420_l4_core_hwmod,
 136         .slave  = &omap2420_l4_wkup_hwmod,
 137         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 138 };
 139
 140 /* L4 CORE -> UART1 interface */
 141 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 142         .master         = &omap2420_l4_core_hwmod,
 143         .slave          = &omap2420_uart1_hwmod,
 144         .clk            = "uart1_ick",
 145         .addr           = omap2xxx_uart1_addr_space,
 146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 147 };
 148
 149 /* L4 CORE -> UART2 interface */
 150 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 151         .master         = &omap2420_l4_core_hwmod,
 152         .slave          = &omap2420_uart2_hwmod,
 153         .clk            = "uart2_ick",
 154         .addr           = omap2xxx_uart2_addr_space,
 155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 /* L4 PER -> UART3 interface */
 159 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 160         .master         = &omap2420_l4_core_hwmod,
 161         .slave          = &omap2420_uart3_hwmod,
 162         .clk            = "uart3_ick",
 163         .addr           = omap2xxx_uart3_addr_space,
 164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 165 };
 166
 167 /* L4 CORE -> I2C1 interface */
 168 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 169         .master         = &omap2420_l4_core_hwmod,
 170         .slave          = &omap2420_i2c1_hwmod,
 171         .clk            = "i2c1_ick",
 172         .addr           = omap2_i2c1_addr_space,
 173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 174 };
 175
 176 /* L4 CORE -> I2C2 interface */
 177 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 178         .master         = &omap2420_l4_core_hwmod,
 179         .slave          = &omap2420_i2c2_hwmod,
 180         .clk            = "i2c2_ick",
 181         .addr           = omap2_i2c2_addr_space,
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /* Slave interfaces on the L4_CORE interconnect */
 186 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 187         &omap2420_l3_main__l4_core,
 188 };
 189
 190 /* Master interfaces on the L4_CORE interconnect */
 191 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 192         &omap2420_l4_core__l4_wkup,
 193         &omap2_l4_core__uart1,
 194         &omap2_l4_core__uart2,
 195         &omap2_l4_core__uart3,
 196         &omap2420_l4_core__i2c1,
 197         &omap2420_l4_core__i2c2
 198 };
 199
 200 /* L4 CORE */
 201 static struct omap_hwmod omap2420_l4_core_hwmod = {
 202         .name           = "l4_core",
 203         .class          = &l4_hwmod_class,
 204         .masters        = omap2420_l4_core_masters,
 205         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 206         .slaves         = omap2420_l4_core_slaves,
 207         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 208         .flags          = HWMOD_NO_IDLEST,
 209 };
 210
 211 /* Slave interfaces on the L4_WKUP interconnect */
 212 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 213         &omap2420_l4_core__l4_wkup,
 214 };
 215
 216 /* Master interfaces on the L4_WKUP interconnect */
 217 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 218 };
 219
 220 /* L4 WKUP */
 221 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 222         .name           = "l4_wkup",
 223         .class          = &l4_hwmod_class,
 224         .masters        = omap2420_l4_wkup_masters,
 225         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 226         .slaves         = omap2420_l4_wkup_slaves,
 227         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 228         .flags          = HWMOD_NO_IDLEST,
 229 };
 230
 231 /* Master interfaces on the MPU device */
 232 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 233         &omap2420_mpu__l3_main,
 234 };
 235
 236 /* MPU */
 237 static struct omap_hwmod omap2420_mpu_hwmod = {
 238         .name           = "mpu",
 239         .class          = &mpu_hwmod_class,
 240         .main_clk       = "mpu_ck",
 241         .masters        = omap2420_mpu_masters,
 242         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 243 };
 244
 245 /*
 246  * IVA1 interface data
 247  */
 248
 249 /* IVA <- L3 interface */
 250 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 251         .master         = &omap2420_l3_main_hwmod,
 252         .slave          = &omap2420_iva_hwmod,
 253         .clk            = "iva1_ifck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 258         &omap2420_l3__iva,
 259 };
 260
 261 /*
 262  * IVA2 (IVA2)
 263  */
 264
 265 static struct omap_hwmod omap2420_iva_hwmod = {
 266         .name           = "iva",
 267         .class          = &iva_hwmod_class,
 268         .masters        = omap2420_iva_masters,
 269         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 270 };
 271
 272 /* always-on timers dev attribute */
 273 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 274         .timer_capability       = OMAP_TIMER_ALWON,
 275 };
 276
 277 /* pwm timers dev attribute */
 278 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 279         .timer_capability       = OMAP_TIMER_HAS_PWM,
 280 };
 281
 282 /* timer1 */
 283 static struct omap_hwmod omap2420_timer1_hwmod;
 284
 285 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 286         {
 287                 .pa_start       = 0x48028000,
 288                 .pa_end         = 0x48028000 + SZ_1K - 1,
 289                 .flags          = ADDR_TYPE_RT
 290         },
 291         { }
 292 };
 293
 294 /* l4_wkup -> timer1 */
 295 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 296         .master         = &omap2420_l4_wkup_hwmod,
 297         .slave          = &omap2420_timer1_hwmod,
 298         .clk            = "gpt1_ick",
 299         .addr           = omap2420_timer1_addrs,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* timer1 slave port */
 304 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 305         &omap2420_l4_wkup__timer1,
 306 };
 307
 308 /* timer1 hwmod */
 309 static struct omap_hwmod omap2420_timer1_hwmod = {
 310         .name           = "timer1",
 311         .mpu_irqs       = omap2_timer1_mpu_irqs,
 312         .main_clk       = "gpt1_fck",
 313         .prcm           = {
 314                 .omap2 = {
 315                         .prcm_reg_id = 1,
 316                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 317                         .module_offs = WKUP_MOD,
 318                         .idlest_reg_id = 1,
 319                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 320                 },
 321         },
 322         .dev_attr       = &capability_alwon_dev_attr,
 323         .slaves         = omap2420_timer1_slaves,
 324         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 325         .class          = &omap2xxx_timer_hwmod_class,
 326 };
 327
 328 /* timer2 */
 329 static struct omap_hwmod omap2420_timer2_hwmod;
 330
 331 /* l4_core -> timer2 */
 332 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 333         .master         = &omap2420_l4_core_hwmod,
 334         .slave          = &omap2420_timer2_hwmod,
 335         .clk            = "gpt2_ick",
 336         .addr           = omap2xxx_timer2_addrs,
 337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 338 };
 339
 340 /* timer2 slave port */
 341 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 342         &omap2420_l4_core__timer2,
 343 };
 344
 345 /* timer2 hwmod */
 346 static struct omap_hwmod omap2420_timer2_hwmod = {
 347         .name           = "timer2",
 348         .mpu_irqs       = omap2_timer2_mpu_irqs,
 349         .main_clk       = "gpt2_fck",
 350         .prcm           = {
 351                 .omap2 = {
 352                         .prcm_reg_id = 1,
 353                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 354                         .module_offs = CORE_MOD,
 355                         .idlest_reg_id = 1,
 356                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 357                 },
 358         },
 359         .dev_attr       = &capability_alwon_dev_attr,
 360         .slaves         = omap2420_timer2_slaves,
 361         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 362         .class          = &omap2xxx_timer_hwmod_class,
 363 };
 364
 365 /* timer3 */
 366 static struct omap_hwmod omap2420_timer3_hwmod;
 367
 368 /* l4_core -> timer3 */
 369 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 370         .master         = &omap2420_l4_core_hwmod,
 371         .slave          = &omap2420_timer3_hwmod,
 372         .clk            = "gpt3_ick",
 373         .addr           = omap2xxx_timer3_addrs,
 374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 375 };
 376
 377 /* timer3 slave port */
 378 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 379         &omap2420_l4_core__timer3,
 380 };
 381
 382 /* timer3 hwmod */
 383 static struct omap_hwmod omap2420_timer3_hwmod = {
 384         .name           = "timer3",
 385         .mpu_irqs       = omap2_timer3_mpu_irqs,
 386         .main_clk       = "gpt3_fck",
 387         .prcm           = {
 388                 .omap2 = {
 389                         .prcm_reg_id = 1,
 390                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 391                         .module_offs = CORE_MOD,
 392                         .idlest_reg_id = 1,
 393                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 394                 },
 395         },
 396         .dev_attr       = &capability_alwon_dev_attr,
 397         .slaves         = omap2420_timer3_slaves,
 398         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 399         .class          = &omap2xxx_timer_hwmod_class,
 400 };
 401
 402 /* timer4 */
 403 static struct omap_hwmod omap2420_timer4_hwmod;
 404
 405 /* l4_core -> timer4 */
 406 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 407         .master         = &omap2420_l4_core_hwmod,
 408         .slave          = &omap2420_timer4_hwmod,
 409         .clk            = "gpt4_ick",
 410         .addr           = omap2xxx_timer4_addrs,
 411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 412 };
 413
 414 /* timer4 slave port */
 415 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 416         &omap2420_l4_core__timer4,
 417 };
 418
 419 /* timer4 hwmod */
 420 static struct omap_hwmod omap2420_timer4_hwmod = {
 421         .name           = "timer4",
 422         .mpu_irqs       = omap2_timer4_mpu_irqs,
 423         .main_clk       = "gpt4_fck",
 424         .prcm           = {
 425                 .omap2 = {
 426                         .prcm_reg_id = 1,
 427                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 428                         .module_offs = CORE_MOD,
 429                         .idlest_reg_id = 1,
 430                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 431                 },
 432         },
 433         .dev_attr       = &capability_alwon_dev_attr,
 434         .slaves         = omap2420_timer4_slaves,
 435         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 436         .class          = &omap2xxx_timer_hwmod_class,
 437 };
 438
 439 /* timer5 */
 440 static struct omap_hwmod omap2420_timer5_hwmod;
 441
 442 /* l4_core -> timer5 */
 443 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 444         .master         = &omap2420_l4_core_hwmod,
 445         .slave          = &omap2420_timer5_hwmod,
 446         .clk            = "gpt5_ick",
 447         .addr           = omap2xxx_timer5_addrs,
 448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 449 };
 450
 451 /* timer5 slave port */
 452 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 453         &omap2420_l4_core__timer5,
 454 };
 455
 456 /* timer5 hwmod */
 457 static struct omap_hwmod omap2420_timer5_hwmod = {
 458         .name           = "timer5",
 459         .mpu_irqs       = omap2_timer5_mpu_irqs,
 460         .main_clk       = "gpt5_fck",
 461         .prcm           = {
 462                 .omap2 = {
 463                         .prcm_reg_id = 1,
 464                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 465                         .module_offs = CORE_MOD,
 466                         .idlest_reg_id = 1,
 467                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 468                 },
 469         },
 470         .dev_attr       = &capability_alwon_dev_attr,
 471         .slaves         = omap2420_timer5_slaves,
 472         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 473         .class          = &omap2xxx_timer_hwmod_class,
 474 };
 475
 476
 477 /* timer6 */
 478 static struct omap_hwmod omap2420_timer6_hwmod;
 479
 480 /* l4_core -> timer6 */
 481 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 482         .master         = &omap2420_l4_core_hwmod,
 483         .slave          = &omap2420_timer6_hwmod,
 484         .clk            = "gpt6_ick",
 485         .addr           = omap2xxx_timer6_addrs,
 486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 487 };
 488
 489 /* timer6 slave port */
 490 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 491         &omap2420_l4_core__timer6,
 492 };
 493
 494 /* timer6 hwmod */
 495 static struct omap_hwmod omap2420_timer6_hwmod = {
 496         .name           = "timer6",
 497         .mpu_irqs       = omap2_timer6_mpu_irqs,
 498         .main_clk       = "gpt6_fck",
 499         .prcm           = {
 500                 .omap2 = {
 501                         .prcm_reg_id = 1,
 502                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 503                         .module_offs = CORE_MOD,
 504                         .idlest_reg_id = 1,
 505                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 506                 },
 507         },
 508         .dev_attr       = &capability_alwon_dev_attr,
 509         .slaves         = omap2420_timer6_slaves,
 510         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 511         .class          = &omap2xxx_timer_hwmod_class,
 512 };
 513
 514 /* timer7 */
 515 static struct omap_hwmod omap2420_timer7_hwmod;
 516
 517 /* l4_core -> timer7 */
 518 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 519         .master         = &omap2420_l4_core_hwmod,
 520         .slave          = &omap2420_timer7_hwmod,
 521         .clk            = "gpt7_ick",
 522         .addr           = omap2xxx_timer7_addrs,
 523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 524 };
 525
 526 /* timer7 slave port */
 527 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 528         &omap2420_l4_core__timer7,
 529 };
 530
 531 /* timer7 hwmod */
 532 static struct omap_hwmod omap2420_timer7_hwmod = {
 533         .name           = "timer7",
 534         .mpu_irqs       = omap2_timer7_mpu_irqs,
 535         .main_clk       = "gpt7_fck",
 536         .prcm           = {
 537                 .omap2 = {
 538                         .prcm_reg_id = 1,
 539                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 540                         .module_offs = CORE_MOD,
 541                         .idlest_reg_id = 1,
 542                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 543                 },
 544         },
 545         .dev_attr       = &capability_alwon_dev_attr,
 546         .slaves         = omap2420_timer7_slaves,
 547         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 548         .class          = &omap2xxx_timer_hwmod_class,
 549 };
 550
 551 /* timer8 */
 552 static struct omap_hwmod omap2420_timer8_hwmod;
 553
 554 /* l4_core -> timer8 */
 555 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 556         .master         = &omap2420_l4_core_hwmod,
 557         .slave          = &omap2420_timer8_hwmod,
 558         .clk            = "gpt8_ick",
 559         .addr           = omap2xxx_timer8_addrs,
 560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 561 };
 562
 563 /* timer8 slave port */
 564 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 565         &omap2420_l4_core__timer8,
 566 };
 567
 568 /* timer8 hwmod */
 569 static struct omap_hwmod omap2420_timer8_hwmod = {
 570         .name           = "timer8",
 571         .mpu_irqs       = omap2_timer8_mpu_irqs,
 572         .main_clk       = "gpt8_fck",
 573         .prcm           = {
 574                 .omap2 = {
 575                         .prcm_reg_id = 1,
 576                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 577                         .module_offs = CORE_MOD,
 578                         .idlest_reg_id = 1,
 579                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 580                 },
 581         },
 582         .dev_attr       = &capability_alwon_dev_attr,
 583         .slaves         = omap2420_timer8_slaves,
 584         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 585         .class          = &omap2xxx_timer_hwmod_class,
 586 };
 587
 588 /* timer9 */
 589 static struct omap_hwmod omap2420_timer9_hwmod;
 590
 591 /* l4_core -> timer9 */
 592 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 593         .master         = &omap2420_l4_core_hwmod,
 594         .slave          = &omap2420_timer9_hwmod,
 595         .clk            = "gpt9_ick",
 596         .addr           = omap2xxx_timer9_addrs,
 597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 598 };
 599
 600 /* timer9 slave port */
 601 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 602         &omap2420_l4_core__timer9,
 603 };
 604
 605 /* timer9 hwmod */
 606 static struct omap_hwmod omap2420_timer9_hwmod = {
 607         .name           = "timer9",
 608         .mpu_irqs       = omap2_timer9_mpu_irqs,
 609         .main_clk       = "gpt9_fck",
 610         .prcm           = {
 611                 .omap2 = {
 612                         .prcm_reg_id = 1,
 613                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 614                         .module_offs = CORE_MOD,
 615                         .idlest_reg_id = 1,
 616                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 617                 },
 618         },
 619         .dev_attr       = &capability_pwm_dev_attr,
 620         .slaves         = omap2420_timer9_slaves,
 621         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 622         .class          = &omap2xxx_timer_hwmod_class,
 623 };
 624
 625 /* timer10 */
 626 static struct omap_hwmod omap2420_timer10_hwmod;
 627
 628 /* l4_core -> timer10 */
 629 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 630         .master         = &omap2420_l4_core_hwmod,
 631         .slave          = &omap2420_timer10_hwmod,
 632         .clk            = "gpt10_ick",
 633         .addr           = omap2_timer10_addrs,
 634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 635 };
 636
 637 /* timer10 slave port */
 638 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 639         &omap2420_l4_core__timer10,
 640 };
 641
 642 /* timer10 hwmod */
 643 static struct omap_hwmod omap2420_timer10_hwmod = {
 644         .name           = "timer10",
 645         .mpu_irqs       = omap2_timer10_mpu_irqs,
 646         .main_clk       = "gpt10_fck",
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 651                         .module_offs = CORE_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 654                 },
 655         },
 656         .dev_attr       = &capability_pwm_dev_attr,
 657         .slaves         = omap2420_timer10_slaves,
 658         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 659         .class          = &omap2xxx_timer_hwmod_class,
 660 };
 661
 662 /* timer11 */
 663 static struct omap_hwmod omap2420_timer11_hwmod;
 664
 665 /* l4_core -> timer11 */
 666 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 667         .master         = &omap2420_l4_core_hwmod,
 668         .slave          = &omap2420_timer11_hwmod,
 669         .clk            = "gpt11_ick",
 670         .addr           = omap2_timer11_addrs,
 671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 672 };
 673
 674 /* timer11 slave port */
 675 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 676         &omap2420_l4_core__timer11,
 677 };
 678
 679 /* timer11 hwmod */
 680 static struct omap_hwmod omap2420_timer11_hwmod = {
 681         .name           = "timer11",
 682         .mpu_irqs       = omap2_timer11_mpu_irqs,
 683         .main_clk       = "gpt11_fck",
 684         .prcm           = {
 685                 .omap2 = {
 686                         .prcm_reg_id = 1,
 687                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 688                         .module_offs = CORE_MOD,
 689                         .idlest_reg_id = 1,
 690                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 691                 },
 692         },
 693         .dev_attr       = &capability_pwm_dev_attr,
 694         .slaves         = omap2420_timer11_slaves,
 695         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 696         .class          = &omap2xxx_timer_hwmod_class,
 697 };
 698
 699 /* timer12 */
 700 static struct omap_hwmod omap2420_timer12_hwmod;
 701
 702 /* l4_core -> timer12 */
 703 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 704         .master         = &omap2420_l4_core_hwmod,
 705         .slave          = &omap2420_timer12_hwmod,
 706         .clk            = "gpt12_ick",
 707         .addr           = omap2xxx_timer12_addrs,
 708         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 709 };
 710
 711 /* timer12 slave port */
 712 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 713         &omap2420_l4_core__timer12,
 714 };
 715
 716 /* timer12 hwmod */
 717 static struct omap_hwmod omap2420_timer12_hwmod = {
 718         .name           = "timer12",
 719         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 720         .main_clk       = "gpt12_fck",
 721         .prcm           = {
 722                 .omap2 = {
 723                         .prcm_reg_id = 1,
 724                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 725                         .module_offs = CORE_MOD,
 726                         .idlest_reg_id = 1,
 727                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 728                 },
 729         },
 730         .dev_attr       = &capability_pwm_dev_attr,
 731         .slaves         = omap2420_timer12_slaves,
 732         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 733         .class          = &omap2xxx_timer_hwmod_class,
 734 };
 735
 736 /* l4_wkup -> wd_timer2 */
 737 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 738         {
 739                 .pa_start       = 0x48022000,
 740                 .pa_end         = 0x4802207f,
 741                 .flags          = ADDR_TYPE_RT
 742         },
 743         { }
 744 };
 745
 746 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 747         .master         = &omap2420_l4_wkup_hwmod,
 748         .slave          = &omap2420_wd_timer2_hwmod,
 749         .clk            = "mpu_wdt_ick",
 750         .addr           = omap2420_wd_timer2_addrs,
 751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 752 };
 753
 754 /* wd_timer2 */
 755 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 756         &omap2420_l4_wkup__wd_timer2,
 757 };
 758
 759 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 760         .name           = "wd_timer2",
 761         .class          = &omap2xxx_wd_timer_hwmod_class,
 762         .main_clk       = "mpu_wdt_fck",
 763         .prcm           = {
 764                 .omap2 = {
 765                         .prcm_reg_id = 1,
 766                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 767                         .module_offs = WKUP_MOD,
 768                         .idlest_reg_id = 1,
 769                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 770                 },
 771         },
 772         .slaves         = omap2420_wd_timer2_slaves,
 773         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 774 };
 775
 776 /* UART1 */
 777
 778 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 779         &omap2_l4_core__uart1,
 780 };
 781
 782 static struct omap_hwmod omap2420_uart1_hwmod = {
 783         .name           = "uart1",
 784         .mpu_irqs       = omap2_uart1_mpu_irqs,
 785         .sdma_reqs      = omap2_uart1_sdma_reqs,
 786         .main_clk       = "uart1_fck",
 787         .prcm           = {
 788                 .omap2 = {
 789                         .module_offs = CORE_MOD,
 790                         .prcm_reg_id = 1,
 791                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 792                         .idlest_reg_id = 1,
 793                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 794                 },
 795         },
 796         .slaves         = omap2420_uart1_slaves,
 797         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 798         .class          = &omap2_uart_class,
 799 };
 800
 801 /* UART2 */
 802
 803 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 804         &omap2_l4_core__uart2,
 805 };
 806
 807 static struct omap_hwmod omap2420_uart2_hwmod = {
 808         .name           = "uart2",
 809         .mpu_irqs       = omap2_uart2_mpu_irqs,
 810         .sdma_reqs      = omap2_uart2_sdma_reqs,
 811         .main_clk       = "uart2_fck",
 812         .prcm           = {
 813                 .omap2 = {
 814                         .module_offs = CORE_MOD,
 815                         .prcm_reg_id = 1,
 816                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 817                         .idlest_reg_id = 1,
 818                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 819                 },
 820         },
 821         .slaves         = omap2420_uart2_slaves,
 822         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 823         .class          = &omap2_uart_class,
 824 };
 825
 826 /* UART3 */
 827
 828 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 829         &omap2_l4_core__uart3,
 830 };
 831
 832 static struct omap_hwmod omap2420_uart3_hwmod = {
 833         .name           = "uart3",
 834         .mpu_irqs       = omap2_uart3_mpu_irqs,
 835         .sdma_reqs      = omap2_uart3_sdma_reqs,
 836         .main_clk       = "uart3_fck",
 837         .prcm           = {
 838                 .omap2 = {
 839                         .module_offs = CORE_MOD,
 840                         .prcm_reg_id = 2,
 841                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 842                         .idlest_reg_id = 2,
 843                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 844                 },
 845         },
 846         .slaves         = omap2420_uart3_slaves,
 847         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 848         .class          = &omap2_uart_class,
 849 };
 850
 851 /* dss */
 852 /* dss master ports */
 853 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
 854         &omap2420_dss__l3,
 855 };
 856
 857 /* l4_core -> dss */
 858 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
 859         .master         = &omap2420_l4_core_hwmod,
 860         .slave          = &omap2420_dss_core_hwmod,
 861         .clk            = "dss_ick",
 862         .addr           = omap2_dss_addrs,
 863         .fw = {
 864                 .omap2 = {
 865                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 866                         .flags  = OMAP_FIREWALL_L4,
 867                 }
 868         },
 869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 870 };
 871
 872 /* dss slave ports */
 873 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 874         &omap2420_l4_core__dss,
 875 };
 876
 877 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 878         { .role = "tv_clk", .clk = "dss_54m_fck" },
 879         { .role = "sys_clk", .clk = "dss2_fck" },
 880 };
 881
 882 static struct omap_hwmod omap2420_dss_core_hwmod = {
 883         .name           = "dss_core",
 884         .class          = &omap2_dss_hwmod_class,
 885         .main_clk       = "dss1_fck", /* instead of dss_fck */
 886         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 887         .prcm           = {
 888                 .omap2 = {
 889                         .prcm_reg_id = 1,
 890                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 891                         .module_offs = CORE_MOD,
 892                         .idlest_reg_id = 1,
 893                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 894                 },
 895         },
 896         .opt_clks       = dss_opt_clks,
 897         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 898         .slaves         = omap2420_dss_slaves,
 899         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
 900         .masters        = omap2420_dss_masters,
 901         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
 902         .flags          = HWMOD_NO_IDLEST,
 903 };
 904
 905 /* l4_core -> dss_dispc */
 906 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
 907         .master         = &omap2420_l4_core_hwmod,
 908         .slave          = &omap2420_dss_dispc_hwmod,
 909         .clk            = "dss_ick",
 910         .addr           = omap2_dss_dispc_addrs,
 911         .fw = {
 912                 .omap2 = {
 913                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
 914                         .flags  = OMAP_FIREWALL_L4,
 915                 }
 916         },
 917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 918 };
 919
 920 /* dss_dispc slave ports */
 921 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
 922         &omap2420_l4_core__dss_dispc,
 923 };
 924
 925 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
 926         .name           = "dss_dispc",
 927         .class          = &omap2_dispc_hwmod_class,
 928         .mpu_irqs       = omap2_dispc_irqs,
 929         .main_clk       = "dss1_fck",
 930         .prcm           = {
 931                 .omap2 = {
 932                         .prcm_reg_id = 1,
 933                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 934                         .module_offs = CORE_MOD,
 935                         .idlest_reg_id = 1,
 936                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 937                 },
 938         },
 939         .slaves         = omap2420_dss_dispc_slaves,
 940         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
 941         .flags          = HWMOD_NO_IDLEST,
 942 };
 943
 944 /* l4_core -> dss_rfbi */
 945 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
 946         .master         = &omap2420_l4_core_hwmod,
 947         .slave          = &omap2420_dss_rfbi_hwmod,
 948         .clk            = "dss_ick",
 949         .addr           = omap2_dss_rfbi_addrs,
 950         .fw = {
 951                 .omap2 = {
 952                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 953                         .flags  = OMAP_FIREWALL_L4,
 954                 }
 955         },
 956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 957 };
 958
 959 /* dss_rfbi slave ports */
 960 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
 961         &omap2420_l4_core__dss_rfbi,
 962 };
 963
 964 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
 965         .name           = "dss_rfbi",
 966         .class          = &omap2_rfbi_hwmod_class,
 967         .main_clk       = "dss1_fck",
 968         .prcm           = {
 969                 .omap2 = {
 970                         .prcm_reg_id = 1,
 971                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 972                         .module_offs = CORE_MOD,
 973                 },
 974         },
 975         .slaves         = omap2420_dss_rfbi_slaves,
 976         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
 977         .flags          = HWMOD_NO_IDLEST,
 978 };
 979
 980 /* l4_core -> dss_venc */
 981 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
 982         .master         = &omap2420_l4_core_hwmod,
 983         .slave          = &omap2420_dss_venc_hwmod,
 984         .clk            = "dss_54m_fck",
 985         .addr           = omap2_dss_venc_addrs,
 986         .fw = {
 987                 .omap2 = {
 988                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
 989                         .flags  = OMAP_FIREWALL_L4,
 990                 }
 991         },
 992         .flags          = OCPIF_SWSUP_IDLE,
 993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 994 };
 995
 996 /* dss_venc slave ports */
 997 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
 998         &omap2420_l4_core__dss_venc,
 999 };
1000
1001 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1002         .name           = "dss_venc",
1003         .class          = &omap2_venc_hwmod_class,
1004         .main_clk       = "dss1_fck",
1005         .prcm           = {
1006                 .omap2 = {
1007                         .prcm_reg_id = 1,
1008                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1009                         .module_offs = CORE_MOD,
1010                 },
1011         },
1012         .slaves         = omap2420_dss_venc_slaves,
1013         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
1014         .flags          = HWMOD_NO_IDLEST,
1015 };
1016
1017 /* I2C common */
1018 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1019         .rev_offs       = 0x00,
1020         .sysc_offs      = 0x20,
1021         .syss_offs      = 0x10,
1022         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1023         .sysc_fields    = &omap_hwmod_sysc_type1,
1024 };
1025
1026 static struct omap_hwmod_class i2c_class = {
1027         .name           = "i2c",
1028         .sysc           = &i2c_sysc,
1029         .rev            = OMAP_I2C_IP_VERSION_1,
1030         .reset          = &omap_i2c_reset,
1031 };
1032
1033 static struct omap_i2c_dev_attr i2c_dev_attr = {
1034         .flags          = OMAP_I2C_FLAG_NO_FIFO |
1035                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
1036                           OMAP_I2C_FLAG_16BIT_DATA_REG |
1037                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1038 };
1039
1040 /* I2C1 */
1041
1042 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1043         &omap2420_l4_core__i2c1,
1044 };
1045
1046 static struct omap_hwmod omap2420_i2c1_hwmod = {
1047         .name           = "i2c1",
1048         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1049         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1050         .main_clk       = "i2c1_fck",
1051         .prcm           = {
1052                 .omap2 = {
1053                         .module_offs = CORE_MOD,
1054                         .prcm_reg_id = 1,
1055                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1056                         .idlest_reg_id = 1,
1057                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1058                 },
1059         },
1060         .slaves         = omap2420_i2c1_slaves,
1061         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1062         .class          = &i2c_class,
1063         .dev_attr       = &i2c_dev_attr,
1064         .flags          = HWMOD_16BIT_REG,
1065 };
1066
1067 /* I2C2 */
1068
1069 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1070         &omap2420_l4_core__i2c2,
1071 };
1072
1073 static struct omap_hwmod omap2420_i2c2_hwmod = {
1074         .name           = "i2c2",
1075         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1076         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1077         .main_clk       = "i2c2_fck",
1078         .prcm           = {
1079                 .omap2 = {
1080                         .module_offs = CORE_MOD,
1081                         .prcm_reg_id = 1,
1082                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1083                         .idlest_reg_id = 1,
1084                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1085                 },
1086         },
1087         .slaves         = omap2420_i2c2_slaves,
1088         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1089         .class          = &i2c_class,
1090         .dev_attr       = &i2c_dev_attr,
1091         .flags          = HWMOD_16BIT_REG,
1092 };
1093
1094 /* l4_wkup -> gpio1 */
1095 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1096         {
1097                 .pa_start       = 0x48018000,
1098                 .pa_end         = 0x480181ff,
1099                 .flags          = ADDR_TYPE_RT
1100         },
1101         { }
1102 };
1103
1104 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1105         .master         = &omap2420_l4_wkup_hwmod,
1106         .slave          = &omap2420_gpio1_hwmod,
1107         .clk            = "gpios_ick",
1108         .addr           = omap2420_gpio1_addr_space,
1109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1110 };
1111
1112 /* l4_wkup -> gpio2 */
1113 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1114         {
1115                 .pa_start       = 0x4801a000,
1116                 .pa_end         = 0x4801a1ff,
1117                 .flags          = ADDR_TYPE_RT
1118         },
1119         { }
1120 };
1121
1122 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1123         .master         = &omap2420_l4_wkup_hwmod,
1124         .slave          = &omap2420_gpio2_hwmod,
1125         .clk            = "gpios_ick",
1126         .addr           = omap2420_gpio2_addr_space,
1127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1128 };
1129
1130 /* l4_wkup -> gpio3 */
1131 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1132         {
1133                 .pa_start       = 0x4801c000,
1134                 .pa_end         = 0x4801c1ff,
1135                 .flags          = ADDR_TYPE_RT
1136         },
1137         { }
1138 };
1139
1140 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1141         .master         = &omap2420_l4_wkup_hwmod,
1142         .slave          = &omap2420_gpio3_hwmod,
1143         .clk            = "gpios_ick",
1144         .addr           = omap2420_gpio3_addr_space,
1145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1146 };
1147
1148 /* l4_wkup -> gpio4 */
1149 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1150         {
1151                 .pa_start       = 0x4801e000,
1152                 .pa_end         = 0x4801e1ff,
1153                 .flags          = ADDR_TYPE_RT
1154         },
1155         { }
1156 };
1157
1158 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1159         .master         = &omap2420_l4_wkup_hwmod,
1160         .slave          = &omap2420_gpio4_hwmod,
1161         .clk            = "gpios_ick",
1162         .addr           = omap2420_gpio4_addr_space,
1163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1164 };
1165
1166 /* gpio dev_attr */
1167 static struct omap_gpio_dev_attr gpio_dev_attr = {
1168         .bank_width = 32,
1169         .dbck_flag = false,
1170 };
1171
1172 /* gpio1 */
1173 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1174         &omap2420_l4_wkup__gpio1,
1175 };
1176
1177 static struct omap_hwmod omap2420_gpio1_hwmod = {
1178         .name           = "gpio1",
1179         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1180         .mpu_irqs       = omap2_gpio1_irqs,
1181         .main_clk       = "gpios_fck",
1182         .prcm           = {
1183                 .omap2 = {
1184                         .prcm_reg_id = 1,
1185                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1186                         .module_offs = WKUP_MOD,
1187                         .idlest_reg_id = 1,
1188                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1189                 },
1190         },
1191         .slaves         = omap2420_gpio1_slaves,
1192         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1193         .class          = &omap2xxx_gpio_hwmod_class,
1194         .dev_attr       = &gpio_dev_attr,
1195 };
1196
1197 /* gpio2 */
1198 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1199         &omap2420_l4_wkup__gpio2,
1200 };
1201
1202 static struct omap_hwmod omap2420_gpio2_hwmod = {
1203         .name           = "gpio2",
1204         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1205         .mpu_irqs       = omap2_gpio2_irqs,
1206         .main_clk       = "gpios_fck",
1207         .prcm           = {
1208                 .omap2 = {
1209                         .prcm_reg_id = 1,
1210                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1211                         .module_offs = WKUP_MOD,
1212                         .idlest_reg_id = 1,
1213                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1214                 },
1215         },
1216         .slaves         = omap2420_gpio2_slaves,
1217         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1218         .class          = &omap2xxx_gpio_hwmod_class,
1219         .dev_attr       = &gpio_dev_attr,
1220 };
1221
1222 /* gpio3 */
1223 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1224         &omap2420_l4_wkup__gpio3,
1225 };
1226
1227 static struct omap_hwmod omap2420_gpio3_hwmod = {
1228         .name           = "gpio3",
1229         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1230         .mpu_irqs       = omap2_gpio3_irqs,
1231         .main_clk       = "gpios_fck",
1232         .prcm           = {
1233                 .omap2 = {
1234                         .prcm_reg_id = 1,
1235                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1236                         .module_offs = WKUP_MOD,
1237                         .idlest_reg_id = 1,
1238                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1239                 },
1240         },
1241         .slaves         = omap2420_gpio3_slaves,
1242         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1243         .class          = &omap2xxx_gpio_hwmod_class,
1244         .dev_attr       = &gpio_dev_attr,
1245 };
1246
1247 /* gpio4 */
1248 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1249         &omap2420_l4_wkup__gpio4,
1250 };
1251
1252 static struct omap_hwmod omap2420_gpio4_hwmod = {
1253         .name           = "gpio4",
1254         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1255         .mpu_irqs       = omap2_gpio4_irqs,
1256         .main_clk       = "gpios_fck",
1257         .prcm           = {
1258                 .omap2 = {
1259                         .prcm_reg_id = 1,
1260                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1261                         .module_offs = WKUP_MOD,
1262                         .idlest_reg_id = 1,
1263                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1264                 },
1265         },
1266         .slaves         = omap2420_gpio4_slaves,
1267         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1268         .class          = &omap2xxx_gpio_hwmod_class,
1269         .dev_attr       = &gpio_dev_attr,
1270 };
1271
1272 /* dma attributes */
1273 static struct omap_dma_dev_attr dma_dev_attr = {
1274         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1275                                                 IS_CSSA_32 | IS_CDSA_32,
1276         .lch_count = 32,
1277 };
1278
1279 /* dma_system -> L3 */
1280 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1281         .master         = &omap2420_dma_system_hwmod,
1282         .slave          = &omap2420_l3_main_hwmod,
1283         .clk            = "core_l3_ck",
1284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1285 };
1286
1287 /* dma_system master ports */
1288 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1289         &omap2420_dma_system__l3,
1290 };
1291
1292 /* l4_core -> dma_system */
1293 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1294         .master         = &omap2420_l4_core_hwmod,
1295         .slave          = &omap2420_dma_system_hwmod,
1296         .clk            = "sdma_ick",
1297         .addr           = omap2_dma_system_addrs,
1298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1299 };
1300
1301 /* dma_system slave ports */
1302 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1303         &omap2420_l4_core__dma_system,
1304 };
1305
1306 static struct omap_hwmod omap2420_dma_system_hwmod = {
1307         .name           = "dma",
1308         .class          = &omap2xxx_dma_hwmod_class,
1309         .mpu_irqs       = omap2_dma_system_irqs,
1310         .main_clk       = "core_l3_ck",
1311         .slaves         = omap2420_dma_system_slaves,
1312         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1313         .masters        = omap2420_dma_system_masters,
1314         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1315         .dev_attr       = &dma_dev_attr,
1316         .flags          = HWMOD_NO_IDLEST,
1317 };
1318
1319 /* mailbox */
1320 static struct omap_hwmod omap2420_mailbox_hwmod;
1321 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1322         { .name = "dsp", .irq = 26 },
1323         { .name = "iva", .irq = 34 },
1324         { .irq = -1 }
1325 };
1326
1327 /* l4_core -> mailbox */
1328 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1329         .master         = &omap2420_l4_core_hwmod,
1330         .slave          = &omap2420_mailbox_hwmod,
1331         .addr           = omap2_mailbox_addrs,
1332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1333 };
1334
1335 /* mailbox slave ports */
1336 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1337         &omap2420_l4_core__mailbox,
1338 };
1339
1340 static struct omap_hwmod omap2420_mailbox_hwmod = {
1341         .name           = "mailbox",
1342         .class          = &omap2xxx_mailbox_hwmod_class,
1343         .mpu_irqs       = omap2420_mailbox_irqs,
1344         .main_clk       = "mailboxes_ick",
1345         .prcm           = {
1346                 .omap2 = {
1347                         .prcm_reg_id = 1,
1348                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1349                         .module_offs = CORE_MOD,
1350                         .idlest_reg_id = 1,
1351                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1352                 },
1353         },
1354         .slaves         = omap2420_mailbox_slaves,
1355         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1356 };
1357
1358 /* mcspi1 */
1359 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1360         &omap2420_l4_core__mcspi1,
1361 };
1362
1363 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1364         .num_chipselect = 4,
1365 };
1366
1367 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1368         .name           = "mcspi1_hwmod",
1369         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1370         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1371         .main_clk       = "mcspi1_fck",
1372         .prcm           = {
1373                 .omap2 = {
1374                         .module_offs = CORE_MOD,
1375                         .prcm_reg_id = 1,
1376                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1377                         .idlest_reg_id = 1,
1378                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1379                 },
1380         },
1381         .slaves         = omap2420_mcspi1_slaves,
1382         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1383         .class          = &omap2xxx_mcspi_class,
1384         .dev_attr       = &omap_mcspi1_dev_attr,
1385 };
1386
1387 /* mcspi2 */
1388 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1389         &omap2420_l4_core__mcspi2,
1390 };
1391
1392 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1393         .num_chipselect = 2,
1394 };
1395
1396 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1397         .name           = "mcspi2_hwmod",
1398         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1399         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1400         .main_clk       = "mcspi2_fck",
1401         .prcm           = {
1402                 .omap2 = {
1403                         .module_offs = CORE_MOD,
1404                         .prcm_reg_id = 1,
1405                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1406                         .idlest_reg_id = 1,
1407                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1408                 },
1409         },
1410         .slaves         = omap2420_mcspi2_slaves,
1411         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
1412         .class          = &omap2xxx_mcspi_class,
1413         .dev_attr       = &omap_mcspi2_dev_attr,
1414 };
1415
1416 /*
1417  * 'mcbsp' class
1418  * multi channel buffered serial port controller
1419  */
1420
1421 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1422         .name = "mcbsp",
1423 };
1424
1425 /* mcbsp1 */
1426 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1427         { .name = "tx", .irq = 59 },
1428         { .name = "rx", .irq = 60 },
1429         { .irq = -1 }
1430 };
1431
1432 /* l4_core -> mcbsp1 */
1433 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1434         .master         = &omap2420_l4_core_hwmod,
1435         .slave          = &omap2420_mcbsp1_hwmod,
1436         .clk            = "mcbsp1_ick",
1437         .addr           = omap2_mcbsp1_addrs,
1438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1439 };
1440
1441 /* mcbsp1 slave ports */
1442 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1443         &omap2420_l4_core__mcbsp1,
1444 };
1445
1446 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1447         .name           = "mcbsp1",
1448         .class          = &omap2420_mcbsp_hwmod_class,
1449         .mpu_irqs       = omap2420_mcbsp1_irqs,
1450         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1451         .main_clk       = "mcbsp1_fck",
1452         .prcm           = {
1453                 .omap2 = {
1454                         .prcm_reg_id = 1,
1455                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1456                         .module_offs = CORE_MOD,
1457                         .idlest_reg_id = 1,
1458                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1459                 },
1460         },
1461         .slaves         = omap2420_mcbsp1_slaves,
1462         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1463 };
1464
1465 /* mcbsp2 */
1466 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1467         { .name = "tx", .irq = 62 },
1468         { .name = "rx", .irq = 63 },
1469         { .irq = -1 }
1470 };
1471
1472 /* l4_core -> mcbsp2 */
1473 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1474         .master         = &omap2420_l4_core_hwmod,
1475         .slave          = &omap2420_mcbsp2_hwmod,
1476         .clk            = "mcbsp2_ick",
1477         .addr           = omap2xxx_mcbsp2_addrs,
1478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1479 };
1480
1481 /* mcbsp2 slave ports */
1482 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1483         &omap2420_l4_core__mcbsp2,
1484 };
1485
1486 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1487         .name           = "mcbsp2",
1488         .class          = &omap2420_mcbsp_hwmod_class,
1489         .mpu_irqs       = omap2420_mcbsp2_irqs,
1490         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1491         .main_clk       = "mcbsp2_fck",
1492         .prcm           = {
1493                 .omap2 = {
1494                         .prcm_reg_id = 1,
1495                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1496                         .module_offs = CORE_MOD,
1497                         .idlest_reg_id = 1,
1498                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1499                 },
1500         },
1501         .slaves         = omap2420_mcbsp2_slaves,
1502         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1503 };
1504
1505 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1506         &omap2420_l3_main_hwmod,
1507         &omap2420_l4_core_hwmod,
1508         &omap2420_l4_wkup_hwmod,
1509         &omap2420_mpu_hwmod,
1510         &omap2420_iva_hwmod,
1511
1512         &omap2420_timer1_hwmod,
1513         &omap2420_timer2_hwmod,
1514         &omap2420_timer3_hwmod,
1515         &omap2420_timer4_hwmod,
1516         &omap2420_timer5_hwmod,
1517         &omap2420_timer6_hwmod,
1518         &omap2420_timer7_hwmod,
1519         &omap2420_timer8_hwmod,
1520         &omap2420_timer9_hwmod,
1521         &omap2420_timer10_hwmod,
1522         &omap2420_timer11_hwmod,
1523         &omap2420_timer12_hwmod,
1524
1525         &omap2420_wd_timer2_hwmod,
1526         &omap2420_uart1_hwmod,
1527         &omap2420_uart2_hwmod,
1528         &omap2420_uart3_hwmod,
1529         /* dss class */
1530         &omap2420_dss_core_hwmod,
1531         &omap2420_dss_dispc_hwmod,
1532         &omap2420_dss_rfbi_hwmod,
1533         &omap2420_dss_venc_hwmod,
1534         /* i2c class */
1535         &omap2420_i2c1_hwmod,
1536         &omap2420_i2c2_hwmod,
1537
1538         /* gpio class */
1539         &omap2420_gpio1_hwmod,
1540         &omap2420_gpio2_hwmod,
1541         &omap2420_gpio3_hwmod,
1542         &omap2420_gpio4_hwmod,
1543
1544         /* dma_system class*/
1545         &omap2420_dma_system_hwmod,
1546
1547         /* mailbox class */
1548         &omap2420_mailbox_hwmod,
1549
1550         /* mcbsp class */
1551         &omap2420_mcbsp1_hwmod,
1552         &omap2420_mcbsp2_hwmod,
1553
1554         /* mcspi class */
1555         &omap2420_mcspi1_hwmod,
1556         &omap2420_mcspi2_hwmod,
1557         NULL,
1558 };
1559
1560 int __init omap2420_hwmod_init(void)
1561 {
1562         return omap_hwmod_register(omap2420_hwmods);
1563 }