arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/cputype.h>
  23
  24 #include <plat/common.h>
  25 #include <plat/cpu.h>
  26
  27 #include <mach/id.h>
  28
  29 #include "control.h"
  30
  31 static unsigned int omap_revision;
  32 static const char *cpu_rev;
  33 u32 omap_features;
  34
  35 unsigned int omap_rev(void)
  36 {
  37         return omap_revision;
  38 }
  39 EXPORT_SYMBOL(omap_rev);
  40
  41 int omap_type(void)
  42 {
  43         u32 val = 0;
  44
  45         if (cpu_is_omap24xx()) {
  46                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  47         } else if (cpu_is_omap34xx()) {
  48                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  49         } else if (cpu_is_omap44xx()) {
  50                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  51         } else {
  52                 pr_err("Cannot detect omap type!\n");
  53                 goto out;
  54         }
  55
  56         val &= OMAP2_DEVICETYPE_MASK;
  57         val >>= 8;
  58
  59 out:
  60         return val;
  61 }
  62 EXPORT_SYMBOL(omap_type);
  63
  64
  65 /*----------------------------------------------------------------------------*/
  66
  67 #define OMAP_TAP_IDCODE         0x0204
  68 #define OMAP_TAP_DIE_ID_0       0x0218
  69 #define OMAP_TAP_DIE_ID_1       0x021C
  70 #define OMAP_TAP_DIE_ID_2       0x0220
  71 #define OMAP_TAP_DIE_ID_3       0x0224
  72
  73 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  74 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  75 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  76 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  77
  78 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  79
  80 struct omap_id {
  81         u16     hawkeye;        /* Silicon type (Hawkeye id) */
  82         u8      dev;            /* Device type from production_id reg */
  83         u32     type;           /* Combined type id copied to omap_revision */
  84 };
  85
  86 /* Register values to detect the OMAP version */
  87 static struct omap_id omap_ids[] __initdata = {
  88         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  89         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  90         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  91         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  92         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
  93         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
  94 };
  95
  96 static void __iomem *tap_base;
  97 static u16 tap_prod_id;
  98
  99 void omap_get_die_id(struct omap_die_id *odi)
 100 {
 101         if (cpu_is_omap44xx()) {
 102                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 103                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 104                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 105                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 106
 107                 return;
 108         }
 109         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 110         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 111         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 112         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 113 }
 114
 115 void __init omap2xxx_check_revision(void)
 116 {
 117         int i, j;
 118         u32 idcode, prod_id;
 119         u16 hawkeye;
 120         u8  dev_type, rev;
 121         struct omap_die_id odi;
 122
 123         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 124         prod_id = read_tap_reg(tap_prod_id);
 125         hawkeye = (idcode >> 12) & 0xffff;
 126         rev = (idcode >> 28) & 0x0f;
 127         dev_type = (prod_id >> 16) & 0x0f;
 128         omap_get_die_id(&odi);
 129
 130         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 131                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 132         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 133         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 134                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 135         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 136         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 137         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 138                  prod_id, dev_type);
 139
 140         /* Check hawkeye ids */
 141         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 142                 if (hawkeye == omap_ids[i].hawkeye)
 143                         break;
 144         }
 145
 146         if (i == ARRAY_SIZE(omap_ids)) {
 147                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 148                 return;
 149         }
 150
 151         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 152                 if (dev_type == omap_ids[j].dev)
 153                         break;
 154         }
 155
 156         if (j == ARRAY_SIZE(omap_ids)) {
 157                 printk(KERN_ERR "Unknown OMAP device type. "
 158                                 "Handling it as OMAP%04x\n",
 159                                 omap_ids[i].type >> 16);
 160                 j = i;
 161         }
 162
 163         pr_info("OMAP%04x", omap_rev() >> 16);
 164         if ((omap_rev() >> 8) & 0x0f)
 165                 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
 166         pr_info("\n");
 167 }
 168
 169 #define OMAP3_SHOW_FEATURE(feat)                \
 170         if (omap3_has_ ##feat())                \
 171                 printk(#feat" ");
 172
 173 static void __init omap3_cpuinfo(void)
 174 {
 175         const char *cpu_name;
 176
 177         /*
 178          * OMAP3430 and OMAP3530 are assumed to be same.
 179          *
 180          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 181          * on available features. Upon detection, update the CPU id
 182          * and CPU class bits.
 183          */
 184         if (cpu_is_omap3630()) {
 185                 cpu_name = "OMAP3630";
 186         } else if (cpu_is_omap3517()) {
 187                 /* AM35xx devices */
 188                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 189         } else if (cpu_is_ti816x()) {
 190                 cpu_name = "TI816X";
 191         } else if (omap3_has_iva() && omap3_has_sgx()) {
 192                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 193                 cpu_name = "OMAP3430/3530";
 194         } else if (omap3_has_iva()) {
 195                 cpu_name = "OMAP3525";
 196         } else if (omap3_has_sgx()) {
 197                 cpu_name = "OMAP3515";
 198         } else {
 199                 cpu_name = "OMAP3503";
 200         }
 201
 202         /* Print verbose information */
 203         pr_info("%s ES%s (", cpu_name, cpu_rev);
 204
 205         OMAP3_SHOW_FEATURE(l2cache);
 206         OMAP3_SHOW_FEATURE(iva);
 207         OMAP3_SHOW_FEATURE(sgx);
 208         OMAP3_SHOW_FEATURE(neon);
 209         OMAP3_SHOW_FEATURE(isp);
 210         OMAP3_SHOW_FEATURE(192mhz_clk);
 211
 212         printk(")\n");
 213 }
 214
 215 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 216         if (((status & OMAP3_ ##feat## _MASK)                           \
 217                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 218                 omap_features |= OMAP3_HAS_ ##feat;                     \
 219         }
 220
 221 void __init omap3xxx_check_features(void)
 222 {
 223         u32 status;
 224
 225         omap_features = 0;
 226
 227         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 228
 229         OMAP3_CHECK_FEATURE(status, L2CACHE);
 230         OMAP3_CHECK_FEATURE(status, IVA);
 231         OMAP3_CHECK_FEATURE(status, SGX);
 232         OMAP3_CHECK_FEATURE(status, NEON);
 233         OMAP3_CHECK_FEATURE(status, ISP);
 234         if (cpu_is_omap3630())
 235                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 236         if (cpu_is_omap3430() || cpu_is_omap3630())
 237                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 238         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 239             omap_rev() == OMAP3430_REV_ES3_1_2)
 240                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 241
 242         omap_features |= OMAP3_HAS_SDRC;
 243
 244         /*
 245          * TODO: Get additional info (where applicable)
 246          *       e.g. Size of L2 cache.
 247          */
 248
 249         omap3_cpuinfo();
 250 }
 251
 252 void __init omap4xxx_check_features(void)
 253 {
 254         u32 si_type;
 255
 256         if (cpu_is_omap443x())
 257                 omap_features |= OMAP4_HAS_MPU_1GHZ;
 258
 259
 260         if (cpu_is_omap446x()) {
 261                 si_type =
 262                         read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
 263                 switch ((si_type & (3 << 16)) >> 16) {
 264                 case 2:
 265                         /* High performance device */
 266                         omap_features |= OMAP4_HAS_MPU_1_5GHZ;
 267                         break;
 268                 case 1:
 269                 default:
 270                         /* Standard device */
 271                         omap_features |= OMAP4_HAS_MPU_1_2GHZ;
 272                         break;
 273                 }
 274         }
 275 }
 276
 277 void __init ti81xx_check_features(void)
 278 {
 279         omap_features = OMAP3_HAS_NEON;
 280         omap3_cpuinfo();
 281 }
 282
 283 void __init omap3xxx_check_revision(void)
 284 {
 285         u32 cpuid, idcode;
 286         u16 hawkeye;
 287         u8 rev;
 288
 289         /*
 290          * We cannot access revision registers on ES1.0.
 291          * If the processor type is Cortex-A8 and the revision is 0x0
 292          * it means its Cortex r0p0 which is 3430 ES1.0.
 293          */
 294         cpuid = read_cpuid(CPUID_ID);
 295         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 296                 omap_revision = OMAP3430_REV_ES1_0;
 297                 cpu_rev = "1.0";
 298                 return;
 299         }
 300
 301         /*
 302          * Detection for 34xx ES2.0 and above can be done with just
 303          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 304          * Note that rev does not map directly to our defined processor
 305          * revision numbers as ES1.0 uses value 0.
 306          */
 307         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 308         hawkeye = (idcode >> 12) & 0xffff;
 309         rev = (idcode >> 28) & 0xff;
 310
 311         switch (hawkeye) {
 312         case 0xb7ae:
 313                 /* Handle 34xx/35xx devices */
 314                 switch (rev) {
 315                 case 0: /* Take care of early samples */
 316                 case 1:
 317                         omap_revision = OMAP3430_REV_ES2_0;
 318                         cpu_rev = "2.0";
 319                         break;
 320                 case 2:
 321                         omap_revision = OMAP3430_REV_ES2_1;
 322                         cpu_rev = "2.1";
 323                         break;
 324                 case 3:
 325                         omap_revision = OMAP3430_REV_ES3_0;
 326                         cpu_rev = "3.0";
 327                         break;
 328                 case 4:
 329                         omap_revision = OMAP3430_REV_ES3_1;
 330                         cpu_rev = "3.1";
 331                         break;
 332                 case 7:
 333                 /* FALLTHROUGH */
 334                 default:
 335                         /* Use the latest known revision as default */
 336                         omap_revision = OMAP3430_REV_ES3_1_2;
 337                         cpu_rev = "3.1.2";
 338                 }
 339                 break;
 340         case 0xb868:
 341                 /*
 342                  * Handle OMAP/AM 3505/3517 devices
 343                  *
 344                  * Set the device to be OMAP3517 here. Actual device
 345                  * is identified later based on the features.
 346                  */
 347                 switch (rev) {
 348                 case 0:
 349                         omap_revision = OMAP3517_REV_ES1_0;
 350                         cpu_rev = "1.0";
 351                         break;
 352                 case 1:
 353                 /* FALLTHROUGH */
 354                 default:
 355                         omap_revision = OMAP3517_REV_ES1_1;
 356                         cpu_rev = "1.1";
 357                 }
 358                 break;
 359         case 0xb891:
 360                 /* Handle 36xx devices */
 361
 362                 switch(rev) {
 363                 case 0: /* Take care of early samples */
 364                         omap_revision = OMAP3630_REV_ES1_0;
 365                         cpu_rev = "1.0";
 366                         break;
 367                 case 1:
 368                         omap_revision = OMAP3630_REV_ES1_1;
 369                         cpu_rev = "1.1";
 370                         break;
 371                 case 2:
 372                 /* FALLTHROUGH */
 373                 default:
 374                         omap_revision = OMAP3630_REV_ES1_2;
 375                         cpu_rev = "1.2";
 376                 }
 377                 break;
 378         case 0xb81e:
 379                 switch (rev) {
 380                 case 0:
 381                         omap_revision = TI8168_REV_ES1_0;
 382                         cpu_rev = "1.0";
 383                         break;
 384                 case 1:
 385                 /* FALLTHROUGH */
 386                 default:
 387                         omap_revision = TI8168_REV_ES1_1;
 388                         cpu_rev = "1.1";
 389                         break;
 390                 }
 391                 break;
 392         default:
 393                 /* Unknown default to latest silicon rev as default */
 394                 omap_revision = OMAP3630_REV_ES1_2;
 395                 cpu_rev = "1.2";
 396                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 397         }
 398 }
 399
 400 void __init omap4xxx_check_revision(void)
 401 {
 402         u32 idcode;
 403         u16 hawkeye;
 404         u8 rev;
 405
 406         /*
 407          * The IC rev detection is done with hawkeye and rev.
 408          * Note that rev does not map directly to defined processor
 409          * revision numbers as ES1.0 uses value 0.
 410          */
 411         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 412         hawkeye = (idcode >> 12) & 0xffff;
 413         rev = (idcode >> 28) & 0xf;
 414
 415         /*
 416          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 417          * Use ARM register to detect the correct ES version
 418          */
 419         if (!rev && (hawkeye != 0xb94e)) {
 420                 idcode = read_cpuid(CPUID_ID);
 421                 rev = (idcode & 0xf) - 1;
 422         }
 423
 424         switch (hawkeye) {
 425         case 0xb852:
 426                 switch (rev) {
 427                 case 0:
 428                         omap_revision = OMAP4430_REV_ES1_0;
 429                         break;
 430                 case 1:
 431                 default:
 432                         omap_revision = OMAP4430_REV_ES2_0;
 433                 }
 434                 break;
 435         case 0xb95c:
 436                 switch (rev) {
 437                 case 3:
 438                         omap_revision = OMAP4430_REV_ES2_1;
 439                         break;
 440                 case 4:
 441                 default:
 442                         omap_revision = OMAP4430_REV_ES2_2;
 443                 }
 444                 break;
 445         case 0xb94e:
 446                 switch (rev) {
 447                 case 0:
 448                 default:
 449                         omap_revision = OMAP4460_REV_ES1_0;
 450                         break;
 451                 }
 452                 break;
 453         default:
 454                 /* Unknown default to latest silicon rev as default */
 455                 omap_revision = OMAP4430_REV_ES2_2;
 456         }
 457
 458         pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
 459                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 460 }
 461
 462 /*
 463  * Set up things for map_io and processor detection later on. Gets called
 464  * pretty much first thing from board init. For multi-omap, this gets
 465  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 466  * detect the exact revision later on in omap2_detect_revision() once map_io
 467  * is done.
 468  */
 469 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
 470 {
 471         omap_revision = omap2_globals->class;
 472         tap_base = omap2_globals->tap;
 473
 474         if (cpu_is_omap34xx())
 475                 tap_prod_id = 0x0210;
 476         else
 477                 tap_prod_id = 0x0208;
 478 }