arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <mach/hardware.h>
  17 #include <plat/mmc.h>
  18 #include <plat/omap-pm.h>
  19 #include <plat/mux.h>
  20 #include <plat/omap_device.h>
  21
  22 #include "mux.h"
  23 #include "hsmmc.h"
  24 #include "control.h"
  25
  26 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  27
  28 static u16 control_pbias_offset;
  29 static u16 control_devconf1_offset;
  30 static u16 control_mmc1;
  31
  32 #define HSMMC_NAME_LEN  9
  33
  34 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  35
  36 static int hsmmc_get_context_loss(struct device *dev)
  37 {
  38         return omap_pm_get_dev_context_loss_count(dev);
  39 }
  40
  41 #else
  42 #define hsmmc_get_context_loss NULL
  43 #endif
  44
  45 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  46                                   int power_on, int vdd)
  47 {
  48         u32 reg, prog_io;
  49         struct omap_mmc_platform_data *mmc = dev->platform_data;
  50
  51         if (mmc->slots[0].remux)
  52                 mmc->slots[0].remux(dev, slot, power_on);
  53
  54         /*
  55          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  56          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  57          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  58          *
  59          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  60          * is most naturally TWL VSIM; those pins also use PBIAS.
  61          *
  62          * FIXME handle VMMC1A as needed ...
  63          */
  64         if (power_on) {
  65                 if (cpu_is_omap2430()) {
  66                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  67                         if ((1 << vdd) >= MMC_VDD_30_31)
  68                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  69                         else
  70                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  71                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  72                 }
  73
  74                 if (mmc->slots[0].internal_clock) {
  75                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  76                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  77                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  78                 }
  79
  80                 reg = omap_ctrl_readl(control_pbias_offset);
  81                 if (cpu_is_omap3630()) {
  82                         /* Set MMC I/O to 52Mhz */
  83                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  84                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  85                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  86                 } else {
  87                         reg |= OMAP2_PBIASSPEEDCTRL0;
  88                 }
  89                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  90                 omap_ctrl_writel(reg, control_pbias_offset);
  91         } else {
  92                 reg = omap_ctrl_readl(control_pbias_offset);
  93                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  94                 omap_ctrl_writel(reg, control_pbias_offset);
  95         }
  96 }
  97
  98 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
  99                                  int power_on, int vdd)
 100 {
 101         u32 reg;
 102
 103         /* 100ms delay required for PBIAS configuration */
 104         msleep(100);
 105
 106         if (power_on) {
 107                 reg = omap_ctrl_readl(control_pbias_offset);
 108                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 109                 if ((1 << vdd) <= MMC_VDD_165_195)
 110                         reg &= ~OMAP2_PBIASLITEVMODE0;
 111                 else
 112                         reg |= OMAP2_PBIASLITEVMODE0;
 113                 omap_ctrl_writel(reg, control_pbias_offset);
 114         } else {
 115                 reg = omap_ctrl_readl(control_pbias_offset);
 116                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 117                         OMAP2_PBIASLITEVMODE0);
 118                 omap_ctrl_writel(reg, control_pbias_offset);
 119         }
 120 }
 121
 122 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 123                                   int power_on, int vdd)
 124 {
 125         u32 reg;
 126
 127         /*
 128          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 129          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 130          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 131          *
 132          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
 133          * is most naturally TWL VSIM; those pins also use PBIAS.
 134          *
 135          * FIXME handle VMMC1A as needed ...
 136          */
 137         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 138         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 139                 OMAP4_MMC1_PWRDNZ_MASK |
 140                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 141         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 142 }
 143
 144 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 145                                  int power_on, int vdd)
 146 {
 147         u32 reg;
 148         unsigned long timeout;
 149
 150         if (power_on) {
 151                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 152                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 153                 if ((1 << vdd) <= MMC_VDD_165_195)
 154                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 155                 else
 156                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 157                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 158                         OMAP4_MMC1_PWRDNZ_MASK |
 159                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 160                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 161
 162                 timeout = jiffies + msecs_to_jiffies(5);
 163                 do {
 164                         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 165                         if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
 166                                 break;
 167                         usleep_range(100, 200);
 168                 } while (!time_after(jiffies, timeout));
 169
 170                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 171                         pr_err("Pbias Voltage is not same as LDO\n");
 172                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 173                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
 174                                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 175                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 176                 }
 177         } else {
 178                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 179                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 180                         OMAP4_MMC1_PWRDNZ_MASK |
 181                         OMAP4_MMC1_PBIASLITE_VMODE_MASK |
 182                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 183                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 184         }
 185 }
 186
 187 static void hsmmc23_before_set_reg(struct device *dev, int slot,
 188                                    int power_on, int vdd)
 189 {
 190         struct omap_mmc_platform_data *mmc = dev->platform_data;
 191
 192         if (mmc->slots[0].remux)
 193                 mmc->slots[0].remux(dev, slot, power_on);
 194
 195         if (power_on) {
 196                 /* Only MMC2 supports a CLKIN */
 197                 if (mmc->slots[0].internal_clock) {
 198                         u32 reg;
 199
 200                         reg = omap_ctrl_readl(control_devconf1_offset);
 201                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 202                         omap_ctrl_writel(reg, control_devconf1_offset);
 203                 }
 204         }
 205 }
 206
 207 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 208                                                         int vdd)
 209 {
 210         return 0;
 211 }
 212
 213 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 214                         int controller_nr)
 215 {
 216         if ((mmc_controller->slots[0].switch_pin > 0) && \
 217                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 218                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 219                                         OMAP_PIN_INPUT_PULLUP);
 220         if ((mmc_controller->slots[0].gpio_wp > 0) && \
 221                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 222                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 223                                         OMAP_PIN_INPUT_PULLUP);
 224         if (cpu_is_omap34xx()) {
 225                 if (controller_nr == 0) {
 226                         omap_mux_init_signal("sdmmc1_clk",
 227                                 OMAP_PIN_INPUT_PULLUP);
 228                         omap_mux_init_signal("sdmmc1_cmd",
 229                                 OMAP_PIN_INPUT_PULLUP);
 230                         omap_mux_init_signal("sdmmc1_dat0",
 231                                 OMAP_PIN_INPUT_PULLUP);
 232                         if (mmc_controller->slots[0].caps &
 233                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 234                                 omap_mux_init_signal("sdmmc1_dat1",
 235                                         OMAP_PIN_INPUT_PULLUP);
 236                                 omap_mux_init_signal("sdmmc1_dat2",
 237                                         OMAP_PIN_INPUT_PULLUP);
 238                                 omap_mux_init_signal("sdmmc1_dat3",
 239                                         OMAP_PIN_INPUT_PULLUP);
 240                         }
 241                         if (mmc_controller->slots[0].caps &
 242                                                 MMC_CAP_8_BIT_DATA) {
 243                                 omap_mux_init_signal("sdmmc1_dat4",
 244                                         OMAP_PIN_INPUT_PULLUP);
 245                                 omap_mux_init_signal("sdmmc1_dat5",
 246                                         OMAP_PIN_INPUT_PULLUP);
 247                                 omap_mux_init_signal("sdmmc1_dat6",
 248                                         OMAP_PIN_INPUT_PULLUP);
 249                                 omap_mux_init_signal("sdmmc1_dat7",
 250                                         OMAP_PIN_INPUT_PULLUP);
 251                         }
 252                 }
 253                 if (controller_nr == 1) {
 254                         /* MMC2 */
 255                         omap_mux_init_signal("sdmmc2_clk",
 256                                 OMAP_PIN_INPUT_PULLUP);
 257                         omap_mux_init_signal("sdmmc2_cmd",
 258                                 OMAP_PIN_INPUT_PULLUP);
 259                         omap_mux_init_signal("sdmmc2_dat0",
 260                                 OMAP_PIN_INPUT_PULLUP);
 261
 262                         /*
 263                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 264                          * need to be muxed in the board-*.c files
 265                          */
 266                         if (mmc_controller->slots[0].caps &
 267                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 268                                 omap_mux_init_signal("sdmmc2_dat1",
 269                                         OMAP_PIN_INPUT_PULLUP);
 270                                 omap_mux_init_signal("sdmmc2_dat2",
 271                                         OMAP_PIN_INPUT_PULLUP);
 272                                 omap_mux_init_signal("sdmmc2_dat3",
 273                                         OMAP_PIN_INPUT_PULLUP);
 274                         }
 275                         if (mmc_controller->slots[0].caps &
 276                                                         MMC_CAP_8_BIT_DATA) {
 277                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 278                                         OMAP_PIN_INPUT_PULLUP);
 279                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 280                                         OMAP_PIN_INPUT_PULLUP);
 281                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 282                                         OMAP_PIN_INPUT_PULLUP);
 283                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 284                                         OMAP_PIN_INPUT_PULLUP);
 285                         }
 286                 }
 287
 288                 /*
 289                  * For MMC3 the pins need to be muxed in the board-*.c files
 290                  */
 291         }
 292 }
 293
 294 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 295                                         struct omap_mmc_platform_data *mmc)
 296 {
 297         char *hc_name;
 298
 299         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 300         if (!hc_name) {
 301                 pr_err("Cannot allocate memory for controller slot name\n");
 302                 kfree(hc_name);
 303                 return -ENOMEM;
 304         }
 305
 306         if (c->name)
 307                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 308         else
 309                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 310                                                                 c->mmc, 1);
 311         mmc->slots[0].name = hc_name;
 312         mmc->nr_slots = 1;
 313         mmc->slots[0].caps = c->caps;
 314         mmc->slots[0].internal_clock = !c->ext_clock;
 315         mmc->dma_mask = 0xffffffff;
 316         if (cpu_is_omap44xx())
 317                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 318         else
 319                 mmc->reg_offset = 0;
 320
 321         mmc->get_context_loss_count = hsmmc_get_context_loss;
 322
 323         mmc->slots[0].switch_pin = c->gpio_cd;
 324         mmc->slots[0].gpio_wp = c->gpio_wp;
 325
 326         mmc->slots[0].remux = c->remux;
 327         mmc->slots[0].init_card = c->init_card;
 328
 329         if (c->cover_only)
 330                 mmc->slots[0].cover = 1;
 331
 332         if (c->nonremovable)
 333                 mmc->slots[0].nonremovable = 1;
 334
 335         if (c->power_saving)
 336                 mmc->slots[0].power_saving = 1;
 337
 338         if (c->no_off)
 339                 mmc->slots[0].no_off = 1;
 340
 341         if (c->no_off_init)
 342                 mmc->slots[0].no_regulator_off_init = c->no_off_init;
 343
 344         if (c->vcc_aux_disable_is_sleep)
 345                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 346
 347         /*
 348          * NOTE:  MMC slots should have a Vcc regulator set up.
 349          * This may be from a TWL4030-family chip, another
 350          * controllable regulator, or a fixed supply.
 351          *
 352          * temporary HACK: ocr_mask instead of fixed supply
 353          */
 354         mmc->slots[0].ocr_mask = c->ocr_mask;
 355
 356         if (cpu_is_omap3517() || cpu_is_omap3505())
 357                 mmc->slots[0].set_power = nop_mmc_set_power;
 358         else
 359                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 360
 361         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 362                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 363
 364         switch (c->mmc) {
 365         case 1:
 366                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 367                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 368                         if (cpu_is_omap44xx()) {
 369                                 mmc->slots[0].before_set_reg =
 370                                                 omap4_hsmmc1_before_set_reg;
 371                                 mmc->slots[0].after_set_reg =
 372                                                 omap4_hsmmc1_after_set_reg;
 373                         } else {
 374                                 mmc->slots[0].before_set_reg =
 375                                                 omap_hsmmc1_before_set_reg;
 376                                 mmc->slots[0].after_set_reg =
 377                                                 omap_hsmmc1_after_set_reg;
 378                         }
 379                 }
 380
 381                 /* OMAP3630 HSMMC1 supports only 4-bit */
 382                 if (cpu_is_omap3630() &&
 383                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 384                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 385                         c->caps |= MMC_CAP_4_BIT_DATA;
 386                         mmc->slots[0].caps = c->caps;
 387                 }
 388                 break;
 389         case 2:
 390                 if (c->ext_clock)
 391                         c->transceiver = 1;
 392                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 393                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 394                         c->caps |= MMC_CAP_4_BIT_DATA;
 395                 }
 396                 /* FALLTHROUGH */
 397         case 3:
 398                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 399                         /* off-chip level shifting, or none */
 400                         mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
 401                         mmc->slots[0].after_set_reg = NULL;
 402                 }
 403                 break;
 404         case 4:
 405         case 5:
 406                 mmc->slots[0].before_set_reg = NULL;
 407                 mmc->slots[0].after_set_reg = NULL;
 408                 break;
 409         default:
 410                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 411                 kfree(hc_name);
 412                 return -ENODEV;
 413         }
 414         return 0;
 415 }
 416
 417 static struct omap_device_pm_latency omap_hsmmc_latency[] = {
 418         [0] = {
 419                 .deactivate_func = omap_device_idle_hwmods,
 420                 .activate_func   = omap_device_enable_hwmods,
 421                 .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
 422         },
 423         /*
 424          * XXX There should also be an entry here to power off/on the
 425          * MMC regulators/PBIAS cells, etc.
 426          */
 427 };
 428
 429 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 430
 431 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 432 {
 433         struct omap_hwmod *oh;
 434         struct omap_device *od;
 435         struct omap_device_pm_latency *ohl;
 436         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 437         struct omap_mmc_platform_data *mmc_data;
 438         struct omap_mmc_dev_attr *mmc_dev_attr;
 439         char *name;
 440         int l;
 441         int ohl_cnt = 0;
 442
 443         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 444         if (!mmc_data) {
 445                 pr_err("Cannot allocate memory for mmc device!\n");
 446                 goto done;
 447         }
 448
 449         if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
 450                 pr_err("%s fails!\n", __func__);
 451                 goto done;
 452         }
 453         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 454
 455         name = "omap_hsmmc";
 456         ohl = omap_hsmmc_latency;
 457         ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
 458
 459         l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 460                      "mmc%d", ctrl_nr);
 461         WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 462              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 463         oh = omap_hwmod_lookup(oh_name);
 464         if (!oh) {
 465                 pr_err("Could not look up %s\n", oh_name);
 466                 kfree(mmc_data->slots[0].name);
 467                 goto done;
 468         }
 469
 470         if (oh->dev_attr != NULL) {
 471                 mmc_dev_attr = oh->dev_attr;
 472                 mmc_data->controller_flags = mmc_dev_attr->flags;
 473         }
 474
 475         od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
 476                 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
 477         if (IS_ERR(od)) {
 478                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
 479                 kfree(mmc_data->slots[0].name);
 480                 goto done;
 481         }
 482         /*
 483          * return device handle to board setup code
 484          * required to populate for regulator framework structure
 485          */
 486         hsmmcinfo->dev = &od->pdev.dev;
 487
 488 done:
 489         kfree(mmc_data);
 490 }
 491
 492 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 493 {
 494         u32 reg;
 495
 496         if (!cpu_is_omap44xx()) {
 497                 if (cpu_is_omap2430()) {
 498                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 499                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 500                 } else {
 501                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 502                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 503                 }
 504         } else {
 505                 control_pbias_offset =
 506                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 507                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 508                 reg = omap4_ctrl_pad_readl(control_mmc1);
 509                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 510                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 511                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 512                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 513                 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
 514                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 515                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 516                 omap4_ctrl_pad_writel(reg, control_mmc1);
 517         }
 518
 519         for (; controllers->mmc; controllers++)
 520                 omap_init_hsmmc(controllers, controllers->mmc);
 521
 522 }
 523
 524 #endif