Merge branch 'hwmod_dss_fixes_3.2rc' of git://git.pwsan.com/linux-2.6 into fixes-dss
[pandora-kernel.git] / arch / arm / mach-omap2 / display.c
1 /*
2  * OMAP2plus display device setup / initialization.
3  *
4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5  *      Senthilvadivu Guruswamy
6  *      Sumit Semwal
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
17
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25
26 #include <video/omapdss.h>
27 #include <plat/omap_hwmod.h>
28 #include <plat/omap_device.h>
29 #include <plat/omap-pm.h>
30 #include <plat/common.h>
31
32 #include "control.h"
33 #include "display.h"
34
35 #define DISPC_CONTROL           0x0040
36 #define DISPC_CONTROL2          0x0238
37 #define DISPC_IRQSTATUS         0x0018
38
39 #define DSS_SYSCONFIG           0x10
40 #define DSS_SYSSTATUS           0x14
41 #define DSS_CONTROL             0x40
42 #define DSS_SDI_CONTROL         0x44
43 #define DSS_PLL_CONTROL         0x48
44
45 #define LCD_EN_MASK             (0x1 << 0)
46 #define DIGIT_EN_MASK           (0x1 << 1)
47
48 #define FRAMEDONE_IRQ_SHIFT     0
49 #define EVSYNC_EVEN_IRQ_SHIFT   2
50 #define EVSYNC_ODD_IRQ_SHIFT    3
51 #define FRAMEDONE2_IRQ_SHIFT    22
52 #define FRAMEDONETV_IRQ_SHIFT   24
53
54 /*
55  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
56  *     reset before deciding that something has gone wrong
57  */
58 #define FRAMEDONE_IRQ_TIMEOUT           100
59
60 static struct platform_device omap_display_device = {
61         .name          = "omapdss",
62         .id            = -1,
63         .dev            = {
64                 .platform_data = NULL,
65         },
66 };
67
68 struct omap_dss_hwmod_data {
69         const char *oh_name;
70         const char *dev_name;
71         const int id;
72 };
73
74 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
75         { "dss_core", "omapdss_dss", -1 },
76         { "dss_dispc", "omapdss_dispc", -1 },
77         { "dss_rfbi", "omapdss_rfbi", -1 },
78         { "dss_venc", "omapdss_venc", -1 },
79 };
80
81 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
82         { "dss_core", "omapdss_dss", -1 },
83         { "dss_dispc", "omapdss_dispc", -1 },
84         { "dss_rfbi", "omapdss_rfbi", -1 },
85         { "dss_venc", "omapdss_venc", -1 },
86         { "dss_dsi1", "omapdss_dsi", 0 },
87 };
88
89 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
90         { "dss_core", "omapdss_dss", -1 },
91         { "dss_dispc", "omapdss_dispc", -1 },
92         { "dss_rfbi", "omapdss_rfbi", -1 },
93         { "dss_venc", "omapdss_venc", -1 },
94         { "dss_dsi1", "omapdss_dsi", 0 },
95         { "dss_dsi2", "omapdss_dsi", 1 },
96         { "dss_hdmi", "omapdss_hdmi", -1 },
97 };
98
99 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
100 {
101         u32 enable_mask, enable_shift;
102         u32 pipd_mask, pipd_shift;
103         u32 reg;
104
105         if (dsi_id == 0) {
106                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
107                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
108                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
109                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
110         } else if (dsi_id == 1) {
111                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
112                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
113                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
114                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
115         } else {
116                 return -ENODEV;
117         }
118
119         reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
120
121         reg &= ~enable_mask;
122         reg &= ~pipd_mask;
123
124         reg |= (lanes << enable_shift) & enable_mask;
125         reg |= (lanes << pipd_shift) & pipd_mask;
126
127         omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
128
129         return 0;
130 }
131
132 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
133 {
134         if (cpu_is_omap44xx())
135                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
136
137         return 0;
138 }
139
140 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
141 {
142         if (cpu_is_omap44xx())
143                 omap4_dsi_mux_pads(dsi_id, 0);
144 }
145
146 int __init omap_display_init(struct omap_dss_board_info *board_data)
147 {
148         int r = 0;
149         struct omap_hwmod *oh;
150         struct platform_device *pdev;
151         int i, oh_count;
152         struct omap_display_platform_data pdata;
153         const struct omap_dss_hwmod_data *curr_dss_hwmod;
154
155         memset(&pdata, 0, sizeof(pdata));
156
157         if (cpu_is_omap24xx()) {
158                 curr_dss_hwmod = omap2_dss_hwmod_data;
159                 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
160         } else if (cpu_is_omap34xx()) {
161                 curr_dss_hwmod = omap3_dss_hwmod_data;
162                 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
163         } else {
164                 curr_dss_hwmod = omap4_dss_hwmod_data;
165                 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
166         }
167
168         if (board_data->dsi_enable_pads == NULL)
169                 board_data->dsi_enable_pads = omap_dsi_enable_pads;
170         if (board_data->dsi_disable_pads == NULL)
171                 board_data->dsi_disable_pads = omap_dsi_disable_pads;
172
173         pdata.board_data = board_data;
174         pdata.board_data->get_context_loss_count =
175                 omap_pm_get_dev_context_loss_count;
176
177         for (i = 0; i < oh_count; i++) {
178                 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
179                 if (!oh) {
180                         pr_err("Could not look up %s\n",
181                                 curr_dss_hwmod[i].oh_name);
182                         return -ENODEV;
183                 }
184
185                 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
186                                 curr_dss_hwmod[i].id, oh, &pdata,
187                                 sizeof(struct omap_display_platform_data),
188                                 NULL, 0, 0);
189
190                 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
191                                 curr_dss_hwmod[i].oh_name))
192                         return -ENODEV;
193         }
194         omap_display_device.dev.platform_data = board_data;
195
196         r = platform_device_register(&omap_display_device);
197         if (r < 0)
198                 printk(KERN_ERR "Unable to register OMAP-Display device\n");
199
200         return r;
201 }
202
203 static void dispc_disable_outputs(void)
204 {
205         u32 v, irq_mask = 0;
206         bool lcd_en, digit_en, lcd2_en = false;
207         int i;
208         struct omap_dss_dispc_dev_attr *da;
209         struct omap_hwmod *oh;
210
211         oh = omap_hwmod_lookup("dss_dispc");
212         if (!oh) {
213                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
214                 return;
215         }
216
217         if (!oh->dev_attr) {
218                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
219                 return;
220         }
221
222         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
223
224         /* store value of LCDENABLE and DIGITENABLE bits */
225         v = omap_hwmod_read(oh, DISPC_CONTROL);
226         lcd_en = v & LCD_EN_MASK;
227         digit_en = v & DIGIT_EN_MASK;
228
229         /* store value of LCDENABLE for LCD2 */
230         if (da->manager_count > 2) {
231                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
232                 lcd2_en = v & LCD_EN_MASK;
233         }
234
235         if (!(lcd_en | digit_en | lcd2_en))
236                 return; /* no managers currently enabled */
237
238         /*
239          * If any manager was enabled, we need to disable it before
240          * DSS clocks are disabled or DISPC module is reset
241          */
242         if (lcd_en)
243                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
244
245         if (digit_en) {
246                 if (da->has_framedonetv_irq) {
247                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
248                 } else {
249                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
250                                 1 << EVSYNC_ODD_IRQ_SHIFT;
251                 }
252         }
253
254         if (lcd2_en)
255                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
256
257         /*
258          * clear any previous FRAMEDONE, FRAMEDONETV,
259          * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
260          */
261         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
262
263         /* disable LCD and TV managers */
264         v = omap_hwmod_read(oh, DISPC_CONTROL);
265         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
266         omap_hwmod_write(v, oh, DISPC_CONTROL);
267
268         /* disable LCD2 manager */
269         if (da->manager_count > 2) {
270                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
271                 v &= ~LCD_EN_MASK;
272                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
273         }
274
275         i = 0;
276         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
277                irq_mask) {
278                 i++;
279                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
280                         pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
281                         break;
282                 }
283                 mdelay(1);
284         }
285 }
286
287 #define MAX_MODULE_SOFTRESET_WAIT       10000
288 int omap_dss_reset(struct omap_hwmod *oh)
289 {
290         struct omap_hwmod_opt_clk *oc;
291         int c = 0;
292         int i, r;
293
294         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
295                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
296                 return -EINVAL;
297         }
298
299         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
300                 if (oc->_clk)
301                         clk_enable(oc->_clk);
302
303         dispc_disable_outputs();
304
305         /* clear SDI registers */
306         if (cpu_is_omap3430()) {
307                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
308                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
309         }
310
311         /*
312          * clear DSS_CONTROL register to switch DSS clock sources to
313          * PRCM clock, if any
314          */
315         omap_hwmod_write(0x0, oh, DSS_CONTROL);
316
317         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
318                                 & SYSS_RESETDONE_MASK),
319                         MAX_MODULE_SOFTRESET_WAIT, c);
320
321         if (c == MAX_MODULE_SOFTRESET_WAIT)
322                 pr_warning("dss_core: waiting for reset to finish failed\n");
323         else
324                 pr_debug("dss_core: softreset done\n");
325
326         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
327                 if (oc->_clk)
328                         clk_disable(oc->_clk);
329
330         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
331
332         return r;
333 }