arch/arm/mach-omap2/devices.c

   1 /*
   2  * linux/arch/arm/mach-omap2/devices.c
   3  *
   4  * OMAP2 platform device setup/initialization
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <mach/hardware.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/mach/map.h>
  22
  23 #include <plat/control.h>
  24 #include <plat/tc.h>
  25 #include <plat/board.h>
  26 #include <plat/mux.h>
  27 #include <mach/gpio.h>
  28 #include <plat/mmc.h>
  29
  30 #include "mux.h"
  31
  32 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  33
  34 static struct resource cam_resources[] = {
  35         {
  36                 .start          = OMAP24XX_CAMERA_BASE,
  37                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
  38                 .flags          = IORESOURCE_MEM,
  39         },
  40         {
  41                 .start          = INT_24XX_CAM_IRQ,
  42                 .flags          = IORESOURCE_IRQ,
  43         }
  44 };
  45
  46 static struct platform_device omap_cam_device = {
  47         .name           = "omap24xxcam",
  48         .id             = -1,
  49         .num_resources  = ARRAY_SIZE(cam_resources),
  50         .resource       = cam_resources,
  51 };
  52
  53 static inline void omap_init_camera(void)
  54 {
  55         platform_device_register(&omap_cam_device);
  56 }
  57
  58 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  59
  60 static struct resource omap3isp_resources[] = {
  61         {
  62                 .start          = OMAP3430_ISP_BASE,
  63                 .end            = OMAP3430_ISP_END,
  64                 .flags          = IORESOURCE_MEM,
  65         },
  66         {
  67                 .start          = OMAP3430_ISP_CBUFF_BASE,
  68                 .end            = OMAP3430_ISP_CBUFF_END,
  69                 .flags          = IORESOURCE_MEM,
  70         },
  71         {
  72                 .start          = OMAP3430_ISP_CCP2_BASE,
  73                 .end            = OMAP3430_ISP_CCP2_END,
  74                 .flags          = IORESOURCE_MEM,
  75         },
  76         {
  77                 .start          = OMAP3430_ISP_CCDC_BASE,
  78                 .end            = OMAP3430_ISP_CCDC_END,
  79                 .flags          = IORESOURCE_MEM,
  80         },
  81         {
  82                 .start          = OMAP3430_ISP_HIST_BASE,
  83                 .end            = OMAP3430_ISP_HIST_END,
  84                 .flags          = IORESOURCE_MEM,
  85         },
  86         {
  87                 .start          = OMAP3430_ISP_H3A_BASE,
  88                 .end            = OMAP3430_ISP_H3A_END,
  89                 .flags          = IORESOURCE_MEM,
  90         },
  91         {
  92                 .start          = OMAP3430_ISP_PREV_BASE,
  93                 .end            = OMAP3430_ISP_PREV_END,
  94                 .flags          = IORESOURCE_MEM,
  95         },
  96         {
  97                 .start          = OMAP3430_ISP_RESZ_BASE,
  98                 .end            = OMAP3430_ISP_RESZ_END,
  99                 .flags          = IORESOURCE_MEM,
 100         },
 101         {
 102                 .start          = OMAP3430_ISP_SBL_BASE,
 103                 .end            = OMAP3430_ISP_SBL_END,
 104                 .flags          = IORESOURCE_MEM,
 105         },
 106         {
 107                 .start          = OMAP3430_ISP_CSI2A_BASE,
 108                 .end            = OMAP3430_ISP_CSI2A_END,
 109                 .flags          = IORESOURCE_MEM,
 110         },
 111         {
 112                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
 113                 .end            = OMAP3430_ISP_CSI2PHY_END,
 114                 .flags          = IORESOURCE_MEM,
 115         },
 116         {
 117                 .start          = INT_34XX_CAM_IRQ,
 118                 .flags          = IORESOURCE_IRQ,
 119         }
 120 };
 121
 122 static struct platform_device omap3isp_device = {
 123         .name           = "omap3isp",
 124         .id             = -1,
 125         .num_resources  = ARRAY_SIZE(omap3isp_resources),
 126         .resource       = omap3isp_resources,
 127 };
 128
 129 static inline void omap_init_camera(void)
 130 {
 131         platform_device_register(&omap3isp_device);
 132 }
 133 #else
 134 static inline void omap_init_camera(void)
 135 {
 136 }
 137 #endif
 138
 139 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 140
 141 #define MBOX_REG_SIZE   0x120
 142
 143 #ifdef CONFIG_ARCH_OMAP2
 144 static struct resource omap2_mbox_resources[] = {
 145         {
 146                 .start          = OMAP24XX_MAILBOX_BASE,
 147                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 148                 .flags          = IORESOURCE_MEM,
 149         },
 150         {
 151                 .start          = INT_24XX_MAIL_U0_MPU,
 152                 .flags          = IORESOURCE_IRQ,
 153         },
 154         {
 155                 .start          = INT_24XX_MAIL_U3_MPU,
 156                 .flags          = IORESOURCE_IRQ,
 157         },
 158 };
 159 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
 160 #else
 161 #define omap2_mbox_resources            NULL
 162 #define omap2_mbox_resources_sz         0
 163 #endif
 164
 165 #ifdef CONFIG_ARCH_OMAP3
 166 static struct resource omap3_mbox_resources[] = {
 167         {
 168                 .start          = OMAP34XX_MAILBOX_BASE,
 169                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 170                 .flags          = IORESOURCE_MEM,
 171         },
 172         {
 173                 .start          = INT_24XX_MAIL_U0_MPU,
 174                 .flags          = IORESOURCE_IRQ,
 175         },
 176 };
 177 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
 178 #else
 179 #define omap3_mbox_resources            NULL
 180 #define omap3_mbox_resources_sz         0
 181 #endif
 182
 183 #ifdef CONFIG_ARCH_OMAP4
 184
 185 #define OMAP4_MBOX_REG_SIZE     0x130
 186 static struct resource omap4_mbox_resources[] = {
 187         {
 188                 .start          = OMAP44XX_MAILBOX_BASE,
 189                 .end            = OMAP44XX_MAILBOX_BASE +
 190                                         OMAP4_MBOX_REG_SIZE - 1,
 191                 .flags          = IORESOURCE_MEM,
 192         },
 193         {
 194                 .start          = OMAP44XX_IRQ_MAIL_U0,
 195                 .flags          = IORESOURCE_IRQ,
 196         },
 197 };
 198 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
 199 #else
 200 #define omap4_mbox_resources            NULL
 201 #define omap4_mbox_resources_sz         0
 202 #endif
 203
 204 static struct platform_device mbox_device = {
 205         .name           = "omap2-mailbox",
 206         .id             = -1,
 207 };
 208
 209 static inline void omap_init_mbox(void)
 210 {
 211         if (cpu_is_omap24xx()) {
 212                 mbox_device.resource = omap2_mbox_resources;
 213                 mbox_device.num_resources = omap2_mbox_resources_sz;
 214         } else if (cpu_is_omap34xx()) {
 215                 mbox_device.resource = omap3_mbox_resources;
 216                 mbox_device.num_resources = omap3_mbox_resources_sz;
 217         } else if (cpu_is_omap44xx()) {
 218                 mbox_device.resource = omap4_mbox_resources;
 219                 mbox_device.num_resources = omap4_mbox_resources_sz;
 220         } else {
 221                 pr_err("%s: platform not supported\n", __func__);
 222                 return;
 223         }
 224         platform_device_register(&mbox_device);
 225 }
 226 #else
 227 static inline void omap_init_mbox(void) { }
 228 #endif /* CONFIG_OMAP_MBOX_FWK */
 229
 230 #if defined(CONFIG_OMAP_STI)
 231
 232 #if defined(CONFIG_ARCH_OMAP2)
 233
 234 #define OMAP2_STI_BASE          0x48068000
 235 #define OMAP2_STI_CHANNEL_BASE  0x54000000
 236 #define OMAP2_STI_IRQ           4
 237
 238 static struct resource sti_resources[] = {
 239         {
 240                 .start          = OMAP2_STI_BASE,
 241                 .end            = OMAP2_STI_BASE + 0x7ff,
 242                 .flags          = IORESOURCE_MEM,
 243         },
 244         {
 245                 .start          = OMAP2_STI_CHANNEL_BASE,
 246                 .end            = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
 247                 .flags          = IORESOURCE_MEM,
 248         },
 249         {
 250                 .start          = OMAP2_STI_IRQ,
 251                 .flags          = IORESOURCE_IRQ,
 252         }
 253 };
 254 #elif defined(CONFIG_ARCH_OMAP3)
 255
 256 #define OMAP3_SDTI_BASE         0x54500000
 257 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
 258
 259 static struct resource sti_resources[] = {
 260         {
 261                 .start          = OMAP3_SDTI_BASE,
 262                 .end            = OMAP3_SDTI_BASE + 0xFFF,
 263                 .flags          = IORESOURCE_MEM,
 264         },
 265         {
 266                 .start          = OMAP3_SDTI_CHANNEL_BASE,
 267                 .end            = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
 268                 .flags          = IORESOURCE_MEM,
 269         }
 270 };
 271
 272 #endif
 273
 274 static struct platform_device sti_device = {
 275         .name           = "sti",
 276         .id             = -1,
 277         .num_resources  = ARRAY_SIZE(sti_resources),
 278         .resource       = sti_resources,
 279 };
 280
 281 static inline void omap_init_sti(void)
 282 {
 283         platform_device_register(&sti_device);
 284 }
 285 #else
 286 static inline void omap_init_sti(void) {}
 287 #endif
 288
 289 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 290
 291 #include <plat/mcspi.h>
 292
 293 #define OMAP2_MCSPI1_BASE               0x48098000
 294 #define OMAP2_MCSPI2_BASE               0x4809a000
 295 #define OMAP2_MCSPI3_BASE               0x480b8000
 296 #define OMAP2_MCSPI4_BASE               0x480ba000
 297
 298 #define OMAP4_MCSPI1_BASE               0x48098100
 299 #define OMAP4_MCSPI2_BASE               0x4809a100
 300 #define OMAP4_MCSPI3_BASE               0x480b8100
 301 #define OMAP4_MCSPI4_BASE               0x480ba100
 302
 303 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
 304         .num_cs         = 4,
 305 };
 306
 307 static struct resource omap2_mcspi1_resources[] = {
 308         {
 309                 .start          = OMAP2_MCSPI1_BASE,
 310                 .end            = OMAP2_MCSPI1_BASE + 0xff,
 311                 .flags          = IORESOURCE_MEM,
 312         },
 313 };
 314
 315 static struct platform_device omap2_mcspi1 = {
 316         .name           = "omap2_mcspi",
 317         .id             = 1,
 318         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
 319         .resource       = omap2_mcspi1_resources,
 320         .dev            = {
 321                 .platform_data = &omap2_mcspi1_config,
 322         },
 323 };
 324
 325 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
 326         .num_cs         = 2,
 327 };
 328
 329 static struct resource omap2_mcspi2_resources[] = {
 330         {
 331                 .start          = OMAP2_MCSPI2_BASE,
 332                 .end            = OMAP2_MCSPI2_BASE + 0xff,
 333                 .flags          = IORESOURCE_MEM,
 334         },
 335 };
 336
 337 static struct platform_device omap2_mcspi2 = {
 338         .name           = "omap2_mcspi",
 339         .id             = 2,
 340         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
 341         .resource       = omap2_mcspi2_resources,
 342         .dev            = {
 343                 .platform_data = &omap2_mcspi2_config,
 344         },
 345 };
 346
 347 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 348         defined(CONFIG_ARCH_OMAP4)
 349 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
 350         .num_cs         = 2,
 351 };
 352
 353 static struct resource omap2_mcspi3_resources[] = {
 354         {
 355         .start          = OMAP2_MCSPI3_BASE,
 356         .end            = OMAP2_MCSPI3_BASE + 0xff,
 357         .flags          = IORESOURCE_MEM,
 358         },
 359 };
 360
 361 static struct platform_device omap2_mcspi3 = {
 362         .name           = "omap2_mcspi",
 363         .id             = 3,
 364         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
 365         .resource       = omap2_mcspi3_resources,
 366         .dev            = {
 367                 .platform_data = &omap2_mcspi3_config,
 368         },
 369 };
 370 #endif
 371
 372 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 373 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
 374         .num_cs         = 1,
 375 };
 376
 377 static struct resource omap2_mcspi4_resources[] = {
 378         {
 379                 .start          = OMAP2_MCSPI4_BASE,
 380                 .end            = OMAP2_MCSPI4_BASE + 0xff,
 381                 .flags          = IORESOURCE_MEM,
 382         },
 383 };
 384
 385 static struct platform_device omap2_mcspi4 = {
 386         .name           = "omap2_mcspi",
 387         .id             = 4,
 388         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
 389         .resource       = omap2_mcspi4_resources,
 390         .dev            = {
 391                 .platform_data = &omap2_mcspi4_config,
 392         },
 393 };
 394 #endif
 395
 396 #ifdef CONFIG_ARCH_OMAP4
 397 static inline void omap4_mcspi_fixup(void)
 398 {
 399         omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
 400         omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
 401         omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
 402         omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
 403         omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
 404         omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
 405         omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
 406         omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
 407 }
 408 #else
 409 static inline void omap4_mcspi_fixup(void)
 410 {
 411 }
 412 #endif
 413
 414 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
 415         defined(CONFIG_ARCH_OMAP4)
 416 static inline void omap2_mcspi3_init(void)
 417 {
 418         platform_device_register(&omap2_mcspi3);
 419 }
 420 #else
 421 static inline void omap2_mcspi3_init(void)
 422 {
 423 }
 424 #endif
 425
 426 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 427 static inline void omap2_mcspi4_init(void)
 428 {
 429         platform_device_register(&omap2_mcspi4);
 430 }
 431 #else
 432 static inline void omap2_mcspi4_init(void)
 433 {
 434 }
 435 #endif
 436
 437 static void omap_init_mcspi(void)
 438 {
 439         if (cpu_is_omap44xx())
 440                 omap4_mcspi_fixup();
 441
 442         platform_device_register(&omap2_mcspi1);
 443         platform_device_register(&omap2_mcspi2);
 444
 445         if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
 446                 omap2_mcspi3_init();
 447
 448         if (cpu_is_omap343x() || cpu_is_omap44xx())
 449                 omap2_mcspi4_init();
 450 }
 451
 452 #else
 453 static inline void omap_init_mcspi(void) {}
 454 #endif
 455
 456 #ifdef CONFIG_OMAP_SHA1_MD5
 457 static struct resource sha1_md5_resources[] = {
 458         {
 459                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
 460                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
 461                 .flags  = IORESOURCE_MEM,
 462         },
 463         {
 464                 .start  = INT_24XX_SHA1MD5,
 465                 .flags  = IORESOURCE_IRQ,
 466         }
 467 };
 468
 469 static struct platform_device sha1_md5_device = {
 470         .name           = "OMAP SHA1/MD5",
 471         .id             = -1,
 472         .num_resources  = ARRAY_SIZE(sha1_md5_resources),
 473         .resource       = sha1_md5_resources,
 474 };
 475
 476 static void omap_init_sha1_md5(void)
 477 {
 478         platform_device_register(&sha1_md5_device);
 479 }
 480 #else
 481 static inline void omap_init_sha1_md5(void) { }
 482 #endif
 483
 484 /*-------------------------------------------------------------------------*/
 485
 486 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 487
 488 #define MMCHS_SYSCONFIG                 0x0010
 489 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
 490 #define MMCHS_SYSSTATUS                 0x0014
 491 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
 492
 493 static struct platform_device dummy_pdev = {
 494         .dev = {
 495                 .bus = &platform_bus_type,
 496         },
 497 };
 498
 499 /**
 500  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 501  *
 502  * Ensure that each MMC controller is fully reset.  Controllers
 503  * left in an unknown state (by bootloader) may prevent retention
 504  * or OFF-mode.  This is especially important in cases where the
 505  * MMC driver is not enabled, _or_ built as a module.
 506  *
 507  * In order for reset to work, interface, functional and debounce
 508  * clocks must be enabled.  The debounce clock comes from func_32k_clk
 509  * and is not under SW control, so we only enable i- and f-clocks.
 510  **/
 511 static void __init omap_hsmmc_reset(void)
 512 {
 513         u32 i, nr_controllers;
 514
 515         if (cpu_is_omap242x())
 516                 return;
 517
 518         nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
 519                 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
 520
 521         for (i = 0; i < nr_controllers; i++) {
 522                 u32 v, base = 0;
 523                 struct clk *iclk, *fclk;
 524                 struct device *dev = &dummy_pdev.dev;
 525
 526                 switch (i) {
 527                 case 0:
 528                         base = OMAP2_MMC1_BASE;
 529                         break;
 530                 case 1:
 531                         base = OMAP2_MMC2_BASE;
 532                         break;
 533                 case 2:
 534                         base = OMAP3_MMC3_BASE;
 535                         break;
 536                 case 3:
 537                         if (!cpu_is_omap44xx())
 538                                 return;
 539                         base = OMAP4_MMC4_BASE;
 540                         break;
 541                 case 4:
 542                         if (!cpu_is_omap44xx())
 543                                 return;
 544                         base = OMAP4_MMC5_BASE;
 545                         break;
 546                 }
 547
 548                 if (cpu_is_omap44xx())
 549                         base += OMAP4_MMC_REG_OFFSET;
 550
 551                 dummy_pdev.id = i;
 552                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
 553                 iclk = clk_get(dev, "ick");
 554                 if (iclk && clk_enable(iclk))
 555                         iclk = NULL;
 556
 557                 fclk = clk_get(dev, "fck");
 558                 if (fclk && clk_enable(fclk))
 559                         fclk = NULL;
 560
 561                 if (!iclk || !fclk) {
 562                         printk(KERN_WARNING
 563                                "%s: Unable to enable clocks for MMC%d, "
 564                                "cannot reset.\n",  __func__, i);
 565                         break;
 566                 }
 567
 568                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
 569                 v = omap_readl(base + MMCHS_SYSSTATUS);
 570                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
 571                          MMCHS_SYSSTATUS_RESETDONE))
 572                         cpu_relax();
 573
 574                 if (fclk) {
 575                         clk_disable(fclk);
 576                         clk_put(fclk);
 577                 }
 578                 if (iclk) {
 579                         clk_disable(iclk);
 580                         clk_put(iclk);
 581                 }
 582         }
 583 }
 584 #else
 585 static inline void omap_hsmmc_reset(void) {}
 586 #endif
 587
 588 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 589         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 590
 591 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 592                         int controller_nr)
 593 {
 594         if (cpu_is_omap2420() && controller_nr == 0) {
 595                 omap_cfg_reg(H18_24XX_MMC_CMD);
 596                 omap_cfg_reg(H15_24XX_MMC_CLKI);
 597                 omap_cfg_reg(G19_24XX_MMC_CLKO);
 598                 omap_cfg_reg(F20_24XX_MMC_DAT0);
 599                 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
 600                 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
 601                 if (mmc_controller->slots[0].wires == 4) {
 602                         omap_cfg_reg(H14_24XX_MMC_DAT1);
 603                         omap_cfg_reg(E19_24XX_MMC_DAT2);
 604                         omap_cfg_reg(D19_24XX_MMC_DAT3);
 605                         omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
 606                         omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
 607                         omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
 608                 }
 609
 610                 /*
 611                  * Use internal loop-back in MMC/SDIO Module Input Clock
 612                  * selection
 613                  */
 614                 if (mmc_controller->slots[0].internal_clock) {
 615                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 616                         v |= (1 << 24);
 617                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 618                 }
 619         }
 620
 621         if (cpu_is_omap34xx()) {
 622                 if (controller_nr == 0) {
 623                         omap_mux_init_signal("sdmmc1_clk",
 624                                 OMAP_PIN_INPUT_PULLUP);
 625                         omap_mux_init_signal("sdmmc1_cmd",
 626                                 OMAP_PIN_INPUT_PULLUP);
 627                         omap_mux_init_signal("sdmmc1_dat0",
 628                                 OMAP_PIN_INPUT_PULLUP);
 629                         if (mmc_controller->slots[0].wires == 4 ||
 630                                 mmc_controller->slots[0].wires == 8) {
 631                                 omap_mux_init_signal("sdmmc1_dat1",
 632                                         OMAP_PIN_INPUT_PULLUP);
 633                                 omap_mux_init_signal("sdmmc1_dat2",
 634                                         OMAP_PIN_INPUT_PULLUP);
 635                                 omap_mux_init_signal("sdmmc1_dat3",
 636                                         OMAP_PIN_INPUT_PULLUP);
 637                         }
 638                         if (mmc_controller->slots[0].wires == 8) {
 639                                 omap_mux_init_signal("sdmmc1_dat4",
 640                                         OMAP_PIN_INPUT_PULLUP);
 641                                 omap_mux_init_signal("sdmmc1_dat5",
 642                                         OMAP_PIN_INPUT_PULLUP);
 643                                 omap_mux_init_signal("sdmmc1_dat6",
 644                                         OMAP_PIN_INPUT_PULLUP);
 645                                 omap_mux_init_signal("sdmmc1_dat7",
 646                                         OMAP_PIN_INPUT_PULLUP);
 647                         }
 648                 }
 649                 if (controller_nr == 1) {
 650                         /* MMC2 */
 651                         omap_mux_init_signal("sdmmc2_clk",
 652                                 OMAP_PIN_INPUT_PULLUP);
 653                         omap_mux_init_signal("sdmmc2_cmd",
 654                                 OMAP_PIN_INPUT_PULLUP);
 655                         omap_mux_init_signal("sdmmc2_dat0",
 656                                 OMAP_PIN_INPUT_PULLUP);
 657
 658                         /*
 659                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
 660                          * in the board-*.c files
 661                          */
 662                         if (mmc_controller->slots[0].wires == 4 ||
 663                                 mmc_controller->slots[0].wires == 8) {
 664                                 omap_mux_init_signal("sdmmc2_dat1",
 665                                         OMAP_PIN_INPUT_PULLUP);
 666                                 omap_mux_init_signal("sdmmc2_dat2",
 667                                         OMAP_PIN_INPUT_PULLUP);
 668                                 omap_mux_init_signal("sdmmc2_dat3",
 669                                         OMAP_PIN_INPUT_PULLUP);
 670                         }
 671                         if (mmc_controller->slots[0].wires == 8) {
 672                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 673                                         OMAP_PIN_INPUT_PULLUP);
 674                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 675                                         OMAP_PIN_INPUT_PULLUP);
 676                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 677                                         OMAP_PIN_INPUT_PULLUP);
 678                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 679                                         OMAP_PIN_INPUT_PULLUP);
 680                         }
 681                 }
 682
 683                 /*
 684                  * For MMC3 the pins need to be muxed in the board-*.c files
 685                  */
 686         }
 687 }
 688
 689 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 690                         int nr_controllers)
 691 {
 692         int i;
 693         char *name;
 694
 695         for (i = 0; i < nr_controllers; i++) {
 696                 unsigned long base, size;
 697                 unsigned int irq = 0;
 698
 699                 if (!mmc_data[i])
 700                         continue;
 701
 702                 omap2_mmc_mux(mmc_data[i], i);
 703
 704                 switch (i) {
 705                 case 0:
 706                         base = OMAP2_MMC1_BASE;
 707                         irq = INT_24XX_MMC_IRQ;
 708                         break;
 709                 case 1:
 710                         base = OMAP2_MMC2_BASE;
 711                         irq = INT_24XX_MMC2_IRQ;
 712                         break;
 713                 case 2:
 714                         if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
 715                                 return;
 716                         base = OMAP3_MMC3_BASE;
 717                         irq = INT_34XX_MMC3_IRQ;
 718                         break;
 719                 case 3:
 720                         if (!cpu_is_omap44xx())
 721                                 return;
 722                         base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
 723                         irq = OMAP44XX_IRQ_MMC4;
 724                         break;
 725                 case 4:
 726                         if (!cpu_is_omap44xx())
 727                                 return;
 728                         base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
 729                         irq = OMAP44XX_IRQ_MMC4;
 730                         break;
 731                 default:
 732                         continue;
 733                 }
 734
 735                 if (cpu_is_omap2420()) {
 736                         size = OMAP2420_MMC_SIZE;
 737                         name = "mmci-omap";
 738                 } else if (cpu_is_omap44xx()) {
 739                         if (i < 3) {
 740                                 base += OMAP4_MMC_REG_OFFSET;
 741                                 irq += OMAP44XX_IRQ_GIC_START;
 742                         }
 743                         size = OMAP4_HSMMC_SIZE;
 744                         name = "mmci-omap-hs";
 745                 } else {
 746                         size = OMAP3_HSMMC_SIZE;
 747                         name = "mmci-omap-hs";
 748                 }
 749                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
 750         };
 751 }
 752
 753 #endif
 754
 755 /*-------------------------------------------------------------------------*/
 756
 757 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 758 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 759 #define OMAP_HDQ_BASE   0x480B2000
 760 #endif
 761 static struct resource omap_hdq_resources[] = {
 762         {
 763                 .start          = OMAP_HDQ_BASE,
 764                 .end            = OMAP_HDQ_BASE + 0x1C,
 765                 .flags          = IORESOURCE_MEM,
 766         },
 767         {
 768                 .start          = INT_24XX_HDQ_IRQ,
 769                 .flags          = IORESOURCE_IRQ,
 770         },
 771 };
 772 static struct platform_device omap_hdq_dev = {
 773         .name = "omap_hdq",
 774         .id = 0,
 775         .dev = {
 776                 .platform_data = NULL,
 777         },
 778         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
 779         .resource       = omap_hdq_resources,
 780 };
 781 static inline void omap_hdq_init(void)
 782 {
 783         (void) platform_device_register(&omap_hdq_dev);
 784 }
 785 #else
 786 static inline void omap_hdq_init(void) {}
 787 #endif
 788
 789 /*-------------------------------------------------------------------------*/
 790
 791 static int __init omap2_init_devices(void)
 792 {
 793         /* please keep these calls, and their implementations above,
 794          * in alphabetical order so they're easier to sort through.
 795          */
 796         omap_hsmmc_reset();
 797         omap_init_camera();
 798         omap_init_mbox();
 799         omap_init_mcspi();
 800         omap_hdq_init();
 801         omap_init_sti();
 802         omap_init_sha1_md5();
 803
 804         return 0;
 805 }
 806 arch_initcall(omap2_init_devices);