arch/arm/mach-omap2/cm2xxx_3xxx.c

   1 /*
   2  * OMAP2/3 CM module functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/delay.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20
  21 #include <plat/common.h>
  22
  23 #include "cm.h"
  24 #include "cm2xxx_3xxx.h"
  25 #include "cm-regbits-24xx.h"
  26 #include "cm-regbits-34xx.h"
  27
  28 static const u8 cm_idlest_offs[] = {
  29         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
  30 };
  31
  32 u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
  33 {
  34         return __raw_readl(cm_base + module + idx);
  35 }
  36
  37 void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
  38 {
  39         __raw_writel(val, cm_base + module + idx);
  40 }
  41
  42 /* Read-modify-write a register in a CM module. Caller must lock */
  43 u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  44 {
  45         u32 v;
  46
  47         v = omap2_cm_read_mod_reg(module, idx);
  48         v &= ~mask;
  49         v |= bits;
  50         omap2_cm_write_mod_reg(v, module, idx);
  51
  52         return v;
  53 }
  54
  55 u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
  56 {
  57         return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
  58 }
  59
  60 u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  61 {
  62         return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
  63 }
  64
  65 /*
  66  *
  67  */
  68
  69 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
  70 {
  71         u32 v;
  72
  73         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  74         v &= ~mask;
  75         v |= c << __ffs(mask);
  76         omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
  77 }
  78
  79 bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
  80 {
  81         u32 v;
  82         bool ret = 0;
  83
  84         BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
  85
  86         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  87         v &= mask;
  88         v >>= __ffs(mask);
  89
  90         if (cpu_is_omap24xx())
  91                 ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
  92         else
  93                 ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
  94
  95         return ret;
  96 }
  97
  98 void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
  99 {
 100         _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
 101 }
 102
 103 void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
 104 {
 105         _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
 106 }
 107
 108 void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
 109 {
 110         _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
 111 }
 112
 113 void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
 114 {
 115         _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
 116 }
 117
 118 void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
 119 {
 120         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
 121 }
 122
 123 void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
 124 {
 125         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
 126 }
 127
 128
 129 /*
 130  *
 131  */
 132
 133 /**
 134  * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
 135  * @prcm_mod: PRCM module offset
 136  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
 137  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
 138  *
 139  * XXX document
 140  */
 141 int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 142 {
 143         int ena = 0, i = 0;
 144         u8 cm_idlest_reg;
 145         u32 mask;
 146
 147         if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
 148                 return -EINVAL;
 149
 150         cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
 151
 152         mask = 1 << idlest_shift;
 153
 154         if (cpu_is_omap24xx())
 155                 ena = mask;
 156         else if (cpu_is_omap34xx())
 157                 ena = 0;
 158         else
 159                 BUG();
 160
 161         omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
 162                           MAX_MODULE_READY_TIME, i);
 163
 164         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 165 }
 166
 167 /*
 168  * Context save/restore code - OMAP3 only
 169  */
 170 #ifdef CONFIG_ARCH_OMAP3
 171 struct omap3_cm_regs {
 172         u32 iva2_cm_clksel1;
 173         u32 iva2_cm_clksel2;
 174         u32 cm_sysconfig;
 175         u32 sgx_cm_clksel;
 176         u32 dss_cm_clksel;
 177         u32 cam_cm_clksel;
 178         u32 per_cm_clksel;
 179         u32 emu_cm_clksel;
 180         u32 emu_cm_clkstctrl;
 181         u32 pll_cm_autoidle2;
 182         u32 pll_cm_clksel4;
 183         u32 pll_cm_clksel5;
 184         u32 pll_cm_clken2;
 185         u32 cm_polctrl;
 186         u32 iva2_cm_fclken;
 187         u32 iva2_cm_clken_pll;
 188         u32 core_cm_fclken1;
 189         u32 core_cm_fclken3;
 190         u32 sgx_cm_fclken;
 191         u32 wkup_cm_fclken;
 192         u32 dss_cm_fclken;
 193         u32 cam_cm_fclken;
 194         u32 per_cm_fclken;
 195         u32 usbhost_cm_fclken;
 196         u32 core_cm_iclken1;
 197         u32 core_cm_iclken2;
 198         u32 core_cm_iclken3;
 199         u32 sgx_cm_iclken;
 200         u32 wkup_cm_iclken;
 201         u32 dss_cm_iclken;
 202         u32 cam_cm_iclken;
 203         u32 per_cm_iclken;
 204         u32 usbhost_cm_iclken;
 205         u32 iva2_cm_autoidle2;
 206         u32 mpu_cm_autoidle2;
 207         u32 iva2_cm_clkstctrl;
 208         u32 mpu_cm_clkstctrl;
 209         u32 core_cm_clkstctrl;
 210         u32 sgx_cm_clkstctrl;
 211         u32 dss_cm_clkstctrl;
 212         u32 cam_cm_clkstctrl;
 213         u32 per_cm_clkstctrl;
 214         u32 neon_cm_clkstctrl;
 215         u32 usbhost_cm_clkstctrl;
 216         u32 core_cm_autoidle1;
 217         u32 core_cm_autoidle2;
 218         u32 core_cm_autoidle3;
 219         u32 wkup_cm_autoidle;
 220         u32 dss_cm_autoidle;
 221         u32 cam_cm_autoidle;
 222         u32 per_cm_autoidle;
 223         u32 usbhost_cm_autoidle;
 224         u32 sgx_cm_sleepdep;
 225         u32 dss_cm_sleepdep;
 226         u32 cam_cm_sleepdep;
 227         u32 per_cm_sleepdep;
 228         u32 usbhost_cm_sleepdep;
 229         u32 cm_clkout_ctrl;
 230 };
 231
 232 static struct omap3_cm_regs cm_context;
 233
 234 void omap3_cm_save_context(void)
 235 {
 236         cm_context.iva2_cm_clksel1 =
 237                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 238         cm_context.iva2_cm_clksel2 =
 239                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 240         cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
 241         cm_context.sgx_cm_clksel =
 242                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 243         cm_context.dss_cm_clksel =
 244                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 245         cm_context.cam_cm_clksel =
 246                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 247         cm_context.per_cm_clksel =
 248                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 249         cm_context.emu_cm_clksel =
 250                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 251         cm_context.emu_cm_clkstctrl =
 252                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
 253         cm_context.pll_cm_autoidle2 =
 254                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 255         cm_context.pll_cm_clksel4 =
 256                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 257         cm_context.pll_cm_clksel5 =
 258                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 259         cm_context.pll_cm_clken2 =
 260                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 261         cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
 262         cm_context.iva2_cm_fclken =
 263                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 264         cm_context.iva2_cm_clken_pll =
 265                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
 266         cm_context.core_cm_fclken1 =
 267                 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 268         cm_context.core_cm_fclken3 =
 269                 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 270         cm_context.sgx_cm_fclken =
 271                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 272         cm_context.wkup_cm_fclken =
 273                 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 274         cm_context.dss_cm_fclken =
 275                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 276         cm_context.cam_cm_fclken =
 277                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 278         cm_context.per_cm_fclken =
 279                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 280         cm_context.usbhost_cm_fclken =
 281                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 282         cm_context.core_cm_iclken1 =
 283                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 284         cm_context.core_cm_iclken2 =
 285                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 286         cm_context.core_cm_iclken3 =
 287                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 288         cm_context.sgx_cm_iclken =
 289                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 290         cm_context.wkup_cm_iclken =
 291                 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 292         cm_context.dss_cm_iclken =
 293                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 294         cm_context.cam_cm_iclken =
 295                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 296         cm_context.per_cm_iclken =
 297                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 298         cm_context.usbhost_cm_iclken =
 299                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 300         cm_context.iva2_cm_autoidle2 =
 301                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 302         cm_context.mpu_cm_autoidle2 =
 303                 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 304         cm_context.iva2_cm_clkstctrl =
 305                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 306         cm_context.mpu_cm_clkstctrl =
 307                 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
 308         cm_context.core_cm_clkstctrl =
 309                 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
 310         cm_context.sgx_cm_clkstctrl =
 311                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
 312         cm_context.dss_cm_clkstctrl =
 313                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
 314         cm_context.cam_cm_clkstctrl =
 315                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
 316         cm_context.per_cm_clkstctrl =
 317                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
 318         cm_context.neon_cm_clkstctrl =
 319                 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
 320         cm_context.usbhost_cm_clkstctrl =
 321                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 322                                       OMAP2_CM_CLKSTCTRL);
 323         cm_context.core_cm_autoidle1 =
 324                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 325         cm_context.core_cm_autoidle2 =
 326                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 327         cm_context.core_cm_autoidle3 =
 328                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 329         cm_context.wkup_cm_autoidle =
 330                 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 331         cm_context.dss_cm_autoidle =
 332                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 333         cm_context.cam_cm_autoidle =
 334                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 335         cm_context.per_cm_autoidle =
 336                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 337         cm_context.usbhost_cm_autoidle =
 338                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 339         cm_context.sgx_cm_sleepdep =
 340                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 341                                       OMAP3430_CM_SLEEPDEP);
 342         cm_context.dss_cm_sleepdep =
 343                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 344         cm_context.cam_cm_sleepdep =
 345                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 346         cm_context.per_cm_sleepdep =
 347                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 348         cm_context.usbhost_cm_sleepdep =
 349                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 350                                       OMAP3430_CM_SLEEPDEP);
 351         cm_context.cm_clkout_ctrl =
 352                 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
 353                                       OMAP3_CM_CLKOUT_CTRL_OFFSET);
 354 }
 355
 356 void omap3_cm_restore_context(void)
 357 {
 358         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 359                                CM_CLKSEL1);
 360         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 361                                CM_CLKSEL2);
 362         __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
 363         omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 364                                CM_CLKSEL);
 365         omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 366                                CM_CLKSEL);
 367         omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 368                                CM_CLKSEL);
 369         omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
 370                                CM_CLKSEL);
 371         omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 372                                CM_CLKSEL1);
 373         omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 374                                OMAP2_CM_CLKSTCTRL);
 375         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
 376                                CM_AUTOIDLE2);
 377         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
 378                                OMAP3430ES2_CM_CLKSEL4);
 379         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
 380                                OMAP3430ES2_CM_CLKSEL5);
 381         omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
 382                                OMAP3430ES2_CM_CLKEN2);
 383         __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
 384         omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 385                                CM_FCLKEN);
 386         omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 387                                OMAP3430_CM_CLKEN_PLL);
 388         omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
 389                                CM_FCLKEN1);
 390         omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
 391                                OMAP3430ES2_CM_FCLKEN3);
 392         omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 393                                CM_FCLKEN);
 394         omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 395         omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 396                                CM_FCLKEN);
 397         omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 398                                CM_FCLKEN);
 399         omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
 400                                CM_FCLKEN);
 401         omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
 402                                OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 403         omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
 404                                CM_ICLKEN1);
 405         omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
 406                                CM_ICLKEN2);
 407         omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
 408                                CM_ICLKEN3);
 409         omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 410                                CM_ICLKEN);
 411         omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 412         omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 413                                CM_ICLKEN);
 414         omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 415                                CM_ICLKEN);
 416         omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
 417                                CM_ICLKEN);
 418         omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
 419                                OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 420         omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
 421                                CM_AUTOIDLE2);
 422         omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
 423                                CM_AUTOIDLE2);
 424         omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 425                                OMAP2_CM_CLKSTCTRL);
 426         omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
 427                                OMAP2_CM_CLKSTCTRL);
 428         omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
 429                                OMAP2_CM_CLKSTCTRL);
 430         omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 431                                OMAP2_CM_CLKSTCTRL);
 432         omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 433                                OMAP2_CM_CLKSTCTRL);
 434         omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 435                                OMAP2_CM_CLKSTCTRL);
 436         omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 437                                OMAP2_CM_CLKSTCTRL);
 438         omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 439                                OMAP2_CM_CLKSTCTRL);
 440         omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
 441                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
 442         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
 443                                CM_AUTOIDLE1);
 444         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
 445                                CM_AUTOIDLE2);
 446         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
 447                                CM_AUTOIDLE3);
 448         omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
 449                                CM_AUTOIDLE);
 450         omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 451                                CM_AUTOIDLE);
 452         omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 453                                CM_AUTOIDLE);
 454         omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 455                                CM_AUTOIDLE);
 456         omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
 457                                OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 458         omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 459                                OMAP3430_CM_SLEEPDEP);
 460         omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 461                                OMAP3430_CM_SLEEPDEP);
 462         omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 463                                OMAP3430_CM_SLEEPDEP);
 464         omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 465                                OMAP3430_CM_SLEEPDEP);
 466         omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
 467                                OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 468         omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 469                                OMAP3_CM_CLKOUT_CTRL_OFFSET);
 470 }
 471 #endif