arch/arm/mach-omap2/cm-regbits-44xx.h

   1 /*
   2  * OMAP44xx Clock Management register bits
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  23 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  24
  25 /*
  26  * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
  27  * CM_TESLA_DYNAMICDEP
  28  */
  29 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
  30 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
  31
  32 /*
  33  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
  34  * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
  35  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  36  */
  37 #define OMAP4430_ABE_STATDEP_SHIFT                              3
  38 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
  39
  40 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
  41 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
  42 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
  43
  44 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
  45 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
  46 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
  47
  48 /*
  49  * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
  50  * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
  51  * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
  52  * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  53  */
  54 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
  55 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
  56
  57 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
  58 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
  59 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
  60
  61 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
  62 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
  63 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
  64
  65 /* Used by CM1_ABE_CLKSTCTRL */
  66 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
  67 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
  68
  69 /* Used by CM1_ABE_CLKSTCTRL */
  70 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
  71 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
  72
  73 /* Used by CM_WKUP_CLKSTCTRL */
  74 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
  75 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
  76
  77 /* Used by CM1_ABE_CLKSTCTRL */
  78 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
  79 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
  80
  81 /* Used by CM1_ABE_CLKSTCTRL */
  82 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
  83 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
  84
  85 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
  86 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
  87 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
  88
  89 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
  90 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
  91 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
  92
  93 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
  94 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
  95 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
  96
  97 /* Used by CM_CAM_CLKSTCTRL */
  98 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
  99 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
 100
 101 /* Used by CM_ALWON_CLKSTCTRL */
 102 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
 103 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 104
 105 /* Used by CM_EMU_CLKSTCTRL */
 106 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
 107 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 108
 109 /* Used by CM_L4CFG_CLKSTCTRL */
 110 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT                9
 111 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                 (1 << 9)
 112
 113 /* Used by CM_CEFUSE_CLKSTCTRL */
 114 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
 115 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 116
 117 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 118 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
 119 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 120
 121 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 122 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
 123 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 124
 125 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 126 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
 127 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 128
 129 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 130 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
 131 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 132
 133 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 134 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
 135 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 136
 137 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 138 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
 139 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 140
 141 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 142 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
 143 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 144
 145 /* Used by CM_DSS_CLKSTCTRL */
 146 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
 147 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 148
 149 /* Used by CM_DSS_CLKSTCTRL */
 150 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
 151 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 152
 153 /* Used by CM_DUCATI_CLKSTCTRL */
 154 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
 155 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 156
 157 /* Used by CM_EMU_CLKSTCTRL */
 158 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
 159 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 160
 161 /* Used by CM_CAM_CLKSTCTRL */
 162 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
 163 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 164
 165 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 166 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
 167 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 168
 169 /* Used by CM1_ABE_CLKSTCTRL */
 170 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
 171 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 172
 173 /* Used by CM_DSS_CLKSTCTRL */
 174 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
 175 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 176
 177 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 178 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
 179 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 180
 181 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 182 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
 183 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 184
 185 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 186 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
 187 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 188
 189 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 190 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
 191 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 192
 193 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 194 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
 195 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 196
 197 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 198 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
 199 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 200
 201 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 202 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
 203 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 204
 205 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 206 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
 207 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 208
 209 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 210 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
 211 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 212
 213 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 214 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
 215 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 216
 217 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 218 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
 219 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 220
 221 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 222 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
 223 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 224
 225 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 226 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
 227 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 228
 229 /* Used by CM_CAM_CLKSTCTRL */
 230 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
 231 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 232
 233 /* Used by CM_IVAHD_CLKSTCTRL */
 234 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
 235 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 236
 237 /* Used by CM_D2D_CLKSTCTRL */
 238 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
 239 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 240
 241 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
 242 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
 243 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 244
 245 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
 246 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
 247 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 248
 249 /* Used by CM_D2D_CLKSTCTRL */
 250 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
 251 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 252
 253 /* Used by CM_SDMA_CLKSTCTRL */
 254 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
 255 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 256
 257 /* Used by CM_DSS_CLKSTCTRL */
 258 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
 259 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 260
 261 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 262 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
 263 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 264
 265 /* Used by CM_GFX_CLKSTCTRL */
 266 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
 267 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 268
 269 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 270 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
 271 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 272
 273 /* Used by CM_L3INSTR_CLKSTCTRL */
 274 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
 275 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 276
 277 /* Used by CM_L4SEC_CLKSTCTRL */
 278 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
 279 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 280
 281 /* Used by CM_ALWON_CLKSTCTRL */
 282 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
 283 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 284
 285 /* Used by CM_CEFUSE_CLKSTCTRL */
 286 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
 287 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 288
 289 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
 290 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
 291 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 292
 293 /* Used by CM_D2D_CLKSTCTRL */
 294 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
 295 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 296
 297 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 298 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
 299 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 300
 301 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 302 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
 303 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 304
 305 /* Used by CM_L4SEC_CLKSTCTRL */
 306 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
 307 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 308
 309 /* Used by CM_WKUP_CLKSTCTRL */
 310 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
 311 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 312
 313 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
 314 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
 315 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 316
 317 /* Used by CM1_ABE_CLKSTCTRL */
 318 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
 319 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 320
 321 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 322 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
 323 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 324
 325 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 326 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
 327 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 328
 329 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 330 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
 331 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 332
 333 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 334 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
 335 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 336
 337 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 338 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
 339 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 340
 341 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 342 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
 343 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 344
 345 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 346 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
 347 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 348
 349 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 350 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
 351 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 352
 353 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 354 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
 355 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 356
 357 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 358 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
 359 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 360
 361 /* Used by CM_GFX_CLKSTCTRL */
 362 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
 363 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 364
 365 /* Used by CM_ALWON_CLKSTCTRL */
 366 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
 367 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 368
 369 /* Used by CM_ALWON_CLKSTCTRL */
 370 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
 371 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 372
 373 /* Used by CM_ALWON_CLKSTCTRL */
 374 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
 375 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 376
 377 /* Used by CM_WKUP_CLKSTCTRL */
 378 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
 379 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 380
 381 /* Used by CM_TESLA_CLKSTCTRL */
 382 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
 383 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 384
 385 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 386 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
 387 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 388
 389 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 390 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
 391 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 392
 393 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 394 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
 395 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 396
 397 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 398 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
 399 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 400
 401 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 402 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
 403 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 404
 405 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 406 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
 407 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 408
 409 /* Used by CM_WKUP_CLKSTCTRL */
 410 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
 411 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 412
 413 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 414 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
 415 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 416
 417 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 418 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
 419 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 420
 421 /* Used by CM_WKUP_CLKSTCTRL */
 422 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
 423 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 424
 425 /* Used by CM_WKUP_CLKSTCTRL */
 426 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT                13
 427 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                 (1 << 13)
 428
 429 /*
 430  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
 431  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
 432  * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
 433  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
 434  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
 435  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
 436  * CM_WKUP_TIMER1_CLKCTRL
 437  */
 438 #define OMAP4430_CLKSEL_SHIFT                                   24
 439 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 440
 441 /*
 442  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
 443  * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
 444  */
 445 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
 446 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 447
 448 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 449 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
 450 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 451
 452 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 453 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
 454 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 455
 456 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 457 #define OMAP4430_CLKSEL_60M_SHIFT                               24
 458 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 459
 460 /* Used by CM_MPU_MPU_CLKCTRL */
 461 #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                      25
 462 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                       (1 << 25)
 463
 464 /* Used by CM1_ABE_AESS_CLKCTRL */
 465 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
 466 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 467
 468 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 469 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
 470 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 471
 472 /*
 473  * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
 474  * CM_SHADOW_FREQ_CONFIG2
 475  */
 476 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
 477 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 478
 479 /* Used by CM_WKUP_USIM_CLKCTRL */
 480 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
 481 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 482
 483 /* Used by CM_MPU_MPU_CLKCTRL */
 484 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                     24
 485 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                      (1 << 24)
 486
 487 /* Used by CM_CAM_FDIF_CLKCTRL */
 488 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
 489 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 490
 491 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 492 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
 493 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 494
 495 /*
 496  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
 497  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 498  * CM1_ABE_MCBSP3_CLKCTRL
 499  */
 500 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
 501 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 502
 503 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 504 #define OMAP4430_CLKSEL_L3_SHIFT                                4
 505 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 506
 507 /*
 508  * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
 509  * CM_SHADOW_FREQ_CONFIG2
 510  */
 511 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
 512 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 513
 514 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 515 #define OMAP4430_CLKSEL_L4_SHIFT                                8
 516 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 517
 518 /* Used by CM_CLKSEL_ABE */
 519 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
 520 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 521
 522 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 523 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
 524 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 525
 526 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 527 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
 528 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 529
 530 /* Used by CM_GFX_GFX_CLKCTRL */
 531 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
 532 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 533
 534 /*
 535  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
 536  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
 537  */
 538 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
 539 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 540
 541 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 542 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
 543 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 544
 545 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 546 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
 547 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 548
 549 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 550 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
 551 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 552
 553 /*
 554  * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
 555  * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
 556  * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
 557  * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
 558  * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
 559  * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
 560  * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
 561  * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
 562  * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
 563  * CM_WKUP_CLKSTCTRL
 564  */
 565 #define OMAP4430_CLKTRCTRL_SHIFT                                0
 566 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 567
 568 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 569 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
 570 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 571
 572 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 573 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
 574 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 575
 576 /* Used by REVISION_CM1, REVISION_CM2 */
 577 #define OMAP4430_CUSTOM_SHIFT                                   6
 578 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 579
 580 /*
 581  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 582  * CM_L4CFG_DYNAMICDEP_RESTORE
 583  */
 584 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
 585 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 586
 587 /* Used by CM_MPU_STATICDEP */
 588 #define OMAP4430_D2D_STATDEP_SHIFT                              18
 589 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 590
 591 /* Used by CM_CLKSEL_DPLL_MPU */
 592 #define OMAP4460_DCC_COUNT_MAX_SHIFT                            24
 593 #define OMAP4460_DCC_COUNT_MAX_MASK                             (0xff << 24)
 594
 595 /* Used by CM_CLKSEL_DPLL_MPU */
 596 #define OMAP4460_DCC_EN_SHIFT                                   22
 597 #define OMAP4460_DCC_EN_MASK                                    (1 << 22)
 598
 599 /*
 600  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
 601  * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
 602  * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
 603  * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
 604  * CM_SSC_DELTAMSTEP_DPLL_USB
 605  */
 606 #define OMAP4430_DELTAMSTEP_SHIFT                               0
 607 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 608
 609 /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
 610 #define OMAP4460_DELTAMSTEP_0_20_SHIFT                          0
 611 #define OMAP4460_DELTAMSTEP_0_20_MASK                           (0x1fffff << 0)
 612
 613 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 614 #define OMAP4430_DLL_OVERRIDE_SHIFT                             2
 615 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 2)
 616
 617 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
 618 #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
 619 #define OMAP4430_DLL_OVERRIDE_0_0_MASK                          (1 << 0)
 620
 621 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 622 #define OMAP4430_DLL_RESET_SHIFT                                3
 623 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 624
 625 /*
 626  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 627  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 628  * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
 629  * CM_CLKSEL_DPLL_USB
 630  */
 631 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
 632 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 633
 634 /* Used by CM_CLKDCOLDO_DPLL_USB */
 635 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
 636 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 637
 638 /* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
 639 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
 640 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 641
 642 /*
 643  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 644  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 645  */
 646 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
 647 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 648
 649 /*
 650  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 651  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 652  */
 653 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
 654 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 655
 656 /*
 657  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 658  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 659  */
 660 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
 661 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 662
 663 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 664 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
 665 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 666
 667 /*
 668  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 669  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 670  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 671  */
 672 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
 673 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 674
 675 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 676 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
 677 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 678
 679 /*
 680  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 681  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 682  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 683  */
 684 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
 685 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 686
 687 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 688 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
 689 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 690
 691 /*
 692  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 693  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 694  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 695  */
 696 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
 697 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 698
 699 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 700 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
 701 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 702
 703 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 704 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
 705 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 706
 707 /* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 708 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
 709 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 710
 711 /*
 712  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 713  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 714  * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
 715  */
 716 #define OMAP4430_DPLL_DIV_SHIFT                                 0
 717 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 718
 719 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 720 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
 721 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 722
 723 /*
 724  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 725  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 726  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 727  */
 728 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
 729 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 730
 731 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 732 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
 733 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 734
 735 /*
 736  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 737  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 738  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 739  * CM_CLKMODE_DPLL_USB
 740  */
 741 #define OMAP4430_DPLL_EN_SHIFT                                  0
 742 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 743
 744 /*
 745  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 746  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 747  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
 748  */
 749 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
 750 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 751
 752 /*
 753  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 754  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 755  * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
 756  */
 757 #define OMAP4430_DPLL_MULT_SHIFT                                8
 758 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 759
 760 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 761 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
 762 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 763
 764 /*
 765  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 766  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 767  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
 768  */
 769 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
 770 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 771
 772 /* Used by CM_CLKSEL_DPLL_USB */
 773 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
 774 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 775
 776 /*
 777  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 778  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 779  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 780  * CM_CLKMODE_DPLL_USB
 781  */
 782 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
 783 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 784
 785 /*
 786  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 787  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 788  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 789  * CM_CLKMODE_DPLL_USB
 790  */
 791 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
 792 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 793
 794 /*
 795  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 796  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 797  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 798  * CM_CLKMODE_DPLL_USB
 799  */
 800 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
 801 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 802
 803 /*
 804  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 805  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
 806  */
 807 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
 808 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 809
 810 /*
 811  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 812  * CM_SDMA_STATICDEP_RESTORE
 813  */
 814 #define OMAP4430_DSS_STATDEP_SHIFT                              8
 815 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 816
 817 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 818 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
 819 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 820
 821 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
 822 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
 823 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 824
 825 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 826 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
 827 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 828
 829 /* Used by REVISION_CM1, REVISION_CM2 */
 830 #define OMAP4430_FUNC_SHIFT                                     16
 831 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 832
 833 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 834 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
 835 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 836
 837 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 838 #define OMAP4430_GFX_STATDEP_SHIFT                              10
 839 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 840
 841 /* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 842 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
 843 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 844
 845 /*
 846  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 847  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 848  */
 849 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
 850 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 851
 852 /*
 853  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 854  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 855  */
 856 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
 857 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 858
 859 /*
 860  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 861  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 862  */
 863 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
 864 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 865
 866 /*
 867  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 868  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 869  */
 870 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
 871 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 872
 873 /*
 874  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 875  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 876  */
 877 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
 878 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 879
 880 /*
 881  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 882  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 883  */
 884 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
 885 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 886
 887 /*
 888  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 889  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 890  */
 891 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
 892 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 893
 894 /*
 895  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 896  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 897  */
 898 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
 899 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 900
 901 /*
 902  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 903  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 904  */
 905 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
 906 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 907
 908 /*
 909  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 910  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 911  */
 912 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
 913 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 914
 915 /*
 916  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 917  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 918  */
 919 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
 920 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 921
 922 /*
 923  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 924  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 925  */
 926 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
 927 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 928
 929 /*
 930  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 931  * CM_DIV_M7_DPLL_PER
 932  */
 933 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
 934 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 935
 936 /*
 937  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 938  * CM_DIV_M7_DPLL_PER
 939  */
 940 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
 941 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 942
 943 /*
 944  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 945  * CM_DIV_M7_DPLL_PER
 946  */
 947 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
 948 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 949
 950 /*
 951  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 952  * CM_DIV_M7_DPLL_PER
 953  */
 954 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
 955 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 956
 957 /*
 958  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
 959  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 960  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 961  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
 962  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
 963  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
 964  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
 965  * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
 966  * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
 967  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
 968  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 969  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
 970  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
 971  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
 972  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
 973  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
 974  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
 975  * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 976  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
 977  * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
 978  * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
 979  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
 980  * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
 981  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
 982  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
 983  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
 984  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 985  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 986  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 987  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
 988  * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
 989  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
 990  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
 991  * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
 992  * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
 993  * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
 994  * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
 995  * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
 996  * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
 997  * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
 998  * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
 999  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1000  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1001  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1002  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1003  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1004  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
1005  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1006  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1007  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
1008  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
1009  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1010  */
1011 #define OMAP4430_IDLEST_SHIFT                                   16
1012 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
1013
1014 /*
1015  * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1016  * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
1017  */
1018 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
1019 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
1020
1021 /*
1022  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1023  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1024  */
1025 #define OMAP4430_ISS_STATDEP_SHIFT                              9
1026 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
1027
1028 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
1029 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
1030 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
1031
1032 /*
1033  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1034  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
1035  * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1036  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1037  */
1038 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
1039 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
1040
1041 /*
1042  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1043  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1044  */
1045 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
1046 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
1047
1048 /*
1049  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1050  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
1051  * CM_TESLA_STATICDEP
1052  */
1053 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
1054 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
1055
1056 /*
1057  * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1058  * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1059  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1060  */
1061 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
1062 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
1063
1064 /*
1065  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1066  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1067  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1068  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1069  */
1070 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
1071 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
1072
1073 /*
1074  * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
1075  * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
1076  * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
1077  * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1078  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1079  */
1080 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
1081 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
1082
1083 /*
1084  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1085  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1086  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1087  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1088  */
1089 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
1090 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
1091
1092 /* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
1093 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
1094 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
1095
1096 /*
1097  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1098  * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1099  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1100  */
1101 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
1102 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
1103
1104 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
1105 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
1106 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
1107
1108 /*
1109  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1110  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1111  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1112  */
1113 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
1114 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
1115
1116 /*
1117  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1118  * CM_L4PER_DYNAMICDEP_RESTORE
1119  */
1120 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
1121 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
1122
1123 /*
1124  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1125  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
1126  */
1127 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
1128 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
1129
1130 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1131 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
1132 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
1133
1134 /*
1135  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1136  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1137  */
1138 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
1139 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
1140
1141 /*
1142  * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
1143  * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1144  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1145  */
1146 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
1147 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
1148
1149 /*
1150  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1151  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1152  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1153  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1154  */
1155 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
1156 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
1157
1158 /*
1159  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1160  * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
1161  * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1162  * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
1163  * CM_SSC_MODFREQDIV_DPLL_USB
1164  */
1165 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
1166 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
1167
1168 /*
1169  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1170  * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
1171  * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1172  * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
1173  * CM_SSC_MODFREQDIV_DPLL_USB
1174  */
1175 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
1176 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
1177
1178 /*
1179  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
1180  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1181  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1182  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1183  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1184  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1185  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1186  * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
1187  * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1188  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1189  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1190  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1191  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1192  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1193  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1194  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1195  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1196  * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1197  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
1198  * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
1199  * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1200  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1201  * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1202  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1203  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1204  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1205  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1206  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1207  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1208  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
1209  * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
1210  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
1211  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1212  * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
1213  * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
1214  * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
1215  * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
1216  * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
1217  * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1218  * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1219  * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1220  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1221  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1222  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1223  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1224  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1225  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
1226  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1227  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1228  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
1229  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
1230  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1231  */
1232 #define OMAP4430_MODULEMODE_SHIFT                               0
1233 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
1234
1235 /* Used by CM_L4CFG_DYNAMICDEP */
1236 #define OMAP4460_MPU_DYNDEP_SHIFT                               19
1237 #define OMAP4460_MPU_DYNDEP_MASK                                (1 << 19)
1238
1239 /* Used by CM_DSS_DSS_CLKCTRL */
1240 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
1241 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
1242
1243 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
1244 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
1245 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
1246
1247 /* Used by CM_ALWON_USBPHY_CLKCTRL */
1248 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
1249 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
1250
1251 /* Used by CM_CAM_ISS_CLKCTRL */
1252 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
1253 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
1254
1255 /*
1256  * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
1257  * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
1258  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
1259  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1260  * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1261  */
1262 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
1263 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
1264
1265 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
1266 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
1267 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
1268
1269 /* Used by CM_DSS_DSS_CLKCTRL */
1270 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
1271 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
1272
1273 /* Used by CM_WKUP_USIM_CLKCTRL */
1274 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
1275 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
1276
1277 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1278 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
1279 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
1280
1281 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1282 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
1283 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
1284
1285 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1286 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
1287 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
1288
1289 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1290 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
1291 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
1292
1293 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1294 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
1295 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
1296
1297 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1298 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
1299 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
1300
1301 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1302 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
1303 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
1304
1305 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1306 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
1307 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
1308
1309 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1310 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
1311 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
1312
1313 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1314 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
1315 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
1316
1317 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
1318 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
1319 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
1320
1321 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1322 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
1323 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
1324
1325 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
1326 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
1327 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
1328
1329 /* Used by CM_DSS_DSS_CLKCTRL */
1330 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
1331 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
1332
1333 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
1334 #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                        8
1335 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                         (1 << 8)
1336
1337 /* Used by CM_DSS_DSS_CLKCTRL */
1338 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
1339 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
1340
1341 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
1342 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
1343 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
1344
1345 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1346 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
1347 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
1348
1349 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1350 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
1351 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
1352
1353 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1354 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
1355 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
1356
1357 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1358 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
1359 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
1360
1361 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1362 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
1363 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
1364
1365 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1366 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
1367 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
1368
1369 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
1370 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
1371 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
1372
1373 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
1374 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
1375 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
1376
1377 /* Used by CM_CLKSEL_ABE */
1378 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
1379 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
1380
1381 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
1382 #define OMAP4430_PERF_CURRENT_SHIFT                             0
1383 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
1384
1385 /*
1386  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
1387  * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
1388  * CM_IVA_DVFS_PERF_TESLA
1389  */
1390 #define OMAP4430_PERF_REQ_SHIFT                                 0
1391 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
1392
1393 /* Used by CM_RESTORE_ST */
1394 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
1395 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
1396
1397 /* Used by CM_RESTORE_ST */
1398 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
1399 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
1400
1401 /* Used by CM_RESTORE_ST */
1402 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
1403 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
1404
1405 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
1406 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
1407 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
1408
1409 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
1410 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
1411 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
1412
1413 /* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
1414 #define OMAP4430_PRESCAL_SHIFT                                  0
1415 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
1416
1417 /* Used by REVISION_CM1, REVISION_CM2 */
1418 #define OMAP4430_R_RTL_SHIFT                                    11
1419 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
1420
1421 /*
1422  * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1423  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1424  */
1425 #define OMAP4430_SAR_MODE_SHIFT                                 4
1426 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
1427
1428 /* Used by CM_SCALE_FCLK */
1429 #define OMAP4430_SCALE_FCLK_SHIFT                               0
1430 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
1431
1432 /* Used by REVISION_CM1, REVISION_CM2 */
1433 #define OMAP4430_SCHEME_SHIFT                                   30
1434 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
1435
1436 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1437 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
1438 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
1439
1440 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1441 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
1442 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
1443
1444 /* Used by CM_CLKSEL_ABE */
1445 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
1446 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
1447
1448 /*
1449  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
1450  * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1451  * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
1452  * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1453  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1454  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1455  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1456  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1457  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1458  * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1459  * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
1460  */
1461 #define OMAP4430_STBYST_SHIFT                                   18
1462 #define OMAP4430_STBYST_MASK                                    (1 << 18)
1463
1464 /*
1465  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1466  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1467  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1468  */
1469 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
1470 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
1471
1472 /* Used by CM_CLKDCOLDO_DPLL_USB */
1473 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
1474 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
1475
1476 /*
1477  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
1478  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
1479  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1480  */
1481 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
1482 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
1483
1484 /*
1485  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1486  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1487  */
1488 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
1489 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
1490
1491 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
1492 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
1493 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
1494
1495 /*
1496  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
1497  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
1498  */
1499 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
1500 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
1501
1502 /*
1503  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
1504  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
1505  */
1506 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
1507 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
1508
1509 /*
1510  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1511  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1512  */
1513 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
1514 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
1515
1516 /*
1517  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1518  * CM_DIV_M7_DPLL_PER
1519  */
1520 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
1521 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
1522
1523 /*
1524  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1525  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1526  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1527  */
1528 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
1529 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
1530
1531 /* Used by CM_SYS_CLKSEL */
1532 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
1533 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
1534
1535 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1536 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
1537 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
1538
1539 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1540 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
1541 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
1542
1543 /*
1544  * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
1545  * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
1546  * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1547  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1548  * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1549  */
1550 #define OMAP4430_WINDOWSIZE_SHIFT                               24
1551 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
1552
1553 /* Used by REVISION_CM1, REVISION_CM2 */
1554 #define OMAP4430_X_MAJOR_SHIFT                                  8
1555 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
1556
1557 /* Used by REVISION_CM1, REVISION_CM2 */
1558 #define OMAP4430_Y_MINOR_SHIFT                                  0
1559 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
1560 #endif