arch/arm/mach-omap2/cm-regbits-44xx.h

   1 /*
   2  * OMAP44xx Clock Management register bits
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  23 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  24
  25 /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
  26 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
  27 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
  28
  29 /*
  30  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
  31  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  32  */
  33 #define OMAP4430_ABE_STATDEP_SHIFT                              3
  34 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
  35
  36 /* Used by CM_L4CFG_DYNAMICDEP */
  37 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
  38 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
  39
  40 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
  41 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
  42 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
  43
  44 /*
  45  * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
  46  * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
  47  * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  48  */
  49 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
  50 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
  51
  52 /* Used by CM_L4CFG_DYNAMICDEP */
  53 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
  54 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
  55
  56 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
  57 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
  58 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
  59
  60 /* Used by CM1_ABE_CLKSTCTRL */
  61 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
  62 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
  63
  64 /* Used by CM1_ABE_CLKSTCTRL */
  65 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
  66 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
  67
  68 /* Used by CM_WKUP_CLKSTCTRL */
  69 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
  70 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
  71
  72 /* Used by CM1_ABE_CLKSTCTRL */
  73 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
  74 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
  75
  76 /* Used by CM1_ABE_CLKSTCTRL */
  77 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
  78 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
  79
  80 /* Used by CM_MEMIF_CLKSTCTRL */
  81 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
  82 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
  83
  84 /* Used by CM_MEMIF_CLKSTCTRL */
  85 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
  86 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
  87
  88 /* Used by CM_MEMIF_CLKSTCTRL */
  89 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
  90 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
  91
  92 /* Used by CM_CAM_CLKSTCTRL */
  93 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
  94 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
  95
  96 /* Used by CM_ALWON_CLKSTCTRL */
  97 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
  98 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
  99
 100 /* Used by CM_EMU_CLKSTCTRL */
 101 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
 102 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 103
 104 /* Used by CM_CEFUSE_CLKSTCTRL */
 105 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
 106 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 107
 108 /* Used by CM_MEMIF_CLKSTCTRL */
 109 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
 110 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 111
 112 /* Used by CM_L4PER_CLKSTCTRL */
 113 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
 114 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 115
 116 /* Used by CM_L4PER_CLKSTCTRL */
 117 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
 118 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 119
 120 /* Used by CM_L4PER_CLKSTCTRL */
 121 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
 122 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 123
 124 /* Used by CM_L4PER_CLKSTCTRL */
 125 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
 126 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 127
 128 /* Used by CM_L4PER_CLKSTCTRL */
 129 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
 130 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 131
 132 /* Used by CM_L4PER_CLKSTCTRL */
 133 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
 134 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 135
 136 /* Used by CM_DSS_CLKSTCTRL */
 137 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
 138 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 139
 140 /* Used by CM_DSS_CLKSTCTRL */
 141 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
 142 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 143
 144 /* Used by CM_DUCATI_CLKSTCTRL */
 145 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
 146 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 147
 148 /* Used by CM_EMU_CLKSTCTRL */
 149 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
 150 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 151
 152 /* Used by CM_CAM_CLKSTCTRL */
 153 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
 154 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 155
 156 /* Used by CM_L4PER_CLKSTCTRL */
 157 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
 158 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 159
 160 /* Used by CM1_ABE_CLKSTCTRL */
 161 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
 162 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 163
 164 /* Used by CM_DSS_CLKSTCTRL */
 165 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
 166 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 167
 168 /* Used by CM_L3INIT_CLKSTCTRL */
 169 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
 170 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 171
 172 /* Used by CM_L3INIT_CLKSTCTRL */
 173 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
 174 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 175
 176 /* Used by CM_L3INIT_CLKSTCTRL */
 177 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
 178 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 179
 180 /* Used by CM_L3INIT_CLKSTCTRL */
 181 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
 182 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 183
 184 /* Used by CM_L3INIT_CLKSTCTRL */
 185 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
 186 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 187
 188 /* Used by CM_L3INIT_CLKSTCTRL */
 189 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
 190 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 191
 192 /* Used by CM_L3INIT_CLKSTCTRL */
 193 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
 194 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 195
 196 /* Used by CM_L3INIT_CLKSTCTRL */
 197 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
 198 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 199
 200 /* Used by CM_L3INIT_CLKSTCTRL */
 201 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
 202 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 203
 204 /* Used by CM_L3INIT_CLKSTCTRL */
 205 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
 206 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 207
 208 /* Used by CM_L3INIT_CLKSTCTRL */
 209 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
 210 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 211
 212 /* Used by CM_L3INIT_CLKSTCTRL */
 213 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
 214 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 215
 216 /* Used by CM_L3INIT_CLKSTCTRL */
 217 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
 218 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 219
 220 /* Used by CM_CAM_CLKSTCTRL */
 221 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
 222 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 223
 224 /* Used by CM_IVAHD_CLKSTCTRL */
 225 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
 226 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 227
 228 /* Used by CM_D2D_CLKSTCTRL */
 229 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
 230 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 231
 232 /* Used by CM_L3_1_CLKSTCTRL */
 233 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
 234 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 235
 236 /* Used by CM_L3_2_CLKSTCTRL */
 237 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
 238 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 239
 240 /* Used by CM_D2D_CLKSTCTRL */
 241 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
 242 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 243
 244 /* Used by CM_SDMA_CLKSTCTRL */
 245 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
 246 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 247
 248 /* Used by CM_DSS_CLKSTCTRL */
 249 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
 250 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 251
 252 /* Used by CM_MEMIF_CLKSTCTRL */
 253 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
 254 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 255
 256 /* Used by CM_GFX_CLKSTCTRL */
 257 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
 258 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 259
 260 /* Used by CM_L3INIT_CLKSTCTRL */
 261 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
 262 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 263
 264 /* Used by CM_L3INSTR_CLKSTCTRL */
 265 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
 266 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 267
 268 /* Used by CM_L4SEC_CLKSTCTRL */
 269 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
 270 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 271
 272 /* Used by CM_ALWON_CLKSTCTRL */
 273 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
 274 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 275
 276 /* Used by CM_CEFUSE_CLKSTCTRL */
 277 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
 278 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 279
 280 /* Used by CM_L4CFG_CLKSTCTRL */
 281 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
 282 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 283
 284 /* Used by CM_D2D_CLKSTCTRL */
 285 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
 286 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 287
 288 /* Used by CM_L3INIT_CLKSTCTRL */
 289 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
 290 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 291
 292 /* Used by CM_L4PER_CLKSTCTRL */
 293 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
 294 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 295
 296 /* Used by CM_L4SEC_CLKSTCTRL */
 297 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
 298 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 299
 300 /* Used by CM_WKUP_CLKSTCTRL */
 301 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
 302 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 303
 304 /* Used by CM_MPU_CLKSTCTRL */
 305 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
 306 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 307
 308 /* Used by CM1_ABE_CLKSTCTRL */
 309 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
 310 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 311
 312 /* Used by CM_L4PER_CLKSTCTRL */
 313 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
 314 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 315
 316 /* Used by CM_L4PER_CLKSTCTRL */
 317 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
 318 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 319
 320 /* Used by CM_L4PER_CLKSTCTRL */
 321 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
 322 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 323
 324 /* Used by CM_L4PER_CLKSTCTRL */
 325 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
 326 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 327
 328 /* Used by CM_L4PER_CLKSTCTRL */
 329 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
 330 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 331
 332 /* Used by CM_L4PER_CLKSTCTRL */
 333 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
 334 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 335
 336 /* Used by CM_L4PER_CLKSTCTRL */
 337 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
 338 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 339
 340 /* Used by CM_L4PER_CLKSTCTRL */
 341 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
 342 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 343
 344 /* Used by CM_L4PER_CLKSTCTRL */
 345 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
 346 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 347
 348 /* Used by CM_MEMIF_CLKSTCTRL */
 349 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
 350 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 351
 352 /* Used by CM_GFX_CLKSTCTRL */
 353 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
 354 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 355
 356 /* Used by CM_ALWON_CLKSTCTRL */
 357 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
 358 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 359
 360 /* Used by CM_ALWON_CLKSTCTRL */
 361 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
 362 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 363
 364 /* Used by CM_ALWON_CLKSTCTRL */
 365 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
 366 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 367
 368 /* Used by CM_WKUP_CLKSTCTRL */
 369 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
 370 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 371
 372 /* Used by CM_TESLA_CLKSTCTRL */
 373 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
 374 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 375
 376 /* Used by CM_L3INIT_CLKSTCTRL */
 377 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
 378 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 379
 380 /* Used by CM_L3INIT_CLKSTCTRL */
 381 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
 382 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 383
 384 /* Used by CM_L3INIT_CLKSTCTRL */
 385 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
 386 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 387
 388 /* Used by CM_L3INIT_CLKSTCTRL */
 389 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
 390 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 391
 392 /* Used by CM_L3INIT_CLKSTCTRL */
 393 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
 394 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 395
 396 /* Used by CM_L3INIT_CLKSTCTRL */
 397 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
 398 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 399
 400 /* Used by CM_WKUP_CLKSTCTRL */
 401 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
 402 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 403
 404 /* Used by CM_L3INIT_CLKSTCTRL */
 405 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
 406 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 407
 408 /* Used by CM_L3INIT_CLKSTCTRL */
 409 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
 410 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 411
 412 /* Used by CM_WKUP_CLKSTCTRL */
 413 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
 414 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 415
 416 /*
 417  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
 418  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
 419  * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
 420  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
 421  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
 422  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
 423  * CM_WKUP_TIMER1_CLKCTRL
 424  */
 425 #define OMAP4430_CLKSEL_SHIFT                                   24
 426 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 427
 428 /*
 429  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
 430  * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
 431  */
 432 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
 433 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 434
 435 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 436 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
 437 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 438
 439 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 440 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
 441 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 442
 443 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 444 #define OMAP4430_CLKSEL_60M_SHIFT                               24
 445 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 446
 447 /* Used by CM1_ABE_AESS_CLKCTRL */
 448 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
 449 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 450
 451 /* Used by CM_CLKSEL_CORE */
 452 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
 453 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 454
 455 /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
 456 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
 457 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 458
 459 /* Used by CM_WKUP_USIM_CLKCTRL */
 460 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
 461 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 462
 463 /* Used by CM_CAM_FDIF_CLKCTRL */
 464 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
 465 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 466
 467 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 468 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
 469 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 470
 471 /*
 472  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
 473  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 474  * CM1_ABE_MCBSP3_CLKCTRL
 475  */
 476 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
 477 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 478
 479 /* Used by CM_CLKSEL_CORE */
 480 #define OMAP4430_CLKSEL_L3_SHIFT                                4
 481 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 482
 483 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
 484 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
 485 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 486
 487 /* Used by CM_CLKSEL_CORE */
 488 #define OMAP4430_CLKSEL_L4_SHIFT                                8
 489 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 490
 491 /* Used by CM_CLKSEL_ABE */
 492 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
 493 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 494
 495 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 496 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
 497 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 498
 499 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 500 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
 501 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 502
 503 /* Used by CM_GFX_GFX_CLKCTRL */
 504 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
 505 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 506
 507 /*
 508  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
 509  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
 510  */
 511 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
 512 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 513
 514 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 515 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
 516 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 517
 518 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 519 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
 520 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 521
 522 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 523 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
 524 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 525
 526 /*
 527  * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
 528  * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
 529  * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
 530  * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
 531  * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
 532  * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
 533  * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
 534  */
 535 #define OMAP4430_CLKTRCTRL_SHIFT                                0
 536 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 537
 538 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 539 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
 540 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 541
 542 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 543 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
 544 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 545
 546 /* Used by REVISION_CM1, REVISION_CM2 */
 547 #define OMAP4430_CUSTOM_SHIFT                                   6
 548 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 549
 550 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 551 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
 552 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 553
 554 /* Used by CM_MPU_STATICDEP */
 555 #define OMAP4430_D2D_STATDEP_SHIFT                              18
 556 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 557
 558 /*
 559  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
 560  * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
 561  * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
 562  * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
 563  */
 564 #define OMAP4430_DELTAMSTEP_SHIFT                               0
 565 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 566
 567 /* Used by CM_DLL_CTRL */
 568 #define OMAP4430_DLL_OVERRIDE_SHIFT                             0
 569 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
 570
 571 /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
 572 #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
 573 #define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
 574
 575 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 576 #define OMAP4430_DLL_RESET_SHIFT                                3
 577 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 578
 579 /*
 580  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 581  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 582  * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
 583  */
 584 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
 585 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 586
 587 /* Used by CM_CLKDCOLDO_DPLL_USB */
 588 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
 589 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 590
 591 /* Used by CM_CLKSEL_DPLL_CORE */
 592 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
 593 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 594
 595 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 596 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
 597 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 598
 599 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 600 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
 601 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 602
 603 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 604 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
 605 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 606
 607 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 608 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
 609 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 610
 611 /*
 612  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 613  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 614  */
 615 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
 616 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 617
 618 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 619 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
 620 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 621
 622 /*
 623  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 624  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 625  */
 626 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
 627 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 628
 629 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 630 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
 631 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 632
 633 /*
 634  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
 635  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 636  */
 637 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
 638 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 639
 640 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 641 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
 642 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 643
 644 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 645 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
 646 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 647
 648 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 649 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
 650 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 651
 652 /*
 653  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 654  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 655  * CM_CLKSEL_DPLL_UNIPRO
 656  */
 657 #define OMAP4430_DPLL_DIV_SHIFT                                 0
 658 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 659
 660 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 661 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
 662 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 663
 664 /*
 665  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 666  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 667  */
 668 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
 669 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 670
 671 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 672 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
 673 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 674
 675 /*
 676  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 677  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 678  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 679  */
 680 #define OMAP4430_DPLL_EN_SHIFT                                  0
 681 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 682
 683 /*
 684  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 685  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 686  * CM_CLKMODE_DPLL_UNIPRO
 687  */
 688 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
 689 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 690
 691 /*
 692  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
 693  * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
 694  * CM_CLKSEL_DPLL_UNIPRO
 695  */
 696 #define OMAP4430_DPLL_MULT_SHIFT                                8
 697 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 698
 699 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 700 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
 701 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 702
 703 /*
 704  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 705  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 706  * CM_CLKMODE_DPLL_UNIPRO
 707  */
 708 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
 709 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 710
 711 /* Used by CM_CLKSEL_DPLL_USB */
 712 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
 713 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 714
 715 /*
 716  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 717  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 718  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 719  */
 720 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
 721 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 722
 723 /*
 724  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 725  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 726  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 727  */
 728 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
 729 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 730
 731 /*
 732  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
 733  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
 734  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
 735  */
 736 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
 737 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 738
 739 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 740 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
 741 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 742
 743 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 744 #define OMAP4430_DSS_STATDEP_SHIFT                              8
 745 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 746
 747 /* Used by CM_L3_2_DYNAMICDEP */
 748 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
 749 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 750
 751 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 752 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
 753 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 754
 755 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 756 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
 757 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 758
 759 /* Used by REVISION_CM1, REVISION_CM2 */
 760 #define OMAP4430_FUNC_SHIFT                                     16
 761 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 762
 763 /* Used by CM_L3_2_DYNAMICDEP */
 764 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
 765 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 766
 767 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 768 #define OMAP4430_GFX_STATDEP_SHIFT                              10
 769 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 770
 771 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 772 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
 773 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 774
 775 /*
 776  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 777  * CM_DIV_M4_DPLL_PER
 778  */
 779 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
 780 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 781
 782 /*
 783  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 784  * CM_DIV_M4_DPLL_PER
 785  */
 786 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
 787 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 788
 789 /*
 790  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 791  * CM_DIV_M4_DPLL_PER
 792  */
 793 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
 794 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 795
 796 /*
 797  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
 798  * CM_DIV_M4_DPLL_PER
 799  */
 800 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
 801 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 802
 803 /*
 804  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 805  * CM_DIV_M5_DPLL_PER
 806  */
 807 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
 808 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 809
 810 /*
 811  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 812  * CM_DIV_M5_DPLL_PER
 813  */
 814 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
 815 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 816
 817 /*
 818  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 819  * CM_DIV_M5_DPLL_PER
 820  */
 821 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
 822 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 823
 824 /*
 825  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
 826  * CM_DIV_M5_DPLL_PER
 827  */
 828 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
 829 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 830
 831 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 832 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
 833 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 834
 835 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 836 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
 837 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 838
 839 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 840 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
 841 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 842
 843 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 844 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
 845 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 846
 847 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 848 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
 849 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 850
 851 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 852 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
 853 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 854
 855 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 856 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
 857 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 858
 859 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 860 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
 861 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 862
 863 /*
 864  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
 865  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 866  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 867  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
 868  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
 869  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
 870  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
 871  * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
 872  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
 873  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 874  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
 875  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
 876  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
 877  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
 878  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
 879  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
 880  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
 881  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
 882  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
 883  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
 884  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
 885  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
 886  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 887  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 888  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 889  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
 890  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
 891  * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
 892  * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
 893  * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
 894  * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
 895  * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
 896  * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
 897  * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
 898  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
 899  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
 900  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
 901  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
 902  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
 903  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
 904  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 905  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
 906  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
 907  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
 908  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
 909  */
 910 #define OMAP4430_IDLEST_SHIFT                                   16
 911 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 912
 913 /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 914 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
 915 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 916
 917 /*
 918  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 919  * CM_TESLA_STATICDEP
 920  */
 921 #define OMAP4430_ISS_STATDEP_SHIFT                              9
 922 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 923
 924 /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 925 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
 926 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 927
 928 /*
 929  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 930  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
 931  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 932  */
 933 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
 934 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 935
 936 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 937 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
 938 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 939
 940 /*
 941  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
 942  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 943  */
 944 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
 945 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 946
 947 /*
 948  * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
 949  * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
 950  */
 951 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
 952 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 953
 954 /*
 955  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 956  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 957  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 958  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 959  */
 960 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
 961 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 962
 963 /*
 964  * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
 965  * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
 966  * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
 967  * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
 968  */
 969 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
 970 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 971
 972 /*
 973  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
 974  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
 975  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
 976  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 977  */
 978 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
 979 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 980
 981 /* Used by CM_L3_1_DYNAMICDEP */
 982 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
 983 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 984
 985 /*
 986  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 987  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 988  */
 989 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
 990 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 991
 992 /* Used by CM_L3_2_DYNAMICDEP */
 993 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
 994 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 995
 996 /*
 997  * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
 998  * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
 999  */
1000 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
1001 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
1002
1003 /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1004 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
1005 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
1006
1007 /*
1008  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1009  * CM_SDMA_STATICDEP
1010  */
1011 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
1012 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
1013
1014 /* Used by CM_L4CFG_DYNAMICDEP */
1015 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
1016 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
1017
1018 /*
1019  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1020  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1021  */
1022 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
1023 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
1024
1025 /*
1026  * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1027  * CM_MPU_DYNAMICDEP
1028  */
1029 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
1030 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
1031
1032 /*
1033  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1034  * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1035  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1036  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1037  */
1038 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
1039 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
1040
1041 /*
1042  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1043  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1044  * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1045  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1046  */
1047 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
1048 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
1049
1050 /*
1051  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1052  * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1053  * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1054  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1055  */
1056 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
1057 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
1058
1059 /*
1060  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
1061  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1062  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1063  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1064  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1065  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1066  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1067  * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
1068  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1069  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1070  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1071  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1072  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1073  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1074  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1075  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1076  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1077  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
1078  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
1079  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1080  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1081  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1082  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1083  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1084  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1085  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1086  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1087  * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
1088  * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
1089  * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
1090  * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
1091  * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
1092  * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
1093  * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1094  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1095  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1096  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1097  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1098  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1099  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
1100  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1101  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1102  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
1103  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
1104  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1105  */
1106 #define OMAP4430_MODULEMODE_SHIFT                               0
1107 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
1108
1109 /* Used by CM_DSS_DSS_CLKCTRL */
1110 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
1111 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
1112
1113 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
1114 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
1115 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
1116
1117 /* Used by CM_ALWON_USBPHY_CLKCTRL */
1118 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
1119 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
1120
1121 /* Used by CM_CAM_ISS_CLKCTRL */
1122 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
1123 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
1124
1125 /*
1126  * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1127  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1128  * CM_WKUP_GPIO1_CLKCTRL
1129  */
1130 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
1131 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
1132
1133 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
1134 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
1135 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
1136
1137 /* Used by CM_DSS_DSS_CLKCTRL */
1138 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
1139 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
1140
1141 /* Used by CM_WKUP_USIM_CLKCTRL */
1142 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
1143 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
1144
1145 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1146 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
1147 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
1148
1149 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1150 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
1151 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
1152
1153 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1154 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
1155 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
1156
1157 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1158 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
1159 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
1160
1161 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1162 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
1163 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
1164
1165 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1166 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
1167 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
1168
1169 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1170 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
1171 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
1172
1173 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1174 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
1175 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
1176
1177 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1178 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
1179 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
1180
1181 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1182 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
1183 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
1184
1185 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
1186 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
1187 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
1188
1189 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1190 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
1191 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
1192
1193 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
1194 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
1195 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
1196
1197 /* Used by CM_DSS_DSS_CLKCTRL */
1198 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
1199 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
1200
1201 /* Used by CM_DSS_DSS_CLKCTRL */
1202 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
1203 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
1204
1205 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
1206 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
1207 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
1208
1209 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1210 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
1211 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
1212
1213 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1214 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
1215 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
1216
1217 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1218 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
1219 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
1220
1221 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1222 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
1223 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
1224
1225 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1226 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
1227 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
1228
1229 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1230 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
1231 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
1232
1233 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
1234 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
1235 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
1236
1237 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
1238 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
1239 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
1240
1241 /* Used by CM_CLKSEL_ABE */
1242 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
1243 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
1244
1245 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
1246 #define OMAP4430_PERF_CURRENT_SHIFT                             0
1247 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
1248
1249 /*
1250  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
1251  * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
1252  * CM_IVA_DVFS_PERF_TESLA
1253  */
1254 #define OMAP4430_PERF_REQ_SHIFT                                 0
1255 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
1256
1257 /* Used by CM_RESTORE_ST */
1258 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
1259 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
1260
1261 /* Used by CM_RESTORE_ST */
1262 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
1263 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
1264
1265 /* Used by CM_RESTORE_ST */
1266 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
1267 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
1268
1269 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
1270 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
1271 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
1272
1273 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
1274 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
1275 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
1276
1277 /* Used by CM_DYN_DEP_PRESCAL */
1278 #define OMAP4430_PRESCAL_SHIFT                                  0
1279 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
1280
1281 /* Used by REVISION_CM1, REVISION_CM2 */
1282 #define OMAP4430_R_RTL_SHIFT                                    11
1283 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
1284
1285 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1286 #define OMAP4430_SAR_MODE_SHIFT                                 4
1287 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
1288
1289 /* Used by CM_SCALE_FCLK */
1290 #define OMAP4430_SCALE_FCLK_SHIFT                               0
1291 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
1292
1293 /* Used by REVISION_CM1, REVISION_CM2 */
1294 #define OMAP4430_SCHEME_SHIFT                                   30
1295 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
1296
1297 /* Used by CM_L4CFG_DYNAMICDEP */
1298 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
1299 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
1300
1301 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1302 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
1303 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
1304
1305 /* Used by CM_CLKSEL_ABE */
1306 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
1307 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
1308
1309 /*
1310  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
1311  * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1312  * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
1313  * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1314  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1315  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1316  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1317  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1318  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
1319  * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1320  * CM_TESLA_TESLA_CLKCTRL
1321  */
1322 #define OMAP4430_STBYST_SHIFT                                   18
1323 #define OMAP4430_STBYST_MASK                                    (1 << 18)
1324
1325 /*
1326  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1327  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1328  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1329  */
1330 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
1331 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
1332
1333 /* Used by CM_CLKDCOLDO_DPLL_USB */
1334 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
1335 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
1336
1337 /*
1338  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
1339  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1340  */
1341 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
1342 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
1343
1344 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1345 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
1346 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
1347
1348 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
1349 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
1350 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
1351
1352 /*
1353  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
1354  * CM_DIV_M4_DPLL_PER
1355  */
1356 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
1357 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
1358
1359 /*
1360  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1361  * CM_DIV_M5_DPLL_PER
1362  */
1363 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
1364 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
1365
1366 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1367 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
1368 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
1369
1370 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1371 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
1372 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
1373
1374 /*
1375  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1376  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1377  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1378  */
1379 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
1380 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
1381
1382 /* Used by CM_SYS_CLKSEL */
1383 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
1384 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
1385
1386 /* Used by CM_L4CFG_DYNAMICDEP */
1387 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
1388 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
1389
1390 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1391 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
1392 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
1393
1394 /*
1395  * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1396  * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1397  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1398  */
1399 #define OMAP4430_WINDOWSIZE_SHIFT                               24
1400 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
1401
1402 /* Used by REVISION_CM1, REVISION_CM2 */
1403 #define OMAP4430_X_MAJOR_SHIFT                                  8
1404 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
1405
1406 /* Used by REVISION_CM1, REVISION_CM2 */
1407 #define OMAP4430_Y_MINOR_SHIFT                                  0
1408 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
1409 #endif