arch/arm/mach-omap2/cm-regbits-44xx.h

   1 /*
   2  * OMAP44xx Clock Management register bits
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  23 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
  24
  25 #include "cm.h"
  26
  27
  28 /*
  29  * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
  30  * CM_TESLA_DYNAMICDEP
  31  */
  32 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
  33 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
  34
  35 /*
  36  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
  37  * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
  38  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  39  */
  40 #define OMAP4430_ABE_STATDEP_SHIFT                              3
  41 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
  42
  43 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
  44 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
  45 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
  46
  47 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
  48 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
  49 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
  50
  51 /*
  52  * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
  53  * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
  54  * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
  55  * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  56  */
  57 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
  58 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
  59
  60 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
  61 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
  62 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
  63
  64 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
  65 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
  66 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
  67
  68 /* Used by CM1_ABE_CLKSTCTRL */
  69 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
  70 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
  71
  72 /* Used by CM1_ABE_CLKSTCTRL */
  73 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
  74 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
  75
  76 /* Used by CM_WKUP_CLKSTCTRL */
  77 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
  78 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
  79
  80 /* Used by CM1_ABE_CLKSTCTRL */
  81 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
  82 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
  83
  84 /* Used by CM1_ABE_CLKSTCTRL */
  85 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
  86 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
  87
  88 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
  89 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
  90 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
  91
  92 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
  93 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
  94 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
  95
  96 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
  97 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
  98 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
  99
 100 /* Used by CM_CAM_CLKSTCTRL */
 101 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
 102 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
 103
 104 /* Used by CM_ALWON_CLKSTCTRL */
 105 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
 106 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 107
 108 /* Used by CM_EMU_CLKSTCTRL */
 109 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
 110 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 111
 112 /* Used by CM_CEFUSE_CLKSTCTRL */
 113 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
 114 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 115
 116 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 117 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
 118 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 119
 120 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 121 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
 122 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 123
 124 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 125 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
 126 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 127
 128 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 129 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
 130 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 131
 132 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 133 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
 134 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 135
 136 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 137 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
 138 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 139
 140 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 141 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
 142 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 143
 144 /* Used by CM_DSS_CLKSTCTRL */
 145 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
 146 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 147
 148 /* Used by CM_DSS_CLKSTCTRL */
 149 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
 150 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 151
 152 /* Used by CM_DUCATI_CLKSTCTRL */
 153 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
 154 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 155
 156 /* Used by CM_EMU_CLKSTCTRL */
 157 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
 158 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 159
 160 /* Used by CM_CAM_CLKSTCTRL */
 161 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
 162 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 163
 164 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 165 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
 166 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 167
 168 /* Used by CM1_ABE_CLKSTCTRL */
 169 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
 170 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 171
 172 /* Used by CM_DSS_CLKSTCTRL */
 173 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
 174 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 175
 176 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 177 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
 178 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 179
 180 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 181 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
 182 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 183
 184 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 185 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
 186 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 187
 188 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 189 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
 190 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 191
 192 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 193 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
 194 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 195
 196 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 197 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
 198 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 199
 200 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 201 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
 202 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 203
 204 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 205 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
 206 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 207
 208 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 209 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
 210 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 211
 212 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 213 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
 214 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 215
 216 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 217 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
 218 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 219
 220 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 221 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
 222 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 223
 224 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 225 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
 226 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 227
 228 /* Used by CM_CAM_CLKSTCTRL */
 229 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
 230 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 231
 232 /* Used by CM_IVAHD_CLKSTCTRL */
 233 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
 234 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 235
 236 /* Used by CM_D2D_CLKSTCTRL */
 237 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
 238 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 239
 240 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
 241 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
 242 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 243
 244 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
 245 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
 246 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 247
 248 /* Used by CM_D2D_CLKSTCTRL */
 249 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
 250 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 251
 252 /* Used by CM_SDMA_CLKSTCTRL */
 253 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
 254 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 255
 256 /* Used by CM_DSS_CLKSTCTRL */
 257 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
 258 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 259
 260 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 261 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
 262 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 263
 264 /* Used by CM_GFX_CLKSTCTRL */
 265 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
 266 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 267
 268 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 269 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
 270 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 271
 272 /* Used by CM_L3INSTR_CLKSTCTRL */
 273 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
 274 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 275
 276 /* Used by CM_L4SEC_CLKSTCTRL */
 277 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
 278 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 279
 280 /* Used by CM_ALWON_CLKSTCTRL */
 281 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
 282 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 283
 284 /* Used by CM_CEFUSE_CLKSTCTRL */
 285 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
 286 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 287
 288 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
 289 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
 290 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 291
 292 /* Used by CM_D2D_CLKSTCTRL */
 293 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
 294 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 295
 296 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 297 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
 298 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 299
 300 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 301 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
 302 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 303
 304 /* Used by CM_L4SEC_CLKSTCTRL */
 305 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
 306 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 307
 308 /* Used by CM_WKUP_CLKSTCTRL */
 309 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
 310 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 311
 312 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
 313 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
 314 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 315
 316 /* Used by CM1_ABE_CLKSTCTRL */
 317 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
 318 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 319
 320 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 321 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
 322 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 323
 324 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 325 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
 326 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 327
 328 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 329 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
 330 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 331
 332 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 333 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
 334 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 335
 336 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 337 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
 338 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 339
 340 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 341 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
 342 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 343
 344 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 345 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
 346 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 347
 348 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 349 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
 350 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 351
 352 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 353 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
 354 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 355
 356 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 357 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
 358 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 359
 360 /* Used by CM_GFX_CLKSTCTRL */
 361 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
 362 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 363
 364 /* Used by CM_ALWON_CLKSTCTRL */
 365 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
 366 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 367
 368 /* Used by CM_ALWON_CLKSTCTRL */
 369 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
 370 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 371
 372 /* Used by CM_ALWON_CLKSTCTRL */
 373 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
 374 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 375
 376 /* Used by CM_WKUP_CLKSTCTRL */
 377 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
 378 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 379
 380 /* Used by CM_TESLA_CLKSTCTRL */
 381 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
 382 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 383
 384 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 385 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
 386 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 387
 388 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 389 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
 390 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 391
 392 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 393 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
 394 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 395
 396 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 397 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
 398 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 399
 400 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 401 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
 402 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 403
 404 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 405 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
 406 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 407
 408 /* Used by CM_WKUP_CLKSTCTRL */
 409 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
 410 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 411
 412 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 413 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
 414 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 415
 416 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 417 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
 418 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 419
 420 /* Used by CM_WKUP_CLKSTCTRL */
 421 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
 422 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 423
 424 /*
 425  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
 426  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
 427  * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
 428  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
 429  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
 430  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
 431  * CM_WKUP_TIMER1_CLKCTRL
 432  */
 433 #define OMAP4430_CLKSEL_SHIFT                                   24
 434 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 435
 436 /*
 437  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
 438  * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
 439  */
 440 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
 441 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 442
 443 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 444 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
 445 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 446
 447 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 448 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
 449 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 450
 451 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 452 #define OMAP4430_CLKSEL_60M_SHIFT                               24
 453 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 454
 455 /* Used by CM1_ABE_AESS_CLKCTRL */
 456 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
 457 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 458
 459 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 460 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
 461 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 462
 463 /*
 464  * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
 465  * CM_SHADOW_FREQ_CONFIG2
 466  */
 467 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
 468 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 469
 470 /* Used by CM_WKUP_USIM_CLKCTRL */
 471 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
 472 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 473
 474 /* Used by CM_CAM_FDIF_CLKCTRL */
 475 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
 476 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 477
 478 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 479 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
 480 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 481
 482 /*
 483  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
 484  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 485  * CM1_ABE_MCBSP3_CLKCTRL
 486  */
 487 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
 488 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 489
 490 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 491 #define OMAP4430_CLKSEL_L3_SHIFT                                4
 492 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 493
 494 /*
 495  * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
 496  * CM_SHADOW_FREQ_CONFIG2
 497  */
 498 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
 499 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 500
 501 /* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 502 #define OMAP4430_CLKSEL_L4_SHIFT                                8
 503 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 504
 505 /* Used by CM_CLKSEL_ABE */
 506 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
 507 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 508
 509 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 510 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
 511 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 512
 513 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 514 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
 515 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 516
 517 /* Used by CM_GFX_GFX_CLKCTRL */
 518 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
 519 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 520
 521 /*
 522  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
 523  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
 524  */
 525 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
 526 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 527
 528 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 529 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
 530 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 531
 532 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 533 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
 534 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 535
 536 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 537 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
 538 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 539
 540 /*
 541  * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
 542  * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
 543  * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
 544  * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
 545  * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
 546  * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
 547  * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
 548  * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
 549  * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
 550  * CM_WKUP_CLKSTCTRL
 551  */
 552 #define OMAP4430_CLKTRCTRL_SHIFT                                0
 553 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 554
 555 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 556 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
 557 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 558
 559 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 560 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
 561 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 562
 563 /* Used by REVISION_CM1, REVISION_CM2 */
 564 #define OMAP4430_CUSTOM_SHIFT                                   6
 565 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 566
 567 /*
 568  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 569  * CM_L4CFG_DYNAMICDEP_RESTORE
 570  */
 571 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
 572 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 573
 574 /* Used by CM_MPU_STATICDEP */
 575 #define OMAP4430_D2D_STATDEP_SHIFT                              18
 576 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 577
 578 /*
 579  * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
 580  * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
 581  * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
 582  * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
 583  * CM_SSC_DELTAMSTEP_DPLL_USB
 584  */
 585 #define OMAP4430_DELTAMSTEP_SHIFT                               0
 586 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 587
 588 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 589 #define OMAP4430_DLL_OVERRIDE_SHIFT                             2
 590 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 2)
 591
 592 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
 593 #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
 594 #define OMAP4430_DLL_OVERRIDE_0_0_MASK                          (1 << 0)
 595
 596 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 597 #define OMAP4430_DLL_RESET_SHIFT                                3
 598 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 599
 600 /*
 601  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 602  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 603  * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
 604  * CM_CLKSEL_DPLL_USB
 605  */
 606 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
 607 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 608
 609 /* Used by CM_CLKDCOLDO_DPLL_USB */
 610 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
 611 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 612
 613 /* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
 614 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
 615 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 616
 617 /*
 618  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 619  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 620  */
 621 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
 622 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 623
 624 /*
 625  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 626  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 627  */
 628 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
 629 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 630
 631 /*
 632  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
 633  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
 634  */
 635 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
 636 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 637
 638 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 639 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
 640 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 641
 642 /*
 643  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 644  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 645  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 646  */
 647 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
 648 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 649
 650 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 651 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
 652 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 653
 654 /*
 655  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 656  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 657  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
 658  */
 659 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
 660 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 661
 662 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 663 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
 664 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 665
 666 /*
 667  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
 668  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
 669  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
 670  */
 671 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
 672 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 673
 674 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 675 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
 676 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 677
 678 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 679 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
 680 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 681
 682 /* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 683 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
 684 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 685
 686 /*
 687  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 688  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 689  * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
 690  */
 691 #define OMAP4430_DPLL_DIV_SHIFT                                 0
 692 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 693
 694 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 695 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
 696 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 697
 698 /*
 699  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 700  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 701  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 702  */
 703 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
 704 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 705
 706 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 707 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
 708 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 709
 710 /*
 711  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 712  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 713  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 714  * CM_CLKMODE_DPLL_USB
 715  */
 716 #define OMAP4430_DPLL_EN_SHIFT                                  0
 717 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 718
 719 /*
 720  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 721  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 722  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
 723  */
 724 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
 725 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 726
 727 /*
 728  * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
 729  * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
 730  * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
 731  */
 732 #define OMAP4430_DPLL_MULT_SHIFT                                8
 733 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 734
 735 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 736 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
 737 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 738
 739 /*
 740  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 741  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 742  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
 743  */
 744 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
 745 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 746
 747 /* Used by CM_CLKSEL_DPLL_USB */
 748 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
 749 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 750
 751 /*
 752  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 753  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 754  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 755  * CM_CLKMODE_DPLL_USB
 756  */
 757 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
 758 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 759
 760 /*
 761  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 762  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 763  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 764  * CM_CLKMODE_DPLL_USB
 765  */
 766 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
 767 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 768
 769 /*
 770  * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
 771  * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
 772  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
 773  * CM_CLKMODE_DPLL_USB
 774  */
 775 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
 776 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 777
 778 /*
 779  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
 780  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
 781  */
 782 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
 783 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 784
 785 /*
 786  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 787  * CM_SDMA_STATICDEP_RESTORE
 788  */
 789 #define OMAP4430_DSS_STATDEP_SHIFT                              8
 790 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 791
 792 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 793 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
 794 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 795
 796 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
 797 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
 798 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 799
 800 /* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 801 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
 802 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 803
 804 /* Used by REVISION_CM1, REVISION_CM2 */
 805 #define OMAP4430_FUNC_SHIFT                                     16
 806 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 807
 808 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 809 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
 810 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 811
 812 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 813 #define OMAP4430_GFX_STATDEP_SHIFT                              10
 814 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 815
 816 /* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 817 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
 818 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 819
 820 /*
 821  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 822  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 823  */
 824 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
 825 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 826
 827 /*
 828  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 829  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 830  */
 831 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
 832 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 833
 834 /*
 835  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 836  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 837  */
 838 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
 839 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 840
 841 /*
 842  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
 843  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
 844  */
 845 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
 846 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 847
 848 /*
 849  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 850  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 851  */
 852 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
 853 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 854
 855 /*
 856  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 857  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 858  */
 859 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
 860 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 861
 862 /*
 863  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 864  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 865  */
 866 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
 867 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 868
 869 /*
 870  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
 871  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
 872  */
 873 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
 874 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 875
 876 /*
 877  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 878  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 879  */
 880 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
 881 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 882
 883 /*
 884  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 885  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 886  */
 887 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
 888 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 889
 890 /*
 891  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 892  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 893  */
 894 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
 895 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 896
 897 /*
 898  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
 899  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
 900  */
 901 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
 902 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 903
 904 /*
 905  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 906  * CM_DIV_M7_DPLL_PER
 907  */
 908 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
 909 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 910
 911 /*
 912  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 913  * CM_DIV_M7_DPLL_PER
 914  */
 915 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
 916 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 917
 918 /*
 919  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 920  * CM_DIV_M7_DPLL_PER
 921  */
 922 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
 923 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 924
 925 /*
 926  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
 927  * CM_DIV_M7_DPLL_PER
 928  */
 929 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
 930 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 931
 932 /*
 933  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
 934  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
 935  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
 936  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
 937  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
 938  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
 939  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
 940  * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
 941  * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
 942  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
 943  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
 944  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
 945  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
 946  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
 947  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
 948  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
 949  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
 950  * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
 951  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
 952  * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
 953  * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
 954  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
 955  * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
 956  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
 957  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
 958  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
 959  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
 960  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
 961  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
 962  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
 963  * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
 964  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
 965  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
 966  * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
 967  * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
 968  * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
 969  * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
 970  * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
 971  * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
 972  * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
 973  * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
 974  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
 975  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
 976  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
 977  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
 978  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
 979  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
 980  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
 981  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
 982  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
 983  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
 984  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
 985  */
 986 #define OMAP4430_IDLEST_SHIFT                                   16
 987 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 988
 989 /*
 990  * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
 991  * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
 992  */
 993 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
 994 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 995
 996 /*
 997  * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
 998  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
 999  */
1000 #define OMAP4430_ISS_STATDEP_SHIFT                              9
1001 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
1002
1003 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
1004 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
1005 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
1006
1007 /*
1008  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1009  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
1010  * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1011  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1012  */
1013 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
1014 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
1015
1016 /*
1017  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1018  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1019  */
1020 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
1021 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
1022
1023 /*
1024  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1025  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
1026  * CM_TESLA_STATICDEP
1027  */
1028 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
1029 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
1030
1031 /*
1032  * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1033  * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1034  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1035  */
1036 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
1037 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
1038
1039 /*
1040  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1041  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1042  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1043  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1044  */
1045 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
1046 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
1047
1048 /*
1049  * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
1050  * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
1051  * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
1052  * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1053  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1054  */
1055 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
1056 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
1057
1058 /*
1059  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1060  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1061  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1062  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1063  */
1064 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
1065 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
1066
1067 /* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
1068 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
1069 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
1070
1071 /*
1072  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1073  * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1074  * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1075  */
1076 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
1077 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
1078
1079 /* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
1080 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
1081 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
1082
1083 /*
1084  * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1085  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1086  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1087  */
1088 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
1089 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
1090
1091 /*
1092  * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1093  * CM_L4PER_DYNAMICDEP_RESTORE
1094  */
1095 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
1096 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
1097
1098 /*
1099  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1100  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
1101  */
1102 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
1103 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
1104
1105 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1106 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
1107 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
1108
1109 /*
1110  * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1111  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1112  */
1113 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
1114 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
1115
1116 /*
1117  * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
1118  * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1119  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1120  */
1121 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
1122 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
1123
1124 /*
1125  * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1126  * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1127  * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1128  * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1129  */
1130 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
1131 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
1132
1133 /*
1134  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1135  * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
1136  * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1137  * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
1138  * CM_SSC_MODFREQDIV_DPLL_USB
1139  */
1140 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
1141 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
1142
1143 /*
1144  * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1145  * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
1146  * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1147  * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
1148  * CM_SSC_MODFREQDIV_DPLL_USB
1149  */
1150 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
1151 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
1152
1153 /*
1154  * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
1155  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1156  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1157  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1158  * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1159  * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1160  * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1161  * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
1162  * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1163  * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1164  * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1165  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1166  * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1167  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1168  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1169  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1170  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1171  * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1172  * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
1173  * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
1174  * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1175  * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1176  * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1177  * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1178  * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1179  * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1180  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1181  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1182  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1183  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
1184  * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
1185  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
1186  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1187  * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
1188  * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
1189  * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
1190  * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
1191  * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
1192  * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1193  * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1194  * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1195  * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1196  * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1197  * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1198  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1199  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1200  * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
1201  * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1202  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1203  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
1204  * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
1205  * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1206  */
1207 #define OMAP4430_MODULEMODE_SHIFT                               0
1208 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
1209
1210 /* Used by CM_DSS_DSS_CLKCTRL */
1211 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
1212 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
1213
1214 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
1215 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
1216 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
1217
1218 /* Used by CM_ALWON_USBPHY_CLKCTRL */
1219 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
1220 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
1221
1222 /* Used by CM_CAM_ISS_CLKCTRL */
1223 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
1224 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
1225
1226 /*
1227  * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
1228  * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
1229  * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
1230  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1231  * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1232  */
1233 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
1234 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
1235
1236 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
1237 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
1238 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
1239
1240 /* Used by CM_DSS_DSS_CLKCTRL */
1241 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
1242 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
1243
1244 /* Used by CM_WKUP_USIM_CLKCTRL */
1245 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
1246 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
1247
1248 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1249 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
1250 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
1251
1252 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1253 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
1254 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
1255
1256 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1257 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
1258 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
1259
1260 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1261 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
1262 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
1263
1264 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1265 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
1266 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
1267
1268 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1269 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
1270 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
1271
1272 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1273 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
1274 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
1275
1276 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1277 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
1278 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
1279
1280 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1281 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
1282 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
1283
1284 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1285 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
1286 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
1287
1288 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
1289 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
1290 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
1291
1292 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1293 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
1294 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
1295
1296 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
1297 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
1298 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
1299
1300 /* Used by CM_DSS_DSS_CLKCTRL */
1301 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
1302 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
1303
1304 /* Used by CM_DSS_DSS_CLKCTRL */
1305 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
1306 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
1307
1308 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
1309 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
1310 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
1311
1312 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1313 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
1314 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
1315
1316 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1317 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
1318 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
1319
1320 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1321 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
1322 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
1323
1324 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1325 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
1326 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
1327
1328 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1329 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
1330 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
1331
1332 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1333 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
1334 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
1335
1336 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
1337 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
1338 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
1339
1340 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
1341 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
1342 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
1343
1344 /* Used by CM_CLKSEL_ABE */
1345 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
1346 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
1347
1348 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
1349 #define OMAP4430_PERF_CURRENT_SHIFT                             0
1350 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
1351
1352 /*
1353  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
1354  * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
1355  * CM_IVA_DVFS_PERF_TESLA
1356  */
1357 #define OMAP4430_PERF_REQ_SHIFT                                 0
1358 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
1359
1360 /* Used by CM_RESTORE_ST */
1361 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
1362 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
1363
1364 /* Used by CM_RESTORE_ST */
1365 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
1366 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
1367
1368 /* Used by CM_RESTORE_ST */
1369 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
1370 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
1371
1372 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
1373 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
1374 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
1375
1376 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
1377 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
1378 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
1379
1380 /* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
1381 #define OMAP4430_PRESCAL_SHIFT                                  0
1382 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
1383
1384 /* Used by REVISION_CM1, REVISION_CM2 */
1385 #define OMAP4430_R_RTL_SHIFT                                    11
1386 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
1387
1388 /*
1389  * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1390  * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1391  */
1392 #define OMAP4430_SAR_MODE_SHIFT                                 4
1393 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
1394
1395 /* Used by CM_SCALE_FCLK */
1396 #define OMAP4430_SCALE_FCLK_SHIFT                               0
1397 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
1398
1399 /* Used by REVISION_CM1, REVISION_CM2 */
1400 #define OMAP4430_SCHEME_SHIFT                                   30
1401 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
1402
1403 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1404 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
1405 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
1406
1407 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1408 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
1409 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
1410
1411 /* Used by CM_CLKSEL_ABE */
1412 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
1413 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
1414
1415 /*
1416  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
1417  * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1418  * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
1419  * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1420  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1421  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1422  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1423  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1424  * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1425  * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1426  * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
1427  */
1428 #define OMAP4430_STBYST_SHIFT                                   18
1429 #define OMAP4430_STBYST_MASK                                    (1 << 18)
1430
1431 /*
1432  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1433  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1434  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1435  */
1436 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
1437 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
1438
1439 /* Used by CM_CLKDCOLDO_DPLL_USB */
1440 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
1441 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
1442
1443 /*
1444  * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
1445  * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
1446  * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1447  */
1448 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
1449 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
1450
1451 /*
1452  * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1453  * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1454  */
1455 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
1456 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
1457
1458 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
1459 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
1460 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
1461
1462 /*
1463  * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
1464  * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
1465  */
1466 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
1467 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
1468
1469 /*
1470  * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
1471  * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
1472  */
1473 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
1474 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
1475
1476 /*
1477  * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1478  * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1479  */
1480 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
1481 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
1482
1483 /*
1484  * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1485  * CM_DIV_M7_DPLL_PER
1486  */
1487 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
1488 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
1489
1490 /*
1491  * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1492  * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1493  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1494  */
1495 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
1496 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
1497
1498 /* Used by CM_SYS_CLKSEL */
1499 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
1500 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
1501
1502 /* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1503 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
1504 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
1505
1506 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1507 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
1508 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
1509
1510 /*
1511  * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
1512  * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
1513  * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1514  * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1515  * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1516  */
1517 #define OMAP4430_WINDOWSIZE_SHIFT                               24
1518 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
1519
1520 /* Used by REVISION_CM1, REVISION_CM2 */
1521 #define OMAP4430_X_MAJOR_SHIFT                                  8
1522 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
1523
1524 /* Used by REVISION_CM1, REVISION_CM2 */
1525 #define OMAP4430_Y_MINOR_SHIFT                                  0
1526 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
1527 #endif