arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c

   1 /*
   2  * OMAP2/3 clockdomains
   3  *
   4  * Copyright (C) 2008-2009 Texas Instruments, Inc.
   5  * Copyright (C) 2008-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley, Jouni Högander
   8  *
   9  * This file contains clockdomains and clockdomain wakeup/sleep
  10  * dependencies for the OMAP2/3 chips.  Some notes:
  11  *
  12  * A useful validation rule for struct clockdomain: Any clockdomain
  13  * referenced by a wkdep_srcs or sleepdep_srcs array must have a
  14  * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
  15  * software-controllable dependencies.  Non-software-controllable
  16  * dependencies do exist, but they are not encoded below (yet).
  17  *
  18  * 24xx does not support programmable sleep dependencies (SLEEPDEP)
  19  *
  20  * The overly-specific dep_bit names are due to a bit name collision
  21  * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
  22  * value are the same for all powerdomains: 2
  23  *
  24  * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
  25  * sanity check?
  26  * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
  27  */
  28
  29 /*
  30  * To-Do List
  31  * -> Port the Sleep/Wakeup dependencies for the domains
  32  *    from the Power domain framework
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/io.h>
  37
  38 #include "clockdomain.h"
  39 #include "prm2xxx_3xxx.h"
  40 #include "cm2xxx_3xxx.h"
  41 #include "cm-regbits-24xx.h"
  42 #include "cm-regbits-34xx.h"
  43 #include "cm-regbits-44xx.h"
  44 #include "prm-regbits-24xx.h"
  45 #include "prm-regbits-34xx.h"
  46
  47 /*
  48  * Clockdomain dependencies for wkdeps/sleepdeps
  49  *
  50  * XXX Hardware dependencies (e.g., dependencies that cannot be
  51  * changed in software) are not included here yet, but should be.
  52  */
  53
  54 /* OMAP2/3-common wakeup dependencies */
  55
  56 /*
  57  * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
  58  * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
  59  * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
  60  * These can share data since they will never be present simultaneously
  61  * on the same device.
  62  */
  63 static struct clkdm_dep gfx_sgx_wkdeps[] = {
  64         {
  65                 .clkdm_name = "core_l3_clkdm",
  66                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  67         },
  68         {
  69                 .clkdm_name = "core_l4_clkdm",
  70                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  71         },
  72         {
  73                 .clkdm_name = "iva2_clkdm",
  74                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  75         },
  76         {
  77                 .clkdm_name = "mpu_clkdm",
  78                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  79                                             CHIP_IS_OMAP3430)
  80         },
  81         {
  82                 .clkdm_name = "wkup_clkdm",
  83                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  84                                             CHIP_IS_OMAP3430)
  85         },
  86         { NULL },
  87 };
  88
  89
  90 /* 24XX-specific possible dependencies */
  91
  92 #ifdef CONFIG_ARCH_OMAP2
  93
  94 /* Wakeup dependency source arrays */
  95
  96 /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
  97 static struct clkdm_dep dsp_24xx_wkdeps[] = {
  98         {
  99                 .clkdm_name = "core_l3_clkdm",
 100                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 101         },
 102         {
 103                 .clkdm_name = "core_l4_clkdm",
 104                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 105         },
 106         {
 107                 .clkdm_name = "mpu_clkdm",
 108                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 109         },
 110         {
 111                 .clkdm_name = "wkup_clkdm",
 112                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 113         },
 114         { NULL },
 115 };
 116
 117 /*
 118  * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
 119  * 2430 adds MDM
 120  */
 121 static struct clkdm_dep mpu_24xx_wkdeps[] = {
 122         {
 123                 .clkdm_name = "core_l3_clkdm",
 124                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 125         },
 126         {
 127                 .clkdm_name = "core_l4_clkdm",
 128                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 129         },
 130         {
 131                 .clkdm_name = "dsp_clkdm",
 132                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 133         },
 134         {
 135                 .clkdm_name = "wkup_clkdm",
 136                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 137         },
 138         {
 139                 .clkdm_name = "mdm_clkdm",
 140                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 141         },
 142         { NULL },
 143 };
 144
 145 /*
 146  * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
 147  * 2430 adds MDM
 148  */
 149 static struct clkdm_dep core_24xx_wkdeps[] = {
 150         {
 151                 .clkdm_name = "dsp_clkdm",
 152                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 153         },
 154         {
 155                 .clkdm_name = "gfx_clkdm",
 156                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 157         },
 158         {
 159                 .clkdm_name = "mpu_clkdm",
 160                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 161         },
 162         {
 163                 .clkdm_name = "wkup_clkdm",
 164                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 165         },
 166         {
 167                 .clkdm_name = "mdm_clkdm",
 168                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 169         },
 170         { NULL },
 171 };
 172
 173 #endif /* CONFIG_ARCH_OMAP2 */
 174
 175 /* 2430-specific possible wakeup dependencies */
 176
 177 #ifdef CONFIG_SOC_OMAP2430
 178
 179 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
 180 static struct clkdm_dep mdm_2430_wkdeps[] = {
 181         {
 182                 .clkdm_name = "core_l3_clkdm",
 183                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 184         },
 185         {
 186                 .clkdm_name = "core_l4_clkdm",
 187                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 188         },
 189         {
 190                 .clkdm_name = "mpu_clkdm",
 191                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 192         },
 193         {
 194                 .clkdm_name = "wkup_clkdm",
 195                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 196         },
 197         { NULL },
 198 };
 199
 200 #endif /* CONFIG_SOC_OMAP2430 */
 201
 202
 203 /* OMAP3-specific possible dependencies */
 204
 205 #ifdef CONFIG_ARCH_OMAP3
 206
 207 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
 208 static struct clkdm_dep per_wkdeps[] = {
 209         {
 210                 .clkdm_name = "core_l3_clkdm",
 211                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 212         },
 213         {
 214                 .clkdm_name = "core_l4_clkdm",
 215                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 216         },
 217         {
 218                 .clkdm_name = "iva2_clkdm",
 219                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 220         },
 221         {
 222                 .clkdm_name = "mpu_clkdm",
 223                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 224         },
 225         {
 226                 .clkdm_name = "wkup_clkdm",
 227                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 228         },
 229         { NULL },
 230 };
 231
 232 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
 233 static struct clkdm_dep usbhost_wkdeps[] = {
 234         {
 235                 .clkdm_name = "core_l3_clkdm",
 236                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 237         },
 238         {
 239                 .clkdm_name = "core_l4_clkdm",
 240                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 241         },
 242         {
 243                 .clkdm_name = "iva2_clkdm",
 244                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 245         },
 246         {
 247                 .clkdm_name = "mpu_clkdm",
 248                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 249         },
 250         {
 251                 .clkdm_name = "wkup_clkdm",
 252                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 253         },
 254         { NULL },
 255 };
 256
 257 /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
 258 static struct clkdm_dep mpu_3xxx_wkdeps[] = {
 259         {
 260                 .clkdm_name = "core_l3_clkdm",
 261                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 262         },
 263         {
 264                 .clkdm_name = "core_l4_clkdm",
 265                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 266         },
 267         {
 268                 .clkdm_name = "iva2_clkdm",
 269                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 270         },
 271         {
 272                 .clkdm_name = "dss_clkdm",
 273                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 274         },
 275         {
 276                 .clkdm_name = "per_clkdm",
 277                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 278         },
 279         { NULL },
 280 };
 281
 282 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
 283 static struct clkdm_dep iva2_wkdeps[] = {
 284         {
 285                 .clkdm_name = "core_l3_clkdm",
 286                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 287         },
 288         {
 289                 .clkdm_name = "core_l4_clkdm",
 290                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 291         },
 292         {
 293                 .clkdm_name = "mpu_clkdm",
 294                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 295         },
 296         {
 297                 .clkdm_name = "wkup_clkdm",
 298                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 299         },
 300         {
 301                 .clkdm_name = "dss_clkdm",
 302                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 303         },
 304         {
 305                 .clkdm_name = "per_clkdm",
 306                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 307         },
 308         { NULL },
 309 };
 310
 311
 312 /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
 313 static struct clkdm_dep cam_wkdeps[] = {
 314         {
 315                 .clkdm_name = "iva2_clkdm",
 316                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 317         },
 318         {
 319                 .clkdm_name = "mpu_clkdm",
 320                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 321         },
 322         {
 323                 .clkdm_name = "wkup_clkdm",
 324                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 325         },
 326         { NULL },
 327 };
 328
 329 /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
 330 static struct clkdm_dep dss_wkdeps[] = {
 331         {
 332                 .clkdm_name = "iva2_clkdm",
 333                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 334         },
 335         {
 336                 .clkdm_name = "mpu_clkdm",
 337                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 338         },
 339         {
 340                 .clkdm_name = "wkup_clkdm",
 341                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 342         },
 343         { NULL },
 344 };
 345
 346 /* 3430: PM_WKDEP_NEON: MPU */
 347 static struct clkdm_dep neon_wkdeps[] = {
 348         {
 349                 .clkdm_name = "mpu_clkdm",
 350                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 351         },
 352         { NULL },
 353 };
 354
 355
 356 /* Sleep dependency source arrays for OMAP3-specific clkdms */
 357
 358 /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
 359 static struct clkdm_dep dss_sleepdeps[] = {
 360         {
 361                 .clkdm_name = "mpu_clkdm",
 362                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 363         },
 364         {
 365                 .clkdm_name = "iva2_clkdm",
 366                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 367         },
 368         { NULL },
 369 };
 370
 371 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
 372 static struct clkdm_dep per_sleepdeps[] = {
 373         {
 374                 .clkdm_name = "mpu_clkdm",
 375                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 376         },
 377         {
 378                 .clkdm_name = "iva2_clkdm",
 379                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 380         },
 381         { NULL },
 382 };
 383
 384 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
 385 static struct clkdm_dep usbhost_sleepdeps[] = {
 386         {
 387                 .clkdm_name = "mpu_clkdm",
 388                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 389         },
 390         {
 391                 .clkdm_name = "iva2_clkdm",
 392                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 393         },
 394         { NULL },
 395 };
 396
 397 /* 3430: CM_SLEEPDEP_CAM: MPU */
 398 static struct clkdm_dep cam_sleepdeps[] = {
 399         {
 400                 .clkdm_name = "mpu_clkdm",
 401                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 402         },
 403         { NULL },
 404 };
 405
 406 /*
 407  * 3430ES1: CM_SLEEPDEP_GFX: MPU
 408  * 3430ES2: CM_SLEEPDEP_SGX: MPU
 409  * These can share data since they will never be present simultaneously
 410  * on the same device.
 411  */
 412 static struct clkdm_dep gfx_sgx_sleepdeps[] = {
 413         {
 414                 .clkdm_name = "mpu_clkdm",
 415                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 416         },
 417         { NULL },
 418 };
 419
 420 #endif /* CONFIG_ARCH_OMAP3 */
 421
 422
 423 /*
 424  * OMAP2/3-common clockdomains
 425  *
 426  * Even though the 2420 has a single PRCM module from the
 427  * interconnect's perspective, internally it does appear to have
 428  * separate PRM and CM clockdomains.  The usual test case is
 429  * sys_clkout/sys_clkout2.
 430  */
 431
 432 /* This is an implicit clockdomain - it is never defined as such in TRM */
 433 static struct clockdomain wkup_clkdm = {
 434         .name           = "wkup_clkdm",
 435         .pwrdm          = { .name = "wkup_pwrdm" },
 436         .dep_bit        = OMAP_EN_WKUP_SHIFT,
 437         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 438 };
 439
 440 static struct clockdomain prm_clkdm = {
 441         .name           = "prm_clkdm",
 442         .pwrdm          = { .name = "wkup_pwrdm" },
 443         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 444 };
 445
 446 static struct clockdomain cm_clkdm = {
 447         .name           = "cm_clkdm",
 448         .pwrdm          = { .name = "core_pwrdm" },
 449         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 450 };
 451
 452 /*
 453  * 2420-only clockdomains
 454  */
 455
 456 #if defined(CONFIG_SOC_OMAP2420)
 457
 458 static struct clockdomain mpu_2420_clkdm = {
 459         .name           = "mpu_clkdm",
 460         .pwrdm          = { .name = "mpu_pwrdm" },
 461         .flags          = CLKDM_CAN_HWSUP,
 462         .wkdep_srcs     = mpu_24xx_wkdeps,
 463         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 464         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 465 };
 466
 467 static struct clockdomain iva1_2420_clkdm = {
 468         .name           = "iva1_clkdm",
 469         .pwrdm          = { .name = "dsp_pwrdm" },
 470         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 471         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 472         .wkdep_srcs     = dsp_24xx_wkdeps,
 473         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
 474         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 475 };
 476
 477 static struct clockdomain dsp_2420_clkdm = {
 478         .name           = "dsp_clkdm",
 479         .pwrdm          = { .name = "dsp_pwrdm" },
 480         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 481         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 482         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 483 };
 484
 485 static struct clockdomain gfx_2420_clkdm = {
 486         .name           = "gfx_clkdm",
 487         .pwrdm          = { .name = "gfx_pwrdm" },
 488         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 489         .wkdep_srcs     = gfx_sgx_wkdeps,
 490         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 491         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 492 };
 493
 494 static struct clockdomain core_l3_2420_clkdm = {
 495         .name           = "core_l3_clkdm",
 496         .pwrdm          = { .name = "core_pwrdm" },
 497         .flags          = CLKDM_CAN_HWSUP,
 498         .wkdep_srcs     = core_24xx_wkdeps,
 499         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 500         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 501 };
 502
 503 static struct clockdomain core_l4_2420_clkdm = {
 504         .name           = "core_l4_clkdm",
 505         .pwrdm          = { .name = "core_pwrdm" },
 506         .flags          = CLKDM_CAN_HWSUP,
 507         .wkdep_srcs     = core_24xx_wkdeps,
 508         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 509         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 510 };
 511
 512 static struct clockdomain dss_2420_clkdm = {
 513         .name           = "dss_clkdm",
 514         .pwrdm          = { .name = "core_pwrdm" },
 515         .flags          = CLKDM_CAN_HWSUP,
 516         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 517         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 518 };
 519
 520 #endif   /* CONFIG_SOC_OMAP2420 */
 521
 522
 523 /*
 524  * 2430-only clockdomains
 525  */
 526
 527 #if defined(CONFIG_SOC_OMAP2430)
 528
 529 static struct clockdomain mpu_2430_clkdm = {
 530         .name           = "mpu_clkdm",
 531         .pwrdm          = { .name = "mpu_pwrdm" },
 532         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 533         .wkdep_srcs     = mpu_24xx_wkdeps,
 534         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 535         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 536 };
 537
 538 /* Another case of bit name collisions between several registers: EN_MDM */
 539 static struct clockdomain mdm_clkdm = {
 540         .name           = "mdm_clkdm",
 541         .pwrdm          = { .name = "mdm_pwrdm" },
 542         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 543         .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
 544         .wkdep_srcs     = mdm_2430_wkdeps,
 545         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
 546         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 547 };
 548
 549 static struct clockdomain dsp_2430_clkdm = {
 550         .name           = "dsp_clkdm",
 551         .pwrdm          = { .name = "dsp_pwrdm" },
 552         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 553         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 554         .wkdep_srcs     = dsp_24xx_wkdeps,
 555         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 556         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 557 };
 558
 559 static struct clockdomain gfx_2430_clkdm = {
 560         .name           = "gfx_clkdm",
 561         .pwrdm          = { .name = "gfx_pwrdm" },
 562         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 563         .wkdep_srcs     = gfx_sgx_wkdeps,
 564         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 565         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 566 };
 567
 568 /*
 569  * XXX add usecounting for clkdm dependencies, otherwise the presence
 570  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 571  * could cause trouble
 572  */
 573 static struct clockdomain core_l3_2430_clkdm = {
 574         .name           = "core_l3_clkdm",
 575         .pwrdm          = { .name = "core_pwrdm" },
 576         .flags          = CLKDM_CAN_HWSUP,
 577         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 578         .wkdep_srcs     = core_24xx_wkdeps,
 579         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 581 };
 582
 583 /*
 584  * XXX add usecounting for clkdm dependencies, otherwise the presence
 585  * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 586  * could cause trouble
 587  */
 588 static struct clockdomain core_l4_2430_clkdm = {
 589         .name           = "core_l4_clkdm",
 590         .pwrdm          = { .name = "core_pwrdm" },
 591         .flags          = CLKDM_CAN_HWSUP,
 592         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 593         .wkdep_srcs     = core_24xx_wkdeps,
 594         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 595         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 596 };
 597
 598 static struct clockdomain dss_2430_clkdm = {
 599         .name           = "dss_clkdm",
 600         .pwrdm          = { .name = "core_pwrdm" },
 601         .flags          = CLKDM_CAN_HWSUP,
 602         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 603         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 604 };
 605
 606 #endif    /* CONFIG_SOC_OMAP2430 */
 607
 608
 609 /*
 610  * OMAP3 clockdomains
 611  */
 612
 613 #if defined(CONFIG_ARCH_OMAP3)
 614
 615 static struct clockdomain mpu_3xxx_clkdm = {
 616         .name           = "mpu_clkdm",
 617         .pwrdm          = { .name = "mpu_pwrdm" },
 618         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
 619         .dep_bit        = OMAP3430_EN_MPU_SHIFT,
 620         .wkdep_srcs     = mpu_3xxx_wkdeps,
 621         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 622         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 623 };
 624
 625 static struct clockdomain neon_clkdm = {
 626         .name           = "neon_clkdm",
 627         .pwrdm          = { .name = "neon_pwrdm" },
 628         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 629         .wkdep_srcs     = neon_wkdeps,
 630         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
 631         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 632 };
 633
 634 static struct clockdomain iva2_clkdm = {
 635         .name           = "iva2_clkdm",
 636         .pwrdm          = { .name = "iva2_pwrdm" },
 637         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 638         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
 639         .wkdep_srcs     = iva2_wkdeps,
 640         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
 641         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 642 };
 643
 644 static struct clockdomain gfx_3430es1_clkdm = {
 645         .name           = "gfx_clkdm",
 646         .pwrdm          = { .name = "gfx_pwrdm" },
 647         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 648         .wkdep_srcs     = gfx_sgx_wkdeps,
 649         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 650         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
 651         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 652 };
 653
 654 static struct clockdomain sgx_clkdm = {
 655         .name           = "sgx_clkdm",
 656         .pwrdm          = { .name = "sgx_pwrdm" },
 657         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 658         .wkdep_srcs     = gfx_sgx_wkdeps,
 659         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 660         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 661         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 662 };
 663
 664 /*
 665  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 666  * then that information was removed from the 34xx ES2+ TRM.  It is
 667  * unclear whether the core is still there, but the clockdomain logic
 668  * is there, and must be programmed to an appropriate state if the
 669  * CORE clockdomain is to become inactive.
 670  */
 671 static struct clockdomain d2d_clkdm = {
 672         .name           = "d2d_clkdm",
 673         .pwrdm          = { .name = "core_pwrdm" },
 674         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 675         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 676         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 677 };
 678
 679 /*
 680  * XXX add usecounting for clkdm dependencies, otherwise the presence
 681  * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
 682  * could cause trouble
 683  */
 684 static struct clockdomain core_l3_3xxx_clkdm = {
 685         .name           = "core_l3_clkdm",
 686         .pwrdm          = { .name = "core_pwrdm" },
 687         .flags          = CLKDM_CAN_HWSUP,
 688         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 689         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
 690         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 691 };
 692
 693 /*
 694  * XXX add usecounting for clkdm dependencies, otherwise the presence
 695  * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
 696  * could cause trouble
 697  */
 698 static struct clockdomain core_l4_3xxx_clkdm = {
 699         .name           = "core_l4_clkdm",
 700         .pwrdm          = { .name = "core_pwrdm" },
 701         .flags          = CLKDM_CAN_HWSUP,
 702         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 703         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
 704         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 705 };
 706
 707 /* Another case of bit name collisions between several registers: EN_DSS */
 708 static struct clockdomain dss_3xxx_clkdm = {
 709         .name           = "dss_clkdm",
 710         .pwrdm          = { .name = "dss_pwrdm" },
 711         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 712         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
 713         .wkdep_srcs     = dss_wkdeps,
 714         .sleepdep_srcs  = dss_sleepdeps,
 715         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 716         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 717 };
 718
 719 static struct clockdomain cam_clkdm = {
 720         .name           = "cam_clkdm",
 721         .pwrdm          = { .name = "cam_pwrdm" },
 722         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 723         .wkdep_srcs     = cam_wkdeps,
 724         .sleepdep_srcs  = cam_sleepdeps,
 725         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
 726         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 727 };
 728
 729 static struct clockdomain usbhost_clkdm = {
 730         .name           = "usbhost_clkdm",
 731         .pwrdm          = { .name = "usbhost_pwrdm" },
 732         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 733         .wkdep_srcs     = usbhost_wkdeps,
 734         .sleepdep_srcs  = usbhost_sleepdeps,
 735         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 736         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 737 };
 738
 739 static struct clockdomain per_clkdm = {
 740         .name           = "per_clkdm",
 741         .pwrdm          = { .name = "per_pwrdm" },
 742         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 743         .dep_bit        = OMAP3430_EN_PER_SHIFT,
 744         .wkdep_srcs     = per_wkdeps,
 745         .sleepdep_srcs  = per_sleepdeps,
 746         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 747         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 748 };
 749
 750 /*
 751  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 752  * switched of even if sdti is in use
 753  */
 754 static struct clockdomain emu_clkdm = {
 755         .name           = "emu_clkdm",
 756         .pwrdm          = { .name = "emu_pwrdm" },
 757         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
 758         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 760 };
 761
 762 static struct clockdomain dpll1_clkdm = {
 763         .name           = "dpll1_clkdm",
 764         .pwrdm          = { .name = "dpll1_pwrdm" },
 765         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 766 };
 767
 768 static struct clockdomain dpll2_clkdm = {
 769         .name           = "dpll2_clkdm",
 770         .pwrdm          = { .name = "dpll2_pwrdm" },
 771         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 772 };
 773
 774 static struct clockdomain dpll3_clkdm = {
 775         .name           = "dpll3_clkdm",
 776         .pwrdm          = { .name = "dpll3_pwrdm" },
 777         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 778 };
 779
 780 static struct clockdomain dpll4_clkdm = {
 781         .name           = "dpll4_clkdm",
 782         .pwrdm          = { .name = "dpll4_pwrdm" },
 783         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 784 };
 785
 786 static struct clockdomain dpll5_clkdm = {
 787         .name           = "dpll5_clkdm",
 788         .pwrdm          = { .name = "dpll5_pwrdm" },
 789         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 790 };
 791
 792 #endif   /* CONFIG_ARCH_OMAP3 */
 793
 794 /*
 795  * Clockdomain hwsup dependencies (OMAP3 only)
 796  */
 797
 798 static struct clkdm_autodep clkdm_autodeps[] = {
 799         {
 800                 .clkdm     = { .name = "mpu_clkdm" },
 801                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 802         },
 803         {
 804                 .clkdm     = { .name = "iva2_clkdm" },
 805                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 806         },
 807         {
 808                 .clkdm     = { .name = NULL },
 809         }
 810 };
 811
 812 static struct clockdomain *clockdomains_omap2[] __initdata = {
 813         &wkup_clkdm,
 814         &cm_clkdm,
 815         &prm_clkdm,
 816
 817 #ifdef CONFIG_SOC_OMAP2420
 818         &mpu_2420_clkdm,
 819         &iva1_2420_clkdm,
 820         &dsp_2420_clkdm,
 821         &gfx_2420_clkdm,
 822         &core_l3_2420_clkdm,
 823         &core_l4_2420_clkdm,
 824         &dss_2420_clkdm,
 825 #endif
 826
 827 #ifdef CONFIG_SOC_OMAP2430
 828         &mpu_2430_clkdm,
 829         &mdm_clkdm,
 830         &dsp_2430_clkdm,
 831         &gfx_2430_clkdm,
 832         &core_l3_2430_clkdm,
 833         &core_l4_2430_clkdm,
 834         &dss_2430_clkdm,
 835 #endif
 836
 837 #ifdef CONFIG_ARCH_OMAP3
 838         &mpu_3xxx_clkdm,
 839         &neon_clkdm,
 840         &iva2_clkdm,
 841         &gfx_3430es1_clkdm,
 842         &sgx_clkdm,
 843         &d2d_clkdm,
 844         &core_l3_3xxx_clkdm,
 845         &core_l4_3xxx_clkdm,
 846         &dss_3xxx_clkdm,
 847         &cam_clkdm,
 848         &usbhost_clkdm,
 849         &per_clkdm,
 850         &emu_clkdm,
 851         &dpll1_clkdm,
 852         &dpll2_clkdm,
 853         &dpll3_clkdm,
 854         &dpll4_clkdm,
 855         &dpll5_clkdm,
 856 #endif
 857         NULL,
 858 };
 859
 860 void __init omap2xxx_clockdomains_init(void)
 861 {
 862         clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
 863 }
 864
 865 void __init omap3xxx_clockdomains_init(void)
 866 {
 867         clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
 868 }