arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39 #include "scrm44xx.h"
  40
  41 /* OMAP4 modulemode control */
  42 #define OMAP4430_MODULEMODE_HWCTRL                      0
  43 #define OMAP4430_MODULEMODE_SWCTRL                      1
  44
  45 /* Root clocks */
  46
  47 static struct clk extalt_clkin_ck = {
  48         .name           = "extalt_clkin_ck",
  49         .rate           = 59000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_clks_ck = {
  54         .name           = "pad_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_omap2_dflt,
  57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  59 };
  60
  61 static struct clk pad_slimbus_core_clks_ck = {
  62         .name           = "pad_slimbus_core_clks_ck",
  63         .rate           = 12000000,
  64         .ops            = &clkops_null,
  65 };
  66
  67 static struct clk secure_32k_clk_src_ck = {
  68         .name           = "secure_32k_clk_src_ck",
  69         .rate           = 32768,
  70         .ops            = &clkops_null,
  71 };
  72
  73 static struct clk slimbus_clk = {
  74         .name           = "slimbus_clk",
  75         .rate           = 12000000,
  76         .ops            = &clkops_omap2_dflt,
  77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79 };
  80
  81 static struct clk sys_32k_ck = {
  82         .name           = "sys_32k_ck",
  83         .rate           = 32768,
  84         .ops            = &clkops_null,
  85 };
  86
  87 static struct clk virt_12000000_ck = {
  88         .name           = "virt_12000000_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 12000000,
  91 };
  92
  93 static struct clk virt_13000000_ck = {
  94         .name           = "virt_13000000_ck",
  95         .ops            = &clkops_null,
  96         .rate           = 13000000,
  97 };
  98
  99 static struct clk virt_16800000_ck = {
 100         .name           = "virt_16800000_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 16800000,
 103 };
 104
 105 static struct clk virt_19200000_ck = {
 106         .name           = "virt_19200000_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 19200000,
 109 };
 110
 111 static struct clk virt_26000000_ck = {
 112         .name           = "virt_26000000_ck",
 113         .ops            = &clkops_null,
 114         .rate           = 26000000,
 115 };
 116
 117 static struct clk virt_27000000_ck = {
 118         .name           = "virt_27000000_ck",
 119         .ops            = &clkops_null,
 120         .rate           = 27000000,
 121 };
 122
 123 static struct clk virt_38400000_ck = {
 124         .name           = "virt_38400000_ck",
 125         .ops            = &clkops_null,
 126         .rate           = 38400000,
 127 };
 128
 129 static const struct clksel_rate div_1_0_rates[] = {
 130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_1_rates[] = {
 135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_2_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_3_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_4_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_5_rates[] = {
 155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel_rate div_1_6_rates[] = {
 160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161         { .div = 0 },
 162 };
 163
 164 static const struct clksel_rate div_1_7_rates[] = {
 165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel sys_clkin_sel[] = {
 170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk sys_clkin_ck = {
 181         .name           = "sys_clkin_ck",
 182         .rate           = 38400000,
 183         .clksel         = sys_clkin_sel,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 187         .ops            = &clkops_null,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk tie_low_clock_ck = {
 192         .name           = "tie_low_clock_ck",
 193         .rate           = 0,
 194         .ops            = &clkops_null,
 195 };
 196
 197 static struct clk utmi_phy_clkout_ck = {
 198         .name           = "utmi_phy_clkout_ck",
 199         .rate           = 60000000,
 200         .ops            = &clkops_null,
 201 };
 202
 203 static struct clk xclk60mhsp1_ck = {
 204         .name           = "xclk60mhsp1_ck",
 205         .rate           = 60000000,
 206         .ops            = &clkops_null,
 207 };
 208
 209 static struct clk xclk60mhsp2_ck = {
 210         .name           = "xclk60mhsp2_ck",
 211         .rate           = 60000000,
 212         .ops            = &clkops_null,
 213 };
 214
 215 static struct clk xclk60motg_ck = {
 216         .name           = "xclk60motg_ck",
 217         .rate           = 60000000,
 218         .ops            = &clkops_null,
 219 };
 220
 221 /* Module clocks and DPLL outputs */
 222
 223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226         { .parent = NULL },
 227 };
 228
 229 static struct clk abe_dpll_bypass_clk_mux_ck = {
 230         .name           = "abe_dpll_bypass_clk_mux_ck",
 231         .parent         = &sys_clkin_ck,
 232         .ops            = &clkops_null,
 233         .recalc         = &followparent_recalc,
 234 };
 235
 236 static struct clk abe_dpll_refclk_mux_ck = {
 237         .name           = "abe_dpll_refclk_mux_ck",
 238         .parent         = &sys_clkin_ck,
 239         .clksel         = abe_dpll_bypass_clk_mux_sel,
 240         .init           = &omap2_init_clksel_parent,
 241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 243         .ops            = &clkops_null,
 244         .recalc         = &omap2_clksel_recalc,
 245 };
 246
 247 /* DPLL_ABE */
 248 static struct dpll_data dpll_abe_dd = {
 249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 251         .clk_ref        = &abe_dpll_refclk_mux_ck,
 252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 261         .max_multiplier = 2047,
 262         .max_divider    = 128,
 263         .min_divider    = 1,
 264 };
 265
 266
 267 static struct clk dpll_abe_ck = {
 268         .name           = "dpll_abe_ck",
 269         .parent         = &abe_dpll_refclk_mux_ck,
 270         .dpll_data      = &dpll_abe_dd,
 271         .init           = &omap2_init_dpll_parent,
 272         .ops            = &clkops_omap3_noncore_dpll_ops,
 273         .recalc         = &omap3_dpll_recalc,
 274         .round_rate     = &omap2_dpll_round_rate,
 275         .set_rate       = &omap3_noncore_dpll_set_rate,
 276 };
 277
 278 static struct clk dpll_abe_x2_ck = {
 279         .name           = "dpll_abe_x2_ck",
 280         .parent         = &dpll_abe_ck,
 281         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 282         .flags          = CLOCK_CLKOUTX2,
 283         .ops            = &clkops_omap4_dpllmx_ops,
 284         .recalc         = &omap3_clkoutx2_recalc,
 285 };
 286
 287 static const struct clksel_rate div31_1to31_rates[] = {
 288         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 289         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 290         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 291         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 292         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 293         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 294         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 295         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 296         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 297         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 298         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 299         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 300         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 301         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 302         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 303         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 304         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 305         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 306         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 307         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 308         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 309         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 310         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 311         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 312         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 313         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 314         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 315         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 316         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 317         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 318         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 319         { .div = 0 },
 320 };
 321
 322 static const struct clksel dpll_abe_m2x2_div[] = {
 323         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 324         { .parent = NULL },
 325 };
 326
 327 static struct clk dpll_abe_m2x2_ck = {
 328         .name           = "dpll_abe_m2x2_ck",
 329         .parent         = &dpll_abe_x2_ck,
 330         .clksel         = dpll_abe_m2x2_div,
 331         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 332         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 333         .ops            = &clkops_omap4_dpllmx_ops,
 334         .recalc         = &omap2_clksel_recalc,
 335         .round_rate     = &omap2_clksel_round_rate,
 336         .set_rate       = &omap2_clksel_set_rate,
 337 };
 338
 339 static struct clk abe_24m_fclk = {
 340         .name           = "abe_24m_fclk",
 341         .parent         = &dpll_abe_m2x2_ck,
 342         .ops            = &clkops_null,
 343         .fixed_div      = 8,
 344         .recalc         = &omap_fixed_divisor_recalc,
 345 };
 346
 347 static const struct clksel_rate div3_1to4_rates[] = {
 348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 351         { .div = 0 },
 352 };
 353
 354 static const struct clksel abe_clk_div[] = {
 355         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 356         { .parent = NULL },
 357 };
 358
 359 static struct clk abe_clk = {
 360         .name           = "abe_clk",
 361         .parent         = &dpll_abe_m2x2_ck,
 362         .clksel         = abe_clk_div,
 363         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 364         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 365         .ops            = &clkops_null,
 366         .recalc         = &omap2_clksel_recalc,
 367         .round_rate     = &omap2_clksel_round_rate,
 368         .set_rate       = &omap2_clksel_set_rate,
 369 };
 370
 371 static const struct clksel_rate div2_1to2_rates[] = {
 372         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 373         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 374         { .div = 0 },
 375 };
 376
 377 static const struct clksel aess_fclk_div[] = {
 378         { .parent = &abe_clk, .rates = div2_1to2_rates },
 379         { .parent = NULL },
 380 };
 381
 382 static struct clk aess_fclk = {
 383         .name           = "aess_fclk",
 384         .parent         = &abe_clk,
 385         .clksel         = aess_fclk_div,
 386         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 387         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 388         .ops            = &clkops_null,
 389         .recalc         = &omap2_clksel_recalc,
 390         .round_rate     = &omap2_clksel_round_rate,
 391         .set_rate       = &omap2_clksel_set_rate,
 392 };
 393
 394 static struct clk dpll_abe_m3x2_ck = {
 395         .name           = "dpll_abe_m3x2_ck",
 396         .parent         = &dpll_abe_x2_ck,
 397         .clksel         = dpll_abe_m2x2_div,
 398         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 399         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 400         .ops            = &clkops_omap4_dpllmx_ops,
 401         .recalc         = &omap2_clksel_recalc,
 402         .round_rate     = &omap2_clksel_round_rate,
 403         .set_rate       = &omap2_clksel_set_rate,
 404 };
 405
 406 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 407         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 408         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 409         { .parent = NULL },
 410 };
 411
 412 static struct clk core_hsd_byp_clk_mux_ck = {
 413         .name           = "core_hsd_byp_clk_mux_ck",
 414         .parent         = &sys_clkin_ck,
 415         .clksel         = core_hsd_byp_clk_mux_sel,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 418         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 419         .ops            = &clkops_null,
 420         .recalc         = &omap2_clksel_recalc,
 421 };
 422
 423 /* DPLL_CORE */
 424 static struct dpll_data dpll_core_dd = {
 425         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 426         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 427         .clk_ref        = &sys_clkin_ck,
 428         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 429         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 430         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 431         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 432         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 433         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 434         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 435         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 436         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 437         .max_multiplier = 2047,
 438         .max_divider    = 128,
 439         .min_divider    = 1,
 440 };
 441
 442
 443 static struct clk dpll_core_ck = {
 444         .name           = "dpll_core_ck",
 445         .parent         = &sys_clkin_ck,
 446         .dpll_data      = &dpll_core_dd,
 447         .init           = &omap2_init_dpll_parent,
 448         .ops            = &clkops_omap3_core_dpll_ops,
 449         .recalc         = &omap3_dpll_recalc,
 450 };
 451
 452 static struct clk dpll_core_x2_ck = {
 453         .name           = "dpll_core_x2_ck",
 454         .parent         = &dpll_core_ck,
 455         .flags          = CLOCK_CLKOUTX2,
 456         .ops            = &clkops_null,
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel dpll_core_m6x2_div[] = {
 461         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 462         { .parent = NULL },
 463 };
 464
 465 static struct clk dpll_core_m6x2_ck = {
 466         .name           = "dpll_core_m6x2_ck",
 467         .parent         = &dpll_core_x2_ck,
 468         .clksel         = dpll_core_m6x2_div,
 469         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 470         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 471         .ops            = &clkops_omap4_dpllmx_ops,
 472         .recalc         = &omap2_clksel_recalc,
 473         .round_rate     = &omap2_clksel_round_rate,
 474         .set_rate       = &omap2_clksel_set_rate,
 475 };
 476
 477 static const struct clksel dbgclk_mux_sel[] = {
 478         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 479         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 480         { .parent = NULL },
 481 };
 482
 483 static struct clk dbgclk_mux_ck = {
 484         .name           = "dbgclk_mux_ck",
 485         .parent         = &sys_clkin_ck,
 486         .ops            = &clkops_null,
 487         .recalc         = &followparent_recalc,
 488 };
 489
 490 static const struct clksel dpll_core_m2_div[] = {
 491         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 492         { .parent = NULL },
 493 };
 494
 495 static struct clk dpll_core_m2_ck = {
 496         .name           = "dpll_core_m2_ck",
 497         .parent         = &dpll_core_ck,
 498         .clksel         = dpll_core_m2_div,
 499         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 500         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 501         .ops            = &clkops_omap4_dpllmx_ops,
 502         .recalc         = &omap2_clksel_recalc,
 503         .round_rate     = &omap2_clksel_round_rate,
 504         .set_rate       = &omap2_clksel_set_rate,
 505 };
 506
 507 static struct clk ddrphy_ck = {
 508         .name           = "ddrphy_ck",
 509         .parent         = &dpll_core_m2_ck,
 510         .ops            = &clkops_null,
 511         .fixed_div      = 2,
 512         .recalc         = &omap_fixed_divisor_recalc,
 513 };
 514
 515 static struct clk dpll_core_m5x2_ck = {
 516         .name           = "dpll_core_m5x2_ck",
 517         .parent         = &dpll_core_x2_ck,
 518         .clksel         = dpll_core_m6x2_div,
 519         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 520         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 521         .ops            = &clkops_omap4_dpllmx_ops,
 522         .recalc         = &omap2_clksel_recalc,
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap2_clksel_set_rate,
 525 };
 526
 527 static const struct clksel div_core_div[] = {
 528         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 529         { .parent = NULL },
 530 };
 531
 532 static struct clk div_core_ck = {
 533         .name           = "div_core_ck",
 534         .parent         = &dpll_core_m5x2_ck,
 535         .clksel         = div_core_div,
 536         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 537         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 538         .ops            = &clkops_null,
 539         .recalc         = &omap2_clksel_recalc,
 540         .round_rate     = &omap2_clksel_round_rate,
 541         .set_rate       = &omap2_clksel_set_rate,
 542 };
 543
 544 static const struct clksel_rate div4_1to8_rates[] = {
 545         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 546         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 547         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 548         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 549         { .div = 0 },
 550 };
 551
 552 static const struct clksel div_iva_hs_clk_div[] = {
 553         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 554         { .parent = NULL },
 555 };
 556
 557 static struct clk div_iva_hs_clk = {
 558         .name           = "div_iva_hs_clk",
 559         .parent         = &dpll_core_m5x2_ck,
 560         .clksel         = div_iva_hs_clk_div,
 561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 563         .ops            = &clkops_null,
 564         .recalc         = &omap2_clksel_recalc,
 565         .round_rate     = &omap2_clksel_round_rate,
 566         .set_rate       = &omap2_clksel_set_rate,
 567 };
 568
 569 static struct clk div_mpu_hs_clk = {
 570         .name           = "div_mpu_hs_clk",
 571         .parent         = &dpll_core_m5x2_ck,
 572         .clksel         = div_iva_hs_clk_div,
 573         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 574         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 575         .ops            = &clkops_null,
 576         .recalc         = &omap2_clksel_recalc,
 577         .round_rate     = &omap2_clksel_round_rate,
 578         .set_rate       = &omap2_clksel_set_rate,
 579 };
 580
 581 static struct clk dpll_core_m4x2_ck = {
 582         .name           = "dpll_core_m4x2_ck",
 583         .parent         = &dpll_core_x2_ck,
 584         .clksel         = dpll_core_m6x2_div,
 585         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 586         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 587         .ops            = &clkops_omap4_dpllmx_ops,
 588         .recalc         = &omap2_clksel_recalc,
 589         .round_rate     = &omap2_clksel_round_rate,
 590         .set_rate       = &omap2_clksel_set_rate,
 591 };
 592
 593 static struct clk dll_clk_div_ck = {
 594         .name           = "dll_clk_div_ck",
 595         .parent         = &dpll_core_m4x2_ck,
 596         .ops            = &clkops_null,
 597         .fixed_div      = 2,
 598         .recalc         = &omap_fixed_divisor_recalc,
 599 };
 600
 601 static const struct clksel dpll_abe_m2_div[] = {
 602         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 603         { .parent = NULL },
 604 };
 605
 606 static struct clk dpll_abe_m2_ck = {
 607         .name           = "dpll_abe_m2_ck",
 608         .parent         = &dpll_abe_ck,
 609         .clksel         = dpll_abe_m2_div,
 610         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 611         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 612         .ops            = &clkops_omap4_dpllmx_ops,
 613         .recalc         = &omap2_clksel_recalc,
 614         .round_rate     = &omap2_clksel_round_rate,
 615         .set_rate       = &omap2_clksel_set_rate,
 616 };
 617
 618 static struct clk dpll_core_m3x2_ck = {
 619         .name           = "dpll_core_m3x2_ck",
 620         .parent         = &dpll_core_x2_ck,
 621         .clksel         = dpll_core_m6x2_div,
 622         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 623         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 624         .ops            = &clkops_omap2_dflt,
 625         .recalc         = &omap2_clksel_recalc,
 626         .round_rate     = &omap2_clksel_round_rate,
 627         .set_rate       = &omap2_clksel_set_rate,
 628         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 629         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 630 };
 631
 632 static struct clk dpll_core_m7x2_ck = {
 633         .name           = "dpll_core_m7x2_ck",
 634         .parent         = &dpll_core_x2_ck,
 635         .clksel         = dpll_core_m6x2_div,
 636         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 637         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 638         .ops            = &clkops_omap4_dpllmx_ops,
 639         .recalc         = &omap2_clksel_recalc,
 640         .round_rate     = &omap2_clksel_round_rate,
 641         .set_rate       = &omap2_clksel_set_rate,
 642 };
 643
 644 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 645         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 646         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 647         { .parent = NULL },
 648 };
 649
 650 static struct clk iva_hsd_byp_clk_mux_ck = {
 651         .name           = "iva_hsd_byp_clk_mux_ck",
 652         .parent         = &sys_clkin_ck,
 653         .clksel         = iva_hsd_byp_clk_mux_sel,
 654         .init           = &omap2_init_clksel_parent,
 655         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 656         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 657         .ops            = &clkops_null,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 /* DPLL_IVA */
 662 static struct dpll_data dpll_iva_dd = {
 663         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 664         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 665         .clk_ref        = &sys_clkin_ck,
 666         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 667         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 668         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 669         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 670         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 671         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 672         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 673         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 674         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 675         .max_multiplier = 2047,
 676         .max_divider    = 128,
 677         .min_divider    = 1,
 678 };
 679
 680
 681 static struct clk dpll_iva_ck = {
 682         .name           = "dpll_iva_ck",
 683         .parent         = &sys_clkin_ck,
 684         .dpll_data      = &dpll_iva_dd,
 685         .init           = &omap2_init_dpll_parent,
 686         .ops            = &clkops_omap3_noncore_dpll_ops,
 687         .recalc         = &omap3_dpll_recalc,
 688         .round_rate     = &omap2_dpll_round_rate,
 689         .set_rate       = &omap3_noncore_dpll_set_rate,
 690 };
 691
 692 static struct clk dpll_iva_x2_ck = {
 693         .name           = "dpll_iva_x2_ck",
 694         .parent         = &dpll_iva_ck,
 695         .flags          = CLOCK_CLKOUTX2,
 696         .ops            = &clkops_null,
 697         .recalc         = &omap3_clkoutx2_recalc,
 698 };
 699
 700 static const struct clksel dpll_iva_m4x2_div[] = {
 701         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 702         { .parent = NULL },
 703 };
 704
 705 static struct clk dpll_iva_m4x2_ck = {
 706         .name           = "dpll_iva_m4x2_ck",
 707         .parent         = &dpll_iva_x2_ck,
 708         .clksel         = dpll_iva_m4x2_div,
 709         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 710         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 711         .ops            = &clkops_omap4_dpllmx_ops,
 712         .recalc         = &omap2_clksel_recalc,
 713         .round_rate     = &omap2_clksel_round_rate,
 714         .set_rate       = &omap2_clksel_set_rate,
 715 };
 716
 717 static struct clk dpll_iva_m5x2_ck = {
 718         .name           = "dpll_iva_m5x2_ck",
 719         .parent         = &dpll_iva_x2_ck,
 720         .clksel         = dpll_iva_m4x2_div,
 721         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 722         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 723         .ops            = &clkops_omap4_dpllmx_ops,
 724         .recalc         = &omap2_clksel_recalc,
 725         .round_rate     = &omap2_clksel_round_rate,
 726         .set_rate       = &omap2_clksel_set_rate,
 727 };
 728
 729 /* DPLL_MPU */
 730 static struct dpll_data dpll_mpu_dd = {
 731         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 732         .clk_bypass     = &div_mpu_hs_clk,
 733         .clk_ref        = &sys_clkin_ck,
 734         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 735         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 736         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 737         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 738         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 739         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 740         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 741         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 742         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 743         .max_multiplier = 2047,
 744         .max_divider    = 128,
 745         .min_divider    = 1,
 746 };
 747
 748
 749 static struct clk dpll_mpu_ck = {
 750         .name           = "dpll_mpu_ck",
 751         .parent         = &sys_clkin_ck,
 752         .dpll_data      = &dpll_mpu_dd,
 753         .init           = &omap2_init_dpll_parent,
 754         .ops            = &clkops_omap3_noncore_dpll_ops,
 755         .recalc         = &omap3_dpll_recalc,
 756         .round_rate     = &omap2_dpll_round_rate,
 757         .set_rate       = &omap3_noncore_dpll_set_rate,
 758 };
 759
 760 static const struct clksel dpll_mpu_m2_div[] = {
 761         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 762         { .parent = NULL },
 763 };
 764
 765 static struct clk dpll_mpu_m2_ck = {
 766         .name           = "dpll_mpu_m2_ck",
 767         .parent         = &dpll_mpu_ck,
 768         .clksel         = dpll_mpu_m2_div,
 769         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 770         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 771         .ops            = &clkops_omap4_dpllmx_ops,
 772         .recalc         = &omap2_clksel_recalc,
 773         .round_rate     = &omap2_clksel_round_rate,
 774         .set_rate       = &omap2_clksel_set_rate,
 775 };
 776
 777 static struct clk per_hs_clk_div_ck = {
 778         .name           = "per_hs_clk_div_ck",
 779         .parent         = &dpll_abe_m3x2_ck,
 780         .ops            = &clkops_null,
 781         .fixed_div      = 2,
 782         .recalc         = &omap_fixed_divisor_recalc,
 783 };
 784
 785 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 786         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 787         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 788         { .parent = NULL },
 789 };
 790
 791 static struct clk per_hsd_byp_clk_mux_ck = {
 792         .name           = "per_hsd_byp_clk_mux_ck",
 793         .parent         = &sys_clkin_ck,
 794         .clksel         = per_hsd_byp_clk_mux_sel,
 795         .init           = &omap2_init_clksel_parent,
 796         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 797         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 798         .ops            = &clkops_null,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 /* DPLL_PER */
 803 static struct dpll_data dpll_per_dd = {
 804         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 805         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 806         .clk_ref        = &sys_clkin_ck,
 807         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 808         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 809         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 810         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 811         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 812         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 813         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 814         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 815         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 816         .max_multiplier = 2047,
 817         .max_divider    = 128,
 818         .min_divider    = 1,
 819 };
 820
 821
 822 static struct clk dpll_per_ck = {
 823         .name           = "dpll_per_ck",
 824         .parent         = &sys_clkin_ck,
 825         .dpll_data      = &dpll_per_dd,
 826         .init           = &omap2_init_dpll_parent,
 827         .ops            = &clkops_omap3_noncore_dpll_ops,
 828         .recalc         = &omap3_dpll_recalc,
 829         .round_rate     = &omap2_dpll_round_rate,
 830         .set_rate       = &omap3_noncore_dpll_set_rate,
 831 };
 832
 833 static const struct clksel dpll_per_m2_div[] = {
 834         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 835         { .parent = NULL },
 836 };
 837
 838 static struct clk dpll_per_m2_ck = {
 839         .name           = "dpll_per_m2_ck",
 840         .parent         = &dpll_per_ck,
 841         .clksel         = dpll_per_m2_div,
 842         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 843         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 844         .ops            = &clkops_omap4_dpllmx_ops,
 845         .recalc         = &omap2_clksel_recalc,
 846         .round_rate     = &omap2_clksel_round_rate,
 847         .set_rate       = &omap2_clksel_set_rate,
 848 };
 849
 850 static struct clk dpll_per_x2_ck = {
 851         .name           = "dpll_per_x2_ck",
 852         .parent         = &dpll_per_ck,
 853         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 854         .flags          = CLOCK_CLKOUTX2,
 855         .ops            = &clkops_omap4_dpllmx_ops,
 856         .recalc         = &omap3_clkoutx2_recalc,
 857 };
 858
 859 static const struct clksel dpll_per_m2x2_div[] = {
 860         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 861         { .parent = NULL },
 862 };
 863
 864 static struct clk dpll_per_m2x2_ck = {
 865         .name           = "dpll_per_m2x2_ck",
 866         .parent         = &dpll_per_x2_ck,
 867         .clksel         = dpll_per_m2x2_div,
 868         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 869         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 870         .ops            = &clkops_omap4_dpllmx_ops,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate,
 874 };
 875
 876 static struct clk dpll_per_m3x2_ck = {
 877         .name           = "dpll_per_m3x2_ck",
 878         .parent         = &dpll_per_x2_ck,
 879         .clksel         = dpll_per_m2x2_div,
 880         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 881         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 882         .ops            = &clkops_omap2_dflt,
 883         .recalc         = &omap2_clksel_recalc,
 884         .round_rate     = &omap2_clksel_round_rate,
 885         .set_rate       = &omap2_clksel_set_rate,
 886         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 887         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 888 };
 889
 890 static struct clk dpll_per_m4x2_ck = {
 891         .name           = "dpll_per_m4x2_ck",
 892         .parent         = &dpll_per_x2_ck,
 893         .clksel         = dpll_per_m2x2_div,
 894         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 896         .ops            = &clkops_omap4_dpllmx_ops,
 897         .recalc         = &omap2_clksel_recalc,
 898         .round_rate     = &omap2_clksel_round_rate,
 899         .set_rate       = &omap2_clksel_set_rate,
 900 };
 901
 902 static struct clk dpll_per_m5x2_ck = {
 903         .name           = "dpll_per_m5x2_ck",
 904         .parent         = &dpll_per_x2_ck,
 905         .clksel         = dpll_per_m2x2_div,
 906         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 907         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 908         .ops            = &clkops_omap4_dpllmx_ops,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate,
 912 };
 913
 914 static struct clk dpll_per_m6x2_ck = {
 915         .name           = "dpll_per_m6x2_ck",
 916         .parent         = &dpll_per_x2_ck,
 917         .clksel         = dpll_per_m2x2_div,
 918         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 919         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 920         .ops            = &clkops_omap4_dpllmx_ops,
 921         .recalc         = &omap2_clksel_recalc,
 922         .round_rate     = &omap2_clksel_round_rate,
 923         .set_rate       = &omap2_clksel_set_rate,
 924 };
 925
 926 static struct clk dpll_per_m7x2_ck = {
 927         .name           = "dpll_per_m7x2_ck",
 928         .parent         = &dpll_per_x2_ck,
 929         .clksel         = dpll_per_m2x2_div,
 930         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 931         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 932         .ops            = &clkops_omap4_dpllmx_ops,
 933         .recalc         = &omap2_clksel_recalc,
 934         .round_rate     = &omap2_clksel_round_rate,
 935         .set_rate       = &omap2_clksel_set_rate,
 936 };
 937
 938 /* DPLL_UNIPRO */
 939 static struct dpll_data dpll_unipro_dd = {
 940         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 941         .clk_bypass     = &sys_clkin_ck,
 942         .clk_ref        = &sys_clkin_ck,
 943         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 944         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 945         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 946         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 947         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 948         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 949         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 950         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 951         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 952         .max_multiplier = 2047,
 953         .max_divider    = 128,
 954         .min_divider    = 1,
 955 };
 956
 957
 958 static struct clk dpll_unipro_ck = {
 959         .name           = "dpll_unipro_ck",
 960         .parent         = &sys_clkin_ck,
 961         .dpll_data      = &dpll_unipro_dd,
 962         .init           = &omap2_init_dpll_parent,
 963         .ops            = &clkops_omap3_noncore_dpll_ops,
 964         .recalc         = &omap3_dpll_recalc,
 965         .round_rate     = &omap2_dpll_round_rate,
 966         .set_rate       = &omap3_noncore_dpll_set_rate,
 967 };
 968
 969 static struct clk dpll_unipro_x2_ck = {
 970         .name           = "dpll_unipro_x2_ck",
 971         .parent         = &dpll_unipro_ck,
 972         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 973         .flags          = CLOCK_CLKOUTX2,
 974         .ops            = &clkops_omap4_dpllmx_ops,
 975         .recalc         = &omap3_clkoutx2_recalc,
 976 };
 977
 978 static const struct clksel dpll_unipro_m2x2_div[] = {
 979         { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
 980         { .parent = NULL },
 981 };
 982
 983 static struct clk dpll_unipro_m2x2_ck = {
 984         .name           = "dpll_unipro_m2x2_ck",
 985         .parent         = &dpll_unipro_x2_ck,
 986         .clksel         = dpll_unipro_m2x2_div,
 987         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 988         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 989         .ops            = &clkops_omap4_dpllmx_ops,
 990         .recalc         = &omap2_clksel_recalc,
 991         .round_rate     = &omap2_clksel_round_rate,
 992         .set_rate       = &omap2_clksel_set_rate,
 993 };
 994
 995 static struct clk usb_hs_clk_div_ck = {
 996         .name           = "usb_hs_clk_div_ck",
 997         .parent         = &dpll_abe_m3x2_ck,
 998         .ops            = &clkops_null,
 999         .fixed_div      = 3,
1000         .recalc         = &omap_fixed_divisor_recalc,
1001 };
1002
1003 /* DPLL_USB */
1004 static struct dpll_data dpll_usb_dd = {
1005         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
1006         .clk_bypass     = &usb_hs_clk_div_ck,
1007         .flags          = DPLL_J_TYPE,
1008         .clk_ref        = &sys_clkin_ck,
1009         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
1010         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1011         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1012         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1013         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1014         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1015         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1016         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1017         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1018         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
1019         .max_multiplier = 4095,
1020         .max_divider    = 256,
1021         .min_divider    = 1,
1022 };
1023
1024
1025 static struct clk dpll_usb_ck = {
1026         .name           = "dpll_usb_ck",
1027         .parent         = &sys_clkin_ck,
1028         .dpll_data      = &dpll_usb_dd,
1029         .init           = &omap2_init_dpll_parent,
1030         .ops            = &clkops_omap3_noncore_dpll_ops,
1031         .recalc         = &omap3_dpll_recalc,
1032         .round_rate     = &omap2_dpll_round_rate,
1033         .set_rate       = &omap3_noncore_dpll_set_rate,
1034 };
1035
1036 static struct clk dpll_usb_clkdcoldo_ck = {
1037         .name           = "dpll_usb_clkdcoldo_ck",
1038         .parent         = &dpll_usb_ck,
1039         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
1040         .ops            = &clkops_omap4_dpllmx_ops,
1041         .recalc         = &followparent_recalc,
1042 };
1043
1044 static const struct clksel dpll_usb_m2_div[] = {
1045         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1046         { .parent = NULL },
1047 };
1048
1049 static struct clk dpll_usb_m2_ck = {
1050         .name           = "dpll_usb_m2_ck",
1051         .parent         = &dpll_usb_ck,
1052         .clksel         = dpll_usb_m2_div,
1053         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1054         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1055         .ops            = &clkops_omap4_dpllmx_ops,
1056         .recalc         = &omap2_clksel_recalc,
1057         .round_rate     = &omap2_clksel_round_rate,
1058         .set_rate       = &omap2_clksel_set_rate,
1059 };
1060
1061 static const struct clksel ducati_clk_mux_sel[] = {
1062         { .parent = &div_core_ck, .rates = div_1_0_rates },
1063         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1064         { .parent = NULL },
1065 };
1066
1067 static struct clk ducati_clk_mux_ck = {
1068         .name           = "ducati_clk_mux_ck",
1069         .parent         = &div_core_ck,
1070         .clksel         = ducati_clk_mux_sel,
1071         .init           = &omap2_init_clksel_parent,
1072         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1073         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1074         .ops            = &clkops_null,
1075         .recalc         = &omap2_clksel_recalc,
1076 };
1077
1078 static struct clk func_12m_fclk = {
1079         .name           = "func_12m_fclk",
1080         .parent         = &dpll_per_m2x2_ck,
1081         .ops            = &clkops_null,
1082         .fixed_div      = 16,
1083         .recalc         = &omap_fixed_divisor_recalc,
1084 };
1085
1086 static struct clk func_24m_clk = {
1087         .name           = "func_24m_clk",
1088         .parent         = &dpll_per_m2_ck,
1089         .ops            = &clkops_null,
1090         .fixed_div      = 4,
1091         .recalc         = &omap_fixed_divisor_recalc,
1092 };
1093
1094 static struct clk func_24mc_fclk = {
1095         .name           = "func_24mc_fclk",
1096         .parent         = &dpll_per_m2x2_ck,
1097         .ops            = &clkops_null,
1098         .fixed_div      = 8,
1099         .recalc         = &omap_fixed_divisor_recalc,
1100 };
1101
1102 static const struct clksel_rate div2_4to8_rates[] = {
1103         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1104         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1105         { .div = 0 },
1106 };
1107
1108 static const struct clksel func_48m_fclk_div[] = {
1109         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1110         { .parent = NULL },
1111 };
1112
1113 static struct clk func_48m_fclk = {
1114         .name           = "func_48m_fclk",
1115         .parent         = &dpll_per_m2x2_ck,
1116         .clksel         = func_48m_fclk_div,
1117         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1118         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1119         .ops            = &clkops_null,
1120         .recalc         = &omap2_clksel_recalc,
1121         .round_rate     = &omap2_clksel_round_rate,
1122         .set_rate       = &omap2_clksel_set_rate,
1123 };
1124
1125 static struct clk func_48mc_fclk = {
1126         .name           = "func_48mc_fclk",
1127         .parent         = &dpll_per_m2x2_ck,
1128         .ops            = &clkops_null,
1129         .fixed_div      = 4,
1130         .recalc         = &omap_fixed_divisor_recalc,
1131 };
1132
1133 static const struct clksel_rate div2_2to4_rates[] = {
1134         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1135         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1136         { .div = 0 },
1137 };
1138
1139 static const struct clksel func_64m_fclk_div[] = {
1140         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1141         { .parent = NULL },
1142 };
1143
1144 static struct clk func_64m_fclk = {
1145         .name           = "func_64m_fclk",
1146         .parent         = &dpll_per_m4x2_ck,
1147         .clksel         = func_64m_fclk_div,
1148         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1149         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1150         .ops            = &clkops_null,
1151         .recalc         = &omap2_clksel_recalc,
1152         .round_rate     = &omap2_clksel_round_rate,
1153         .set_rate       = &omap2_clksel_set_rate,
1154 };
1155
1156 static const struct clksel func_96m_fclk_div[] = {
1157         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1158         { .parent = NULL },
1159 };
1160
1161 static struct clk func_96m_fclk = {
1162         .name           = "func_96m_fclk",
1163         .parent         = &dpll_per_m2x2_ck,
1164         .clksel         = func_96m_fclk_div,
1165         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1166         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1167         .ops            = &clkops_null,
1168         .recalc         = &omap2_clksel_recalc,
1169         .round_rate     = &omap2_clksel_round_rate,
1170         .set_rate       = &omap2_clksel_set_rate,
1171 };
1172
1173 static const struct clksel_rate div2_1to8_rates[] = {
1174         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1175         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1176         { .div = 0 },
1177 };
1178
1179 static const struct clksel init_60m_fclk_div[] = {
1180         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1181         { .parent = NULL },
1182 };
1183
1184 static struct clk init_60m_fclk = {
1185         .name           = "init_60m_fclk",
1186         .parent         = &dpll_usb_m2_ck,
1187         .clksel         = init_60m_fclk_div,
1188         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1189         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1190         .ops            = &clkops_null,
1191         .recalc         = &omap2_clksel_recalc,
1192         .round_rate     = &omap2_clksel_round_rate,
1193         .set_rate       = &omap2_clksel_set_rate,
1194 };
1195
1196 static const struct clksel l3_div_div[] = {
1197         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1198         { .parent = NULL },
1199 };
1200
1201 static struct clk l3_div_ck = {
1202         .name           = "l3_div_ck",
1203         .parent         = &div_core_ck,
1204         .clksel         = l3_div_div,
1205         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1206         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1207         .ops            = &clkops_null,
1208         .recalc         = &omap2_clksel_recalc,
1209         .round_rate     = &omap2_clksel_round_rate,
1210         .set_rate       = &omap2_clksel_set_rate,
1211 };
1212
1213 static const struct clksel l4_div_div[] = {
1214         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1215         { .parent = NULL },
1216 };
1217
1218 static struct clk l4_div_ck = {
1219         .name           = "l4_div_ck",
1220         .parent         = &l3_div_ck,
1221         .clksel         = l4_div_div,
1222         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1223         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1224         .ops            = &clkops_null,
1225         .recalc         = &omap2_clksel_recalc,
1226         .round_rate     = &omap2_clksel_round_rate,
1227         .set_rate       = &omap2_clksel_set_rate,
1228 };
1229
1230 static struct clk lp_clk_div_ck = {
1231         .name           = "lp_clk_div_ck",
1232         .parent         = &dpll_abe_m2x2_ck,
1233         .ops            = &clkops_null,
1234         .fixed_div      = 16,
1235         .recalc         = &omap_fixed_divisor_recalc,
1236 };
1237
1238 static const struct clksel l4_wkup_clk_mux_sel[] = {
1239         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1240         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1241         { .parent = NULL },
1242 };
1243
1244 static struct clk l4_wkup_clk_mux_ck = {
1245         .name           = "l4_wkup_clk_mux_ck",
1246         .parent         = &sys_clkin_ck,
1247         .clksel         = l4_wkup_clk_mux_sel,
1248         .init           = &omap2_init_clksel_parent,
1249         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1250         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1251         .ops            = &clkops_null,
1252         .recalc         = &omap2_clksel_recalc,
1253 };
1254
1255 static struct clk ocp_abe_iclk = {
1256         .name           = "ocp_abe_iclk",
1257         .parent         = &aess_fclk,
1258         .ops            = &clkops_null,
1259         .recalc         = &followparent_recalc,
1260 };
1261
1262 static struct clk per_abe_24m_fclk = {
1263         .name           = "per_abe_24m_fclk",
1264         .parent         = &dpll_abe_m2_ck,
1265         .ops            = &clkops_null,
1266         .fixed_div      = 4,
1267         .recalc         = &omap_fixed_divisor_recalc,
1268 };
1269
1270 static const struct clksel per_abe_nc_fclk_div[] = {
1271         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1272         { .parent = NULL },
1273 };
1274
1275 static struct clk per_abe_nc_fclk = {
1276         .name           = "per_abe_nc_fclk",
1277         .parent         = &dpll_abe_m2_ck,
1278         .clksel         = per_abe_nc_fclk_div,
1279         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1280         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1281         .ops            = &clkops_null,
1282         .recalc         = &omap2_clksel_recalc,
1283         .round_rate     = &omap2_clksel_round_rate,
1284         .set_rate       = &omap2_clksel_set_rate,
1285 };
1286
1287 static const struct clksel pmd_stm_clock_mux_sel[] = {
1288         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1289         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1290         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1291         { .parent = NULL },
1292 };
1293
1294 static struct clk pmd_stm_clock_mux_ck = {
1295         .name           = "pmd_stm_clock_mux_ck",
1296         .parent         = &sys_clkin_ck,
1297         .ops            = &clkops_null,
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 static struct clk pmd_trace_clk_mux_ck = {
1302         .name           = "pmd_trace_clk_mux_ck",
1303         .parent         = &sys_clkin_ck,
1304         .ops            = &clkops_null,
1305         .recalc         = &followparent_recalc,
1306 };
1307
1308 static const struct clksel syc_clk_div_div[] = {
1309         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1310         { .parent = NULL },
1311 };
1312
1313 static struct clk syc_clk_div_ck = {
1314         .name           = "syc_clk_div_ck",
1315         .parent         = &sys_clkin_ck,
1316         .clksel         = syc_clk_div_div,
1317         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1318         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1319         .ops            = &clkops_null,
1320         .recalc         = &omap2_clksel_recalc,
1321         .round_rate     = &omap2_clksel_round_rate,
1322         .set_rate       = &omap2_clksel_set_rate,
1323 };
1324
1325 /* Leaf clocks controlled by modules */
1326
1327 static struct clk aes1_fck = {
1328         .name           = "aes1_fck",
1329         .ops            = &clkops_omap2_dflt,
1330         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1331         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1332         .clkdm_name     = "l4_secure_clkdm",
1333         .parent         = &l3_div_ck,
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk aes2_fck = {
1338         .name           = "aes2_fck",
1339         .ops            = &clkops_omap2_dflt,
1340         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1341         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1342         .clkdm_name     = "l4_secure_clkdm",
1343         .parent         = &l3_div_ck,
1344         .recalc         = &followparent_recalc,
1345 };
1346
1347 static struct clk aess_fck = {
1348         .name           = "aess_fck",
1349         .ops            = &clkops_omap2_dflt,
1350         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1351         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1352         .clkdm_name     = "abe_clkdm",
1353         .parent         = &aess_fclk,
1354         .recalc         = &followparent_recalc,
1355 };
1356
1357 static struct clk bandgap_fclk = {
1358         .name           = "bandgap_fclk",
1359         .ops            = &clkops_omap2_dflt,
1360         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1361         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1362         .clkdm_name     = "l4_wkup_clkdm",
1363         .parent         = &sys_32k_ck,
1364         .recalc         = &followparent_recalc,
1365 };
1366
1367 static struct clk des3des_fck = {
1368         .name           = "des3des_fck",
1369         .ops            = &clkops_omap2_dflt,
1370         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1371         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1372         .clkdm_name     = "l4_secure_clkdm",
1373         .parent         = &l4_div_ck,
1374         .recalc         = &followparent_recalc,
1375 };
1376
1377 static const struct clksel dmic_sync_mux_sel[] = {
1378         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1379         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1380         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1381         { .parent = NULL },
1382 };
1383
1384 static struct clk dmic_sync_mux_ck = {
1385         .name           = "dmic_sync_mux_ck",
1386         .parent         = &abe_24m_fclk,
1387         .clksel         = dmic_sync_mux_sel,
1388         .init           = &omap2_init_clksel_parent,
1389         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1390         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1391         .ops            = &clkops_null,
1392         .recalc         = &omap2_clksel_recalc,
1393 };
1394
1395 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1396         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1397         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1398         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1399         { .parent = NULL },
1400 };
1401
1402 /* Merged func_dmic_abe_gfclk into dmic */
1403 static struct clk dmic_fck = {
1404         .name           = "dmic_fck",
1405         .parent         = &dmic_sync_mux_ck,
1406         .clksel         = func_dmic_abe_gfclk_sel,
1407         .init           = &omap2_init_clksel_parent,
1408         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1409         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1410         .ops            = &clkops_omap2_dflt,
1411         .recalc         = &omap2_clksel_recalc,
1412         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1413         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1414         .clkdm_name     = "abe_clkdm",
1415 };
1416
1417 static struct clk dsp_fck = {
1418         .name           = "dsp_fck",
1419         .ops            = &clkops_omap2_dflt,
1420         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1421         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1422         .clkdm_name     = "tesla_clkdm",
1423         .parent         = &dpll_iva_m4x2_ck,
1424         .recalc         = &followparent_recalc,
1425 };
1426
1427 static struct clk dss_sys_clk = {
1428         .name           = "dss_sys_clk",
1429         .ops            = &clkops_omap2_dflt,
1430         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1431         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1432         .clkdm_name     = "l3_dss_clkdm",
1433         .parent         = &syc_clk_div_ck,
1434         .recalc         = &followparent_recalc,
1435 };
1436
1437 static struct clk dss_tv_clk = {
1438         .name           = "dss_tv_clk",
1439         .ops            = &clkops_omap2_dflt,
1440         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1441         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1442         .clkdm_name     = "l3_dss_clkdm",
1443         .parent         = &extalt_clkin_ck,
1444         .recalc         = &followparent_recalc,
1445 };
1446
1447 static struct clk dss_dss_clk = {
1448         .name           = "dss_dss_clk",
1449         .ops            = &clkops_omap2_dflt,
1450         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1451         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1452         .clkdm_name     = "l3_dss_clkdm",
1453         .parent         = &dpll_per_m5x2_ck,
1454         .recalc         = &followparent_recalc,
1455 };
1456
1457 static struct clk dss_48mhz_clk = {
1458         .name           = "dss_48mhz_clk",
1459         .ops            = &clkops_omap2_dflt,
1460         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1461         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1462         .clkdm_name     = "l3_dss_clkdm",
1463         .parent         = &func_48mc_fclk,
1464         .recalc         = &followparent_recalc,
1465 };
1466
1467 static struct clk dss_fck = {
1468         .name           = "dss_fck",
1469         .ops            = &clkops_omap2_dflt,
1470         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1471         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1472         .clkdm_name     = "l3_dss_clkdm",
1473         .parent         = &l3_div_ck,
1474         .recalc         = &followparent_recalc,
1475 };
1476
1477 static struct clk efuse_ctrl_cust_fck = {
1478         .name           = "efuse_ctrl_cust_fck",
1479         .ops            = &clkops_omap2_dflt,
1480         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1481         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1482         .clkdm_name     = "l4_cefuse_clkdm",
1483         .parent         = &sys_clkin_ck,
1484         .recalc         = &followparent_recalc,
1485 };
1486
1487 static struct clk emif1_fck = {
1488         .name           = "emif1_fck",
1489         .ops            = &clkops_omap2_dflt,
1490         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1491         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1492         .flags          = ENABLE_ON_INIT,
1493         .clkdm_name     = "l3_emif_clkdm",
1494         .parent         = &ddrphy_ck,
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk emif2_fck = {
1499         .name           = "emif2_fck",
1500         .ops            = &clkops_omap2_dflt,
1501         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1502         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1503         .flags          = ENABLE_ON_INIT,
1504         .clkdm_name     = "l3_emif_clkdm",
1505         .parent         = &ddrphy_ck,
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static const struct clksel fdif_fclk_div[] = {
1510         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1511         { .parent = NULL },
1512 };
1513
1514 /* Merged fdif_fclk into fdif */
1515 static struct clk fdif_fck = {
1516         .name           = "fdif_fck",
1517         .parent         = &dpll_per_m4x2_ck,
1518         .clksel         = fdif_fclk_div,
1519         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1520         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1521         .ops            = &clkops_omap2_dflt,
1522         .recalc         = &omap2_clksel_recalc,
1523         .round_rate     = &omap2_clksel_round_rate,
1524         .set_rate       = &omap2_clksel_set_rate,
1525         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1526         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1527         .clkdm_name     = "iss_clkdm",
1528 };
1529
1530 static struct clk fpka_fck = {
1531         .name           = "fpka_fck",
1532         .ops            = &clkops_omap2_dflt,
1533         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1534         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1535         .clkdm_name     = "l4_secure_clkdm",
1536         .parent         = &l4_div_ck,
1537         .recalc         = &followparent_recalc,
1538 };
1539
1540 static struct clk gpio1_dbclk = {
1541         .name           = "gpio1_dbclk",
1542         .ops            = &clkops_omap2_dflt,
1543         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1544         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1545         .clkdm_name     = "l4_wkup_clkdm",
1546         .parent         = &sys_32k_ck,
1547         .recalc         = &followparent_recalc,
1548 };
1549
1550 static struct clk gpio1_ick = {
1551         .name           = "gpio1_ick",
1552         .ops            = &clkops_omap2_dflt,
1553         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1554         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1555         .clkdm_name     = "l4_wkup_clkdm",
1556         .parent         = &l4_wkup_clk_mux_ck,
1557         .recalc         = &followparent_recalc,
1558 };
1559
1560 static struct clk gpio2_dbclk = {
1561         .name           = "gpio2_dbclk",
1562         .ops            = &clkops_omap2_dflt,
1563         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1564         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1565         .clkdm_name     = "l4_per_clkdm",
1566         .parent         = &sys_32k_ck,
1567         .recalc         = &followparent_recalc,
1568 };
1569
1570 static struct clk gpio2_ick = {
1571         .name           = "gpio2_ick",
1572         .ops            = &clkops_omap2_dflt,
1573         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1574         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1575         .clkdm_name     = "l4_per_clkdm",
1576         .parent         = &l4_div_ck,
1577         .recalc         = &followparent_recalc,
1578 };
1579
1580 static struct clk gpio3_dbclk = {
1581         .name           = "gpio3_dbclk",
1582         .ops            = &clkops_omap2_dflt,
1583         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1584         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1585         .clkdm_name     = "l4_per_clkdm",
1586         .parent         = &sys_32k_ck,
1587         .recalc         = &followparent_recalc,
1588 };
1589
1590 static struct clk gpio3_ick = {
1591         .name           = "gpio3_ick",
1592         .ops            = &clkops_omap2_dflt,
1593         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1594         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1595         .clkdm_name     = "l4_per_clkdm",
1596         .parent         = &l4_div_ck,
1597         .recalc         = &followparent_recalc,
1598 };
1599
1600 static struct clk gpio4_dbclk = {
1601         .name           = "gpio4_dbclk",
1602         .ops            = &clkops_omap2_dflt,
1603         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1604         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1605         .clkdm_name     = "l4_per_clkdm",
1606         .parent         = &sys_32k_ck,
1607         .recalc         = &followparent_recalc,
1608 };
1609
1610 static struct clk gpio4_ick = {
1611         .name           = "gpio4_ick",
1612         .ops            = &clkops_omap2_dflt,
1613         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1614         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1615         .clkdm_name     = "l4_per_clkdm",
1616         .parent         = &l4_div_ck,
1617         .recalc         = &followparent_recalc,
1618 };
1619
1620 static struct clk gpio5_dbclk = {
1621         .name           = "gpio5_dbclk",
1622         .ops            = &clkops_omap2_dflt,
1623         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1624         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1625         .clkdm_name     = "l4_per_clkdm",
1626         .parent         = &sys_32k_ck,
1627         .recalc         = &followparent_recalc,
1628 };
1629
1630 static struct clk gpio5_ick = {
1631         .name           = "gpio5_ick",
1632         .ops            = &clkops_omap2_dflt,
1633         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1634         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1635         .clkdm_name     = "l4_per_clkdm",
1636         .parent         = &l4_div_ck,
1637         .recalc         = &followparent_recalc,
1638 };
1639
1640 static struct clk gpio6_dbclk = {
1641         .name           = "gpio6_dbclk",
1642         .ops            = &clkops_omap2_dflt,
1643         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1644         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1645         .clkdm_name     = "l4_per_clkdm",
1646         .parent         = &sys_32k_ck,
1647         .recalc         = &followparent_recalc,
1648 };
1649
1650 static struct clk gpio6_ick = {
1651         .name           = "gpio6_ick",
1652         .ops            = &clkops_omap2_dflt,
1653         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1654         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1655         .clkdm_name     = "l4_per_clkdm",
1656         .parent         = &l4_div_ck,
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 static struct clk gpmc_ick = {
1661         .name           = "gpmc_ick",
1662         .ops            = &clkops_omap2_dflt,
1663         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1664         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1665         .clkdm_name     = "l3_2_clkdm",
1666         .parent         = &l3_div_ck,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static const struct clksel sgx_clk_mux_sel[] = {
1671         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1672         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1673         { .parent = NULL },
1674 };
1675
1676 /* Merged sgx_clk_mux into gpu */
1677 static struct clk gpu_fck = {
1678         .name           = "gpu_fck",
1679         .parent         = &dpll_core_m7x2_ck,
1680         .clksel         = sgx_clk_mux_sel,
1681         .init           = &omap2_init_clksel_parent,
1682         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1683         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1684         .ops            = &clkops_omap2_dflt,
1685         .recalc         = &omap2_clksel_recalc,
1686         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1687         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1688         .clkdm_name     = "l3_gfx_clkdm",
1689 };
1690
1691 static struct clk hdq1w_fck = {
1692         .name           = "hdq1w_fck",
1693         .ops            = &clkops_omap2_dflt,
1694         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1695         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1696         .clkdm_name     = "l4_per_clkdm",
1697         .parent         = &func_12m_fclk,
1698         .recalc         = &followparent_recalc,
1699 };
1700
1701 static const struct clksel hsi_fclk_div[] = {
1702         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1703         { .parent = NULL },
1704 };
1705
1706 /* Merged hsi_fclk into hsi */
1707 static struct clk hsi_fck = {
1708         .name           = "hsi_fck",
1709         .parent         = &dpll_per_m2x2_ck,
1710         .clksel         = hsi_fclk_div,
1711         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1712         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1713         .ops            = &clkops_omap2_dflt,
1714         .recalc         = &omap2_clksel_recalc,
1715         .round_rate     = &omap2_clksel_round_rate,
1716         .set_rate       = &omap2_clksel_set_rate,
1717         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1718         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1719         .clkdm_name     = "l3_init_clkdm",
1720 };
1721
1722 static struct clk i2c1_fck = {
1723         .name           = "i2c1_fck",
1724         .ops            = &clkops_omap2_dflt,
1725         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1726         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1727         .clkdm_name     = "l4_per_clkdm",
1728         .parent         = &func_96m_fclk,
1729         .recalc         = &followparent_recalc,
1730 };
1731
1732 static struct clk i2c2_fck = {
1733         .name           = "i2c2_fck",
1734         .ops            = &clkops_omap2_dflt,
1735         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1736         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1737         .clkdm_name     = "l4_per_clkdm",
1738         .parent         = &func_96m_fclk,
1739         .recalc         = &followparent_recalc,
1740 };
1741
1742 static struct clk i2c3_fck = {
1743         .name           = "i2c3_fck",
1744         .ops            = &clkops_omap2_dflt,
1745         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1746         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1747         .clkdm_name     = "l4_per_clkdm",
1748         .parent         = &func_96m_fclk,
1749         .recalc         = &followparent_recalc,
1750 };
1751
1752 static struct clk i2c4_fck = {
1753         .name           = "i2c4_fck",
1754         .ops            = &clkops_omap2_dflt,
1755         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1756         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1757         .clkdm_name     = "l4_per_clkdm",
1758         .parent         = &func_96m_fclk,
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 static struct clk ipu_fck = {
1763         .name           = "ipu_fck",
1764         .ops            = &clkops_omap2_dflt,
1765         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1766         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1767         .clkdm_name     = "ducati_clkdm",
1768         .parent         = &ducati_clk_mux_ck,
1769         .recalc         = &followparent_recalc,
1770 };
1771
1772 static struct clk iss_ctrlclk = {
1773         .name           = "iss_ctrlclk",
1774         .ops            = &clkops_omap2_dflt,
1775         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1776         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1777         .clkdm_name     = "iss_clkdm",
1778         .parent         = &func_96m_fclk,
1779         .recalc         = &followparent_recalc,
1780 };
1781
1782 static struct clk iss_fck = {
1783         .name           = "iss_fck",
1784         .ops            = &clkops_omap2_dflt,
1785         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1786         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1787         .clkdm_name     = "iss_clkdm",
1788         .parent         = &ducati_clk_mux_ck,
1789         .recalc         = &followparent_recalc,
1790 };
1791
1792 static struct clk iva_fck = {
1793         .name           = "iva_fck",
1794         .ops            = &clkops_omap2_dflt,
1795         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1796         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1797         .clkdm_name     = "ivahd_clkdm",
1798         .parent         = &dpll_iva_m5x2_ck,
1799         .recalc         = &followparent_recalc,
1800 };
1801
1802 static struct clk kbd_fck = {
1803         .name           = "kbd_fck",
1804         .ops            = &clkops_omap2_dflt,
1805         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1806         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1807         .clkdm_name     = "l4_wkup_clkdm",
1808         .parent         = &sys_32k_ck,
1809         .recalc         = &followparent_recalc,
1810 };
1811
1812 static struct clk l3_instr_ick = {
1813         .name           = "l3_instr_ick",
1814         .ops            = &clkops_omap2_dflt,
1815         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1816         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1817         .flags          = ENABLE_ON_INIT,
1818         .clkdm_name     = "l3_instr_clkdm",
1819         .parent         = &l3_div_ck,
1820         .recalc         = &followparent_recalc,
1821 };
1822
1823 static struct clk l3_main_3_ick = {
1824         .name           = "l3_main_3_ick",
1825         .ops            = &clkops_omap2_dflt,
1826         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1827         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1828         .flags          = ENABLE_ON_INIT,
1829         .clkdm_name     = "l3_instr_clkdm",
1830         .parent         = &l3_div_ck,
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 static struct clk mcasp_sync_mux_ck = {
1835         .name           = "mcasp_sync_mux_ck",
1836         .parent         = &abe_24m_fclk,
1837         .clksel         = dmic_sync_mux_sel,
1838         .init           = &omap2_init_clksel_parent,
1839         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1840         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1841         .ops            = &clkops_null,
1842         .recalc         = &omap2_clksel_recalc,
1843 };
1844
1845 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1846         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1847         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1848         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1849         { .parent = NULL },
1850 };
1851
1852 /* Merged func_mcasp_abe_gfclk into mcasp */
1853 static struct clk mcasp_fck = {
1854         .name           = "mcasp_fck",
1855         .parent         = &mcasp_sync_mux_ck,
1856         .clksel         = func_mcasp_abe_gfclk_sel,
1857         .init           = &omap2_init_clksel_parent,
1858         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1859         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1860         .ops            = &clkops_omap2_dflt,
1861         .recalc         = &omap2_clksel_recalc,
1862         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1863         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1864         .clkdm_name     = "abe_clkdm",
1865 };
1866
1867 static struct clk mcbsp1_sync_mux_ck = {
1868         .name           = "mcbsp1_sync_mux_ck",
1869         .parent         = &abe_24m_fclk,
1870         .clksel         = dmic_sync_mux_sel,
1871         .init           = &omap2_init_clksel_parent,
1872         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1873         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1874         .ops            = &clkops_null,
1875         .recalc         = &omap2_clksel_recalc,
1876 };
1877
1878 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1879         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1880         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1881         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1882         { .parent = NULL },
1883 };
1884
1885 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1886 static struct clk mcbsp1_fck = {
1887         .name           = "mcbsp1_fck",
1888         .parent         = &mcbsp1_sync_mux_ck,
1889         .clksel         = func_mcbsp1_gfclk_sel,
1890         .init           = &omap2_init_clksel_parent,
1891         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1892         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1893         .ops            = &clkops_omap2_dflt,
1894         .recalc         = &omap2_clksel_recalc,
1895         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1896         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1897         .clkdm_name     = "abe_clkdm",
1898 };
1899
1900 static struct clk mcbsp2_sync_mux_ck = {
1901         .name           = "mcbsp2_sync_mux_ck",
1902         .parent         = &abe_24m_fclk,
1903         .clksel         = dmic_sync_mux_sel,
1904         .init           = &omap2_init_clksel_parent,
1905         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1906         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1907         .ops            = &clkops_null,
1908         .recalc         = &omap2_clksel_recalc,
1909 };
1910
1911 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1912         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1913         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1914         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1915         { .parent = NULL },
1916 };
1917
1918 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1919 static struct clk mcbsp2_fck = {
1920         .name           = "mcbsp2_fck",
1921         .parent         = &mcbsp2_sync_mux_ck,
1922         .clksel         = func_mcbsp2_gfclk_sel,
1923         .init           = &omap2_init_clksel_parent,
1924         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1925         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1926         .ops            = &clkops_omap2_dflt,
1927         .recalc         = &omap2_clksel_recalc,
1928         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1929         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1930         .clkdm_name     = "abe_clkdm",
1931 };
1932
1933 static struct clk mcbsp3_sync_mux_ck = {
1934         .name           = "mcbsp3_sync_mux_ck",
1935         .parent         = &abe_24m_fclk,
1936         .clksel         = dmic_sync_mux_sel,
1937         .init           = &omap2_init_clksel_parent,
1938         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1939         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1940         .ops            = &clkops_null,
1941         .recalc         = &omap2_clksel_recalc,
1942 };
1943
1944 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1945         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1946         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1947         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1948         { .parent = NULL },
1949 };
1950
1951 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1952 static struct clk mcbsp3_fck = {
1953         .name           = "mcbsp3_fck",
1954         .parent         = &mcbsp3_sync_mux_ck,
1955         .clksel         = func_mcbsp3_gfclk_sel,
1956         .init           = &omap2_init_clksel_parent,
1957         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1958         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1959         .ops            = &clkops_omap2_dflt,
1960         .recalc         = &omap2_clksel_recalc,
1961         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1962         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1963         .clkdm_name     = "abe_clkdm",
1964 };
1965
1966 static const struct clksel mcbsp4_sync_mux_sel[] = {
1967         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1968         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1969         { .parent = NULL },
1970 };
1971
1972 static struct clk mcbsp4_sync_mux_ck = {
1973         .name           = "mcbsp4_sync_mux_ck",
1974         .parent         = &func_96m_fclk,
1975         .clksel         = mcbsp4_sync_mux_sel,
1976         .init           = &omap2_init_clksel_parent,
1977         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1978         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1979         .ops            = &clkops_null,
1980         .recalc         = &omap2_clksel_recalc,
1981 };
1982
1983 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1984         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1985         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1986         { .parent = NULL },
1987 };
1988
1989 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1990 static struct clk mcbsp4_fck = {
1991         .name           = "mcbsp4_fck",
1992         .parent         = &mcbsp4_sync_mux_ck,
1993         .clksel         = per_mcbsp4_gfclk_sel,
1994         .init           = &omap2_init_clksel_parent,
1995         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1996         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1997         .ops            = &clkops_omap2_dflt,
1998         .recalc         = &omap2_clksel_recalc,
1999         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2000         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2001         .clkdm_name     = "l4_per_clkdm",
2002 };
2003
2004 static struct clk mcpdm_fck = {
2005         .name           = "mcpdm_fck",
2006         .ops            = &clkops_omap2_dflt,
2007         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2008         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2009         .clkdm_name     = "abe_clkdm",
2010         .parent         = &pad_clks_ck,
2011         .recalc         = &followparent_recalc,
2012 };
2013
2014 static struct clk mcspi1_fck = {
2015         .name           = "mcspi1_fck",
2016         .ops            = &clkops_omap2_dflt,
2017         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2018         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2019         .clkdm_name     = "l4_per_clkdm",
2020         .parent         = &func_48m_fclk,
2021         .recalc         = &followparent_recalc,
2022 };
2023
2024 static struct clk mcspi2_fck = {
2025         .name           = "mcspi2_fck",
2026         .ops            = &clkops_omap2_dflt,
2027         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2028         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2029         .clkdm_name     = "l4_per_clkdm",
2030         .parent         = &func_48m_fclk,
2031         .recalc         = &followparent_recalc,
2032 };
2033
2034 static struct clk mcspi3_fck = {
2035         .name           = "mcspi3_fck",
2036         .ops            = &clkops_omap2_dflt,
2037         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2038         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2039         .clkdm_name     = "l4_per_clkdm",
2040         .parent         = &func_48m_fclk,
2041         .recalc         = &followparent_recalc,
2042 };
2043
2044 static struct clk mcspi4_fck = {
2045         .name           = "mcspi4_fck",
2046         .ops            = &clkops_omap2_dflt,
2047         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2048         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2049         .clkdm_name     = "l4_per_clkdm",
2050         .parent         = &func_48m_fclk,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 static const struct clksel hsmmc1_fclk_sel[] = {
2055         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2056         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2057         { .parent = NULL },
2058 };
2059
2060 /* Merged hsmmc1_fclk into mmc1 */
2061 static struct clk mmc1_fck = {
2062         .name           = "mmc1_fck",
2063         .parent         = &func_64m_fclk,
2064         .clksel         = hsmmc1_fclk_sel,
2065         .init           = &omap2_init_clksel_parent,
2066         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2067         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2068         .ops            = &clkops_omap2_dflt,
2069         .recalc         = &omap2_clksel_recalc,
2070         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2071         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2072         .clkdm_name     = "l3_init_clkdm",
2073 };
2074
2075 /* Merged hsmmc2_fclk into mmc2 */
2076 static struct clk mmc2_fck = {
2077         .name           = "mmc2_fck",
2078         .parent         = &func_64m_fclk,
2079         .clksel         = hsmmc1_fclk_sel,
2080         .init           = &omap2_init_clksel_parent,
2081         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2082         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2083         .ops            = &clkops_omap2_dflt,
2084         .recalc         = &omap2_clksel_recalc,
2085         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2086         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2087         .clkdm_name     = "l3_init_clkdm",
2088 };
2089
2090 static struct clk mmc3_fck = {
2091         .name           = "mmc3_fck",
2092         .ops            = &clkops_omap2_dflt,
2093         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2094         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2095         .clkdm_name     = "l4_per_clkdm",
2096         .parent         = &func_48m_fclk,
2097         .recalc         = &followparent_recalc,
2098 };
2099
2100 static struct clk mmc4_fck = {
2101         .name           = "mmc4_fck",
2102         .ops            = &clkops_omap2_dflt,
2103         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2104         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2105         .clkdm_name     = "l4_per_clkdm",
2106         .parent         = &func_48m_fclk,
2107         .recalc         = &followparent_recalc,
2108 };
2109
2110 static struct clk mmc5_fck = {
2111         .name           = "mmc5_fck",
2112         .ops            = &clkops_omap2_dflt,
2113         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2114         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2115         .clkdm_name     = "l4_per_clkdm",
2116         .parent         = &func_48m_fclk,
2117         .recalc         = &followparent_recalc,
2118 };
2119
2120 static struct clk ocp2scp_usb_phy_phy_48m = {
2121         .name           = "ocp2scp_usb_phy_phy_48m",
2122         .ops            = &clkops_omap2_dflt,
2123         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2124         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2125         .clkdm_name     = "l3_init_clkdm",
2126         .parent         = &func_48m_fclk,
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk ocp2scp_usb_phy_ick = {
2131         .name           = "ocp2scp_usb_phy_ick",
2132         .ops            = &clkops_omap2_dflt,
2133         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2134         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2135         .clkdm_name     = "l3_init_clkdm",
2136         .parent         = &l4_div_ck,
2137         .recalc         = &followparent_recalc,
2138 };
2139
2140 static struct clk ocp_wp_noc_ick = {
2141         .name           = "ocp_wp_noc_ick",
2142         .ops            = &clkops_omap2_dflt,
2143         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2144         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2145         .flags          = ENABLE_ON_INIT,
2146         .clkdm_name     = "l3_instr_clkdm",
2147         .parent         = &l3_div_ck,
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk rng_ick = {
2152         .name           = "rng_ick",
2153         .ops            = &clkops_omap2_dflt,
2154         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2155         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2156         .clkdm_name     = "l4_secure_clkdm",
2157         .parent         = &l4_div_ck,
2158         .recalc         = &followparent_recalc,
2159 };
2160
2161 static struct clk sha2md5_fck = {
2162         .name           = "sha2md5_fck",
2163         .ops            = &clkops_omap2_dflt,
2164         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2165         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2166         .clkdm_name     = "l4_secure_clkdm",
2167         .parent         = &l3_div_ck,
2168         .recalc         = &followparent_recalc,
2169 };
2170
2171 static struct clk sl2if_ick = {
2172         .name           = "sl2if_ick",
2173         .ops            = &clkops_omap2_dflt,
2174         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2175         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2176         .clkdm_name     = "ivahd_clkdm",
2177         .parent         = &dpll_iva_m5x2_ck,
2178         .recalc         = &followparent_recalc,
2179 };
2180
2181 static struct clk slimbus1_fclk_1 = {
2182         .name           = "slimbus1_fclk_1",
2183         .ops            = &clkops_omap2_dflt,
2184         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2185         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2186         .clkdm_name     = "abe_clkdm",
2187         .parent         = &func_24m_clk,
2188         .recalc         = &followparent_recalc,
2189 };
2190
2191 static struct clk slimbus1_fclk_0 = {
2192         .name           = "slimbus1_fclk_0",
2193         .ops            = &clkops_omap2_dflt,
2194         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2195         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2196         .clkdm_name     = "abe_clkdm",
2197         .parent         = &abe_24m_fclk,
2198         .recalc         = &followparent_recalc,
2199 };
2200
2201 static struct clk slimbus1_fclk_2 = {
2202         .name           = "slimbus1_fclk_2",
2203         .ops            = &clkops_omap2_dflt,
2204         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2205         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2206         .clkdm_name     = "abe_clkdm",
2207         .parent         = &pad_clks_ck,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211 static struct clk slimbus1_slimbus_clk = {
2212         .name           = "slimbus1_slimbus_clk",
2213         .ops            = &clkops_omap2_dflt,
2214         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2215         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2216         .clkdm_name     = "abe_clkdm",
2217         .parent         = &slimbus_clk,
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 static struct clk slimbus1_fck = {
2222         .name           = "slimbus1_fck",
2223         .ops            = &clkops_omap2_dflt,
2224         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2225         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2226         .clkdm_name     = "abe_clkdm",
2227         .parent         = &ocp_abe_iclk,
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk slimbus2_fclk_1 = {
2232         .name           = "slimbus2_fclk_1",
2233         .ops            = &clkops_omap2_dflt,
2234         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2235         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2236         .clkdm_name     = "l4_per_clkdm",
2237         .parent         = &per_abe_24m_fclk,
2238         .recalc         = &followparent_recalc,
2239 };
2240
2241 static struct clk slimbus2_fclk_0 = {
2242         .name           = "slimbus2_fclk_0",
2243         .ops            = &clkops_omap2_dflt,
2244         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2245         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2246         .clkdm_name     = "l4_per_clkdm",
2247         .parent         = &func_24mc_fclk,
2248         .recalc         = &followparent_recalc,
2249 };
2250
2251 static struct clk slimbus2_slimbus_clk = {
2252         .name           = "slimbus2_slimbus_clk",
2253         .ops            = &clkops_omap2_dflt,
2254         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2255         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2256         .clkdm_name     = "l4_per_clkdm",
2257         .parent         = &pad_slimbus_core_clks_ck,
2258         .recalc         = &followparent_recalc,
2259 };
2260
2261 static struct clk slimbus2_fck = {
2262         .name           = "slimbus2_fck",
2263         .ops            = &clkops_omap2_dflt,
2264         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2265         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2266         .clkdm_name     = "l4_per_clkdm",
2267         .parent         = &l4_div_ck,
2268         .recalc         = &followparent_recalc,
2269 };
2270
2271 static struct clk smartreflex_core_fck = {
2272         .name           = "smartreflex_core_fck",
2273         .ops            = &clkops_omap2_dflt,
2274         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2275         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2276         .clkdm_name     = "l4_ao_clkdm",
2277         .parent         = &l4_wkup_clk_mux_ck,
2278         .recalc         = &followparent_recalc,
2279 };
2280
2281 static struct clk smartreflex_iva_fck = {
2282         .name           = "smartreflex_iva_fck",
2283         .ops            = &clkops_omap2_dflt,
2284         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2285         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2286         .clkdm_name     = "l4_ao_clkdm",
2287         .parent         = &l4_wkup_clk_mux_ck,
2288         .recalc         = &followparent_recalc,
2289 };
2290
2291 static struct clk smartreflex_mpu_fck = {
2292         .name           = "smartreflex_mpu_fck",
2293         .ops            = &clkops_omap2_dflt,
2294         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2295         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2296         .clkdm_name     = "l4_ao_clkdm",
2297         .parent         = &l4_wkup_clk_mux_ck,
2298         .recalc         = &followparent_recalc,
2299 };
2300
2301 /* Merged dmt1_clk_mux into timer1 */
2302 static struct clk timer1_fck = {
2303         .name           = "timer1_fck",
2304         .parent         = &sys_clkin_ck,
2305         .clksel         = abe_dpll_bypass_clk_mux_sel,
2306         .init           = &omap2_init_clksel_parent,
2307         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2308         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2309         .ops            = &clkops_omap2_dflt,
2310         .recalc         = &omap2_clksel_recalc,
2311         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2312         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2313         .clkdm_name     = "l4_wkup_clkdm",
2314 };
2315
2316 /* Merged cm2_dm10_mux into timer10 */
2317 static struct clk timer10_fck = {
2318         .name           = "timer10_fck",
2319         .parent         = &sys_clkin_ck,
2320         .clksel         = abe_dpll_bypass_clk_mux_sel,
2321         .init           = &omap2_init_clksel_parent,
2322         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2323         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2324         .ops            = &clkops_omap2_dflt,
2325         .recalc         = &omap2_clksel_recalc,
2326         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2327         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2328         .clkdm_name     = "l4_per_clkdm",
2329 };
2330
2331 /* Merged cm2_dm11_mux into timer11 */
2332 static struct clk timer11_fck = {
2333         .name           = "timer11_fck",
2334         .parent         = &sys_clkin_ck,
2335         .clksel         = abe_dpll_bypass_clk_mux_sel,
2336         .init           = &omap2_init_clksel_parent,
2337         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2338         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2339         .ops            = &clkops_omap2_dflt,
2340         .recalc         = &omap2_clksel_recalc,
2341         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2342         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2343         .clkdm_name     = "l4_per_clkdm",
2344 };
2345
2346 /* Merged cm2_dm2_mux into timer2 */
2347 static struct clk timer2_fck = {
2348         .name           = "timer2_fck",
2349         .parent         = &sys_clkin_ck,
2350         .clksel         = abe_dpll_bypass_clk_mux_sel,
2351         .init           = &omap2_init_clksel_parent,
2352         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2353         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2354         .ops            = &clkops_omap2_dflt,
2355         .recalc         = &omap2_clksel_recalc,
2356         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2357         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2358         .clkdm_name     = "l4_per_clkdm",
2359 };
2360
2361 /* Merged cm2_dm3_mux into timer3 */
2362 static struct clk timer3_fck = {
2363         .name           = "timer3_fck",
2364         .parent         = &sys_clkin_ck,
2365         .clksel         = abe_dpll_bypass_clk_mux_sel,
2366         .init           = &omap2_init_clksel_parent,
2367         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2368         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2369         .ops            = &clkops_omap2_dflt,
2370         .recalc         = &omap2_clksel_recalc,
2371         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2372         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2373         .clkdm_name     = "l4_per_clkdm",
2374 };
2375
2376 /* Merged cm2_dm4_mux into timer4 */
2377 static struct clk timer4_fck = {
2378         .name           = "timer4_fck",
2379         .parent         = &sys_clkin_ck,
2380         .clksel         = abe_dpll_bypass_clk_mux_sel,
2381         .init           = &omap2_init_clksel_parent,
2382         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2383         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2384         .ops            = &clkops_omap2_dflt,
2385         .recalc         = &omap2_clksel_recalc,
2386         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2387         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2388         .clkdm_name     = "l4_per_clkdm",
2389 };
2390
2391 static const struct clksel timer5_sync_mux_sel[] = {
2392         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2393         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2394         { .parent = NULL },
2395 };
2396
2397 /* Merged timer5_sync_mux into timer5 */
2398 static struct clk timer5_fck = {
2399         .name           = "timer5_fck",
2400         .parent         = &syc_clk_div_ck,
2401         .clksel         = timer5_sync_mux_sel,
2402         .init           = &omap2_init_clksel_parent,
2403         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2404         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2405         .ops            = &clkops_omap2_dflt,
2406         .recalc         = &omap2_clksel_recalc,
2407         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2408         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2409         .clkdm_name     = "abe_clkdm",
2410 };
2411
2412 /* Merged timer6_sync_mux into timer6 */
2413 static struct clk timer6_fck = {
2414         .name           = "timer6_fck",
2415         .parent         = &syc_clk_div_ck,
2416         .clksel         = timer5_sync_mux_sel,
2417         .init           = &omap2_init_clksel_parent,
2418         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2419         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2420         .ops            = &clkops_omap2_dflt,
2421         .recalc         = &omap2_clksel_recalc,
2422         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2423         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2424         .clkdm_name     = "abe_clkdm",
2425 };
2426
2427 /* Merged timer7_sync_mux into timer7 */
2428 static struct clk timer7_fck = {
2429         .name           = "timer7_fck",
2430         .parent         = &syc_clk_div_ck,
2431         .clksel         = timer5_sync_mux_sel,
2432         .init           = &omap2_init_clksel_parent,
2433         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2434         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2435         .ops            = &clkops_omap2_dflt,
2436         .recalc         = &omap2_clksel_recalc,
2437         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2438         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2439         .clkdm_name     = "abe_clkdm",
2440 };
2441
2442 /* Merged timer8_sync_mux into timer8 */
2443 static struct clk timer8_fck = {
2444         .name           = "timer8_fck",
2445         .parent         = &syc_clk_div_ck,
2446         .clksel         = timer5_sync_mux_sel,
2447         .init           = &omap2_init_clksel_parent,
2448         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2449         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2450         .ops            = &clkops_omap2_dflt,
2451         .recalc         = &omap2_clksel_recalc,
2452         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2453         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2454         .clkdm_name     = "abe_clkdm",
2455 };
2456
2457 /* Merged cm2_dm9_mux into timer9 */
2458 static struct clk timer9_fck = {
2459         .name           = "timer9_fck",
2460         .parent         = &sys_clkin_ck,
2461         .clksel         = abe_dpll_bypass_clk_mux_sel,
2462         .init           = &omap2_init_clksel_parent,
2463         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2464         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2465         .ops            = &clkops_omap2_dflt,
2466         .recalc         = &omap2_clksel_recalc,
2467         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2468         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2469         .clkdm_name     = "l4_per_clkdm",
2470 };
2471
2472 static struct clk uart1_fck = {
2473         .name           = "uart1_fck",
2474         .ops            = &clkops_omap2_dflt,
2475         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2476         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2477         .clkdm_name     = "l4_per_clkdm",
2478         .parent         = &func_48m_fclk,
2479         .recalc         = &followparent_recalc,
2480 };
2481
2482 static struct clk uart2_fck = {
2483         .name           = "uart2_fck",
2484         .ops            = &clkops_omap2_dflt,
2485         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2486         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2487         .clkdm_name     = "l4_per_clkdm",
2488         .parent         = &func_48m_fclk,
2489         .recalc         = &followparent_recalc,
2490 };
2491
2492 static struct clk uart3_fck = {
2493         .name           = "uart3_fck",
2494         .ops            = &clkops_omap2_dflt,
2495         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2496         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2497         .clkdm_name     = "l4_per_clkdm",
2498         .parent         = &func_48m_fclk,
2499         .recalc         = &followparent_recalc,
2500 };
2501
2502 static struct clk uart4_fck = {
2503         .name           = "uart4_fck",
2504         .ops            = &clkops_omap2_dflt,
2505         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2506         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2507         .clkdm_name     = "l4_per_clkdm",
2508         .parent         = &func_48m_fclk,
2509         .recalc         = &followparent_recalc,
2510 };
2511
2512 static struct clk usb_host_fs_fck = {
2513         .name           = "usb_host_fs_fck",
2514         .ops            = &clkops_omap2_dflt,
2515         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2516         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2517         .clkdm_name     = "l3_init_clkdm",
2518         .parent         = &func_48mc_fclk,
2519         .recalc         = &followparent_recalc,
2520 };
2521
2522 static const struct clksel utmi_p1_gfclk_sel[] = {
2523         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2524         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2525         { .parent = NULL },
2526 };
2527
2528 static struct clk utmi_p1_gfclk = {
2529         .name           = "utmi_p1_gfclk",
2530         .parent         = &init_60m_fclk,
2531         .clksel         = utmi_p1_gfclk_sel,
2532         .init           = &omap2_init_clksel_parent,
2533         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2534         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2535         .ops            = &clkops_null,
2536         .recalc         = &omap2_clksel_recalc,
2537 };
2538
2539 static struct clk usb_host_hs_utmi_p1_clk = {
2540         .name           = "usb_host_hs_utmi_p1_clk",
2541         .ops            = &clkops_omap2_dflt,
2542         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2543         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2544         .clkdm_name     = "l3_init_clkdm",
2545         .parent         = &utmi_p1_gfclk,
2546         .recalc         = &followparent_recalc,
2547 };
2548
2549 static const struct clksel utmi_p2_gfclk_sel[] = {
2550         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2551         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2552         { .parent = NULL },
2553 };
2554
2555 static struct clk utmi_p2_gfclk = {
2556         .name           = "utmi_p2_gfclk",
2557         .parent         = &init_60m_fclk,
2558         .clksel         = utmi_p2_gfclk_sel,
2559         .init           = &omap2_init_clksel_parent,
2560         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2561         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2562         .ops            = &clkops_null,
2563         .recalc         = &omap2_clksel_recalc,
2564 };
2565
2566 static struct clk usb_host_hs_utmi_p2_clk = {
2567         .name           = "usb_host_hs_utmi_p2_clk",
2568         .ops            = &clkops_omap2_dflt,
2569         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2570         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2571         .clkdm_name     = "l3_init_clkdm",
2572         .parent         = &utmi_p2_gfclk,
2573         .recalc         = &followparent_recalc,
2574 };
2575
2576 static struct clk usb_host_hs_utmi_p3_clk = {
2577         .name           = "usb_host_hs_utmi_p3_clk",
2578         .ops            = &clkops_omap2_dflt,
2579         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2580         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2581         .clkdm_name     = "l3_init_clkdm",
2582         .parent         = &init_60m_fclk,
2583         .recalc         = &followparent_recalc,
2584 };
2585
2586 static struct clk usb_host_hs_hsic480m_p1_clk = {
2587         .name           = "usb_host_hs_hsic480m_p1_clk",
2588         .ops            = &clkops_omap2_dflt,
2589         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2590         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2591         .clkdm_name     = "l3_init_clkdm",
2592         .parent         = &dpll_usb_m2_ck,
2593         .recalc         = &followparent_recalc,
2594 };
2595
2596 static struct clk usb_host_hs_hsic60m_p1_clk = {
2597         .name           = "usb_host_hs_hsic60m_p1_clk",
2598         .ops            = &clkops_omap2_dflt,
2599         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2600         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2601         .clkdm_name     = "l3_init_clkdm",
2602         .parent         = &init_60m_fclk,
2603         .recalc         = &followparent_recalc,
2604 };
2605
2606 static struct clk usb_host_hs_hsic60m_p2_clk = {
2607         .name           = "usb_host_hs_hsic60m_p2_clk",
2608         .ops            = &clkops_omap2_dflt,
2609         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2610         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2611         .clkdm_name     = "l3_init_clkdm",
2612         .parent         = &init_60m_fclk,
2613         .recalc         = &followparent_recalc,
2614 };
2615
2616 static struct clk usb_host_hs_hsic480m_p2_clk = {
2617         .name           = "usb_host_hs_hsic480m_p2_clk",
2618         .ops            = &clkops_omap2_dflt,
2619         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2620         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2621         .clkdm_name     = "l3_init_clkdm",
2622         .parent         = &dpll_usb_m2_ck,
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk usb_host_hs_func48mclk = {
2627         .name           = "usb_host_hs_func48mclk",
2628         .ops            = &clkops_omap2_dflt,
2629         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2630         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2631         .clkdm_name     = "l3_init_clkdm",
2632         .parent         = &func_48mc_fclk,
2633         .recalc         = &followparent_recalc,
2634 };
2635
2636 static struct clk usb_host_hs_fck = {
2637         .name           = "usb_host_hs_fck",
2638         .ops            = &clkops_omap2_dflt,
2639         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2640         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2641         .clkdm_name     = "l3_init_clkdm",
2642         .parent         = &init_60m_fclk,
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 static const struct clksel otg_60m_gfclk_sel[] = {
2647         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2648         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2649         { .parent = NULL },
2650 };
2651
2652 static struct clk otg_60m_gfclk = {
2653         .name           = "otg_60m_gfclk",
2654         .parent         = &utmi_phy_clkout_ck,
2655         .clksel         = otg_60m_gfclk_sel,
2656         .init           = &omap2_init_clksel_parent,
2657         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2658         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2659         .ops            = &clkops_null,
2660         .recalc         = &omap2_clksel_recalc,
2661 };
2662
2663 static struct clk usb_otg_hs_xclk = {
2664         .name           = "usb_otg_hs_xclk",
2665         .ops            = &clkops_omap2_dflt,
2666         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2667         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2668         .clkdm_name     = "l3_init_clkdm",
2669         .parent         = &otg_60m_gfclk,
2670         .recalc         = &followparent_recalc,
2671 };
2672
2673 static struct clk usb_otg_hs_ick = {
2674         .name           = "usb_otg_hs_ick",
2675         .ops            = &clkops_omap2_dflt,
2676         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2677         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2678         .clkdm_name     = "l3_init_clkdm",
2679         .parent         = &l3_div_ck,
2680         .recalc         = &followparent_recalc,
2681 };
2682
2683 static struct clk usb_phy_cm_clk32k = {
2684         .name           = "usb_phy_cm_clk32k",
2685         .ops            = &clkops_omap2_dflt,
2686         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2687         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2688         .clkdm_name     = "l4_ao_clkdm",
2689         .parent         = &sys_32k_ck,
2690         .recalc         = &followparent_recalc,
2691 };
2692
2693 static struct clk usb_tll_hs_usb_ch2_clk = {
2694         .name           = "usb_tll_hs_usb_ch2_clk",
2695         .ops            = &clkops_omap2_dflt,
2696         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2697         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2698         .clkdm_name     = "l3_init_clkdm",
2699         .parent         = &init_60m_fclk,
2700         .recalc         = &followparent_recalc,
2701 };
2702
2703 static struct clk usb_tll_hs_usb_ch0_clk = {
2704         .name           = "usb_tll_hs_usb_ch0_clk",
2705         .ops            = &clkops_omap2_dflt,
2706         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2707         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2708         .clkdm_name     = "l3_init_clkdm",
2709         .parent         = &init_60m_fclk,
2710         .recalc         = &followparent_recalc,
2711 };
2712
2713 static struct clk usb_tll_hs_usb_ch1_clk = {
2714         .name           = "usb_tll_hs_usb_ch1_clk",
2715         .ops            = &clkops_omap2_dflt,
2716         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2717         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2718         .clkdm_name     = "l3_init_clkdm",
2719         .parent         = &init_60m_fclk,
2720         .recalc         = &followparent_recalc,
2721 };
2722
2723 static struct clk usb_tll_hs_ick = {
2724         .name           = "usb_tll_hs_ick",
2725         .ops            = &clkops_omap2_dflt,
2726         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2727         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2728         .clkdm_name     = "l3_init_clkdm",
2729         .parent         = &l4_div_ck,
2730         .recalc         = &followparent_recalc,
2731 };
2732
2733 static const struct clksel_rate div2_14to18_rates[] = {
2734         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2735         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2736         { .div = 0 },
2737 };
2738
2739 static const struct clksel usim_fclk_div[] = {
2740         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2741         { .parent = NULL },
2742 };
2743
2744 static struct clk usim_ck = {
2745         .name           = "usim_ck",
2746         .parent         = &dpll_per_m4x2_ck,
2747         .clksel         = usim_fclk_div,
2748         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2749         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2750         .ops            = &clkops_null,
2751         .recalc         = &omap2_clksel_recalc,
2752         .round_rate     = &omap2_clksel_round_rate,
2753         .set_rate       = &omap2_clksel_set_rate,
2754 };
2755
2756 static struct clk usim_fclk = {
2757         .name           = "usim_fclk",
2758         .ops            = &clkops_omap2_dflt,
2759         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2760         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2761         .clkdm_name     = "l4_wkup_clkdm",
2762         .parent         = &usim_ck,
2763         .recalc         = &followparent_recalc,
2764 };
2765
2766 static struct clk usim_fck = {
2767         .name           = "usim_fck",
2768         .ops            = &clkops_omap2_dflt,
2769         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2770         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2771         .clkdm_name     = "l4_wkup_clkdm",
2772         .parent         = &sys_32k_ck,
2773         .recalc         = &followparent_recalc,
2774 };
2775
2776 static struct clk wd_timer2_fck = {
2777         .name           = "wd_timer2_fck",
2778         .ops            = &clkops_omap2_dflt,
2779         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2780         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2781         .clkdm_name     = "l4_wkup_clkdm",
2782         .parent         = &sys_32k_ck,
2783         .recalc         = &followparent_recalc,
2784 };
2785
2786 static struct clk wd_timer3_fck = {
2787         .name           = "wd_timer3_fck",
2788         .ops            = &clkops_omap2_dflt,
2789         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2790         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2791         .clkdm_name     = "abe_clkdm",
2792         .parent         = &sys_32k_ck,
2793         .recalc         = &followparent_recalc,
2794 };
2795
2796 /* Remaining optional clocks */
2797 static const struct clksel stm_clk_div_div[] = {
2798         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2799         { .parent = NULL },
2800 };
2801
2802 static struct clk stm_clk_div_ck = {
2803         .name           = "stm_clk_div_ck",
2804         .parent         = &pmd_stm_clock_mux_ck,
2805         .clksel         = stm_clk_div_div,
2806         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2807         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2808         .ops            = &clkops_null,
2809         .recalc         = &omap2_clksel_recalc,
2810         .round_rate     = &omap2_clksel_round_rate,
2811         .set_rate       = &omap2_clksel_set_rate,
2812 };
2813
2814 static const struct clksel trace_clk_div_div[] = {
2815         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2816         { .parent = NULL },
2817 };
2818
2819 static struct clk trace_clk_div_ck = {
2820         .name           = "trace_clk_div_ck",
2821         .parent         = &pmd_trace_clk_mux_ck,
2822         .clksel         = trace_clk_div_div,
2823         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2824         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2825         .ops            = &clkops_null,
2826         .recalc         = &omap2_clksel_recalc,
2827         .round_rate     = &omap2_clksel_round_rate,
2828         .set_rate       = &omap2_clksel_set_rate,
2829 };
2830
2831 /* SCRM aux clk nodes */
2832
2833 static const struct clksel auxclk_sel[] = {
2834         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2835         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2836         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2837         { .parent = NULL },
2838 };
2839
2840 static struct clk auxclk0_ck = {
2841         .name           = "auxclk0_ck",
2842         .parent         = &sys_clkin_ck,
2843         .init           = &omap2_init_clksel_parent,
2844         .ops            = &clkops_omap2_dflt,
2845         .clksel         = auxclk_sel,
2846         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2847         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2848         .recalc         = &omap2_clksel_recalc,
2849         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2850         .enable_bit     = OMAP4_ENABLE_SHIFT,
2851 };
2852
2853 static struct clk auxclk1_ck = {
2854         .name           = "auxclk1_ck",
2855         .parent         = &sys_clkin_ck,
2856         .init           = &omap2_init_clksel_parent,
2857         .ops            = &clkops_omap2_dflt,
2858         .clksel         = auxclk_sel,
2859         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2860         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2861         .recalc         = &omap2_clksel_recalc,
2862         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2863         .enable_bit     = OMAP4_ENABLE_SHIFT,
2864 };
2865
2866 static struct clk auxclk2_ck = {
2867         .name           = "auxclk2_ck",
2868         .parent         = &sys_clkin_ck,
2869         .init           = &omap2_init_clksel_parent,
2870         .ops            = &clkops_omap2_dflt,
2871         .clksel         = auxclk_sel,
2872         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2873         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2874         .recalc         = &omap2_clksel_recalc,
2875         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2876         .enable_bit     = OMAP4_ENABLE_SHIFT,
2877 };
2878
2879 static struct clk auxclk3_ck = {
2880         .name           = "auxclk3_ck",
2881         .parent         = &sys_clkin_ck,
2882         .init           = &omap2_init_clksel_parent,
2883         .ops            = &clkops_omap2_dflt,
2884         .clksel         = auxclk_sel,
2885         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2886         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2887         .recalc         = &omap2_clksel_recalc,
2888         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2889         .enable_bit     = OMAP4_ENABLE_SHIFT,
2890 };
2891
2892 static struct clk auxclk4_ck = {
2893         .name           = "auxclk4_ck",
2894         .parent         = &sys_clkin_ck,
2895         .init           = &omap2_init_clksel_parent,
2896         .ops            = &clkops_omap2_dflt,
2897         .clksel         = auxclk_sel,
2898         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2899         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2900         .recalc         = &omap2_clksel_recalc,
2901         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2902         .enable_bit     = OMAP4_ENABLE_SHIFT,
2903 };
2904
2905 static struct clk auxclk5_ck = {
2906         .name           = "auxclk5_ck",
2907         .parent         = &sys_clkin_ck,
2908         .init           = &omap2_init_clksel_parent,
2909         .ops            = &clkops_omap2_dflt,
2910         .clksel         = auxclk_sel,
2911         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2912         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2913         .recalc         = &omap2_clksel_recalc,
2914         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2915         .enable_bit     = OMAP4_ENABLE_SHIFT,
2916 };
2917
2918 static const struct clksel auxclkreq_sel[] = {
2919         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2920         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2921         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2922         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2923         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2924         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2925         { .parent = NULL },
2926 };
2927
2928 static struct clk auxclkreq0_ck = {
2929         .name           = "auxclkreq0_ck",
2930         .parent         = &auxclk0_ck,
2931         .init           = &omap2_init_clksel_parent,
2932         .ops            = &clkops_null,
2933         .clksel         = auxclkreq_sel,
2934         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2935         .clksel_mask    = OMAP4_MAPPING_MASK,
2936         .recalc         = &omap2_clksel_recalc,
2937 };
2938
2939 static struct clk auxclkreq1_ck = {
2940         .name           = "auxclkreq1_ck",
2941         .parent         = &auxclk1_ck,
2942         .init           = &omap2_init_clksel_parent,
2943         .ops            = &clkops_null,
2944         .clksel         = auxclkreq_sel,
2945         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2946         .clksel_mask    = OMAP4_MAPPING_MASK,
2947         .recalc         = &omap2_clksel_recalc,
2948 };
2949
2950 static struct clk auxclkreq2_ck = {
2951         .name           = "auxclkreq2_ck",
2952         .parent         = &auxclk2_ck,
2953         .init           = &omap2_init_clksel_parent,
2954         .ops            = &clkops_null,
2955         .clksel         = auxclkreq_sel,
2956         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2957         .clksel_mask    = OMAP4_MAPPING_MASK,
2958         .recalc         = &omap2_clksel_recalc,
2959 };
2960
2961 static struct clk auxclkreq3_ck = {
2962         .name           = "auxclkreq3_ck",
2963         .parent         = &auxclk3_ck,
2964         .init           = &omap2_init_clksel_parent,
2965         .ops            = &clkops_null,
2966         .clksel         = auxclkreq_sel,
2967         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2968         .clksel_mask    = OMAP4_MAPPING_MASK,
2969         .recalc         = &omap2_clksel_recalc,
2970 };
2971
2972 static struct clk auxclkreq4_ck = {
2973         .name           = "auxclkreq4_ck",
2974         .parent         = &auxclk4_ck,
2975         .init           = &omap2_init_clksel_parent,
2976         .ops            = &clkops_null,
2977         .clksel         = auxclkreq_sel,
2978         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2979         .clksel_mask    = OMAP4_MAPPING_MASK,
2980         .recalc         = &omap2_clksel_recalc,
2981 };
2982
2983 static struct clk auxclkreq5_ck = {
2984         .name           = "auxclkreq5_ck",
2985         .parent         = &auxclk5_ck,
2986         .init           = &omap2_init_clksel_parent,
2987         .ops            = &clkops_null,
2988         .clksel         = auxclkreq_sel,
2989         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
2990         .clksel_mask    = OMAP4_MAPPING_MASK,
2991         .recalc         = &omap2_clksel_recalc,
2992 };
2993
2994 /*
2995  * clkdev
2996  */
2997
2998 static struct omap_clk omap44xx_clks[] = {
2999         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3000         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3001         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3002         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3003         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3004         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3005         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3006         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3007         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3008         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3009         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3010         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3011         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3012         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3013         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3014         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3015         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3016         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3017         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3018         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3019         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3020         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3021         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3022         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3023         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3024         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3025         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3026         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3027         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3028         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3029         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3030         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3031         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3032         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3033         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3034         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3035         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3036         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3037         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3038         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3039         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3040         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3041         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3042         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3043         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3044         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3045         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3046         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3047         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3048         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3049         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3050         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3051         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3052         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3053         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3054         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3055         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3056         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3057         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3058         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3059         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3060         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3061         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
3062         CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
3063         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
3064         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3065         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3066         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3067         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3068         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3069         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3070         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3071         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3072         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3073         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3074         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3075         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3076         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3077         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3078         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3079         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3080         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3081         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3082         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3083         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3084         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3085         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3086         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3087         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3088         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3089         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3090         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3091         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3092         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3093         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3094         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3095         CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
3096         CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
3097         CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
3098         CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
3099         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
3100         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3101         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3102         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3103         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3104         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3105         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3106         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3107         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3108         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3109         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3110         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3111         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3112         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3113         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3114         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3115         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3116         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3117         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3118         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3119         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
3120         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3121         CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
3122         CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
3123         CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
3124         CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
3125         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3126         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3127         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3128         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3129         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3130         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3131         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3132         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3133         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3134         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3135         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
3136         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3137         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
3138         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3139         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
3140         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3141         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
3142         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3143         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
3144         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
3145         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
3146         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
3147         CLK("omap_hsmmc.0",     "fck",                          &mmc1_fck,      CK_443X),
3148         CLK("omap_hsmmc.1",     "fck",                          &mmc2_fck,      CK_443X),
3149         CLK("omap_hsmmc.2",     "fck",                          &mmc3_fck,      CK_443X),
3150         CLK("omap_hsmmc.3",     "fck",                          &mmc4_fck,      CK_443X),
3151         CLK("omap_hsmmc.4",     "fck",                          &mmc5_fck,      CK_443X),
3152         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3153         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3154         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3155         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3156         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3157         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3158         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3159         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3160         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3161         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3162         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3163         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3164         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3165         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3166         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3167         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3168         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3169         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3170         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3171         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3172         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3173         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3174         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3175         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3176         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3177         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3178         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3179         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3180         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3181         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3182         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3183         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3184         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3185         CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
3186         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3187         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3188         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3189         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3190         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3191         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3192         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3193         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3194         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3195         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3196         CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
3197         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3198         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3199         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
3200         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3201         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3202         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3203         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3204         CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
3205         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3206         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3207         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3208         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
3209         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3210         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3211         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3212         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3213         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3214         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3215         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3216         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3217         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3218         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3219         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3220         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3221         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3222         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3223         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3224         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3225         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
3226         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
3227         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
3228         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
3229         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
3230         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
3231         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
3232         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
3233         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
3234         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
3235         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
3236         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3237         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3238         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3239         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3240         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3241         CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
3242         CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
3243         CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
3244         CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
3245         CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
3246         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3247         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3248         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3249         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3250         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3251         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3252         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3253         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3254         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3255         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3256         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3257         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3258         CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
3259         CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
3260         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3261 };
3262
3263 int __init omap4xxx_clk_init(void)
3264 {
3265         struct omap_clk *c;
3266         u32 cpu_clkflg;
3267
3268         if (cpu_is_omap44xx()) {
3269                 cpu_mask = RATE_IN_4430;
3270                 cpu_clkflg = CK_443X;
3271         }
3272
3273         clk_init(&omap2_clk_functions);
3274
3275         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3276                                                                           c++)
3277                 clk_preinit(c->lk.clk);
3278
3279         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3280                                                                           c++)
3281                 if (c->cpu & cpu_clkflg) {
3282                         clkdev_add(&c->lk);
3283                         clk_register(c->lk.clk);
3284                         omap2_init_clk_clkdm(c->lk.clk);
3285                 }
3286
3287         /* Disable autoidle on all clocks; let the PM code enable it later */
3288         omap_clk_disable_autoidle_all();
3289
3290         recalculate_root_clocks();
3291
3292         /*
3293          * Only enable those clocks we will need, let the drivers
3294          * enable other clocks as necessary
3295          */
3296         clk_enable_init_clocks();
3297
3298         return 0;
3299 }