arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39 #include "scrm44xx.h"
  40
  41 /* OMAP4 modulemode control */
  42 #define OMAP4430_MODULEMODE_HWCTRL                      0
  43 #define OMAP4430_MODULEMODE_SWCTRL                      1
  44
  45 /* Root clocks */
  46
  47 static struct clk extalt_clkin_ck = {
  48         .name           = "extalt_clkin_ck",
  49         .rate           = 59000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_clks_ck = {
  54         .name           = "pad_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_omap2_dflt,
  57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  59 };
  60
  61 static struct clk pad_slimbus_core_clks_ck = {
  62         .name           = "pad_slimbus_core_clks_ck",
  63         .rate           = 12000000,
  64         .ops            = &clkops_null,
  65 };
  66
  67 static struct clk secure_32k_clk_src_ck = {
  68         .name           = "secure_32k_clk_src_ck",
  69         .rate           = 32768,
  70         .ops            = &clkops_null,
  71 };
  72
  73 static struct clk slimbus_clk = {
  74         .name           = "slimbus_clk",
  75         .rate           = 12000000,
  76         .ops            = &clkops_omap2_dflt,
  77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79 };
  80
  81 static struct clk sys_32k_ck = {
  82         .name           = "sys_32k_ck",
  83         .rate           = 32768,
  84         .ops            = &clkops_null,
  85 };
  86
  87 static struct clk virt_12000000_ck = {
  88         .name           = "virt_12000000_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 12000000,
  91 };
  92
  93 static struct clk virt_13000000_ck = {
  94         .name           = "virt_13000000_ck",
  95         .ops            = &clkops_null,
  96         .rate           = 13000000,
  97 };
  98
  99 static struct clk virt_16800000_ck = {
 100         .name           = "virt_16800000_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 16800000,
 103 };
 104
 105 static struct clk virt_19200000_ck = {
 106         .name           = "virt_19200000_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 19200000,
 109 };
 110
 111 static struct clk virt_26000000_ck = {
 112         .name           = "virt_26000000_ck",
 113         .ops            = &clkops_null,
 114         .rate           = 26000000,
 115 };
 116
 117 static struct clk virt_27000000_ck = {
 118         .name           = "virt_27000000_ck",
 119         .ops            = &clkops_null,
 120         .rate           = 27000000,
 121 };
 122
 123 static struct clk virt_38400000_ck = {
 124         .name           = "virt_38400000_ck",
 125         .ops            = &clkops_null,
 126         .rate           = 38400000,
 127 };
 128
 129 static const struct clksel_rate div_1_0_rates[] = {
 130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_1_rates[] = {
 135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_2_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_3_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_4_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_5_rates[] = {
 155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel_rate div_1_6_rates[] = {
 160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161         { .div = 0 },
 162 };
 163
 164 static const struct clksel_rate div_1_7_rates[] = {
 165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel sys_clkin_sel[] = {
 170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk sys_clkin_ck = {
 181         .name           = "sys_clkin_ck",
 182         .rate           = 38400000,
 183         .clksel         = sys_clkin_sel,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 187         .ops            = &clkops_null,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk tie_low_clock_ck = {
 192         .name           = "tie_low_clock_ck",
 193         .rate           = 0,
 194         .ops            = &clkops_null,
 195 };
 196
 197 static struct clk utmi_phy_clkout_ck = {
 198         .name           = "utmi_phy_clkout_ck",
 199         .rate           = 60000000,
 200         .ops            = &clkops_null,
 201 };
 202
 203 static struct clk xclk60mhsp1_ck = {
 204         .name           = "xclk60mhsp1_ck",
 205         .rate           = 60000000,
 206         .ops            = &clkops_null,
 207 };
 208
 209 static struct clk xclk60mhsp2_ck = {
 210         .name           = "xclk60mhsp2_ck",
 211         .rate           = 60000000,
 212         .ops            = &clkops_null,
 213 };
 214
 215 static struct clk xclk60motg_ck = {
 216         .name           = "xclk60motg_ck",
 217         .rate           = 60000000,
 218         .ops            = &clkops_null,
 219 };
 220
 221 /* Module clocks and DPLL outputs */
 222
 223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226         { .parent = NULL },
 227 };
 228
 229 static struct clk abe_dpll_bypass_clk_mux_ck = {
 230         .name           = "abe_dpll_bypass_clk_mux_ck",
 231         .parent         = &sys_clkin_ck,
 232         .ops            = &clkops_null,
 233         .recalc         = &followparent_recalc,
 234 };
 235
 236 static struct clk abe_dpll_refclk_mux_ck = {
 237         .name           = "abe_dpll_refclk_mux_ck",
 238         .parent         = &sys_clkin_ck,
 239         .clksel         = abe_dpll_bypass_clk_mux_sel,
 240         .init           = &omap2_init_clksel_parent,
 241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 243         .ops            = &clkops_null,
 244         .recalc         = &omap2_clksel_recalc,
 245 };
 246
 247 /* DPLL_ABE */
 248 static struct dpll_data dpll_abe_dd = {
 249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 251         .clk_ref        = &abe_dpll_refclk_mux_ck,
 252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 261         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 262         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 263         .min_divider    = 1,
 264 };
 265
 266
 267 static struct clk dpll_abe_ck = {
 268         .name           = "dpll_abe_ck",
 269         .parent         = &abe_dpll_refclk_mux_ck,
 270         .dpll_data      = &dpll_abe_dd,
 271         .init           = &omap2_init_dpll_parent,
 272         .ops            = &clkops_omap3_noncore_dpll_ops,
 273         .recalc         = &omap3_dpll_recalc,
 274         .round_rate     = &omap2_dpll_round_rate,
 275         .set_rate       = &omap3_noncore_dpll_set_rate,
 276 };
 277
 278 static struct clk dpll_abe_x2_ck = {
 279         .name           = "dpll_abe_x2_ck",
 280         .parent         = &dpll_abe_ck,
 281         .flags          = CLOCK_CLKOUTX2,
 282         .ops            = &clkops_omap4_dpllmx_ops,
 283         .recalc         = &omap3_clkoutx2_recalc,
 284         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 285 };
 286
 287 static const struct clksel_rate div31_1to31_rates[] = {
 288         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 289         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 290         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 291         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 292         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 293         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 294         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 295         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 296         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 297         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 298         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 299         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 300         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 301         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 302         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 303         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 304         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 305         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 306         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 307         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 308         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 309         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 310         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 311         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 312         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 313         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 314         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 315         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 316         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 317         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 318         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 319         { .div = 0 },
 320 };
 321
 322 static const struct clksel dpll_abe_m2x2_div[] = {
 323         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 324         { .parent = NULL },
 325 };
 326
 327 static struct clk dpll_abe_m2x2_ck = {
 328         .name           = "dpll_abe_m2x2_ck",
 329         .parent         = &dpll_abe_x2_ck,
 330         .clksel         = dpll_abe_m2x2_div,
 331         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 332         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 333         .ops            = &clkops_omap4_dpllmx_ops,
 334         .recalc         = &omap2_clksel_recalc,
 335         .round_rate     = &omap2_clksel_round_rate,
 336         .set_rate       = &omap2_clksel_set_rate,
 337 };
 338
 339 static struct clk abe_24m_fclk = {
 340         .name           = "abe_24m_fclk",
 341         .parent         = &dpll_abe_m2x2_ck,
 342         .ops            = &clkops_null,
 343         .fixed_div      = 8,
 344         .recalc         = &omap_fixed_divisor_recalc,
 345 };
 346
 347 static const struct clksel_rate div3_1to4_rates[] = {
 348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 351         { .div = 0 },
 352 };
 353
 354 static const struct clksel abe_clk_div[] = {
 355         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 356         { .parent = NULL },
 357 };
 358
 359 static struct clk abe_clk = {
 360         .name           = "abe_clk",
 361         .parent         = &dpll_abe_m2x2_ck,
 362         .clksel         = abe_clk_div,
 363         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 364         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 365         .ops            = &clkops_null,
 366         .recalc         = &omap2_clksel_recalc,
 367         .round_rate     = &omap2_clksel_round_rate,
 368         .set_rate       = &omap2_clksel_set_rate,
 369 };
 370
 371 static const struct clksel_rate div2_1to2_rates[] = {
 372         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 373         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 374         { .div = 0 },
 375 };
 376
 377 static const struct clksel aess_fclk_div[] = {
 378         { .parent = &abe_clk, .rates = div2_1to2_rates },
 379         { .parent = NULL },
 380 };
 381
 382 static struct clk aess_fclk = {
 383         .name           = "aess_fclk",
 384         .parent         = &abe_clk,
 385         .clksel         = aess_fclk_div,
 386         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 387         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 388         .ops            = &clkops_null,
 389         .recalc         = &omap2_clksel_recalc,
 390         .round_rate     = &omap2_clksel_round_rate,
 391         .set_rate       = &omap2_clksel_set_rate,
 392 };
 393
 394 static struct clk dpll_abe_m3x2_ck = {
 395         .name           = "dpll_abe_m3x2_ck",
 396         .parent         = &dpll_abe_x2_ck,
 397         .clksel         = dpll_abe_m2x2_div,
 398         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 399         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 400         .ops            = &clkops_omap4_dpllmx_ops,
 401         .recalc         = &omap2_clksel_recalc,
 402         .round_rate     = &omap2_clksel_round_rate,
 403         .set_rate       = &omap2_clksel_set_rate,
 404 };
 405
 406 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 407         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 408         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 409         { .parent = NULL },
 410 };
 411
 412 static struct clk core_hsd_byp_clk_mux_ck = {
 413         .name           = "core_hsd_byp_clk_mux_ck",
 414         .parent         = &sys_clkin_ck,
 415         .clksel         = core_hsd_byp_clk_mux_sel,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 418         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 419         .ops            = &clkops_null,
 420         .recalc         = &omap2_clksel_recalc,
 421 };
 422
 423 /* DPLL_CORE */
 424 static struct dpll_data dpll_core_dd = {
 425         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 426         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 427         .clk_ref        = &sys_clkin_ck,
 428         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 429         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 430         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 431         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 432         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 433         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 434         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 435         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 436         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 437         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 438         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 439         .min_divider    = 1,
 440 };
 441
 442
 443 static struct clk dpll_core_ck = {
 444         .name           = "dpll_core_ck",
 445         .parent         = &sys_clkin_ck,
 446         .dpll_data      = &dpll_core_dd,
 447         .init           = &omap2_init_dpll_parent,
 448         .ops            = &clkops_omap3_core_dpll_ops,
 449         .recalc         = &omap3_dpll_recalc,
 450 };
 451
 452 static struct clk dpll_core_x2_ck = {
 453         .name           = "dpll_core_x2_ck",
 454         .parent         = &dpll_core_ck,
 455         .flags          = CLOCK_CLKOUTX2,
 456         .ops            = &clkops_null,
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel dpll_core_m6x2_div[] = {
 461         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 462         { .parent = NULL },
 463 };
 464
 465 static struct clk dpll_core_m6x2_ck = {
 466         .name           = "dpll_core_m6x2_ck",
 467         .parent         = &dpll_core_x2_ck,
 468         .clksel         = dpll_core_m6x2_div,
 469         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 470         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 471         .ops            = &clkops_omap4_dpllmx_ops,
 472         .recalc         = &omap2_clksel_recalc,
 473         .round_rate     = &omap2_clksel_round_rate,
 474         .set_rate       = &omap2_clksel_set_rate,
 475 };
 476
 477 static const struct clksel dbgclk_mux_sel[] = {
 478         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 479         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 480         { .parent = NULL },
 481 };
 482
 483 static struct clk dbgclk_mux_ck = {
 484         .name           = "dbgclk_mux_ck",
 485         .parent         = &sys_clkin_ck,
 486         .ops            = &clkops_null,
 487         .recalc         = &followparent_recalc,
 488 };
 489
 490 static const struct clksel dpll_core_m2_div[] = {
 491         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 492         { .parent = NULL },
 493 };
 494
 495 static struct clk dpll_core_m2_ck = {
 496         .name           = "dpll_core_m2_ck",
 497         .parent         = &dpll_core_ck,
 498         .clksel         = dpll_core_m2_div,
 499         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 500         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 501         .ops            = &clkops_omap4_dpllmx_ops,
 502         .recalc         = &omap2_clksel_recalc,
 503         .round_rate     = &omap2_clksel_round_rate,
 504         .set_rate       = &omap2_clksel_set_rate,
 505 };
 506
 507 static struct clk ddrphy_ck = {
 508         .name           = "ddrphy_ck",
 509         .parent         = &dpll_core_m2_ck,
 510         .ops            = &clkops_null,
 511         .fixed_div      = 2,
 512         .recalc         = &omap_fixed_divisor_recalc,
 513 };
 514
 515 static struct clk dpll_core_m5x2_ck = {
 516         .name           = "dpll_core_m5x2_ck",
 517         .parent         = &dpll_core_x2_ck,
 518         .clksel         = dpll_core_m6x2_div,
 519         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 520         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 521         .ops            = &clkops_omap4_dpllmx_ops,
 522         .recalc         = &omap2_clksel_recalc,
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap2_clksel_set_rate,
 525 };
 526
 527 static const struct clksel div_core_div[] = {
 528         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 529         { .parent = NULL },
 530 };
 531
 532 static struct clk div_core_ck = {
 533         .name           = "div_core_ck",
 534         .parent         = &dpll_core_m5x2_ck,
 535         .clksel         = div_core_div,
 536         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 537         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 538         .ops            = &clkops_null,
 539         .recalc         = &omap2_clksel_recalc,
 540         .round_rate     = &omap2_clksel_round_rate,
 541         .set_rate       = &omap2_clksel_set_rate,
 542 };
 543
 544 static const struct clksel_rate div4_1to8_rates[] = {
 545         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 546         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 547         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 548         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 549         { .div = 0 },
 550 };
 551
 552 static const struct clksel div_iva_hs_clk_div[] = {
 553         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 554         { .parent = NULL },
 555 };
 556
 557 static struct clk div_iva_hs_clk = {
 558         .name           = "div_iva_hs_clk",
 559         .parent         = &dpll_core_m5x2_ck,
 560         .clksel         = div_iva_hs_clk_div,
 561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 563         .ops            = &clkops_null,
 564         .recalc         = &omap2_clksel_recalc,
 565         .round_rate     = &omap2_clksel_round_rate,
 566         .set_rate       = &omap2_clksel_set_rate,
 567 };
 568
 569 static struct clk div_mpu_hs_clk = {
 570         .name           = "div_mpu_hs_clk",
 571         .parent         = &dpll_core_m5x2_ck,
 572         .clksel         = div_iva_hs_clk_div,
 573         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 574         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 575         .ops            = &clkops_null,
 576         .recalc         = &omap2_clksel_recalc,
 577         .round_rate     = &omap2_clksel_round_rate,
 578         .set_rate       = &omap2_clksel_set_rate,
 579 };
 580
 581 static struct clk dpll_core_m4x2_ck = {
 582         .name           = "dpll_core_m4x2_ck",
 583         .parent         = &dpll_core_x2_ck,
 584         .clksel         = dpll_core_m6x2_div,
 585         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 586         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 587         .ops            = &clkops_omap4_dpllmx_ops,
 588         .recalc         = &omap2_clksel_recalc,
 589         .round_rate     = &omap2_clksel_round_rate,
 590         .set_rate       = &omap2_clksel_set_rate,
 591 };
 592
 593 static struct clk dll_clk_div_ck = {
 594         .name           = "dll_clk_div_ck",
 595         .parent         = &dpll_core_m4x2_ck,
 596         .ops            = &clkops_null,
 597         .fixed_div      = 2,
 598         .recalc         = &omap_fixed_divisor_recalc,
 599 };
 600
 601 static const struct clksel dpll_abe_m2_div[] = {
 602         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 603         { .parent = NULL },
 604 };
 605
 606 static struct clk dpll_abe_m2_ck = {
 607         .name           = "dpll_abe_m2_ck",
 608         .parent         = &dpll_abe_ck,
 609         .clksel         = dpll_abe_m2_div,
 610         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 611         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 612         .ops            = &clkops_omap4_dpllmx_ops,
 613         .recalc         = &omap2_clksel_recalc,
 614         .round_rate     = &omap2_clksel_round_rate,
 615         .set_rate       = &omap2_clksel_set_rate,
 616 };
 617
 618 static struct clk dpll_core_m3x2_ck = {
 619         .name           = "dpll_core_m3x2_ck",
 620         .parent         = &dpll_core_x2_ck,
 621         .clksel         = dpll_core_m6x2_div,
 622         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 623         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 624         .ops            = &clkops_omap2_dflt,
 625         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 626         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 627         .recalc         = &omap2_clksel_recalc,
 628         .round_rate     = &omap2_clksel_round_rate,
 629         .set_rate       = &omap2_clksel_set_rate,
 630 };
 631
 632 static struct clk dpll_core_m7x2_ck = {
 633         .name           = "dpll_core_m7x2_ck",
 634         .parent         = &dpll_core_x2_ck,
 635         .clksel         = dpll_core_m6x2_div,
 636         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 637         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 638         .ops            = &clkops_omap4_dpllmx_ops,
 639         .recalc         = &omap2_clksel_recalc,
 640         .round_rate     = &omap2_clksel_round_rate,
 641         .set_rate       = &omap2_clksel_set_rate,
 642 };
 643
 644 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 645         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 646         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 647         { .parent = NULL },
 648 };
 649
 650 static struct clk iva_hsd_byp_clk_mux_ck = {
 651         .name           = "iva_hsd_byp_clk_mux_ck",
 652         .parent         = &sys_clkin_ck,
 653         .clksel         = iva_hsd_byp_clk_mux_sel,
 654         .init           = &omap2_init_clksel_parent,
 655         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 656         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 657         .ops            = &clkops_null,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 /* DPLL_IVA */
 662 static struct dpll_data dpll_iva_dd = {
 663         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 664         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 665         .clk_ref        = &sys_clkin_ck,
 666         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 667         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 668         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 669         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 670         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 671         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 672         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 673         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 674         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 675         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 676         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 677         .min_divider    = 1,
 678 };
 679
 680
 681 static struct clk dpll_iva_ck = {
 682         .name           = "dpll_iva_ck",
 683         .parent         = &sys_clkin_ck,
 684         .dpll_data      = &dpll_iva_dd,
 685         .init           = &omap2_init_dpll_parent,
 686         .ops            = &clkops_omap3_noncore_dpll_ops,
 687         .recalc         = &omap3_dpll_recalc,
 688         .round_rate     = &omap2_dpll_round_rate,
 689         .set_rate       = &omap3_noncore_dpll_set_rate,
 690 };
 691
 692 static struct clk dpll_iva_x2_ck = {
 693         .name           = "dpll_iva_x2_ck",
 694         .parent         = &dpll_iva_ck,
 695         .flags          = CLOCK_CLKOUTX2,
 696         .ops            = &clkops_null,
 697         .recalc         = &omap3_clkoutx2_recalc,
 698 };
 699
 700 static const struct clksel dpll_iva_m4x2_div[] = {
 701         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 702         { .parent = NULL },
 703 };
 704
 705 static struct clk dpll_iva_m4x2_ck = {
 706         .name           = "dpll_iva_m4x2_ck",
 707         .parent         = &dpll_iva_x2_ck,
 708         .clksel         = dpll_iva_m4x2_div,
 709         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 710         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 711         .ops            = &clkops_omap4_dpllmx_ops,
 712         .recalc         = &omap2_clksel_recalc,
 713         .round_rate     = &omap2_clksel_round_rate,
 714         .set_rate       = &omap2_clksel_set_rate,
 715 };
 716
 717 static struct clk dpll_iva_m5x2_ck = {
 718         .name           = "dpll_iva_m5x2_ck",
 719         .parent         = &dpll_iva_x2_ck,
 720         .clksel         = dpll_iva_m4x2_div,
 721         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 722         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 723         .ops            = &clkops_omap4_dpllmx_ops,
 724         .recalc         = &omap2_clksel_recalc,
 725         .round_rate     = &omap2_clksel_round_rate,
 726         .set_rate       = &omap2_clksel_set_rate,
 727 };
 728
 729 /* DPLL_MPU */
 730 static struct dpll_data dpll_mpu_dd = {
 731         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 732         .clk_bypass     = &div_mpu_hs_clk,
 733         .clk_ref        = &sys_clkin_ck,
 734         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 735         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 736         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 737         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 738         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 739         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 740         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 741         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 742         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 743         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 744         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 745         .min_divider    = 1,
 746 };
 747
 748
 749 static struct clk dpll_mpu_ck = {
 750         .name           = "dpll_mpu_ck",
 751         .parent         = &sys_clkin_ck,
 752         .dpll_data      = &dpll_mpu_dd,
 753         .init           = &omap2_init_dpll_parent,
 754         .ops            = &clkops_omap3_noncore_dpll_ops,
 755         .recalc         = &omap3_dpll_recalc,
 756         .round_rate     = &omap2_dpll_round_rate,
 757         .set_rate       = &omap3_noncore_dpll_set_rate,
 758 };
 759
 760 static const struct clksel dpll_mpu_m2_div[] = {
 761         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 762         { .parent = NULL },
 763 };
 764
 765 static struct clk dpll_mpu_m2_ck = {
 766         .name           = "dpll_mpu_m2_ck",
 767         .parent         = &dpll_mpu_ck,
 768         .clksel         = dpll_mpu_m2_div,
 769         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 770         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 771         .ops            = &clkops_omap4_dpllmx_ops,
 772         .recalc         = &omap2_clksel_recalc,
 773         .round_rate     = &omap2_clksel_round_rate,
 774         .set_rate       = &omap2_clksel_set_rate,
 775 };
 776
 777 static struct clk per_hs_clk_div_ck = {
 778         .name           = "per_hs_clk_div_ck",
 779         .parent         = &dpll_abe_m3x2_ck,
 780         .ops            = &clkops_null,
 781         .fixed_div      = 2,
 782         .recalc         = &omap_fixed_divisor_recalc,
 783 };
 784
 785 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 786         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 787         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 788         { .parent = NULL },
 789 };
 790
 791 static struct clk per_hsd_byp_clk_mux_ck = {
 792         .name           = "per_hsd_byp_clk_mux_ck",
 793         .parent         = &sys_clkin_ck,
 794         .clksel         = per_hsd_byp_clk_mux_sel,
 795         .init           = &omap2_init_clksel_parent,
 796         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 797         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 798         .ops            = &clkops_null,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 /* DPLL_PER */
 803 static struct dpll_data dpll_per_dd = {
 804         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 805         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 806         .clk_ref        = &sys_clkin_ck,
 807         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 808         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 809         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 810         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 811         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 812         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 813         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 814         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 815         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 816         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 817         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 818         .min_divider    = 1,
 819 };
 820
 821
 822 static struct clk dpll_per_ck = {
 823         .name           = "dpll_per_ck",
 824         .parent         = &sys_clkin_ck,
 825         .dpll_data      = &dpll_per_dd,
 826         .init           = &omap2_init_dpll_parent,
 827         .ops            = &clkops_omap3_noncore_dpll_ops,
 828         .recalc         = &omap3_dpll_recalc,
 829         .round_rate     = &omap2_dpll_round_rate,
 830         .set_rate       = &omap3_noncore_dpll_set_rate,
 831 };
 832
 833 static const struct clksel dpll_per_m2_div[] = {
 834         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 835         { .parent = NULL },
 836 };
 837
 838 static struct clk dpll_per_m2_ck = {
 839         .name           = "dpll_per_m2_ck",
 840         .parent         = &dpll_per_ck,
 841         .clksel         = dpll_per_m2_div,
 842         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 843         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 844         .ops            = &clkops_omap4_dpllmx_ops,
 845         .recalc         = &omap2_clksel_recalc,
 846         .round_rate     = &omap2_clksel_round_rate,
 847         .set_rate       = &omap2_clksel_set_rate,
 848 };
 849
 850 static struct clk dpll_per_x2_ck = {
 851         .name           = "dpll_per_x2_ck",
 852         .parent         = &dpll_per_ck,
 853         .flags          = CLOCK_CLKOUTX2,
 854         .ops            = &clkops_omap4_dpllmx_ops,
 855         .recalc         = &omap3_clkoutx2_recalc,
 856         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 857 };
 858
 859 static const struct clksel dpll_per_m2x2_div[] = {
 860         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 861         { .parent = NULL },
 862 };
 863
 864 static struct clk dpll_per_m2x2_ck = {
 865         .name           = "dpll_per_m2x2_ck",
 866         .parent         = &dpll_per_x2_ck,
 867         .clksel         = dpll_per_m2x2_div,
 868         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 869         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 870         .ops            = &clkops_omap4_dpllmx_ops,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate,
 874 };
 875
 876 static struct clk dpll_per_m3x2_ck = {
 877         .name           = "dpll_per_m3x2_ck",
 878         .parent         = &dpll_per_x2_ck,
 879         .clksel         = dpll_per_m2x2_div,
 880         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 881         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 882         .ops            = &clkops_omap2_dflt,
 883         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 884         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 885         .recalc         = &omap2_clksel_recalc,
 886         .round_rate     = &omap2_clksel_round_rate,
 887         .set_rate       = &omap2_clksel_set_rate,
 888 };
 889
 890 static struct clk dpll_per_m4x2_ck = {
 891         .name           = "dpll_per_m4x2_ck",
 892         .parent         = &dpll_per_x2_ck,
 893         .clksel         = dpll_per_m2x2_div,
 894         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 896         .ops            = &clkops_omap4_dpllmx_ops,
 897         .recalc         = &omap2_clksel_recalc,
 898         .round_rate     = &omap2_clksel_round_rate,
 899         .set_rate       = &omap2_clksel_set_rate,
 900 };
 901
 902 static struct clk dpll_per_m5x2_ck = {
 903         .name           = "dpll_per_m5x2_ck",
 904         .parent         = &dpll_per_x2_ck,
 905         .clksel         = dpll_per_m2x2_div,
 906         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 907         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 908         .ops            = &clkops_omap4_dpllmx_ops,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate,
 912 };
 913
 914 static struct clk dpll_per_m6x2_ck = {
 915         .name           = "dpll_per_m6x2_ck",
 916         .parent         = &dpll_per_x2_ck,
 917         .clksel         = dpll_per_m2x2_div,
 918         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 919         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 920         .ops            = &clkops_omap4_dpllmx_ops,
 921         .recalc         = &omap2_clksel_recalc,
 922         .round_rate     = &omap2_clksel_round_rate,
 923         .set_rate       = &omap2_clksel_set_rate,
 924 };
 925
 926 static struct clk dpll_per_m7x2_ck = {
 927         .name           = "dpll_per_m7x2_ck",
 928         .parent         = &dpll_per_x2_ck,
 929         .clksel         = dpll_per_m2x2_div,
 930         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 931         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 932         .ops            = &clkops_omap4_dpllmx_ops,
 933         .recalc         = &omap2_clksel_recalc,
 934         .round_rate     = &omap2_clksel_round_rate,
 935         .set_rate       = &omap2_clksel_set_rate,
 936 };
 937
 938 /* DPLL_UNIPRO */
 939 static struct dpll_data dpll_unipro_dd = {
 940         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 941         .clk_bypass     = &sys_clkin_ck,
 942         .clk_ref        = &sys_clkin_ck,
 943         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 944         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 945         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 946         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 947         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 948         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 949         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 950         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 951         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 952         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 953         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 954         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 955         .min_divider    = 1,
 956 };
 957
 958
 959 static struct clk dpll_unipro_ck = {
 960         .name           = "dpll_unipro_ck",
 961         .parent         = &sys_clkin_ck,
 962         .dpll_data      = &dpll_unipro_dd,
 963         .init           = &omap2_init_dpll_parent,
 964         .ops            = &clkops_omap3_noncore_dpll_ops,
 965         .recalc         = &omap3_dpll_recalc,
 966         .round_rate     = &omap2_dpll_round_rate,
 967         .set_rate       = &omap3_noncore_dpll_set_rate,
 968 };
 969
 970 static struct clk dpll_unipro_x2_ck = {
 971         .name           = "dpll_unipro_x2_ck",
 972         .parent         = &dpll_unipro_ck,
 973         .flags          = CLOCK_CLKOUTX2,
 974         .ops            = &clkops_null,
 975         .recalc         = &omap3_clkoutx2_recalc,
 976 };
 977
 978 static const struct clksel dpll_unipro_m2x2_div[] = {
 979         { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
 980         { .parent = NULL },
 981 };
 982
 983 static struct clk dpll_unipro_m2x2_ck = {
 984         .name           = "dpll_unipro_m2x2_ck",
 985         .parent         = &dpll_unipro_x2_ck,
 986         .clksel         = dpll_unipro_m2x2_div,
 987         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 988         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 989         .ops            = &clkops_omap4_dpllmx_ops,
 990         .recalc         = &omap2_clksel_recalc,
 991         .round_rate     = &omap2_clksel_round_rate,
 992         .set_rate       = &omap2_clksel_set_rate,
 993 };
 994
 995 static struct clk usb_hs_clk_div_ck = {
 996         .name           = "usb_hs_clk_div_ck",
 997         .parent         = &dpll_abe_m3x2_ck,
 998         .ops            = &clkops_null,
 999         .fixed_div      = 3,
1000         .recalc         = &omap_fixed_divisor_recalc,
1001 };
1002
1003 /* DPLL_USB */
1004 static struct dpll_data dpll_usb_dd = {
1005         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
1006         .clk_bypass     = &usb_hs_clk_div_ck,
1007         .flags          = DPLL_J_TYPE,
1008         .clk_ref        = &sys_clkin_ck,
1009         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
1010         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1011         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1012         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1013         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1014         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1015         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1016         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1017         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1018         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
1019         .max_divider    = OMAP4430_MAX_DPLL_DIV,
1020         .min_divider    = 1,
1021 };
1022
1023
1024 static struct clk dpll_usb_ck = {
1025         .name           = "dpll_usb_ck",
1026         .parent         = &sys_clkin_ck,
1027         .dpll_data      = &dpll_usb_dd,
1028         .init           = &omap2_init_dpll_parent,
1029         .ops            = &clkops_omap3_noncore_dpll_ops,
1030         .recalc         = &omap3_dpll_recalc,
1031         .round_rate     = &omap2_dpll_round_rate,
1032         .set_rate       = &omap3_noncore_dpll_set_rate,
1033 };
1034
1035 static struct clk dpll_usb_clkdcoldo_ck = {
1036         .name           = "dpll_usb_clkdcoldo_ck",
1037         .parent         = &dpll_usb_ck,
1038         .ops            = &clkops_omap4_dpllmx_ops,
1039         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
1040         .recalc         = &followparent_recalc,
1041 };
1042
1043 static const struct clksel dpll_usb_m2_div[] = {
1044         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1045         { .parent = NULL },
1046 };
1047
1048 static struct clk dpll_usb_m2_ck = {
1049         .name           = "dpll_usb_m2_ck",
1050         .parent         = &dpll_usb_ck,
1051         .clksel         = dpll_usb_m2_div,
1052         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1053         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1054         .ops            = &clkops_omap4_dpllmx_ops,
1055         .recalc         = &omap2_clksel_recalc,
1056         .round_rate     = &omap2_clksel_round_rate,
1057         .set_rate       = &omap2_clksel_set_rate,
1058 };
1059
1060 static const struct clksel ducati_clk_mux_sel[] = {
1061         { .parent = &div_core_ck, .rates = div_1_0_rates },
1062         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1063         { .parent = NULL },
1064 };
1065
1066 static struct clk ducati_clk_mux_ck = {
1067         .name           = "ducati_clk_mux_ck",
1068         .parent         = &div_core_ck,
1069         .clksel         = ducati_clk_mux_sel,
1070         .init           = &omap2_init_clksel_parent,
1071         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1072         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1073         .ops            = &clkops_null,
1074         .recalc         = &omap2_clksel_recalc,
1075 };
1076
1077 static struct clk func_12m_fclk = {
1078         .name           = "func_12m_fclk",
1079         .parent         = &dpll_per_m2x2_ck,
1080         .ops            = &clkops_null,
1081         .fixed_div      = 16,
1082         .recalc         = &omap_fixed_divisor_recalc,
1083 };
1084
1085 static struct clk func_24m_clk = {
1086         .name           = "func_24m_clk",
1087         .parent         = &dpll_per_m2_ck,
1088         .ops            = &clkops_null,
1089         .fixed_div      = 4,
1090         .recalc         = &omap_fixed_divisor_recalc,
1091 };
1092
1093 static struct clk func_24mc_fclk = {
1094         .name           = "func_24mc_fclk",
1095         .parent         = &dpll_per_m2x2_ck,
1096         .ops            = &clkops_null,
1097         .fixed_div      = 8,
1098         .recalc         = &omap_fixed_divisor_recalc,
1099 };
1100
1101 static const struct clksel_rate div2_4to8_rates[] = {
1102         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1103         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1104         { .div = 0 },
1105 };
1106
1107 static const struct clksel func_48m_fclk_div[] = {
1108         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1109         { .parent = NULL },
1110 };
1111
1112 static struct clk func_48m_fclk = {
1113         .name           = "func_48m_fclk",
1114         .parent         = &dpll_per_m2x2_ck,
1115         .clksel         = func_48m_fclk_div,
1116         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1117         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1118         .ops            = &clkops_null,
1119         .recalc         = &omap2_clksel_recalc,
1120         .round_rate     = &omap2_clksel_round_rate,
1121         .set_rate       = &omap2_clksel_set_rate,
1122 };
1123
1124 static struct clk func_48mc_fclk = {
1125         .name           = "func_48mc_fclk",
1126         .parent         = &dpll_per_m2x2_ck,
1127         .ops            = &clkops_null,
1128         .fixed_div      = 4,
1129         .recalc         = &omap_fixed_divisor_recalc,
1130 };
1131
1132 static const struct clksel_rate div2_2to4_rates[] = {
1133         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1134         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1135         { .div = 0 },
1136 };
1137
1138 static const struct clksel func_64m_fclk_div[] = {
1139         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1140         { .parent = NULL },
1141 };
1142
1143 static struct clk func_64m_fclk = {
1144         .name           = "func_64m_fclk",
1145         .parent         = &dpll_per_m4x2_ck,
1146         .clksel         = func_64m_fclk_div,
1147         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1148         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1149         .ops            = &clkops_null,
1150         .recalc         = &omap2_clksel_recalc,
1151         .round_rate     = &omap2_clksel_round_rate,
1152         .set_rate       = &omap2_clksel_set_rate,
1153 };
1154
1155 static const struct clksel func_96m_fclk_div[] = {
1156         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1157         { .parent = NULL },
1158 };
1159
1160 static struct clk func_96m_fclk = {
1161         .name           = "func_96m_fclk",
1162         .parent         = &dpll_per_m2x2_ck,
1163         .clksel         = func_96m_fclk_div,
1164         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1165         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1166         .ops            = &clkops_null,
1167         .recalc         = &omap2_clksel_recalc,
1168         .round_rate     = &omap2_clksel_round_rate,
1169         .set_rate       = &omap2_clksel_set_rate,
1170 };
1171
1172 static const struct clksel hsmmc6_fclk_sel[] = {
1173         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1174         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1175         { .parent = NULL },
1176 };
1177
1178 static struct clk hsmmc6_fclk = {
1179         .name           = "hsmmc6_fclk",
1180         .parent         = &func_64m_fclk,
1181         .ops            = &clkops_null,
1182         .recalc         = &followparent_recalc,
1183 };
1184
1185 static const struct clksel_rate div2_1to8_rates[] = {
1186         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1187         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1188         { .div = 0 },
1189 };
1190
1191 static const struct clksel init_60m_fclk_div[] = {
1192         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1193         { .parent = NULL },
1194 };
1195
1196 static struct clk init_60m_fclk = {
1197         .name           = "init_60m_fclk",
1198         .parent         = &dpll_usb_m2_ck,
1199         .clksel         = init_60m_fclk_div,
1200         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1201         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1202         .ops            = &clkops_null,
1203         .recalc         = &omap2_clksel_recalc,
1204         .round_rate     = &omap2_clksel_round_rate,
1205         .set_rate       = &omap2_clksel_set_rate,
1206 };
1207
1208 static const struct clksel l3_div_div[] = {
1209         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1210         { .parent = NULL },
1211 };
1212
1213 static struct clk l3_div_ck = {
1214         .name           = "l3_div_ck",
1215         .parent         = &div_core_ck,
1216         .clksel         = l3_div_div,
1217         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1218         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1219         .ops            = &clkops_null,
1220         .recalc         = &omap2_clksel_recalc,
1221         .round_rate     = &omap2_clksel_round_rate,
1222         .set_rate       = &omap2_clksel_set_rate,
1223 };
1224
1225 static const struct clksel l4_div_div[] = {
1226         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1227         { .parent = NULL },
1228 };
1229
1230 static struct clk l4_div_ck = {
1231         .name           = "l4_div_ck",
1232         .parent         = &l3_div_ck,
1233         .clksel         = l4_div_div,
1234         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1235         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1236         .ops            = &clkops_null,
1237         .recalc         = &omap2_clksel_recalc,
1238         .round_rate     = &omap2_clksel_round_rate,
1239         .set_rate       = &omap2_clksel_set_rate,
1240 };
1241
1242 static struct clk lp_clk_div_ck = {
1243         .name           = "lp_clk_div_ck",
1244         .parent         = &dpll_abe_m2x2_ck,
1245         .ops            = &clkops_null,
1246         .fixed_div      = 16,
1247         .recalc         = &omap_fixed_divisor_recalc,
1248 };
1249
1250 static const struct clksel l4_wkup_clk_mux_sel[] = {
1251         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1252         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1253         { .parent = NULL },
1254 };
1255
1256 static struct clk l4_wkup_clk_mux_ck = {
1257         .name           = "l4_wkup_clk_mux_ck",
1258         .parent         = &sys_clkin_ck,
1259         .clksel         = l4_wkup_clk_mux_sel,
1260         .init           = &omap2_init_clksel_parent,
1261         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1262         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1263         .ops            = &clkops_null,
1264         .recalc         = &omap2_clksel_recalc,
1265 };
1266
1267 static const struct clksel per_abe_nc_fclk_div[] = {
1268         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1269         { .parent = NULL },
1270 };
1271
1272 static struct clk per_abe_nc_fclk = {
1273         .name           = "per_abe_nc_fclk",
1274         .parent         = &dpll_abe_m2_ck,
1275         .clksel         = per_abe_nc_fclk_div,
1276         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1277         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1278         .ops            = &clkops_null,
1279         .recalc         = &omap2_clksel_recalc,
1280         .round_rate     = &omap2_clksel_round_rate,
1281         .set_rate       = &omap2_clksel_set_rate,
1282 };
1283
1284 static const struct clksel mcasp2_fclk_sel[] = {
1285         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1286         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1287         { .parent = NULL },
1288 };
1289
1290 static struct clk mcasp2_fclk = {
1291         .name           = "mcasp2_fclk",
1292         .parent         = &func_96m_fclk,
1293         .ops            = &clkops_null,
1294         .recalc         = &followparent_recalc,
1295 };
1296
1297 static struct clk mcasp3_fclk = {
1298         .name           = "mcasp3_fclk",
1299         .parent         = &func_96m_fclk,
1300         .ops            = &clkops_null,
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk ocp_abe_iclk = {
1305         .name           = "ocp_abe_iclk",
1306         .parent         = &aess_fclk,
1307         .ops            = &clkops_null,
1308         .recalc         = &followparent_recalc,
1309 };
1310
1311 static struct clk per_abe_24m_fclk = {
1312         .name           = "per_abe_24m_fclk",
1313         .parent         = &dpll_abe_m2_ck,
1314         .ops            = &clkops_null,
1315         .fixed_div      = 4,
1316         .recalc         = &omap_fixed_divisor_recalc,
1317 };
1318
1319 static const struct clksel pmd_stm_clock_mux_sel[] = {
1320         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1321         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1322         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1323         { .parent = NULL },
1324 };
1325
1326 static struct clk pmd_stm_clock_mux_ck = {
1327         .name           = "pmd_stm_clock_mux_ck",
1328         .parent         = &sys_clkin_ck,
1329         .ops            = &clkops_null,
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 static struct clk pmd_trace_clk_mux_ck = {
1334         .name           = "pmd_trace_clk_mux_ck",
1335         .parent         = &sys_clkin_ck,
1336         .ops            = &clkops_null,
1337         .recalc         = &followparent_recalc,
1338 };
1339
1340 static const struct clksel syc_clk_div_div[] = {
1341         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1342         { .parent = NULL },
1343 };
1344
1345 static struct clk syc_clk_div_ck = {
1346         .name           = "syc_clk_div_ck",
1347         .parent         = &sys_clkin_ck,
1348         .clksel         = syc_clk_div_div,
1349         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1350         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1351         .ops            = &clkops_null,
1352         .recalc         = &omap2_clksel_recalc,
1353         .round_rate     = &omap2_clksel_round_rate,
1354         .set_rate       = &omap2_clksel_set_rate,
1355 };
1356
1357 /* Leaf clocks controlled by modules */
1358
1359 static struct clk aes1_fck = {
1360         .name           = "aes1_fck",
1361         .ops            = &clkops_omap2_dflt,
1362         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1363         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1364         .clkdm_name     = "l4_secure_clkdm",
1365         .parent         = &l3_div_ck,
1366         .recalc         = &followparent_recalc,
1367 };
1368
1369 static struct clk aes2_fck = {
1370         .name           = "aes2_fck",
1371         .ops            = &clkops_omap2_dflt,
1372         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1373         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1374         .clkdm_name     = "l4_secure_clkdm",
1375         .parent         = &l3_div_ck,
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 static struct clk aess_fck = {
1380         .name           = "aess_fck",
1381         .ops            = &clkops_omap2_dflt,
1382         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1383         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1384         .clkdm_name     = "abe_clkdm",
1385         .parent         = &aess_fclk,
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 static struct clk bandgap_fclk = {
1390         .name           = "bandgap_fclk",
1391         .ops            = &clkops_omap2_dflt,
1392         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1393         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1394         .clkdm_name     = "l4_wkup_clkdm",
1395         .parent         = &sys_32k_ck,
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 static struct clk des3des_fck = {
1400         .name           = "des3des_fck",
1401         .ops            = &clkops_omap2_dflt,
1402         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1403         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1404         .clkdm_name     = "l4_secure_clkdm",
1405         .parent         = &l4_div_ck,
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 static const struct clksel dmic_sync_mux_sel[] = {
1410         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1411         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1412         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1413         { .parent = NULL },
1414 };
1415
1416 static struct clk dmic_sync_mux_ck = {
1417         .name           = "dmic_sync_mux_ck",
1418         .parent         = &abe_24m_fclk,
1419         .clksel         = dmic_sync_mux_sel,
1420         .init           = &omap2_init_clksel_parent,
1421         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1422         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1423         .ops            = &clkops_null,
1424         .recalc         = &omap2_clksel_recalc,
1425 };
1426
1427 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1428         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1429         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1430         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1431         { .parent = NULL },
1432 };
1433
1434 /* Merged func_dmic_abe_gfclk into dmic */
1435 static struct clk dmic_fck = {
1436         .name           = "dmic_fck",
1437         .parent         = &dmic_sync_mux_ck,
1438         .clksel         = func_dmic_abe_gfclk_sel,
1439         .init           = &omap2_init_clksel_parent,
1440         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1441         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1442         .ops            = &clkops_omap2_dflt,
1443         .recalc         = &omap2_clksel_recalc,
1444         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1445         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1446         .clkdm_name     = "abe_clkdm",
1447 };
1448
1449 static struct clk dsp_fck = {
1450         .name           = "dsp_fck",
1451         .ops            = &clkops_omap2_dflt,
1452         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1453         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1454         .clkdm_name     = "tesla_clkdm",
1455         .parent         = &dpll_iva_m4x2_ck,
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static struct clk dss_sys_clk = {
1460         .name           = "dss_sys_clk",
1461         .ops            = &clkops_omap2_dflt,
1462         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1463         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1464         .clkdm_name     = "l3_dss_clkdm",
1465         .parent         = &syc_clk_div_ck,
1466         .recalc         = &followparent_recalc,
1467 };
1468
1469 static struct clk dss_tv_clk = {
1470         .name           = "dss_tv_clk",
1471         .ops            = &clkops_omap2_dflt,
1472         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1473         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1474         .clkdm_name     = "l3_dss_clkdm",
1475         .parent         = &extalt_clkin_ck,
1476         .recalc         = &followparent_recalc,
1477 };
1478
1479 static struct clk dss_dss_clk = {
1480         .name           = "dss_dss_clk",
1481         .ops            = &clkops_omap2_dflt,
1482         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1483         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1484         .clkdm_name     = "l3_dss_clkdm",
1485         .parent         = &dpll_per_m5x2_ck,
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static struct clk dss_48mhz_clk = {
1490         .name           = "dss_48mhz_clk",
1491         .ops            = &clkops_omap2_dflt,
1492         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1493         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1494         .clkdm_name     = "l3_dss_clkdm",
1495         .parent         = &func_48mc_fclk,
1496         .recalc         = &followparent_recalc,
1497 };
1498
1499 static struct clk dss_fck = {
1500         .name           = "dss_fck",
1501         .ops            = &clkops_omap2_dflt,
1502         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1503         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1504         .clkdm_name     = "l3_dss_clkdm",
1505         .parent         = &l3_div_ck,
1506         .recalc         = &followparent_recalc,
1507 };
1508
1509 static struct clk efuse_ctrl_cust_fck = {
1510         .name           = "efuse_ctrl_cust_fck",
1511         .ops            = &clkops_omap2_dflt,
1512         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1513         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1514         .clkdm_name     = "l4_cefuse_clkdm",
1515         .parent         = &sys_clkin_ck,
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk emif1_fck = {
1520         .name           = "emif1_fck",
1521         .ops            = &clkops_omap2_dflt,
1522         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1523         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1524         .flags          = ENABLE_ON_INIT,
1525         .clkdm_name     = "l3_emif_clkdm",
1526         .parent         = &ddrphy_ck,
1527         .recalc         = &followparent_recalc,
1528 };
1529
1530 static struct clk emif2_fck = {
1531         .name           = "emif2_fck",
1532         .ops            = &clkops_omap2_dflt,
1533         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1534         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1535         .flags          = ENABLE_ON_INIT,
1536         .clkdm_name     = "l3_emif_clkdm",
1537         .parent         = &ddrphy_ck,
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static const struct clksel fdif_fclk_div[] = {
1542         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1543         { .parent = NULL },
1544 };
1545
1546 /* Merged fdif_fclk into fdif */
1547 static struct clk fdif_fck = {
1548         .name           = "fdif_fck",
1549         .parent         = &dpll_per_m4x2_ck,
1550         .clksel         = fdif_fclk_div,
1551         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1552         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1553         .ops            = &clkops_omap2_dflt,
1554         .recalc         = &omap2_clksel_recalc,
1555         .round_rate     = &omap2_clksel_round_rate,
1556         .set_rate       = &omap2_clksel_set_rate,
1557         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1558         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1559         .clkdm_name     = "iss_clkdm",
1560 };
1561
1562 static struct clk fpka_fck = {
1563         .name           = "fpka_fck",
1564         .ops            = &clkops_omap2_dflt,
1565         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1566         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1567         .clkdm_name     = "l4_secure_clkdm",
1568         .parent         = &l4_div_ck,
1569         .recalc         = &followparent_recalc,
1570 };
1571
1572 static struct clk gpio1_dbclk = {
1573         .name           = "gpio1_dbclk",
1574         .ops            = &clkops_omap2_dflt,
1575         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1576         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1577         .clkdm_name     = "l4_wkup_clkdm",
1578         .parent         = &sys_32k_ck,
1579         .recalc         = &followparent_recalc,
1580 };
1581
1582 static struct clk gpio1_ick = {
1583         .name           = "gpio1_ick",
1584         .ops            = &clkops_omap2_dflt,
1585         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1586         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1587         .clkdm_name     = "l4_wkup_clkdm",
1588         .parent         = &l4_wkup_clk_mux_ck,
1589         .recalc         = &followparent_recalc,
1590 };
1591
1592 static struct clk gpio2_dbclk = {
1593         .name           = "gpio2_dbclk",
1594         .ops            = &clkops_omap2_dflt,
1595         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1596         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1597         .clkdm_name     = "l4_per_clkdm",
1598         .parent         = &sys_32k_ck,
1599         .recalc         = &followparent_recalc,
1600 };
1601
1602 static struct clk gpio2_ick = {
1603         .name           = "gpio2_ick",
1604         .ops            = &clkops_omap2_dflt,
1605         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1606         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1607         .clkdm_name     = "l4_per_clkdm",
1608         .parent         = &l4_div_ck,
1609         .recalc         = &followparent_recalc,
1610 };
1611
1612 static struct clk gpio3_dbclk = {
1613         .name           = "gpio3_dbclk",
1614         .ops            = &clkops_omap2_dflt,
1615         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1616         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1617         .clkdm_name     = "l4_per_clkdm",
1618         .parent         = &sys_32k_ck,
1619         .recalc         = &followparent_recalc,
1620 };
1621
1622 static struct clk gpio3_ick = {
1623         .name           = "gpio3_ick",
1624         .ops            = &clkops_omap2_dflt,
1625         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1626         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1627         .clkdm_name     = "l4_per_clkdm",
1628         .parent         = &l4_div_ck,
1629         .recalc         = &followparent_recalc,
1630 };
1631
1632 static struct clk gpio4_dbclk = {
1633         .name           = "gpio4_dbclk",
1634         .ops            = &clkops_omap2_dflt,
1635         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1636         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1637         .clkdm_name     = "l4_per_clkdm",
1638         .parent         = &sys_32k_ck,
1639         .recalc         = &followparent_recalc,
1640 };
1641
1642 static struct clk gpio4_ick = {
1643         .name           = "gpio4_ick",
1644         .ops            = &clkops_omap2_dflt,
1645         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1646         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1647         .clkdm_name     = "l4_per_clkdm",
1648         .parent         = &l4_div_ck,
1649         .recalc         = &followparent_recalc,
1650 };
1651
1652 static struct clk gpio5_dbclk = {
1653         .name           = "gpio5_dbclk",
1654         .ops            = &clkops_omap2_dflt,
1655         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1656         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1657         .clkdm_name     = "l4_per_clkdm",
1658         .parent         = &sys_32k_ck,
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static struct clk gpio5_ick = {
1663         .name           = "gpio5_ick",
1664         .ops            = &clkops_omap2_dflt,
1665         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1666         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1667         .clkdm_name     = "l4_per_clkdm",
1668         .parent         = &l4_div_ck,
1669         .recalc         = &followparent_recalc,
1670 };
1671
1672 static struct clk gpio6_dbclk = {
1673         .name           = "gpio6_dbclk",
1674         .ops            = &clkops_omap2_dflt,
1675         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1676         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1677         .clkdm_name     = "l4_per_clkdm",
1678         .parent         = &sys_32k_ck,
1679         .recalc         = &followparent_recalc,
1680 };
1681
1682 static struct clk gpio6_ick = {
1683         .name           = "gpio6_ick",
1684         .ops            = &clkops_omap2_dflt,
1685         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1686         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1687         .clkdm_name     = "l4_per_clkdm",
1688         .parent         = &l4_div_ck,
1689         .recalc         = &followparent_recalc,
1690 };
1691
1692 static struct clk gpmc_ick = {
1693         .name           = "gpmc_ick",
1694         .ops            = &clkops_omap2_dflt,
1695         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1696         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1697         .flags          = ENABLE_ON_INIT,
1698         .clkdm_name     = "l3_2_clkdm",
1699         .parent         = &l3_div_ck,
1700         .recalc         = &followparent_recalc,
1701 };
1702
1703 static const struct clksel sgx_clk_mux_sel[] = {
1704         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1705         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1706         { .parent = NULL },
1707 };
1708
1709 /* Merged sgx_clk_mux into gpu */
1710 static struct clk gpu_fck = {
1711         .name           = "gpu_fck",
1712         .parent         = &dpll_core_m7x2_ck,
1713         .clksel         = sgx_clk_mux_sel,
1714         .init           = &omap2_init_clksel_parent,
1715         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1716         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1717         .ops            = &clkops_omap2_dflt,
1718         .recalc         = &omap2_clksel_recalc,
1719         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1720         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1721         .clkdm_name     = "l3_gfx_clkdm",
1722 };
1723
1724 static struct clk hdq1w_fck = {
1725         .name           = "hdq1w_fck",
1726         .ops            = &clkops_omap2_dflt,
1727         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1728         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1729         .clkdm_name     = "l4_per_clkdm",
1730         .parent         = &func_12m_fclk,
1731         .recalc         = &followparent_recalc,
1732 };
1733
1734 static const struct clksel hsi_fclk_div[] = {
1735         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1736         { .parent = NULL },
1737 };
1738
1739 /* Merged hsi_fclk into hsi */
1740 static struct clk hsi_fck = {
1741         .name           = "hsi_fck",
1742         .parent         = &dpll_per_m2x2_ck,
1743         .clksel         = hsi_fclk_div,
1744         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1745         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1746         .ops            = &clkops_omap2_dflt,
1747         .recalc         = &omap2_clksel_recalc,
1748         .round_rate     = &omap2_clksel_round_rate,
1749         .set_rate       = &omap2_clksel_set_rate,
1750         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1751         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1752         .clkdm_name     = "l3_init_clkdm",
1753 };
1754
1755 static struct clk i2c1_fck = {
1756         .name           = "i2c1_fck",
1757         .ops            = &clkops_omap2_dflt,
1758         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1759         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1760         .clkdm_name     = "l4_per_clkdm",
1761         .parent         = &func_96m_fclk,
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 static struct clk i2c2_fck = {
1766         .name           = "i2c2_fck",
1767         .ops            = &clkops_omap2_dflt,
1768         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1769         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1770         .clkdm_name     = "l4_per_clkdm",
1771         .parent         = &func_96m_fclk,
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk i2c3_fck = {
1776         .name           = "i2c3_fck",
1777         .ops            = &clkops_omap2_dflt,
1778         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1779         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1780         .clkdm_name     = "l4_per_clkdm",
1781         .parent         = &func_96m_fclk,
1782         .recalc         = &followparent_recalc,
1783 };
1784
1785 static struct clk i2c4_fck = {
1786         .name           = "i2c4_fck",
1787         .ops            = &clkops_omap2_dflt,
1788         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1789         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1790         .clkdm_name     = "l4_per_clkdm",
1791         .parent         = &func_96m_fclk,
1792         .recalc         = &followparent_recalc,
1793 };
1794
1795 static struct clk ipu_fck = {
1796         .name           = "ipu_fck",
1797         .ops            = &clkops_omap2_dflt,
1798         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1799         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1800         .clkdm_name     = "ducati_clkdm",
1801         .parent         = &ducati_clk_mux_ck,
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk iss_ctrlclk = {
1806         .name           = "iss_ctrlclk",
1807         .ops            = &clkops_omap2_dflt,
1808         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1809         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1810         .clkdm_name     = "iss_clkdm",
1811         .parent         = &func_96m_fclk,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk iss_fck = {
1816         .name           = "iss_fck",
1817         .ops            = &clkops_omap2_dflt,
1818         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1819         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1820         .clkdm_name     = "iss_clkdm",
1821         .parent         = &ducati_clk_mux_ck,
1822         .recalc         = &followparent_recalc,
1823 };
1824
1825 static struct clk iva_fck = {
1826         .name           = "iva_fck",
1827         .ops            = &clkops_omap2_dflt,
1828         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1829         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1830         .clkdm_name     = "ivahd_clkdm",
1831         .parent         = &dpll_iva_m5x2_ck,
1832         .recalc         = &followparent_recalc,
1833 };
1834
1835 static struct clk kbd_fck = {
1836         .name           = "kbd_fck",
1837         .ops            = &clkops_omap2_dflt,
1838         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1839         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1840         .clkdm_name     = "l4_wkup_clkdm",
1841         .parent         = &sys_32k_ck,
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 static struct clk l3_instr_ick = {
1846         .name           = "l3_instr_ick",
1847         .ops            = &clkops_omap2_dflt,
1848         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1849         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1850         .clkdm_name     = "l3_instr_clkdm",
1851         .flags          = ENABLE_ON_INIT,
1852         .parent         = &l3_div_ck,
1853         .recalc         = &followparent_recalc,
1854 };
1855
1856 static struct clk l3_main_3_ick = {
1857         .name           = "l3_main_3_ick",
1858         .ops            = &clkops_omap2_dflt,
1859         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1860         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1861         .clkdm_name     = "l3_instr_clkdm",
1862         .flags          = ENABLE_ON_INIT,
1863         .parent         = &l3_div_ck,
1864         .recalc         = &followparent_recalc,
1865 };
1866
1867 static struct clk mcasp_sync_mux_ck = {
1868         .name           = "mcasp_sync_mux_ck",
1869         .parent         = &abe_24m_fclk,
1870         .clksel         = dmic_sync_mux_sel,
1871         .init           = &omap2_init_clksel_parent,
1872         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1873         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1874         .ops            = &clkops_null,
1875         .recalc         = &omap2_clksel_recalc,
1876 };
1877
1878 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1879         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1880         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1881         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1882         { .parent = NULL },
1883 };
1884
1885 /* Merged func_mcasp_abe_gfclk into mcasp */
1886 static struct clk mcasp_fck = {
1887         .name           = "mcasp_fck",
1888         .parent         = &mcasp_sync_mux_ck,
1889         .clksel         = func_mcasp_abe_gfclk_sel,
1890         .init           = &omap2_init_clksel_parent,
1891         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1892         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1893         .ops            = &clkops_omap2_dflt,
1894         .recalc         = &omap2_clksel_recalc,
1895         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1896         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1897         .clkdm_name     = "abe_clkdm",
1898 };
1899
1900 static struct clk mcbsp1_sync_mux_ck = {
1901         .name           = "mcbsp1_sync_mux_ck",
1902         .parent         = &abe_24m_fclk,
1903         .clksel         = dmic_sync_mux_sel,
1904         .init           = &omap2_init_clksel_parent,
1905         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1906         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1907         .ops            = &clkops_null,
1908         .recalc         = &omap2_clksel_recalc,
1909 };
1910
1911 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1912         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1913         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1914         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1915         { .parent = NULL },
1916 };
1917
1918 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1919 static struct clk mcbsp1_fck = {
1920         .name           = "mcbsp1_fck",
1921         .parent         = &mcbsp1_sync_mux_ck,
1922         .clksel         = func_mcbsp1_gfclk_sel,
1923         .init           = &omap2_init_clksel_parent,
1924         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1925         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1926         .ops            = &clkops_omap2_dflt,
1927         .recalc         = &omap2_clksel_recalc,
1928         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1929         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1930         .clkdm_name     = "abe_clkdm",
1931 };
1932
1933 static struct clk mcbsp2_sync_mux_ck = {
1934         .name           = "mcbsp2_sync_mux_ck",
1935         .parent         = &abe_24m_fclk,
1936         .clksel         = dmic_sync_mux_sel,
1937         .init           = &omap2_init_clksel_parent,
1938         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1939         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1940         .ops            = &clkops_null,
1941         .recalc         = &omap2_clksel_recalc,
1942 };
1943
1944 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1945         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1946         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1947         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1948         { .parent = NULL },
1949 };
1950
1951 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1952 static struct clk mcbsp2_fck = {
1953         .name           = "mcbsp2_fck",
1954         .parent         = &mcbsp2_sync_mux_ck,
1955         .clksel         = func_mcbsp2_gfclk_sel,
1956         .init           = &omap2_init_clksel_parent,
1957         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1958         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1959         .ops            = &clkops_omap2_dflt,
1960         .recalc         = &omap2_clksel_recalc,
1961         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1962         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1963         .clkdm_name     = "abe_clkdm",
1964 };
1965
1966 static struct clk mcbsp3_sync_mux_ck = {
1967         .name           = "mcbsp3_sync_mux_ck",
1968         .parent         = &abe_24m_fclk,
1969         .clksel         = dmic_sync_mux_sel,
1970         .init           = &omap2_init_clksel_parent,
1971         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1972         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1973         .ops            = &clkops_null,
1974         .recalc         = &omap2_clksel_recalc,
1975 };
1976
1977 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1978         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1979         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1980         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1981         { .parent = NULL },
1982 };
1983
1984 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1985 static struct clk mcbsp3_fck = {
1986         .name           = "mcbsp3_fck",
1987         .parent         = &mcbsp3_sync_mux_ck,
1988         .clksel         = func_mcbsp3_gfclk_sel,
1989         .init           = &omap2_init_clksel_parent,
1990         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1991         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1992         .ops            = &clkops_omap2_dflt,
1993         .recalc         = &omap2_clksel_recalc,
1994         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1995         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1996         .clkdm_name     = "abe_clkdm",
1997 };
1998
1999 static struct clk mcbsp4_sync_mux_ck = {
2000         .name           = "mcbsp4_sync_mux_ck",
2001         .parent         = &func_96m_fclk,
2002         .clksel         = mcasp2_fclk_sel,
2003         .init           = &omap2_init_clksel_parent,
2004         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2005         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2006         .ops            = &clkops_null,
2007         .recalc         = &omap2_clksel_recalc,
2008 };
2009
2010 static const struct clksel per_mcbsp4_gfclk_sel[] = {
2011         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
2012         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2013         { .parent = NULL },
2014 };
2015
2016 /* Merged per_mcbsp4_gfclk into mcbsp4 */
2017 static struct clk mcbsp4_fck = {
2018         .name           = "mcbsp4_fck",
2019         .parent         = &mcbsp4_sync_mux_ck,
2020         .clksel         = per_mcbsp4_gfclk_sel,
2021         .init           = &omap2_init_clksel_parent,
2022         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2023         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2024         .ops            = &clkops_omap2_dflt,
2025         .recalc         = &omap2_clksel_recalc,
2026         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2027         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2028         .clkdm_name     = "l4_per_clkdm",
2029 };
2030
2031 static struct clk mcpdm_fck = {
2032         .name           = "mcpdm_fck",
2033         .ops            = &clkops_omap2_dflt,
2034         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2035         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2036         .clkdm_name     = "abe_clkdm",
2037         .parent         = &pad_clks_ck,
2038         .recalc         = &followparent_recalc,
2039 };
2040
2041 static struct clk mcspi1_fck = {
2042         .name           = "mcspi1_fck",
2043         .ops            = &clkops_omap2_dflt,
2044         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2045         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2046         .clkdm_name     = "l4_per_clkdm",
2047         .parent         = &func_48m_fclk,
2048         .recalc         = &followparent_recalc,
2049 };
2050
2051 static struct clk mcspi2_fck = {
2052         .name           = "mcspi2_fck",
2053         .ops            = &clkops_omap2_dflt,
2054         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2055         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2056         .clkdm_name     = "l4_per_clkdm",
2057         .parent         = &func_48m_fclk,
2058         .recalc         = &followparent_recalc,
2059 };
2060
2061 static struct clk mcspi3_fck = {
2062         .name           = "mcspi3_fck",
2063         .ops            = &clkops_omap2_dflt,
2064         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2065         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2066         .clkdm_name     = "l4_per_clkdm",
2067         .parent         = &func_48m_fclk,
2068         .recalc         = &followparent_recalc,
2069 };
2070
2071 static struct clk mcspi4_fck = {
2072         .name           = "mcspi4_fck",
2073         .ops            = &clkops_omap2_dflt,
2074         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2075         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2076         .clkdm_name     = "l4_per_clkdm",
2077         .parent         = &func_48m_fclk,
2078         .recalc         = &followparent_recalc,
2079 };
2080
2081 /* Merged hsmmc1_fclk into mmc1 */
2082 static struct clk mmc1_fck = {
2083         .name           = "mmc1_fck",
2084         .parent         = &func_64m_fclk,
2085         .clksel         = hsmmc6_fclk_sel,
2086         .init           = &omap2_init_clksel_parent,
2087         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2088         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2089         .ops            = &clkops_omap2_dflt,
2090         .recalc         = &omap2_clksel_recalc,
2091         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2092         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2093         .clkdm_name     = "l3_init_clkdm",
2094 };
2095
2096 /* Merged hsmmc2_fclk into mmc2 */
2097 static struct clk mmc2_fck = {
2098         .name           = "mmc2_fck",
2099         .parent         = &func_64m_fclk,
2100         .clksel         = hsmmc6_fclk_sel,
2101         .init           = &omap2_init_clksel_parent,
2102         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2103         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2104         .ops            = &clkops_omap2_dflt,
2105         .recalc         = &omap2_clksel_recalc,
2106         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2107         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2108         .clkdm_name     = "l3_init_clkdm",
2109 };
2110
2111 static struct clk mmc3_fck = {
2112         .name           = "mmc3_fck",
2113         .ops            = &clkops_omap2_dflt,
2114         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2115         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2116         .clkdm_name     = "l4_per_clkdm",
2117         .parent         = &func_48m_fclk,
2118         .recalc         = &followparent_recalc,
2119 };
2120
2121 static struct clk mmc4_fck = {
2122         .name           = "mmc4_fck",
2123         .ops            = &clkops_omap2_dflt,
2124         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2125         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2126         .clkdm_name     = "l4_per_clkdm",
2127         .parent         = &func_48m_fclk,
2128         .recalc         = &followparent_recalc,
2129 };
2130
2131 static struct clk mmc5_fck = {
2132         .name           = "mmc5_fck",
2133         .ops            = &clkops_omap2_dflt,
2134         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2135         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2136         .clkdm_name     = "l4_per_clkdm",
2137         .parent         = &func_48m_fclk,
2138         .recalc         = &followparent_recalc,
2139 };
2140
2141 static struct clk ocp2scp_usb_phy_phy_48m = {
2142         .name           = "ocp2scp_usb_phy_phy_48m",
2143         .ops            = &clkops_omap2_dflt,
2144         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2145         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2146         .clkdm_name     = "l3_init_clkdm",
2147         .parent         = &func_48m_fclk,
2148         .recalc         = &followparent_recalc,
2149 };
2150
2151 static struct clk ocp2scp_usb_phy_ick = {
2152         .name           = "ocp2scp_usb_phy_ick",
2153         .ops            = &clkops_omap2_dflt,
2154         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2155         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2156         .clkdm_name     = "l3_init_clkdm",
2157         .parent         = &l4_div_ck,
2158         .recalc         = &followparent_recalc,
2159 };
2160
2161 static struct clk ocp_wp_noc_ick = {
2162         .name           = "ocp_wp_noc_ick",
2163         .ops            = &clkops_omap2_dflt,
2164         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2165         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2166         .clkdm_name     = "l3_instr_clkdm",
2167         .flags          = ENABLE_ON_INIT,
2168         .parent         = &l3_div_ck,
2169         .recalc         = &followparent_recalc,
2170 };
2171
2172 static struct clk rng_ick = {
2173         .name           = "rng_ick",
2174         .ops            = &clkops_omap2_dflt,
2175         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2176         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2177         .clkdm_name     = "l4_secure_clkdm",
2178         .parent         = &l4_div_ck,
2179         .recalc         = &followparent_recalc,
2180 };
2181
2182 static struct clk sha2md5_fck = {
2183         .name           = "sha2md5_fck",
2184         .ops            = &clkops_omap2_dflt,
2185         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2186         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2187         .clkdm_name     = "l4_secure_clkdm",
2188         .parent         = &l3_div_ck,
2189         .recalc         = &followparent_recalc,
2190 };
2191
2192 static struct clk sl2if_ick = {
2193         .name           = "sl2if_ick",
2194         .ops            = &clkops_omap2_dflt,
2195         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2196         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2197         .clkdm_name     = "ivahd_clkdm",
2198         .parent         = &dpll_iva_m5x2_ck,
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk slimbus1_fclk_1 = {
2203         .name           = "slimbus1_fclk_1",
2204         .ops            = &clkops_omap2_dflt,
2205         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2206         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2207         .clkdm_name     = "abe_clkdm",
2208         .parent         = &func_24m_clk,
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 static struct clk slimbus1_fclk_0 = {
2213         .name           = "slimbus1_fclk_0",
2214         .ops            = &clkops_omap2_dflt,
2215         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2216         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2217         .clkdm_name     = "abe_clkdm",
2218         .parent         = &abe_24m_fclk,
2219         .recalc         = &followparent_recalc,
2220 };
2221
2222 static struct clk slimbus1_fclk_2 = {
2223         .name           = "slimbus1_fclk_2",
2224         .ops            = &clkops_omap2_dflt,
2225         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2226         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2227         .clkdm_name     = "abe_clkdm",
2228         .parent         = &pad_clks_ck,
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 static struct clk slimbus1_slimbus_clk = {
2233         .name           = "slimbus1_slimbus_clk",
2234         .ops            = &clkops_omap2_dflt,
2235         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2236         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2237         .clkdm_name     = "abe_clkdm",
2238         .parent         = &slimbus_clk,
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk slimbus1_fck = {
2243         .name           = "slimbus1_fck",
2244         .ops            = &clkops_omap2_dflt,
2245         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2246         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2247         .clkdm_name     = "abe_clkdm",
2248         .parent         = &ocp_abe_iclk,
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk slimbus2_fclk_1 = {
2253         .name           = "slimbus2_fclk_1",
2254         .ops            = &clkops_omap2_dflt,
2255         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2256         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2257         .clkdm_name     = "l4_per_clkdm",
2258         .parent         = &per_abe_24m_fclk,
2259         .recalc         = &followparent_recalc,
2260 };
2261
2262 static struct clk slimbus2_fclk_0 = {
2263         .name           = "slimbus2_fclk_0",
2264         .ops            = &clkops_omap2_dflt,
2265         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2266         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2267         .clkdm_name     = "l4_per_clkdm",
2268         .parent         = &func_24mc_fclk,
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk slimbus2_slimbus_clk = {
2273         .name           = "slimbus2_slimbus_clk",
2274         .ops            = &clkops_omap2_dflt,
2275         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2276         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2277         .clkdm_name     = "l4_per_clkdm",
2278         .parent         = &pad_slimbus_core_clks_ck,
2279         .recalc         = &followparent_recalc,
2280 };
2281
2282 static struct clk slimbus2_fck = {
2283         .name           = "slimbus2_fck",
2284         .ops            = &clkops_omap2_dflt,
2285         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2286         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2287         .clkdm_name     = "l4_per_clkdm",
2288         .parent         = &l4_div_ck,
2289         .recalc         = &followparent_recalc,
2290 };
2291
2292 static struct clk smartreflex_core_fck = {
2293         .name           = "smartreflex_core_fck",
2294         .ops            = &clkops_omap2_dflt,
2295         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2296         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2297         .clkdm_name     = "l4_ao_clkdm",
2298         .parent         = &l4_wkup_clk_mux_ck,
2299         .recalc         = &followparent_recalc,
2300 };
2301
2302 static struct clk smartreflex_iva_fck = {
2303         .name           = "smartreflex_iva_fck",
2304         .ops            = &clkops_omap2_dflt,
2305         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2306         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2307         .clkdm_name     = "l4_ao_clkdm",
2308         .parent         = &l4_wkup_clk_mux_ck,
2309         .recalc         = &followparent_recalc,
2310 };
2311
2312 static struct clk smartreflex_mpu_fck = {
2313         .name           = "smartreflex_mpu_fck",
2314         .ops            = &clkops_omap2_dflt,
2315         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2316         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2317         .clkdm_name     = "l4_ao_clkdm",
2318         .parent         = &l4_wkup_clk_mux_ck,
2319         .recalc         = &followparent_recalc,
2320 };
2321
2322 /* Merged dmt1_clk_mux into timer1 */
2323 static struct clk timer1_fck = {
2324         .name           = "timer1_fck",
2325         .parent         = &sys_clkin_ck,
2326         .clksel         = abe_dpll_bypass_clk_mux_sel,
2327         .init           = &omap2_init_clksel_parent,
2328         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2329         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2330         .ops            = &clkops_omap2_dflt,
2331         .recalc         = &omap2_clksel_recalc,
2332         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2333         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2334         .clkdm_name     = "l4_wkup_clkdm",
2335 };
2336
2337 /* Merged cm2_dm10_mux into timer10 */
2338 static struct clk timer10_fck = {
2339         .name           = "timer10_fck",
2340         .parent         = &sys_clkin_ck,
2341         .clksel         = abe_dpll_bypass_clk_mux_sel,
2342         .init           = &omap2_init_clksel_parent,
2343         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2344         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2345         .ops            = &clkops_omap2_dflt,
2346         .recalc         = &omap2_clksel_recalc,
2347         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2348         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2349         .clkdm_name     = "l4_per_clkdm",
2350 };
2351
2352 /* Merged cm2_dm11_mux into timer11 */
2353 static struct clk timer11_fck = {
2354         .name           = "timer11_fck",
2355         .parent         = &sys_clkin_ck,
2356         .clksel         = abe_dpll_bypass_clk_mux_sel,
2357         .init           = &omap2_init_clksel_parent,
2358         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2359         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2360         .ops            = &clkops_omap2_dflt,
2361         .recalc         = &omap2_clksel_recalc,
2362         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2363         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2364         .clkdm_name     = "l4_per_clkdm",
2365 };
2366
2367 /* Merged cm2_dm2_mux into timer2 */
2368 static struct clk timer2_fck = {
2369         .name           = "timer2_fck",
2370         .parent         = &sys_clkin_ck,
2371         .clksel         = abe_dpll_bypass_clk_mux_sel,
2372         .init           = &omap2_init_clksel_parent,
2373         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2374         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2375         .ops            = &clkops_omap2_dflt,
2376         .recalc         = &omap2_clksel_recalc,
2377         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2378         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2379         .clkdm_name     = "l4_per_clkdm",
2380 };
2381
2382 /* Merged cm2_dm3_mux into timer3 */
2383 static struct clk timer3_fck = {
2384         .name           = "timer3_fck",
2385         .parent         = &sys_clkin_ck,
2386         .clksel         = abe_dpll_bypass_clk_mux_sel,
2387         .init           = &omap2_init_clksel_parent,
2388         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2389         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2390         .ops            = &clkops_omap2_dflt,
2391         .recalc         = &omap2_clksel_recalc,
2392         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2393         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2394         .clkdm_name     = "l4_per_clkdm",
2395 };
2396
2397 /* Merged cm2_dm4_mux into timer4 */
2398 static struct clk timer4_fck = {
2399         .name           = "timer4_fck",
2400         .parent         = &sys_clkin_ck,
2401         .clksel         = abe_dpll_bypass_clk_mux_sel,
2402         .init           = &omap2_init_clksel_parent,
2403         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2404         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2405         .ops            = &clkops_omap2_dflt,
2406         .recalc         = &omap2_clksel_recalc,
2407         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2408         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2409         .clkdm_name     = "l4_per_clkdm",
2410 };
2411
2412 static const struct clksel timer5_sync_mux_sel[] = {
2413         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2414         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2415         { .parent = NULL },
2416 };
2417
2418 /* Merged timer5_sync_mux into timer5 */
2419 static struct clk timer5_fck = {
2420         .name           = "timer5_fck",
2421         .parent         = &syc_clk_div_ck,
2422         .clksel         = timer5_sync_mux_sel,
2423         .init           = &omap2_init_clksel_parent,
2424         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2425         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2426         .ops            = &clkops_omap2_dflt,
2427         .recalc         = &omap2_clksel_recalc,
2428         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2429         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2430         .clkdm_name     = "abe_clkdm",
2431 };
2432
2433 /* Merged timer6_sync_mux into timer6 */
2434 static struct clk timer6_fck = {
2435         .name           = "timer6_fck",
2436         .parent         = &syc_clk_div_ck,
2437         .clksel         = timer5_sync_mux_sel,
2438         .init           = &omap2_init_clksel_parent,
2439         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2440         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2441         .ops            = &clkops_omap2_dflt,
2442         .recalc         = &omap2_clksel_recalc,
2443         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2444         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2445         .clkdm_name     = "abe_clkdm",
2446 };
2447
2448 /* Merged timer7_sync_mux into timer7 */
2449 static struct clk timer7_fck = {
2450         .name           = "timer7_fck",
2451         .parent         = &syc_clk_div_ck,
2452         .clksel         = timer5_sync_mux_sel,
2453         .init           = &omap2_init_clksel_parent,
2454         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2455         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2456         .ops            = &clkops_omap2_dflt,
2457         .recalc         = &omap2_clksel_recalc,
2458         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2459         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2460         .clkdm_name     = "abe_clkdm",
2461 };
2462
2463 /* Merged timer8_sync_mux into timer8 */
2464 static struct clk timer8_fck = {
2465         .name           = "timer8_fck",
2466         .parent         = &syc_clk_div_ck,
2467         .clksel         = timer5_sync_mux_sel,
2468         .init           = &omap2_init_clksel_parent,
2469         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2470         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2471         .ops            = &clkops_omap2_dflt,
2472         .recalc         = &omap2_clksel_recalc,
2473         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2474         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2475         .clkdm_name     = "abe_clkdm",
2476 };
2477
2478 /* Merged cm2_dm9_mux into timer9 */
2479 static struct clk timer9_fck = {
2480         .name           = "timer9_fck",
2481         .parent         = &sys_clkin_ck,
2482         .clksel         = abe_dpll_bypass_clk_mux_sel,
2483         .init           = &omap2_init_clksel_parent,
2484         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2485         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2486         .ops            = &clkops_omap2_dflt,
2487         .recalc         = &omap2_clksel_recalc,
2488         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2489         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2490         .clkdm_name     = "l4_per_clkdm",
2491 };
2492
2493 static struct clk uart1_fck = {
2494         .name           = "uart1_fck",
2495         .ops            = &clkops_omap2_dflt,
2496         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2497         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2498         .clkdm_name     = "l4_per_clkdm",
2499         .parent         = &func_48m_fclk,
2500         .recalc         = &followparent_recalc,
2501 };
2502
2503 static struct clk uart2_fck = {
2504         .name           = "uart2_fck",
2505         .ops            = &clkops_omap2_dflt,
2506         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2507         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2508         .clkdm_name     = "l4_per_clkdm",
2509         .parent         = &func_48m_fclk,
2510         .recalc         = &followparent_recalc,
2511 };
2512
2513 static struct clk uart3_fck = {
2514         .name           = "uart3_fck",
2515         .ops            = &clkops_omap2_dflt,
2516         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2517         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2518         .clkdm_name     = "l4_per_clkdm",
2519         .parent         = &func_48m_fclk,
2520         .recalc         = &followparent_recalc,
2521 };
2522
2523 static struct clk uart4_fck = {
2524         .name           = "uart4_fck",
2525         .ops            = &clkops_omap2_dflt,
2526         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2527         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2528         .clkdm_name     = "l4_per_clkdm",
2529         .parent         = &func_48m_fclk,
2530         .recalc         = &followparent_recalc,
2531 };
2532
2533 static struct clk usb_host_fs_fck = {
2534         .name           = "usb_host_fs_fck",
2535         .ops            = &clkops_omap2_dflt,
2536         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2537         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2538         .clkdm_name     = "l3_init_clkdm",
2539         .parent         = &func_48mc_fclk,
2540         .recalc         = &followparent_recalc,
2541 };
2542
2543 static const struct clksel utmi_p1_gfclk_sel[] = {
2544         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2545         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2546         { .parent = NULL },
2547 };
2548
2549 static struct clk utmi_p1_gfclk = {
2550         .name           = "utmi_p1_gfclk",
2551         .parent         = &init_60m_fclk,
2552         .clksel         = utmi_p1_gfclk_sel,
2553         .init           = &omap2_init_clksel_parent,
2554         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2555         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2556         .ops            = &clkops_null,
2557         .recalc         = &omap2_clksel_recalc,
2558 };
2559
2560 static struct clk usb_host_hs_utmi_p1_clk = {
2561         .name           = "usb_host_hs_utmi_p1_clk",
2562         .ops            = &clkops_omap2_dflt,
2563         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2564         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2565         .clkdm_name     = "l3_init_clkdm",
2566         .parent         = &utmi_p1_gfclk,
2567         .recalc         = &followparent_recalc,
2568 };
2569
2570 static const struct clksel utmi_p2_gfclk_sel[] = {
2571         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2572         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2573         { .parent = NULL },
2574 };
2575
2576 static struct clk utmi_p2_gfclk = {
2577         .name           = "utmi_p2_gfclk",
2578         .parent         = &init_60m_fclk,
2579         .clksel         = utmi_p2_gfclk_sel,
2580         .init           = &omap2_init_clksel_parent,
2581         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2582         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2583         .ops            = &clkops_null,
2584         .recalc         = &omap2_clksel_recalc,
2585 };
2586
2587 static struct clk usb_host_hs_utmi_p2_clk = {
2588         .name           = "usb_host_hs_utmi_p2_clk",
2589         .ops            = &clkops_omap2_dflt,
2590         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2591         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2592         .clkdm_name     = "l3_init_clkdm",
2593         .parent         = &utmi_p2_gfclk,
2594         .recalc         = &followparent_recalc,
2595 };
2596
2597 static struct clk usb_host_hs_utmi_p3_clk = {
2598         .name           = "usb_host_hs_utmi_p3_clk",
2599         .ops            = &clkops_omap2_dflt,
2600         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2601         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2602         .clkdm_name     = "l3_init_clkdm",
2603         .parent         = &init_60m_fclk,
2604         .recalc         = &followparent_recalc,
2605 };
2606
2607 static struct clk usb_host_hs_hsic480m_p1_clk = {
2608         .name           = "usb_host_hs_hsic480m_p1_clk",
2609         .ops            = &clkops_omap2_dflt,
2610         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2611         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2612         .clkdm_name     = "l3_init_clkdm",
2613         .parent         = &dpll_usb_m2_ck,
2614         .recalc         = &followparent_recalc,
2615 };
2616
2617 static struct clk usb_host_hs_hsic60m_p1_clk = {
2618         .name           = "usb_host_hs_hsic60m_p1_clk",
2619         .ops            = &clkops_omap2_dflt,
2620         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2621         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2622         .clkdm_name     = "l3_init_clkdm",
2623         .parent         = &init_60m_fclk,
2624         .recalc         = &followparent_recalc,
2625 };
2626
2627 static struct clk usb_host_hs_hsic60m_p2_clk = {
2628         .name           = "usb_host_hs_hsic60m_p2_clk",
2629         .ops            = &clkops_omap2_dflt,
2630         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2631         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2632         .clkdm_name     = "l3_init_clkdm",
2633         .parent         = &init_60m_fclk,
2634         .recalc         = &followparent_recalc,
2635 };
2636
2637 static struct clk usb_host_hs_hsic480m_p2_clk = {
2638         .name           = "usb_host_hs_hsic480m_p2_clk",
2639         .ops            = &clkops_omap2_dflt,
2640         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2641         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2642         .clkdm_name     = "l3_init_clkdm",
2643         .parent         = &dpll_usb_m2_ck,
2644         .recalc         = &followparent_recalc,
2645 };
2646
2647 static struct clk usb_host_hs_func48mclk = {
2648         .name           = "usb_host_hs_func48mclk",
2649         .ops            = &clkops_omap2_dflt,
2650         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2651         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2652         .clkdm_name     = "l3_init_clkdm",
2653         .parent         = &func_48mc_fclk,
2654         .recalc         = &followparent_recalc,
2655 };
2656
2657 static struct clk usb_host_hs_fck = {
2658         .name           = "usb_host_hs_fck",
2659         .ops            = &clkops_omap2_dflt,
2660         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2661         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2662         .clkdm_name     = "l3_init_clkdm",
2663         .parent         = &init_60m_fclk,
2664         .recalc         = &followparent_recalc,
2665 };
2666
2667 static const struct clksel otg_60m_gfclk_sel[] = {
2668         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2669         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2670         { .parent = NULL },
2671 };
2672
2673 static struct clk otg_60m_gfclk = {
2674         .name           = "otg_60m_gfclk",
2675         .parent         = &utmi_phy_clkout_ck,
2676         .clksel         = otg_60m_gfclk_sel,
2677         .init           = &omap2_init_clksel_parent,
2678         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2679         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2680         .ops            = &clkops_null,
2681         .recalc         = &omap2_clksel_recalc,
2682 };
2683
2684 static struct clk usb_otg_hs_xclk = {
2685         .name           = "usb_otg_hs_xclk",
2686         .ops            = &clkops_omap2_dflt,
2687         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2688         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2689         .clkdm_name     = "l3_init_clkdm",
2690         .parent         = &otg_60m_gfclk,
2691         .recalc         = &followparent_recalc,
2692 };
2693
2694 static struct clk usb_otg_hs_ick = {
2695         .name           = "usb_otg_hs_ick",
2696         .ops            = &clkops_omap2_dflt,
2697         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2698         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2699         .clkdm_name     = "l3_init_clkdm",
2700         .parent         = &l3_div_ck,
2701         .recalc         = &followparent_recalc,
2702 };
2703
2704 static struct clk usb_phy_cm_clk32k = {
2705         .name           = "usb_phy_cm_clk32k",
2706         .ops            = &clkops_omap2_dflt,
2707         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2708         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2709         .clkdm_name     = "l4_ao_clkdm",
2710         .parent         = &sys_32k_ck,
2711         .recalc         = &followparent_recalc,
2712 };
2713
2714 static struct clk usb_tll_hs_usb_ch2_clk = {
2715         .name           = "usb_tll_hs_usb_ch2_clk",
2716         .ops            = &clkops_omap2_dflt,
2717         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2718         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2719         .clkdm_name     = "l3_init_clkdm",
2720         .parent         = &init_60m_fclk,
2721         .recalc         = &followparent_recalc,
2722 };
2723
2724 static struct clk usb_tll_hs_usb_ch0_clk = {
2725         .name           = "usb_tll_hs_usb_ch0_clk",
2726         .ops            = &clkops_omap2_dflt,
2727         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2728         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2729         .clkdm_name     = "l3_init_clkdm",
2730         .parent         = &init_60m_fclk,
2731         .recalc         = &followparent_recalc,
2732 };
2733
2734 static struct clk usb_tll_hs_usb_ch1_clk = {
2735         .name           = "usb_tll_hs_usb_ch1_clk",
2736         .ops            = &clkops_omap2_dflt,
2737         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2738         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2739         .clkdm_name     = "l3_init_clkdm",
2740         .parent         = &init_60m_fclk,
2741         .recalc         = &followparent_recalc,
2742 };
2743
2744 static struct clk usb_tll_hs_ick = {
2745         .name           = "usb_tll_hs_ick",
2746         .ops            = &clkops_omap2_dflt,
2747         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2748         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2749         .clkdm_name     = "l3_init_clkdm",
2750         .parent         = &l4_div_ck,
2751         .recalc         = &followparent_recalc,
2752 };
2753
2754 static const struct clksel_rate div2_14to18_rates[] = {
2755         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2756         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2757         { .div = 0 },
2758 };
2759
2760 static const struct clksel usim_fclk_div[] = {
2761         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2762         { .parent = NULL },
2763 };
2764
2765 static struct clk usim_ck = {
2766         .name           = "usim_ck",
2767         .parent         = &dpll_per_m4x2_ck,
2768         .clksel         = usim_fclk_div,
2769         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2770         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2771         .ops            = &clkops_null,
2772         .recalc         = &omap2_clksel_recalc,
2773         .round_rate     = &omap2_clksel_round_rate,
2774         .set_rate       = &omap2_clksel_set_rate,
2775 };
2776
2777 static struct clk usim_fclk = {
2778         .name           = "usim_fclk",
2779         .ops            = &clkops_omap2_dflt,
2780         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2781         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2782         .clkdm_name     = "l4_wkup_clkdm",
2783         .parent         = &usim_ck,
2784         .recalc         = &followparent_recalc,
2785 };
2786
2787 static struct clk usim_fck = {
2788         .name           = "usim_fck",
2789         .ops            = &clkops_omap2_dflt,
2790         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2791         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2792         .clkdm_name     = "l4_wkup_clkdm",
2793         .parent         = &sys_32k_ck,
2794         .recalc         = &followparent_recalc,
2795 };
2796
2797 static struct clk wd_timer2_fck = {
2798         .name           = "wd_timer2_fck",
2799         .ops            = &clkops_omap2_dflt,
2800         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2801         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2802         .clkdm_name     = "l4_wkup_clkdm",
2803         .parent         = &sys_32k_ck,
2804         .recalc         = &followparent_recalc,
2805 };
2806
2807 static struct clk wd_timer3_fck = {
2808         .name           = "wd_timer3_fck",
2809         .ops            = &clkops_omap2_dflt,
2810         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2811         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2812         .clkdm_name     = "abe_clkdm",
2813         .parent         = &sys_32k_ck,
2814         .recalc         = &followparent_recalc,
2815 };
2816
2817 /* Remaining optional clocks */
2818 static const struct clksel stm_clk_div_div[] = {
2819         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2820         { .parent = NULL },
2821 };
2822
2823 static struct clk stm_clk_div_ck = {
2824         .name           = "stm_clk_div_ck",
2825         .parent         = &pmd_stm_clock_mux_ck,
2826         .clksel         = stm_clk_div_div,
2827         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2828         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2829         .ops            = &clkops_null,
2830         .recalc         = &omap2_clksel_recalc,
2831         .round_rate     = &omap2_clksel_round_rate,
2832         .set_rate       = &omap2_clksel_set_rate,
2833 };
2834
2835 static const struct clksel trace_clk_div_div[] = {
2836         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2837         { .parent = NULL },
2838 };
2839
2840 static struct clk trace_clk_div_ck = {
2841         .name           = "trace_clk_div_ck",
2842         .parent         = &pmd_trace_clk_mux_ck,
2843         .clksel         = trace_clk_div_div,
2844         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2845         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2846         .ops            = &clkops_null,
2847         .recalc         = &omap2_clksel_recalc,
2848         .round_rate     = &omap2_clksel_round_rate,
2849         .set_rate       = &omap2_clksel_set_rate,
2850 };
2851
2852 /* SCRM aux clk nodes */
2853
2854 static const struct clksel auxclk_sel[] = {
2855         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2856         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2857         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2858         { .parent = NULL },
2859 };
2860
2861 static struct clk auxclk0_ck = {
2862         .name           = "auxclk0_ck",
2863         .parent         = &sys_clkin_ck,
2864         .init           = &omap2_init_clksel_parent,
2865         .ops            = &clkops_omap2_dflt,
2866         .clksel         = auxclk_sel,
2867         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2868         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2869         .recalc         = &omap2_clksel_recalc,
2870         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2871         .enable_bit     = OMAP4_ENABLE_SHIFT,
2872 };
2873
2874 static struct clk auxclk1_ck = {
2875         .name           = "auxclk1_ck",
2876         .parent         = &sys_clkin_ck,
2877         .init           = &omap2_init_clksel_parent,
2878         .ops            = &clkops_omap2_dflt,
2879         .clksel         = auxclk_sel,
2880         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2881         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2882         .recalc         = &omap2_clksel_recalc,
2883         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2884         .enable_bit     = OMAP4_ENABLE_SHIFT,
2885 };
2886
2887 static struct clk auxclk2_ck = {
2888         .name           = "auxclk2_ck",
2889         .parent         = &sys_clkin_ck,
2890         .init           = &omap2_init_clksel_parent,
2891         .ops            = &clkops_omap2_dflt,
2892         .clksel         = auxclk_sel,
2893         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2894         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2895         .recalc         = &omap2_clksel_recalc,
2896         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2897         .enable_bit     = OMAP4_ENABLE_SHIFT,
2898 };
2899 static struct clk auxclk3_ck = {
2900         .name           = "auxclk3_ck",
2901         .parent         = &sys_clkin_ck,
2902         .init           = &omap2_init_clksel_parent,
2903         .ops            = &clkops_omap2_dflt,
2904         .clksel         = auxclk_sel,
2905         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2906         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2907         .recalc         = &omap2_clksel_recalc,
2908         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2909         .enable_bit     = OMAP4_ENABLE_SHIFT,
2910 };
2911
2912 static struct clk auxclk4_ck = {
2913         .name           = "auxclk4_ck",
2914         .parent         = &sys_clkin_ck,
2915         .init           = &omap2_init_clksel_parent,
2916         .ops            = &clkops_omap2_dflt,
2917         .clksel         = auxclk_sel,
2918         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2919         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2920         .recalc         = &omap2_clksel_recalc,
2921         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2922         .enable_bit     = OMAP4_ENABLE_SHIFT,
2923 };
2924
2925 static struct clk auxclk5_ck = {
2926         .name           = "auxclk5_ck",
2927         .parent         = &sys_clkin_ck,
2928         .init           = &omap2_init_clksel_parent,
2929         .ops            = &clkops_omap2_dflt,
2930         .clksel         = auxclk_sel,
2931         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2932         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2933         .recalc         = &omap2_clksel_recalc,
2934         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2935         .enable_bit     = OMAP4_ENABLE_SHIFT,
2936 };
2937
2938 static const struct clksel auxclkreq_sel[] = {
2939         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2940         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2941         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2942         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2943         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2944         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2945         { .parent = NULL },
2946 };
2947
2948 static struct clk auxclkreq0_ck = {
2949         .name           = "auxclkreq0_ck",
2950         .parent         = &auxclk0_ck,
2951         .init           = &omap2_init_clksel_parent,
2952         .ops            = &clkops_null,
2953         .clksel         = auxclkreq_sel,
2954         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2955         .clksel_mask    = OMAP4_MAPPING_MASK,
2956         .recalc         = &omap2_clksel_recalc,
2957 };
2958
2959 static struct clk auxclkreq1_ck = {
2960         .name           = "auxclkreq1_ck",
2961         .parent         = &auxclk1_ck,
2962         .init           = &omap2_init_clksel_parent,
2963         .ops            = &clkops_null,
2964         .clksel         = auxclkreq_sel,
2965         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2966         .clksel_mask    = OMAP4_MAPPING_MASK,
2967         .recalc         = &omap2_clksel_recalc,
2968 };
2969
2970 static struct clk auxclkreq2_ck = {
2971         .name           = "auxclkreq2_ck",
2972         .parent         = &auxclk2_ck,
2973         .init           = &omap2_init_clksel_parent,
2974         .ops            = &clkops_null,
2975         .clksel         = auxclkreq_sel,
2976         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2977         .clksel_mask    = OMAP4_MAPPING_MASK,
2978         .recalc         = &omap2_clksel_recalc,
2979 };
2980
2981 static struct clk auxclkreq3_ck = {
2982         .name           = "auxclkreq3_ck",
2983         .parent         = &auxclk3_ck,
2984         .init           = &omap2_init_clksel_parent,
2985         .ops            = &clkops_null,
2986         .clksel         = auxclkreq_sel,
2987         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2988         .clksel_mask    = OMAP4_MAPPING_MASK,
2989         .recalc         = &omap2_clksel_recalc,
2990 };
2991
2992 static struct clk auxclkreq4_ck = {
2993         .name           = "auxclkreq4_ck",
2994         .parent         = &auxclk4_ck,
2995         .init           = &omap2_init_clksel_parent,
2996         .ops            = &clkops_null,
2997         .clksel         = auxclkreq_sel,
2998         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2999         .clksel_mask    = OMAP4_MAPPING_MASK,
3000         .recalc         = &omap2_clksel_recalc,
3001 };
3002
3003 static struct clk auxclkreq5_ck = {
3004         .name           = "auxclkreq5_ck",
3005         .parent         = &auxclk5_ck,
3006         .init           = &omap2_init_clksel_parent,
3007         .ops            = &clkops_null,
3008         .clksel         = auxclkreq_sel,
3009         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
3010         .clksel_mask    = OMAP4_MAPPING_MASK,
3011         .recalc         = &omap2_clksel_recalc,
3012 };
3013
3014 /*
3015  * clkdev
3016  */
3017
3018 static struct omap_clk omap44xx_clks[] = {
3019         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3020         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3021         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3022         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3023         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3024         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3025         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3026         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3027         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3028         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3029         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3030         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3031         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3032         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3033         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3034         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3035         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3036         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3037         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3038         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3039         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3040         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3041         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3042         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3043         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3044         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3045         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3046         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3047         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3048         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3049         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3050         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3051         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3052         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3053         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3054         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3055         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3056         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3057         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3058         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3059         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3060         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3061         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3062         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3063         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3064         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3065         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3066         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3067         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3068         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3069         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3070         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3071         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3072         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3073         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3074         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3075         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3076         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3077         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3078         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3079         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3080         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3081         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
3082         CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
3083         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
3084         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3085         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3086         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3087         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3088         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3089         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3090         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3091         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3092         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3093         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3094         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3095         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3096         CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
3097         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3098         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3099         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3100         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3101         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3102         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3103         CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
3104         CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
3105         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3106         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3107         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3108         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3109         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3110         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3111         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3112         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3113         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3114         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3115         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3116         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3117         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3118         CLK("omapdss_dss",      "sys_clk",                      &dss_sys_clk,   CK_443X),
3119         CLK("omapdss_dss",      "tv_clk",                       &dss_tv_clk,    CK_443X),
3120         CLK("omapdss_dss",      "video_clk",                    &dss_48mhz_clk, CK_443X),
3121         CLK("omapdss_dss",      "fck",                          &dss_dss_clk,   CK_443X),
3122         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
3123         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3124         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3125         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3126         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3127         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3128         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3129         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3130         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3131         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3132         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3133         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3134         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3135         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3136         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3137         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3138         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3139         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3140         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3141         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3142         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
3143         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3144         CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
3145         CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
3146         CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
3147         CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
3148         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3149         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3150         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3151         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3152         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3153         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3154         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3155         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3156         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3157         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3158         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
3159         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3160         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
3161         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3162         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
3163         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3164         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
3165         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3166         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
3167         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
3168         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
3169         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
3170         CLK("omap_hsmmc.0",     "fck",                          &mmc1_fck,      CK_443X),
3171         CLK("omap_hsmmc.1",     "fck",                          &mmc2_fck,      CK_443X),
3172         CLK("omap_hsmmc.2",     "fck",                          &mmc3_fck,      CK_443X),
3173         CLK("omap_hsmmc.3",     "fck",                          &mmc4_fck,      CK_443X),
3174         CLK("omap_hsmmc.4",     "fck",                          &mmc5_fck,      CK_443X),
3175         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3176         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3177         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3178         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3179         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3180         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3181         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3182         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3183         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3184         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3185         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3186         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3187         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3188         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3189         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3190         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3191         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3192         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3193         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3194         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3195         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3196         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3197         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3198         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3199         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3200         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3201         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3202         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3203         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3204         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3205         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3206         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3207         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3208         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
3209         CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
3210         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3211         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3212         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3213         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3214         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3215         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3216         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3217         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3218         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3219         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3220         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
3221         CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
3222         CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
3223         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3224         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3225         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
3226         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3227         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3228         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3229         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3230         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
3231         CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
3232         CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
3233         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3234         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3235         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3236         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
3237         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3238         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3239         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3240         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3241         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3242         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
3243         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
3244         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
3245         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
3246         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
3247         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
3248         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
3249         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
3250         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
3251         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
3252         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
3253         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3254         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3255         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3256         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3257         CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
3258         CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
3259         CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
3260         CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
3261         CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
3262         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3263         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3264         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3265         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3266         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3267         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3268         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3269         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3270         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3271         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3272         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3273         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3274         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3275         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3276         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3277         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3278         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3279         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3280         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3281         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3282         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3283         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3284         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3285         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3286         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3287 };
3288
3289 int __init omap4xxx_clk_init(void)
3290 {
3291         struct omap_clk *c;
3292         u32 cpu_clkflg;
3293
3294         if (cpu_is_omap44xx()) {
3295                 cpu_mask = RATE_IN_4430;
3296                 cpu_clkflg = CK_443X;
3297         }
3298
3299         clk_init(&omap2_clk_functions);
3300
3301         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3302                                                                           c++)
3303                 clk_preinit(c->lk.clk);
3304
3305         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3306                                                                           c++)
3307                 if (c->cpu & cpu_clkflg) {
3308                         clkdev_add(&c->lk);
3309                         clk_register(c->lk.clk);
3310                         omap2_init_clk_clkdm(c->lk.clk);
3311                 }
3312
3313         /* Disable autoidle on all clocks; let the PM code enable it later */
3314         omap_clk_disable_autoidle_all();
3315
3316         recalculate_root_clocks();
3317
3318         /*
3319          * Only enable those clocks we will need, let the drivers
3320          * enable other clocks as necessary
3321          */
3322         clk_enable_init_clocks();
3323
3324         return 0;
3325 }