arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "control.h"
  40 #include "scrm44xx.h"
  41
  42 /* OMAP4 modulemode control */
  43 #define OMAP4430_MODULEMODE_HWCTRL                      0
  44 #define OMAP4430_MODULEMODE_SWCTRL                      1
  45
  46 /* Root clocks */
  47
  48 static struct clk extalt_clkin_ck = {
  49         .name           = "extalt_clkin_ck",
  50         .rate           = 59000000,
  51         .ops            = &clkops_null,
  52 };
  53
  54 static struct clk pad_clks_ck = {
  55         .name           = "pad_clks_ck",
  56         .rate           = 12000000,
  57         .ops            = &clkops_omap2_dflt,
  58         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  59         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  60 };
  61
  62 static struct clk pad_slimbus_core_clks_ck = {
  63         .name           = "pad_slimbus_core_clks_ck",
  64         .rate           = 12000000,
  65         .ops            = &clkops_null,
  66 };
  67
  68 static struct clk secure_32k_clk_src_ck = {
  69         .name           = "secure_32k_clk_src_ck",
  70         .rate           = 32768,
  71         .ops            = &clkops_null,
  72 };
  73
  74 static struct clk slimbus_clk = {
  75         .name           = "slimbus_clk",
  76         .rate           = 12000000,
  77         .ops            = &clkops_omap2_dflt,
  78         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  79         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  80 };
  81
  82 static struct clk sys_32k_ck = {
  83         .name           = "sys_32k_ck",
  84         .rate           = 32768,
  85         .ops            = &clkops_null,
  86 };
  87
  88 static struct clk virt_12000000_ck = {
  89         .name           = "virt_12000000_ck",
  90         .ops            = &clkops_null,
  91         .rate           = 12000000,
  92 };
  93
  94 static struct clk virt_13000000_ck = {
  95         .name           = "virt_13000000_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 13000000,
  98 };
  99
 100 static struct clk virt_16800000_ck = {
 101         .name           = "virt_16800000_ck",
 102         .ops            = &clkops_null,
 103         .rate           = 16800000,
 104 };
 105
 106 static struct clk virt_19200000_ck = {
 107         .name           = "virt_19200000_ck",
 108         .ops            = &clkops_null,
 109         .rate           = 19200000,
 110 };
 111
 112 static struct clk virt_26000000_ck = {
 113         .name           = "virt_26000000_ck",
 114         .ops            = &clkops_null,
 115         .rate           = 26000000,
 116 };
 117
 118 static struct clk virt_27000000_ck = {
 119         .name           = "virt_27000000_ck",
 120         .ops            = &clkops_null,
 121         .rate           = 27000000,
 122 };
 123
 124 static struct clk virt_38400000_ck = {
 125         .name           = "virt_38400000_ck",
 126         .ops            = &clkops_null,
 127         .rate           = 38400000,
 128 };
 129
 130 static const struct clksel_rate div_1_0_rates[] = {
 131         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 132         { .div = 0 },
 133 };
 134
 135 static const struct clksel_rate div_1_1_rates[] = {
 136         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 137         { .div = 0 },
 138 };
 139
 140 static const struct clksel_rate div_1_2_rates[] = {
 141         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 142         { .div = 0 },
 143 };
 144
 145 static const struct clksel_rate div_1_3_rates[] = {
 146         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 147         { .div = 0 },
 148 };
 149
 150 static const struct clksel_rate div_1_4_rates[] = {
 151         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 152         { .div = 0 },
 153 };
 154
 155 static const struct clksel_rate div_1_5_rates[] = {
 156         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 157         { .div = 0 },
 158 };
 159
 160 static const struct clksel_rate div_1_6_rates[] = {
 161         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 162         { .div = 0 },
 163 };
 164
 165 static const struct clksel_rate div_1_7_rates[] = {
 166         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 167         { .div = 0 },
 168 };
 169
 170 static const struct clksel sys_clkin_sel[] = {
 171         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 172         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 173         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 174         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 175         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 176         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 177         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 178         { .parent = NULL },
 179 };
 180
 181 static struct clk sys_clkin_ck = {
 182         .name           = "sys_clkin_ck",
 183         .rate           = 38400000,
 184         .clksel         = sys_clkin_sel,
 185         .init           = &omap2_init_clksel_parent,
 186         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 187         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 188         .ops            = &clkops_null,
 189         .recalc         = &omap2_clksel_recalc,
 190 };
 191
 192 static struct clk tie_low_clock_ck = {
 193         .name           = "tie_low_clock_ck",
 194         .rate           = 0,
 195         .ops            = &clkops_null,
 196 };
 197
 198 static struct clk utmi_phy_clkout_ck = {
 199         .name           = "utmi_phy_clkout_ck",
 200         .rate           = 60000000,
 201         .ops            = &clkops_null,
 202 };
 203
 204 static struct clk xclk60mhsp1_ck = {
 205         .name           = "xclk60mhsp1_ck",
 206         .rate           = 60000000,
 207         .ops            = &clkops_null,
 208 };
 209
 210 static struct clk xclk60mhsp2_ck = {
 211         .name           = "xclk60mhsp2_ck",
 212         .rate           = 60000000,
 213         .ops            = &clkops_null,
 214 };
 215
 216 static struct clk xclk60motg_ck = {
 217         .name           = "xclk60motg_ck",
 218         .rate           = 60000000,
 219         .ops            = &clkops_null,
 220 };
 221
 222 /* Module clocks and DPLL outputs */
 223
 224 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 225         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 226         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 227         { .parent = NULL },
 228 };
 229
 230 static struct clk abe_dpll_bypass_clk_mux_ck = {
 231         .name           = "abe_dpll_bypass_clk_mux_ck",
 232         .parent         = &sys_clkin_ck,
 233         .ops            = &clkops_null,
 234         .recalc         = &followparent_recalc,
 235 };
 236
 237 static struct clk abe_dpll_refclk_mux_ck = {
 238         .name           = "abe_dpll_refclk_mux_ck",
 239         .parent         = &sys_clkin_ck,
 240         .clksel         = abe_dpll_bypass_clk_mux_sel,
 241         .init           = &omap2_init_clksel_parent,
 242         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 243         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 244         .ops            = &clkops_null,
 245         .recalc         = &omap2_clksel_recalc,
 246 };
 247
 248 /* DPLL_ABE */
 249 static struct dpll_data dpll_abe_dd = {
 250         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 251         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 252         .clk_ref        = &abe_dpll_refclk_mux_ck,
 253         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 254         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 255         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 256         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 257         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 258         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 259         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 260         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 261         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 262         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 263         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 264         .min_divider    = 1,
 265 };
 266
 267
 268 static struct clk dpll_abe_ck = {
 269         .name           = "dpll_abe_ck",
 270         .parent         = &abe_dpll_refclk_mux_ck,
 271         .dpll_data      = &dpll_abe_dd,
 272         .init           = &omap2_init_dpll_parent,
 273         .ops            = &clkops_omap3_noncore_dpll_ops,
 274         .recalc         = &omap3_dpll_recalc,
 275         .round_rate     = &omap2_dpll_round_rate,
 276         .set_rate       = &omap3_noncore_dpll_set_rate,
 277 };
 278
 279 static struct clk dpll_abe_x2_ck = {
 280         .name           = "dpll_abe_x2_ck",
 281         .parent         = &dpll_abe_ck,
 282         .ops            = &clkops_null,
 283         .recalc         = &omap3_clkoutx2_recalc,
 284 };
 285
 286 static const struct clksel_rate div31_1to31_rates[] = {
 287         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 288         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 289         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 290         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 291         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 292         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 293         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 294         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 295         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 296         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 297         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 298         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 299         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 300         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 301         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 302         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 303         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 304         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 305         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 306         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 307         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 308         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 309         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 310         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 311         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 312         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 313         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 314         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 315         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 316         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 317         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 318         { .div = 0 },
 319 };
 320
 321 static const struct clksel dpll_abe_m2x2_div[] = {
 322         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 323         { .parent = NULL },
 324 };
 325
 326 static struct clk dpll_abe_m2x2_ck = {
 327         .name           = "dpll_abe_m2x2_ck",
 328         .parent         = &dpll_abe_x2_ck,
 329         .clksel         = dpll_abe_m2x2_div,
 330         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 331         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 332         .ops            = &clkops_null,
 333         .recalc         = &omap2_clksel_recalc,
 334         .round_rate     = &omap2_clksel_round_rate,
 335         .set_rate       = &omap2_clksel_set_rate,
 336 };
 337
 338 static struct clk abe_24m_fclk = {
 339         .name           = "abe_24m_fclk",
 340         .parent         = &dpll_abe_m2x2_ck,
 341         .ops            = &clkops_null,
 342         .fixed_div      = 8,
 343         .recalc         = &omap_fixed_divisor_recalc,
 344 };
 345
 346 static const struct clksel_rate div3_1to4_rates[] = {
 347         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 348         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 349         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 350         { .div = 0 },
 351 };
 352
 353 static const struct clksel abe_clk_div[] = {
 354         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 355         { .parent = NULL },
 356 };
 357
 358 static struct clk abe_clk = {
 359         .name           = "abe_clk",
 360         .parent         = &dpll_abe_m2x2_ck,
 361         .clksel         = abe_clk_div,
 362         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 363         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 364         .ops            = &clkops_null,
 365         .recalc         = &omap2_clksel_recalc,
 366         .round_rate     = &omap2_clksel_round_rate,
 367         .set_rate       = &omap2_clksel_set_rate,
 368 };
 369
 370 static const struct clksel_rate div2_1to2_rates[] = {
 371         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 372         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 373         { .div = 0 },
 374 };
 375
 376 static const struct clksel aess_fclk_div[] = {
 377         { .parent = &abe_clk, .rates = div2_1to2_rates },
 378         { .parent = NULL },
 379 };
 380
 381 static struct clk aess_fclk = {
 382         .name           = "aess_fclk",
 383         .parent         = &abe_clk,
 384         .clksel         = aess_fclk_div,
 385         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 386         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 387         .ops            = &clkops_null,
 388         .recalc         = &omap2_clksel_recalc,
 389         .round_rate     = &omap2_clksel_round_rate,
 390         .set_rate       = &omap2_clksel_set_rate,
 391 };
 392
 393 static struct clk dpll_abe_m3x2_ck = {
 394         .name           = "dpll_abe_m3x2_ck",
 395         .parent         = &dpll_abe_x2_ck,
 396         .clksel         = dpll_abe_m2x2_div,
 397         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 398         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 399         .ops            = &clkops_null,
 400         .recalc         = &omap2_clksel_recalc,
 401         .round_rate     = &omap2_clksel_round_rate,
 402         .set_rate       = &omap2_clksel_set_rate,
 403 };
 404
 405 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 406         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 407         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 408         { .parent = NULL },
 409 };
 410
 411 static struct clk core_hsd_byp_clk_mux_ck = {
 412         .name           = "core_hsd_byp_clk_mux_ck",
 413         .parent         = &sys_clkin_ck,
 414         .clksel         = core_hsd_byp_clk_mux_sel,
 415         .init           = &omap2_init_clksel_parent,
 416         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 417         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 418         .ops            = &clkops_null,
 419         .recalc         = &omap2_clksel_recalc,
 420 };
 421
 422 /* DPLL_CORE */
 423 static struct dpll_data dpll_core_dd = {
 424         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 425         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 426         .clk_ref        = &sys_clkin_ck,
 427         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 428         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 429         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 430         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 431         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 432         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 433         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 434         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 435         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 436         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 437         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 438         .min_divider    = 1,
 439 };
 440
 441
 442 static struct clk dpll_core_ck = {
 443         .name           = "dpll_core_ck",
 444         .parent         = &sys_clkin_ck,
 445         .dpll_data      = &dpll_core_dd,
 446         .init           = &omap2_init_dpll_parent,
 447         .ops            = &clkops_null,
 448         .recalc         = &omap3_dpll_recalc,
 449 };
 450
 451 static struct clk dpll_core_x2_ck = {
 452         .name           = "dpll_core_x2_ck",
 453         .parent         = &dpll_core_ck,
 454         .ops            = &clkops_null,
 455         .recalc         = &omap3_clkoutx2_recalc,
 456 };
 457
 458 static const struct clksel dpll_core_m6x2_div[] = {
 459         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 460         { .parent = NULL },
 461 };
 462
 463 static struct clk dpll_core_m6x2_ck = {
 464         .name           = "dpll_core_m6x2_ck",
 465         .parent         = &dpll_core_x2_ck,
 466         .clksel         = dpll_core_m6x2_div,
 467         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 468         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 469         .ops            = &clkops_null,
 470         .recalc         = &omap2_clksel_recalc,
 471         .round_rate     = &omap2_clksel_round_rate,
 472         .set_rate       = &omap2_clksel_set_rate,
 473 };
 474
 475 static const struct clksel dbgclk_mux_sel[] = {
 476         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 477         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 478         { .parent = NULL },
 479 };
 480
 481 static struct clk dbgclk_mux_ck = {
 482         .name           = "dbgclk_mux_ck",
 483         .parent         = &sys_clkin_ck,
 484         .ops            = &clkops_null,
 485         .recalc         = &followparent_recalc,
 486 };
 487
 488 static const struct clksel dpll_core_m2_div[] = {
 489         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 490         { .parent = NULL },
 491 };
 492
 493 static struct clk dpll_core_m2_ck = {
 494         .name           = "dpll_core_m2_ck",
 495         .parent         = &dpll_core_ck,
 496         .clksel         = dpll_core_m2_div,
 497         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 498         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 499         .ops            = &clkops_null,
 500         .recalc         = &omap2_clksel_recalc,
 501         .round_rate     = &omap2_clksel_round_rate,
 502         .set_rate       = &omap2_clksel_set_rate,
 503 };
 504
 505 static struct clk ddrphy_ck = {
 506         .name           = "ddrphy_ck",
 507         .parent         = &dpll_core_m2_ck,
 508         .ops            = &clkops_null,
 509         .fixed_div      = 2,
 510         .recalc         = &omap_fixed_divisor_recalc,
 511 };
 512
 513 static struct clk dpll_core_m5x2_ck = {
 514         .name           = "dpll_core_m5x2_ck",
 515         .parent         = &dpll_core_x2_ck,
 516         .clksel         = dpll_core_m6x2_div,
 517         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 518         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 519         .ops            = &clkops_null,
 520         .recalc         = &omap2_clksel_recalc,
 521         .round_rate     = &omap2_clksel_round_rate,
 522         .set_rate       = &omap2_clksel_set_rate,
 523 };
 524
 525 static const struct clksel div_core_div[] = {
 526         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 527         { .parent = NULL },
 528 };
 529
 530 static struct clk div_core_ck = {
 531         .name           = "div_core_ck",
 532         .parent         = &dpll_core_m5x2_ck,
 533         .clksel         = div_core_div,
 534         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 535         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 536         .ops            = &clkops_null,
 537         .recalc         = &omap2_clksel_recalc,
 538         .round_rate     = &omap2_clksel_round_rate,
 539         .set_rate       = &omap2_clksel_set_rate,
 540 };
 541
 542 static const struct clksel_rate div4_1to8_rates[] = {
 543         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 544         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 545         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 546         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 547         { .div = 0 },
 548 };
 549
 550 static const struct clksel div_iva_hs_clk_div[] = {
 551         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 552         { .parent = NULL },
 553 };
 554
 555 static struct clk div_iva_hs_clk = {
 556         .name           = "div_iva_hs_clk",
 557         .parent         = &dpll_core_m5x2_ck,
 558         .clksel         = div_iva_hs_clk_div,
 559         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 560         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 561         .ops            = &clkops_null,
 562         .recalc         = &omap2_clksel_recalc,
 563         .round_rate     = &omap2_clksel_round_rate,
 564         .set_rate       = &omap2_clksel_set_rate,
 565 };
 566
 567 static struct clk div_mpu_hs_clk = {
 568         .name           = "div_mpu_hs_clk",
 569         .parent         = &dpll_core_m5x2_ck,
 570         .clksel         = div_iva_hs_clk_div,
 571         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 572         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 573         .ops            = &clkops_null,
 574         .recalc         = &omap2_clksel_recalc,
 575         .round_rate     = &omap2_clksel_round_rate,
 576         .set_rate       = &omap2_clksel_set_rate,
 577 };
 578
 579 static struct clk dpll_core_m4x2_ck = {
 580         .name           = "dpll_core_m4x2_ck",
 581         .parent         = &dpll_core_x2_ck,
 582         .clksel         = dpll_core_m6x2_div,
 583         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 584         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 585         .ops            = &clkops_null,
 586         .recalc         = &omap2_clksel_recalc,
 587         .round_rate     = &omap2_clksel_round_rate,
 588         .set_rate       = &omap2_clksel_set_rate,
 589 };
 590
 591 static struct clk dll_clk_div_ck = {
 592         .name           = "dll_clk_div_ck",
 593         .parent         = &dpll_core_m4x2_ck,
 594         .ops            = &clkops_null,
 595         .fixed_div      = 2,
 596         .recalc         = &omap_fixed_divisor_recalc,
 597 };
 598
 599 static const struct clksel dpll_abe_m2_div[] = {
 600         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 601         { .parent = NULL },
 602 };
 603
 604 static struct clk dpll_abe_m2_ck = {
 605         .name           = "dpll_abe_m2_ck",
 606         .parent         = &dpll_abe_ck,
 607         .clksel         = dpll_abe_m2_div,
 608         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 609         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 610         .ops            = &clkops_null,
 611         .recalc         = &omap2_clksel_recalc,
 612         .round_rate     = &omap2_clksel_round_rate,
 613         .set_rate       = &omap2_clksel_set_rate,
 614 };
 615
 616 static struct clk dpll_core_m3x2_ck = {
 617         .name           = "dpll_core_m3x2_ck",
 618         .parent         = &dpll_core_x2_ck,
 619         .clksel         = dpll_core_m6x2_div,
 620         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 621         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 622         .ops            = &clkops_omap2_dflt,
 623         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 624         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 625         .recalc         = &omap2_clksel_recalc,
 626         .round_rate     = &omap2_clksel_round_rate,
 627         .set_rate       = &omap2_clksel_set_rate,
 628 };
 629
 630 static struct clk dpll_core_m7x2_ck = {
 631         .name           = "dpll_core_m7x2_ck",
 632         .parent         = &dpll_core_x2_ck,
 633         .clksel         = dpll_core_m6x2_div,
 634         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 635         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 636         .ops            = &clkops_null,
 637         .recalc         = &omap2_clksel_recalc,
 638         .round_rate     = &omap2_clksel_round_rate,
 639         .set_rate       = &omap2_clksel_set_rate,
 640 };
 641
 642 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 643         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 644         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 645         { .parent = NULL },
 646 };
 647
 648 static struct clk iva_hsd_byp_clk_mux_ck = {
 649         .name           = "iva_hsd_byp_clk_mux_ck",
 650         .parent         = &sys_clkin_ck,
 651         .clksel         = iva_hsd_byp_clk_mux_sel,
 652         .init           = &omap2_init_clksel_parent,
 653         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 654         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 655         .ops            = &clkops_null,
 656         .recalc         = &omap2_clksel_recalc,
 657 };
 658
 659 /* DPLL_IVA */
 660 static struct dpll_data dpll_iva_dd = {
 661         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 662         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 663         .clk_ref        = &sys_clkin_ck,
 664         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 665         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 666         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 667         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 668         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 669         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 670         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 671         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 672         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 673         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 674         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 675         .min_divider    = 1,
 676 };
 677
 678
 679 static struct clk dpll_iva_ck = {
 680         .name           = "dpll_iva_ck",
 681         .parent         = &sys_clkin_ck,
 682         .dpll_data      = &dpll_iva_dd,
 683         .init           = &omap2_init_dpll_parent,
 684         .ops            = &clkops_omap3_noncore_dpll_ops,
 685         .recalc         = &omap3_dpll_recalc,
 686         .round_rate     = &omap2_dpll_round_rate,
 687         .set_rate       = &omap3_noncore_dpll_set_rate,
 688 };
 689
 690 static struct clk dpll_iva_x2_ck = {
 691         .name           = "dpll_iva_x2_ck",
 692         .parent         = &dpll_iva_ck,
 693         .ops            = &clkops_null,
 694         .recalc         = &omap3_clkoutx2_recalc,
 695 };
 696
 697 static const struct clksel dpll_iva_m4x2_div[] = {
 698         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 699         { .parent = NULL },
 700 };
 701
 702 static struct clk dpll_iva_m4x2_ck = {
 703         .name           = "dpll_iva_m4x2_ck",
 704         .parent         = &dpll_iva_x2_ck,
 705         .clksel         = dpll_iva_m4x2_div,
 706         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 707         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 708         .ops            = &clkops_null,
 709         .recalc         = &omap2_clksel_recalc,
 710         .round_rate     = &omap2_clksel_round_rate,
 711         .set_rate       = &omap2_clksel_set_rate,
 712 };
 713
 714 static struct clk dpll_iva_m5x2_ck = {
 715         .name           = "dpll_iva_m5x2_ck",
 716         .parent         = &dpll_iva_x2_ck,
 717         .clksel         = dpll_iva_m4x2_div,
 718         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 719         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 720         .ops            = &clkops_null,
 721         .recalc         = &omap2_clksel_recalc,
 722         .round_rate     = &omap2_clksel_round_rate,
 723         .set_rate       = &omap2_clksel_set_rate,
 724 };
 725
 726 /* DPLL_MPU */
 727 static struct dpll_data dpll_mpu_dd = {
 728         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 729         .clk_bypass     = &div_mpu_hs_clk,
 730         .clk_ref        = &sys_clkin_ck,
 731         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 732         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 733         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 734         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 735         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 736         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 737         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 738         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 739         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 740         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 741         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 742         .min_divider    = 1,
 743 };
 744
 745
 746 static struct clk dpll_mpu_ck = {
 747         .name           = "dpll_mpu_ck",
 748         .parent         = &sys_clkin_ck,
 749         .dpll_data      = &dpll_mpu_dd,
 750         .init           = &omap2_init_dpll_parent,
 751         .ops            = &clkops_omap3_noncore_dpll_ops,
 752         .recalc         = &omap3_dpll_recalc,
 753         .round_rate     = &omap2_dpll_round_rate,
 754         .set_rate       = &omap3_noncore_dpll_set_rate,
 755 };
 756
 757 static const struct clksel dpll_mpu_m2_div[] = {
 758         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 759         { .parent = NULL },
 760 };
 761
 762 static struct clk dpll_mpu_m2_ck = {
 763         .name           = "dpll_mpu_m2_ck",
 764         .parent         = &dpll_mpu_ck,
 765         .clksel         = dpll_mpu_m2_div,
 766         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 767         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 768         .ops            = &clkops_null,
 769         .recalc         = &omap2_clksel_recalc,
 770         .round_rate     = &omap2_clksel_round_rate,
 771         .set_rate       = &omap2_clksel_set_rate,
 772 };
 773
 774 static struct clk per_hs_clk_div_ck = {
 775         .name           = "per_hs_clk_div_ck",
 776         .parent         = &dpll_abe_m3x2_ck,
 777         .ops            = &clkops_null,
 778         .fixed_div      = 2,
 779         .recalc         = &omap_fixed_divisor_recalc,
 780 };
 781
 782 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 783         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 784         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 785         { .parent = NULL },
 786 };
 787
 788 static struct clk per_hsd_byp_clk_mux_ck = {
 789         .name           = "per_hsd_byp_clk_mux_ck",
 790         .parent         = &sys_clkin_ck,
 791         .clksel         = per_hsd_byp_clk_mux_sel,
 792         .init           = &omap2_init_clksel_parent,
 793         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 794         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 795         .ops            = &clkops_null,
 796         .recalc         = &omap2_clksel_recalc,
 797 };
 798
 799 /* DPLL_PER */
 800 static struct dpll_data dpll_per_dd = {
 801         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 802         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 803         .clk_ref        = &sys_clkin_ck,
 804         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 805         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 806         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 807         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 808         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 809         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 810         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 811         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 812         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 813         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 814         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 815         .min_divider    = 1,
 816 };
 817
 818
 819 static struct clk dpll_per_ck = {
 820         .name           = "dpll_per_ck",
 821         .parent         = &sys_clkin_ck,
 822         .dpll_data      = &dpll_per_dd,
 823         .init           = &omap2_init_dpll_parent,
 824         .ops            = &clkops_omap3_noncore_dpll_ops,
 825         .recalc         = &omap3_dpll_recalc,
 826         .round_rate     = &omap2_dpll_round_rate,
 827         .set_rate       = &omap3_noncore_dpll_set_rate,
 828 };
 829
 830 static const struct clksel dpll_per_m2_div[] = {
 831         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 832         { .parent = NULL },
 833 };
 834
 835 static struct clk dpll_per_m2_ck = {
 836         .name           = "dpll_per_m2_ck",
 837         .parent         = &dpll_per_ck,
 838         .clksel         = dpll_per_m2_div,
 839         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 840         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 841         .ops            = &clkops_null,
 842         .recalc         = &omap2_clksel_recalc,
 843         .round_rate     = &omap2_clksel_round_rate,
 844         .set_rate       = &omap2_clksel_set_rate,
 845 };
 846
 847 static struct clk dpll_per_x2_ck = {
 848         .name           = "dpll_per_x2_ck",
 849         .parent         = &dpll_per_ck,
 850         .ops            = &clkops_null,
 851         .recalc         = &omap3_clkoutx2_recalc,
 852 };
 853
 854 static const struct clksel dpll_per_m2x2_div[] = {
 855         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 856         { .parent = NULL },
 857 };
 858
 859 static struct clk dpll_per_m2x2_ck = {
 860         .name           = "dpll_per_m2x2_ck",
 861         .parent         = &dpll_per_x2_ck,
 862         .clksel         = dpll_per_m2x2_div,
 863         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 864         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 865         .ops            = &clkops_null,
 866         .recalc         = &omap2_clksel_recalc,
 867         .round_rate     = &omap2_clksel_round_rate,
 868         .set_rate       = &omap2_clksel_set_rate,
 869 };
 870
 871 static struct clk dpll_per_m3x2_ck = {
 872         .name           = "dpll_per_m3x2_ck",
 873         .parent         = &dpll_per_x2_ck,
 874         .clksel         = dpll_per_m2x2_div,
 875         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 876         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 877         .ops            = &clkops_omap2_dflt,
 878         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 879         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 880         .recalc         = &omap2_clksel_recalc,
 881         .round_rate     = &omap2_clksel_round_rate,
 882         .set_rate       = &omap2_clksel_set_rate,
 883 };
 884
 885 static struct clk dpll_per_m4x2_ck = {
 886         .name           = "dpll_per_m4x2_ck",
 887         .parent         = &dpll_per_x2_ck,
 888         .clksel         = dpll_per_m2x2_div,
 889         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 890         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 891         .ops            = &clkops_null,
 892         .recalc         = &omap2_clksel_recalc,
 893         .round_rate     = &omap2_clksel_round_rate,
 894         .set_rate       = &omap2_clksel_set_rate,
 895 };
 896
 897 static struct clk dpll_per_m5x2_ck = {
 898         .name           = "dpll_per_m5x2_ck",
 899         .parent         = &dpll_per_x2_ck,
 900         .clksel         = dpll_per_m2x2_div,
 901         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 902         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 903         .ops            = &clkops_null,
 904         .recalc         = &omap2_clksel_recalc,
 905         .round_rate     = &omap2_clksel_round_rate,
 906         .set_rate       = &omap2_clksel_set_rate,
 907 };
 908
 909 static struct clk dpll_per_m6x2_ck = {
 910         .name           = "dpll_per_m6x2_ck",
 911         .parent         = &dpll_per_x2_ck,
 912         .clksel         = dpll_per_m2x2_div,
 913         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 914         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 915         .ops            = &clkops_null,
 916         .recalc         = &omap2_clksel_recalc,
 917         .round_rate     = &omap2_clksel_round_rate,
 918         .set_rate       = &omap2_clksel_set_rate,
 919 };
 920
 921 static struct clk dpll_per_m7x2_ck = {
 922         .name           = "dpll_per_m7x2_ck",
 923         .parent         = &dpll_per_x2_ck,
 924         .clksel         = dpll_per_m2x2_div,
 925         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 926         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 927         .ops            = &clkops_null,
 928         .recalc         = &omap2_clksel_recalc,
 929         .round_rate     = &omap2_clksel_round_rate,
 930         .set_rate       = &omap2_clksel_set_rate,
 931 };
 932
 933 /* DPLL_UNIPRO */
 934 static struct dpll_data dpll_unipro_dd = {
 935         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 936         .clk_bypass     = &sys_clkin_ck,
 937         .clk_ref        = &sys_clkin_ck,
 938         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 939         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 940         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 941         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 942         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 943         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 944         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 945         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 946         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 947         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 948         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 949         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 950         .min_divider    = 1,
 951 };
 952
 953
 954 static struct clk dpll_unipro_ck = {
 955         .name           = "dpll_unipro_ck",
 956         .parent         = &sys_clkin_ck,
 957         .dpll_data      = &dpll_unipro_dd,
 958         .init           = &omap2_init_dpll_parent,
 959         .ops            = &clkops_omap3_noncore_dpll_ops,
 960         .recalc         = &omap3_dpll_recalc,
 961         .round_rate     = &omap2_dpll_round_rate,
 962         .set_rate       = &omap3_noncore_dpll_set_rate,
 963 };
 964
 965 static struct clk dpll_unipro_x2_ck = {
 966         .name           = "dpll_unipro_x2_ck",
 967         .parent         = &dpll_unipro_ck,
 968         .ops            = &clkops_null,
 969         .recalc         = &omap3_clkoutx2_recalc,
 970 };
 971
 972 static const struct clksel dpll_unipro_m2x2_div[] = {
 973         { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
 974         { .parent = NULL },
 975 };
 976
 977 static struct clk dpll_unipro_m2x2_ck = {
 978         .name           = "dpll_unipro_m2x2_ck",
 979         .parent         = &dpll_unipro_x2_ck,
 980         .clksel         = dpll_unipro_m2x2_div,
 981         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 982         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 983         .ops            = &clkops_null,
 984         .recalc         = &omap2_clksel_recalc,
 985         .round_rate     = &omap2_clksel_round_rate,
 986         .set_rate       = &omap2_clksel_set_rate,
 987 };
 988
 989 static struct clk usb_hs_clk_div_ck = {
 990         .name           = "usb_hs_clk_div_ck",
 991         .parent         = &dpll_abe_m3x2_ck,
 992         .ops            = &clkops_null,
 993         .fixed_div      = 3,
 994         .recalc         = &omap_fixed_divisor_recalc,
 995 };
 996
 997 /* DPLL_USB */
 998 static struct dpll_data dpll_usb_dd = {
 999         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
1000         .clk_bypass     = &usb_hs_clk_div_ck,
1001         .flags          = DPLL_J_TYPE,
1002         .clk_ref        = &sys_clkin_ck,
1003         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
1004         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1005         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1006         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1007         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1008         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1009         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1010         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1011         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1012         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
1013         .max_divider    = OMAP4430_MAX_DPLL_DIV,
1014         .min_divider    = 1,
1015 };
1016
1017
1018 static struct clk dpll_usb_ck = {
1019         .name           = "dpll_usb_ck",
1020         .parent         = &sys_clkin_ck,
1021         .dpll_data      = &dpll_usb_dd,
1022         .init           = &omap2_init_dpll_parent,
1023         .ops            = &clkops_omap3_noncore_dpll_ops,
1024         .recalc         = &omap3_dpll_recalc,
1025         .round_rate     = &omap2_dpll_round_rate,
1026         .set_rate       = &omap3_noncore_dpll_set_rate,
1027 };
1028
1029 static struct clk dpll_usb_clkdcoldo_ck = {
1030         .name           = "dpll_usb_clkdcoldo_ck",
1031         .parent         = &dpll_usb_ck,
1032         .ops            = &clkops_null,
1033         .recalc         = &followparent_recalc,
1034 };
1035
1036 static const struct clksel dpll_usb_m2_div[] = {
1037         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1038         { .parent = NULL },
1039 };
1040
1041 static struct clk dpll_usb_m2_ck = {
1042         .name           = "dpll_usb_m2_ck",
1043         .parent         = &dpll_usb_ck,
1044         .clksel         = dpll_usb_m2_div,
1045         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1046         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1047         .ops            = &clkops_null,
1048         .recalc         = &omap2_clksel_recalc,
1049         .round_rate     = &omap2_clksel_round_rate,
1050         .set_rate       = &omap2_clksel_set_rate,
1051 };
1052
1053 static const struct clksel ducati_clk_mux_sel[] = {
1054         { .parent = &div_core_ck, .rates = div_1_0_rates },
1055         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1056         { .parent = NULL },
1057 };
1058
1059 static struct clk ducati_clk_mux_ck = {
1060         .name           = "ducati_clk_mux_ck",
1061         .parent         = &div_core_ck,
1062         .clksel         = ducati_clk_mux_sel,
1063         .init           = &omap2_init_clksel_parent,
1064         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1065         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1066         .ops            = &clkops_null,
1067         .recalc         = &omap2_clksel_recalc,
1068 };
1069
1070 static struct clk func_12m_fclk = {
1071         .name           = "func_12m_fclk",
1072         .parent         = &dpll_per_m2x2_ck,
1073         .ops            = &clkops_null,
1074         .fixed_div      = 16,
1075         .recalc         = &omap_fixed_divisor_recalc,
1076 };
1077
1078 static struct clk func_24m_clk = {
1079         .name           = "func_24m_clk",
1080         .parent         = &dpll_per_m2_ck,
1081         .ops            = &clkops_null,
1082         .fixed_div      = 4,
1083         .recalc         = &omap_fixed_divisor_recalc,
1084 };
1085
1086 static struct clk func_24mc_fclk = {
1087         .name           = "func_24mc_fclk",
1088         .parent         = &dpll_per_m2x2_ck,
1089         .ops            = &clkops_null,
1090         .fixed_div      = 8,
1091         .recalc         = &omap_fixed_divisor_recalc,
1092 };
1093
1094 static const struct clksel_rate div2_4to8_rates[] = {
1095         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1096         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1097         { .div = 0 },
1098 };
1099
1100 static const struct clksel func_48m_fclk_div[] = {
1101         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1102         { .parent = NULL },
1103 };
1104
1105 static struct clk func_48m_fclk = {
1106         .name           = "func_48m_fclk",
1107         .parent         = &dpll_per_m2x2_ck,
1108         .clksel         = func_48m_fclk_div,
1109         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1110         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1111         .ops            = &clkops_null,
1112         .recalc         = &omap2_clksel_recalc,
1113         .round_rate     = &omap2_clksel_round_rate,
1114         .set_rate       = &omap2_clksel_set_rate,
1115 };
1116
1117 static struct clk func_48mc_fclk = {
1118         .name           = "func_48mc_fclk",
1119         .parent         = &dpll_per_m2x2_ck,
1120         .ops            = &clkops_null,
1121         .fixed_div      = 4,
1122         .recalc         = &omap_fixed_divisor_recalc,
1123 };
1124
1125 static const struct clksel_rate div2_2to4_rates[] = {
1126         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1127         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1128         { .div = 0 },
1129 };
1130
1131 static const struct clksel func_64m_fclk_div[] = {
1132         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1133         { .parent = NULL },
1134 };
1135
1136 static struct clk func_64m_fclk = {
1137         .name           = "func_64m_fclk",
1138         .parent         = &dpll_per_m4x2_ck,
1139         .clksel         = func_64m_fclk_div,
1140         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1141         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1142         .ops            = &clkops_null,
1143         .recalc         = &omap2_clksel_recalc,
1144         .round_rate     = &omap2_clksel_round_rate,
1145         .set_rate       = &omap2_clksel_set_rate,
1146 };
1147
1148 static const struct clksel func_96m_fclk_div[] = {
1149         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1150         { .parent = NULL },
1151 };
1152
1153 static struct clk func_96m_fclk = {
1154         .name           = "func_96m_fclk",
1155         .parent         = &dpll_per_m2x2_ck,
1156         .clksel         = func_96m_fclk_div,
1157         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1158         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1159         .ops            = &clkops_null,
1160         .recalc         = &omap2_clksel_recalc,
1161         .round_rate     = &omap2_clksel_round_rate,
1162         .set_rate       = &omap2_clksel_set_rate,
1163 };
1164
1165 static const struct clksel hsmmc6_fclk_sel[] = {
1166         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1167         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1168         { .parent = NULL },
1169 };
1170
1171 static struct clk hsmmc6_fclk = {
1172         .name           = "hsmmc6_fclk",
1173         .parent         = &func_64m_fclk,
1174         .ops            = &clkops_null,
1175         .recalc         = &followparent_recalc,
1176 };
1177
1178 static const struct clksel_rate div2_1to8_rates[] = {
1179         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1180         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1181         { .div = 0 },
1182 };
1183
1184 static const struct clksel init_60m_fclk_div[] = {
1185         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1186         { .parent = NULL },
1187 };
1188
1189 static struct clk init_60m_fclk = {
1190         .name           = "init_60m_fclk",
1191         .parent         = &dpll_usb_m2_ck,
1192         .clksel         = init_60m_fclk_div,
1193         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1194         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1195         .ops            = &clkops_null,
1196         .recalc         = &omap2_clksel_recalc,
1197         .round_rate     = &omap2_clksel_round_rate,
1198         .set_rate       = &omap2_clksel_set_rate,
1199 };
1200
1201 static const struct clksel l3_div_div[] = {
1202         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1203         { .parent = NULL },
1204 };
1205
1206 static struct clk l3_div_ck = {
1207         .name           = "l3_div_ck",
1208         .parent         = &div_core_ck,
1209         .clksel         = l3_div_div,
1210         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1211         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1212         .ops            = &clkops_null,
1213         .recalc         = &omap2_clksel_recalc,
1214         .round_rate     = &omap2_clksel_round_rate,
1215         .set_rate       = &omap2_clksel_set_rate,
1216 };
1217
1218 static const struct clksel l4_div_div[] = {
1219         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1220         { .parent = NULL },
1221 };
1222
1223 static struct clk l4_div_ck = {
1224         .name           = "l4_div_ck",
1225         .parent         = &l3_div_ck,
1226         .clksel         = l4_div_div,
1227         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1228         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1229         .ops            = &clkops_null,
1230         .recalc         = &omap2_clksel_recalc,
1231         .round_rate     = &omap2_clksel_round_rate,
1232         .set_rate       = &omap2_clksel_set_rate,
1233 };
1234
1235 static struct clk lp_clk_div_ck = {
1236         .name           = "lp_clk_div_ck",
1237         .parent         = &dpll_abe_m2x2_ck,
1238         .ops            = &clkops_null,
1239         .fixed_div      = 16,
1240         .recalc         = &omap_fixed_divisor_recalc,
1241 };
1242
1243 static const struct clksel l4_wkup_clk_mux_sel[] = {
1244         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1245         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1246         { .parent = NULL },
1247 };
1248
1249 static struct clk l4_wkup_clk_mux_ck = {
1250         .name           = "l4_wkup_clk_mux_ck",
1251         .parent         = &sys_clkin_ck,
1252         .clksel         = l4_wkup_clk_mux_sel,
1253         .init           = &omap2_init_clksel_parent,
1254         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1255         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1256         .ops            = &clkops_null,
1257         .recalc         = &omap2_clksel_recalc,
1258 };
1259
1260 static const struct clksel per_abe_nc_fclk_div[] = {
1261         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1262         { .parent = NULL },
1263 };
1264
1265 static struct clk per_abe_nc_fclk = {
1266         .name           = "per_abe_nc_fclk",
1267         .parent         = &dpll_abe_m2_ck,
1268         .clksel         = per_abe_nc_fclk_div,
1269         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1270         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1271         .ops            = &clkops_null,
1272         .recalc         = &omap2_clksel_recalc,
1273         .round_rate     = &omap2_clksel_round_rate,
1274         .set_rate       = &omap2_clksel_set_rate,
1275 };
1276
1277 static const struct clksel mcasp2_fclk_sel[] = {
1278         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1279         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1280         { .parent = NULL },
1281 };
1282
1283 static struct clk mcasp2_fclk = {
1284         .name           = "mcasp2_fclk",
1285         .parent         = &func_96m_fclk,
1286         .ops            = &clkops_null,
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 static struct clk mcasp3_fclk = {
1291         .name           = "mcasp3_fclk",
1292         .parent         = &func_96m_fclk,
1293         .ops            = &clkops_null,
1294         .recalc         = &followparent_recalc,
1295 };
1296
1297 static struct clk ocp_abe_iclk = {
1298         .name           = "ocp_abe_iclk",
1299         .parent         = &aess_fclk,
1300         .ops            = &clkops_null,
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk per_abe_24m_fclk = {
1305         .name           = "per_abe_24m_fclk",
1306         .parent         = &dpll_abe_m2_ck,
1307         .ops            = &clkops_null,
1308         .fixed_div      = 4,
1309         .recalc         = &omap_fixed_divisor_recalc,
1310 };
1311
1312 static const struct clksel pmd_stm_clock_mux_sel[] = {
1313         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1314         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1315         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1316         { .parent = NULL },
1317 };
1318
1319 static struct clk pmd_stm_clock_mux_ck = {
1320         .name           = "pmd_stm_clock_mux_ck",
1321         .parent         = &sys_clkin_ck,
1322         .ops            = &clkops_null,
1323         .recalc         = &followparent_recalc,
1324 };
1325
1326 static struct clk pmd_trace_clk_mux_ck = {
1327         .name           = "pmd_trace_clk_mux_ck",
1328         .parent         = &sys_clkin_ck,
1329         .ops            = &clkops_null,
1330         .recalc         = &followparent_recalc,
1331 };
1332
1333 static const struct clksel syc_clk_div_div[] = {
1334         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1335         { .parent = NULL },
1336 };
1337
1338 static struct clk syc_clk_div_ck = {
1339         .name           = "syc_clk_div_ck",
1340         .parent         = &sys_clkin_ck,
1341         .clksel         = syc_clk_div_div,
1342         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1343         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1344         .ops            = &clkops_null,
1345         .recalc         = &omap2_clksel_recalc,
1346         .round_rate     = &omap2_clksel_round_rate,
1347         .set_rate       = &omap2_clksel_set_rate,
1348 };
1349
1350 /* Leaf clocks controlled by modules */
1351
1352 static struct clk aes1_fck = {
1353         .name           = "aes1_fck",
1354         .ops            = &clkops_omap2_dflt,
1355         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1356         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1357         .clkdm_name     = "l4_secure_clkdm",
1358         .parent         = &l3_div_ck,
1359         .recalc         = &followparent_recalc,
1360 };
1361
1362 static struct clk aes2_fck = {
1363         .name           = "aes2_fck",
1364         .ops            = &clkops_omap2_dflt,
1365         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1366         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1367         .clkdm_name     = "l4_secure_clkdm",
1368         .parent         = &l3_div_ck,
1369         .recalc         = &followparent_recalc,
1370 };
1371
1372 static struct clk aess_fck = {
1373         .name           = "aess_fck",
1374         .ops            = &clkops_omap2_dflt,
1375         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1376         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1377         .clkdm_name     = "abe_clkdm",
1378         .parent         = &aess_fclk,
1379         .recalc         = &followparent_recalc,
1380 };
1381
1382 static struct clk bandgap_fclk = {
1383         .name           = "bandgap_fclk",
1384         .ops            = &clkops_omap2_dflt,
1385         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1386         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1387         .clkdm_name     = "l4_wkup_clkdm",
1388         .parent         = &sys_32k_ck,
1389         .recalc         = &followparent_recalc,
1390 };
1391
1392 static struct clk des3des_fck = {
1393         .name           = "des3des_fck",
1394         .ops            = &clkops_omap2_dflt,
1395         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1396         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1397         .clkdm_name     = "l4_secure_clkdm",
1398         .parent         = &l4_div_ck,
1399         .recalc         = &followparent_recalc,
1400 };
1401
1402 static const struct clksel dmic_sync_mux_sel[] = {
1403         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1404         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1405         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1406         { .parent = NULL },
1407 };
1408
1409 static struct clk dmic_sync_mux_ck = {
1410         .name           = "dmic_sync_mux_ck",
1411         .parent         = &abe_24m_fclk,
1412         .clksel         = dmic_sync_mux_sel,
1413         .init           = &omap2_init_clksel_parent,
1414         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1415         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1416         .ops            = &clkops_null,
1417         .recalc         = &omap2_clksel_recalc,
1418 };
1419
1420 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1421         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1422         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1423         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1424         { .parent = NULL },
1425 };
1426
1427 /* Merged func_dmic_abe_gfclk into dmic */
1428 static struct clk dmic_fck = {
1429         .name           = "dmic_fck",
1430         .parent         = &dmic_sync_mux_ck,
1431         .clksel         = func_dmic_abe_gfclk_sel,
1432         .init           = &omap2_init_clksel_parent,
1433         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1434         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1435         .ops            = &clkops_omap2_dflt,
1436         .recalc         = &omap2_clksel_recalc,
1437         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1438         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1439         .clkdm_name     = "abe_clkdm",
1440 };
1441
1442 static struct clk dsp_fck = {
1443         .name           = "dsp_fck",
1444         .ops            = &clkops_omap2_dflt,
1445         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1446         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1447         .clkdm_name     = "tesla_clkdm",
1448         .parent         = &dpll_iva_m4x2_ck,
1449         .recalc         = &followparent_recalc,
1450 };
1451
1452 static struct clk dss_sys_clk = {
1453         .name           = "dss_sys_clk",
1454         .ops            = &clkops_omap2_dflt,
1455         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1456         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1457         .clkdm_name     = "l3_dss_clkdm",
1458         .parent         = &syc_clk_div_ck,
1459         .recalc         = &followparent_recalc,
1460 };
1461
1462 static struct clk dss_tv_clk = {
1463         .name           = "dss_tv_clk",
1464         .ops            = &clkops_omap2_dflt,
1465         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1466         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1467         .clkdm_name     = "l3_dss_clkdm",
1468         .parent         = &extalt_clkin_ck,
1469         .recalc         = &followparent_recalc,
1470 };
1471
1472 static struct clk dss_dss_clk = {
1473         .name           = "dss_dss_clk",
1474         .ops            = &clkops_omap2_dflt,
1475         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1476         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1477         .clkdm_name     = "l3_dss_clkdm",
1478         .parent         = &dpll_per_m5x2_ck,
1479         .recalc         = &followparent_recalc,
1480 };
1481
1482 static struct clk dss_48mhz_clk = {
1483         .name           = "dss_48mhz_clk",
1484         .ops            = &clkops_omap2_dflt,
1485         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1486         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1487         .clkdm_name     = "l3_dss_clkdm",
1488         .parent         = &func_48mc_fclk,
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 static struct clk dss_fck = {
1493         .name           = "dss_fck",
1494         .ops            = &clkops_omap2_dflt,
1495         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1496         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1497         .clkdm_name     = "l3_dss_clkdm",
1498         .parent         = &l3_div_ck,
1499         .recalc         = &followparent_recalc,
1500 };
1501
1502 static struct clk efuse_ctrl_cust_fck = {
1503         .name           = "efuse_ctrl_cust_fck",
1504         .ops            = &clkops_omap2_dflt,
1505         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1506         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1507         .clkdm_name     = "l4_cefuse_clkdm",
1508         .parent         = &sys_clkin_ck,
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk emif1_fck = {
1513         .name           = "emif1_fck",
1514         .ops            = &clkops_omap2_dflt,
1515         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1516         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1517         .flags          = ENABLE_ON_INIT,
1518         .clkdm_name     = "l3_emif_clkdm",
1519         .parent         = &ddrphy_ck,
1520         .recalc         = &followparent_recalc,
1521 };
1522
1523 static struct clk emif2_fck = {
1524         .name           = "emif2_fck",
1525         .ops            = &clkops_omap2_dflt,
1526         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1527         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1528         .flags          = ENABLE_ON_INIT,
1529         .clkdm_name     = "l3_emif_clkdm",
1530         .parent         = &ddrphy_ck,
1531         .recalc         = &followparent_recalc,
1532 };
1533
1534 static const struct clksel fdif_fclk_div[] = {
1535         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1536         { .parent = NULL },
1537 };
1538
1539 /* Merged fdif_fclk into fdif */
1540 static struct clk fdif_fck = {
1541         .name           = "fdif_fck",
1542         .parent         = &dpll_per_m4x2_ck,
1543         .clksel         = fdif_fclk_div,
1544         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1545         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1546         .ops            = &clkops_omap2_dflt,
1547         .recalc         = &omap2_clksel_recalc,
1548         .round_rate     = &omap2_clksel_round_rate,
1549         .set_rate       = &omap2_clksel_set_rate,
1550         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1551         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1552         .clkdm_name     = "iss_clkdm",
1553 };
1554
1555 static struct clk fpka_fck = {
1556         .name           = "fpka_fck",
1557         .ops            = &clkops_omap2_dflt,
1558         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1559         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1560         .clkdm_name     = "l4_secure_clkdm",
1561         .parent         = &l4_div_ck,
1562         .recalc         = &followparent_recalc,
1563 };
1564
1565 static struct clk gpio1_dbclk = {
1566         .name           = "gpio1_dbclk",
1567         .ops            = &clkops_omap2_dflt,
1568         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1569         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1570         .clkdm_name     = "l4_wkup_clkdm",
1571         .parent         = &sys_32k_ck,
1572         .recalc         = &followparent_recalc,
1573 };
1574
1575 static struct clk gpio1_ick = {
1576         .name           = "gpio1_ick",
1577         .ops            = &clkops_omap2_dflt,
1578         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1579         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1580         .clkdm_name     = "l4_wkup_clkdm",
1581         .parent         = &l4_wkup_clk_mux_ck,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static struct clk gpio2_dbclk = {
1586         .name           = "gpio2_dbclk",
1587         .ops            = &clkops_omap2_dflt,
1588         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1589         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1590         .clkdm_name     = "l4_per_clkdm",
1591         .parent         = &sys_32k_ck,
1592         .recalc         = &followparent_recalc,
1593 };
1594
1595 static struct clk gpio2_ick = {
1596         .name           = "gpio2_ick",
1597         .ops            = &clkops_omap2_dflt,
1598         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1599         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1600         .clkdm_name     = "l4_per_clkdm",
1601         .parent         = &l4_div_ck,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk gpio3_dbclk = {
1606         .name           = "gpio3_dbclk",
1607         .ops            = &clkops_omap2_dflt,
1608         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1609         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .parent         = &sys_32k_ck,
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk gpio3_ick = {
1616         .name           = "gpio3_ick",
1617         .ops            = &clkops_omap2_dflt,
1618         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1619         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1620         .clkdm_name     = "l4_per_clkdm",
1621         .parent         = &l4_div_ck,
1622         .recalc         = &followparent_recalc,
1623 };
1624
1625 static struct clk gpio4_dbclk = {
1626         .name           = "gpio4_dbclk",
1627         .ops            = &clkops_omap2_dflt,
1628         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1629         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1630         .clkdm_name     = "l4_per_clkdm",
1631         .parent         = &sys_32k_ck,
1632         .recalc         = &followparent_recalc,
1633 };
1634
1635 static struct clk gpio4_ick = {
1636         .name           = "gpio4_ick",
1637         .ops            = &clkops_omap2_dflt,
1638         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1639         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .parent         = &l4_div_ck,
1642         .recalc         = &followparent_recalc,
1643 };
1644
1645 static struct clk gpio5_dbclk = {
1646         .name           = "gpio5_dbclk",
1647         .ops            = &clkops_omap2_dflt,
1648         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1649         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1650         .clkdm_name     = "l4_per_clkdm",
1651         .parent         = &sys_32k_ck,
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk gpio5_ick = {
1656         .name           = "gpio5_ick",
1657         .ops            = &clkops_omap2_dflt,
1658         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1659         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1660         .clkdm_name     = "l4_per_clkdm",
1661         .parent         = &l4_div_ck,
1662         .recalc         = &followparent_recalc,
1663 };
1664
1665 static struct clk gpio6_dbclk = {
1666         .name           = "gpio6_dbclk",
1667         .ops            = &clkops_omap2_dflt,
1668         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1669         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1670         .clkdm_name     = "l4_per_clkdm",
1671         .parent         = &sys_32k_ck,
1672         .recalc         = &followparent_recalc,
1673 };
1674
1675 static struct clk gpio6_ick = {
1676         .name           = "gpio6_ick",
1677         .ops            = &clkops_omap2_dflt,
1678         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1679         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1680         .clkdm_name     = "l4_per_clkdm",
1681         .parent         = &l4_div_ck,
1682         .recalc         = &followparent_recalc,
1683 };
1684
1685 static struct clk gpmc_ick = {
1686         .name           = "gpmc_ick",
1687         .ops            = &clkops_omap2_dflt,
1688         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1689         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1690         .clkdm_name     = "l3_2_clkdm",
1691         .parent         = &l3_div_ck,
1692         .recalc         = &followparent_recalc,
1693 };
1694
1695 static const struct clksel sgx_clk_mux_sel[] = {
1696         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1697         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1698         { .parent = NULL },
1699 };
1700
1701 /* Merged sgx_clk_mux into gpu */
1702 static struct clk gpu_fck = {
1703         .name           = "gpu_fck",
1704         .parent         = &dpll_core_m7x2_ck,
1705         .clksel         = sgx_clk_mux_sel,
1706         .init           = &omap2_init_clksel_parent,
1707         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1708         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1709         .ops            = &clkops_omap2_dflt,
1710         .recalc         = &omap2_clksel_recalc,
1711         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1712         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1713         .clkdm_name     = "l3_gfx_clkdm",
1714 };
1715
1716 static struct clk hdq1w_fck = {
1717         .name           = "hdq1w_fck",
1718         .ops            = &clkops_omap2_dflt,
1719         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1720         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1721         .clkdm_name     = "l4_per_clkdm",
1722         .parent         = &func_12m_fclk,
1723         .recalc         = &followparent_recalc,
1724 };
1725
1726 static const struct clksel hsi_fclk_div[] = {
1727         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1728         { .parent = NULL },
1729 };
1730
1731 /* Merged hsi_fclk into hsi */
1732 static struct clk hsi_fck = {
1733         .name           = "hsi_fck",
1734         .parent         = &dpll_per_m2x2_ck,
1735         .clksel         = hsi_fclk_div,
1736         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1737         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1738         .ops            = &clkops_omap2_dflt,
1739         .recalc         = &omap2_clksel_recalc,
1740         .round_rate     = &omap2_clksel_round_rate,
1741         .set_rate       = &omap2_clksel_set_rate,
1742         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1743         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1744         .clkdm_name     = "l3_init_clkdm",
1745 };
1746
1747 static struct clk i2c1_fck = {
1748         .name           = "i2c1_fck",
1749         .ops            = &clkops_omap2_dflt,
1750         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1751         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1752         .clkdm_name     = "l4_per_clkdm",
1753         .parent         = &func_96m_fclk,
1754         .recalc         = &followparent_recalc,
1755 };
1756
1757 static struct clk i2c2_fck = {
1758         .name           = "i2c2_fck",
1759         .ops            = &clkops_omap2_dflt,
1760         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1761         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1762         .clkdm_name     = "l4_per_clkdm",
1763         .parent         = &func_96m_fclk,
1764         .recalc         = &followparent_recalc,
1765 };
1766
1767 static struct clk i2c3_fck = {
1768         .name           = "i2c3_fck",
1769         .ops            = &clkops_omap2_dflt,
1770         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1771         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1772         .clkdm_name     = "l4_per_clkdm",
1773         .parent         = &func_96m_fclk,
1774         .recalc         = &followparent_recalc,
1775 };
1776
1777 static struct clk i2c4_fck = {
1778         .name           = "i2c4_fck",
1779         .ops            = &clkops_omap2_dflt,
1780         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1781         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1782         .clkdm_name     = "l4_per_clkdm",
1783         .parent         = &func_96m_fclk,
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk ipu_fck = {
1788         .name           = "ipu_fck",
1789         .ops            = &clkops_omap2_dflt,
1790         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1791         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1792         .clkdm_name     = "ducati_clkdm",
1793         .parent         = &ducati_clk_mux_ck,
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk iss_ctrlclk = {
1798         .name           = "iss_ctrlclk",
1799         .ops            = &clkops_omap2_dflt,
1800         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1801         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1802         .clkdm_name     = "iss_clkdm",
1803         .parent         = &func_96m_fclk,
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 static struct clk iss_fck = {
1808         .name           = "iss_fck",
1809         .ops            = &clkops_omap2_dflt,
1810         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1811         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1812         .clkdm_name     = "iss_clkdm",
1813         .parent         = &ducati_clk_mux_ck,
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk iva_fck = {
1818         .name           = "iva_fck",
1819         .ops            = &clkops_omap2_dflt,
1820         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1821         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1822         .clkdm_name     = "ivahd_clkdm",
1823         .parent         = &dpll_iva_m5x2_ck,
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk kbd_fck = {
1828         .name           = "kbd_fck",
1829         .ops            = &clkops_omap2_dflt,
1830         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1831         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1832         .clkdm_name     = "l4_wkup_clkdm",
1833         .parent         = &sys_32k_ck,
1834         .recalc         = &followparent_recalc,
1835 };
1836
1837 static struct clk l3_instr_ick = {
1838         .name           = "l3_instr_ick",
1839         .ops            = &clkops_omap2_dflt,
1840         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1841         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1842         .clkdm_name     = "l3_instr_clkdm",
1843         .flags          = ENABLE_ON_INIT,
1844         .parent         = &l3_div_ck,
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk l3_main_3_ick = {
1849         .name           = "l3_main_3_ick",
1850         .ops            = &clkops_omap2_dflt,
1851         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1852         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1853         .clkdm_name     = "l3_instr_clkdm",
1854         .flags          = ENABLE_ON_INIT,
1855         .parent         = &l3_div_ck,
1856         .recalc         = &followparent_recalc,
1857 };
1858
1859 static struct clk mcasp_sync_mux_ck = {
1860         .name           = "mcasp_sync_mux_ck",
1861         .parent         = &abe_24m_fclk,
1862         .clksel         = dmic_sync_mux_sel,
1863         .init           = &omap2_init_clksel_parent,
1864         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1865         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1866         .ops            = &clkops_null,
1867         .recalc         = &omap2_clksel_recalc,
1868 };
1869
1870 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1871         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1872         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1873         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1874         { .parent = NULL },
1875 };
1876
1877 /* Merged func_mcasp_abe_gfclk into mcasp */
1878 static struct clk mcasp_fck = {
1879         .name           = "mcasp_fck",
1880         .parent         = &mcasp_sync_mux_ck,
1881         .clksel         = func_mcasp_abe_gfclk_sel,
1882         .init           = &omap2_init_clksel_parent,
1883         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1884         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1885         .ops            = &clkops_omap2_dflt,
1886         .recalc         = &omap2_clksel_recalc,
1887         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1888         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1889         .clkdm_name     = "abe_clkdm",
1890 };
1891
1892 static struct clk mcbsp1_sync_mux_ck = {
1893         .name           = "mcbsp1_sync_mux_ck",
1894         .parent         = &abe_24m_fclk,
1895         .clksel         = dmic_sync_mux_sel,
1896         .init           = &omap2_init_clksel_parent,
1897         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1898         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1899         .ops            = &clkops_null,
1900         .recalc         = &omap2_clksel_recalc,
1901 };
1902
1903 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1904         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1905         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1906         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1907         { .parent = NULL },
1908 };
1909
1910 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1911 static struct clk mcbsp1_fck = {
1912         .name           = "mcbsp1_fck",
1913         .parent         = &mcbsp1_sync_mux_ck,
1914         .clksel         = func_mcbsp1_gfclk_sel,
1915         .init           = &omap2_init_clksel_parent,
1916         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1917         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1918         .ops            = &clkops_omap2_dflt,
1919         .recalc         = &omap2_clksel_recalc,
1920         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1921         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1922         .clkdm_name     = "abe_clkdm",
1923 };
1924
1925 static struct clk mcbsp2_sync_mux_ck = {
1926         .name           = "mcbsp2_sync_mux_ck",
1927         .parent         = &abe_24m_fclk,
1928         .clksel         = dmic_sync_mux_sel,
1929         .init           = &omap2_init_clksel_parent,
1930         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1931         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1932         .ops            = &clkops_null,
1933         .recalc         = &omap2_clksel_recalc,
1934 };
1935
1936 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1937         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1938         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1939         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1940         { .parent = NULL },
1941 };
1942
1943 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1944 static struct clk mcbsp2_fck = {
1945         .name           = "mcbsp2_fck",
1946         .parent         = &mcbsp2_sync_mux_ck,
1947         .clksel         = func_mcbsp2_gfclk_sel,
1948         .init           = &omap2_init_clksel_parent,
1949         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1950         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1951         .ops            = &clkops_omap2_dflt,
1952         .recalc         = &omap2_clksel_recalc,
1953         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1954         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1955         .clkdm_name     = "abe_clkdm",
1956 };
1957
1958 static struct clk mcbsp3_sync_mux_ck = {
1959         .name           = "mcbsp3_sync_mux_ck",
1960         .parent         = &abe_24m_fclk,
1961         .clksel         = dmic_sync_mux_sel,
1962         .init           = &omap2_init_clksel_parent,
1963         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1964         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1965         .ops            = &clkops_null,
1966         .recalc         = &omap2_clksel_recalc,
1967 };
1968
1969 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1970         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1971         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1972         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1973         { .parent = NULL },
1974 };
1975
1976 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1977 static struct clk mcbsp3_fck = {
1978         .name           = "mcbsp3_fck",
1979         .parent         = &mcbsp3_sync_mux_ck,
1980         .clksel         = func_mcbsp3_gfclk_sel,
1981         .init           = &omap2_init_clksel_parent,
1982         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1983         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1984         .ops            = &clkops_omap2_dflt,
1985         .recalc         = &omap2_clksel_recalc,
1986         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1987         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1988         .clkdm_name     = "abe_clkdm",
1989 };
1990
1991 static struct clk mcbsp4_sync_mux_ck = {
1992         .name           = "mcbsp4_sync_mux_ck",
1993         .parent         = &func_96m_fclk,
1994         .clksel         = mcasp2_fclk_sel,
1995         .init           = &omap2_init_clksel_parent,
1996         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1997         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1998         .ops            = &clkops_null,
1999         .recalc         = &omap2_clksel_recalc,
2000 };
2001
2002 static const struct clksel per_mcbsp4_gfclk_sel[] = {
2003         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
2004         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2005         { .parent = NULL },
2006 };
2007
2008 /* Merged per_mcbsp4_gfclk into mcbsp4 */
2009 static struct clk mcbsp4_fck = {
2010         .name           = "mcbsp4_fck",
2011         .parent         = &mcbsp4_sync_mux_ck,
2012         .clksel         = per_mcbsp4_gfclk_sel,
2013         .init           = &omap2_init_clksel_parent,
2014         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2015         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2016         .ops            = &clkops_omap2_dflt,
2017         .recalc         = &omap2_clksel_recalc,
2018         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2019         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2020         .clkdm_name     = "l4_per_clkdm",
2021 };
2022
2023 static struct clk mcpdm_fck = {
2024         .name           = "mcpdm_fck",
2025         .ops            = &clkops_omap2_dflt,
2026         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2027         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2028         .clkdm_name     = "abe_clkdm",
2029         .parent         = &pad_clks_ck,
2030         .recalc         = &followparent_recalc,
2031 };
2032
2033 static struct clk mcspi1_fck = {
2034         .name           = "mcspi1_fck",
2035         .ops            = &clkops_omap2_dflt,
2036         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2037         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2038         .clkdm_name     = "l4_per_clkdm",
2039         .parent         = &func_48m_fclk,
2040         .recalc         = &followparent_recalc,
2041 };
2042
2043 static struct clk mcspi2_fck = {
2044         .name           = "mcspi2_fck",
2045         .ops            = &clkops_omap2_dflt,
2046         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2047         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2048         .clkdm_name     = "l4_per_clkdm",
2049         .parent         = &func_48m_fclk,
2050         .recalc         = &followparent_recalc,
2051 };
2052
2053 static struct clk mcspi3_fck = {
2054         .name           = "mcspi3_fck",
2055         .ops            = &clkops_omap2_dflt,
2056         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2057         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2058         .clkdm_name     = "l4_per_clkdm",
2059         .parent         = &func_48m_fclk,
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk mcspi4_fck = {
2064         .name           = "mcspi4_fck",
2065         .ops            = &clkops_omap2_dflt,
2066         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2067         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2068         .clkdm_name     = "l4_per_clkdm",
2069         .parent         = &func_48m_fclk,
2070         .recalc         = &followparent_recalc,
2071 };
2072
2073 /* Merged hsmmc1_fclk into mmc1 */
2074 static struct clk mmc1_fck = {
2075         .name           = "mmc1_fck",
2076         .parent         = &func_64m_fclk,
2077         .clksel         = hsmmc6_fclk_sel,
2078         .init           = &omap2_init_clksel_parent,
2079         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2080         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2081         .ops            = &clkops_omap2_dflt,
2082         .recalc         = &omap2_clksel_recalc,
2083         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2084         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2085         .clkdm_name     = "l3_init_clkdm",
2086 };
2087
2088 /* Merged hsmmc2_fclk into mmc2 */
2089 static struct clk mmc2_fck = {
2090         .name           = "mmc2_fck",
2091         .parent         = &func_64m_fclk,
2092         .clksel         = hsmmc6_fclk_sel,
2093         .init           = &omap2_init_clksel_parent,
2094         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2095         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2096         .ops            = &clkops_omap2_dflt,
2097         .recalc         = &omap2_clksel_recalc,
2098         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2099         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2100         .clkdm_name     = "l3_init_clkdm",
2101 };
2102
2103 static struct clk mmc3_fck = {
2104         .name           = "mmc3_fck",
2105         .ops            = &clkops_omap2_dflt,
2106         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2107         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2108         .clkdm_name     = "l4_per_clkdm",
2109         .parent         = &func_48m_fclk,
2110         .recalc         = &followparent_recalc,
2111 };
2112
2113 static struct clk mmc4_fck = {
2114         .name           = "mmc4_fck",
2115         .ops            = &clkops_omap2_dflt,
2116         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2117         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2118         .clkdm_name     = "l4_per_clkdm",
2119         .parent         = &func_48m_fclk,
2120         .recalc         = &followparent_recalc,
2121 };
2122
2123 static struct clk mmc5_fck = {
2124         .name           = "mmc5_fck",
2125         .ops            = &clkops_omap2_dflt,
2126         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2127         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2128         .clkdm_name     = "l4_per_clkdm",
2129         .parent         = &func_48m_fclk,
2130         .recalc         = &followparent_recalc,
2131 };
2132
2133 static struct clk ocp2scp_usb_phy_phy_48m = {
2134         .name           = "ocp2scp_usb_phy_phy_48m",
2135         .ops            = &clkops_omap2_dflt,
2136         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2137         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2138         .clkdm_name     = "l3_init_clkdm",
2139         .parent         = &func_48m_fclk,
2140         .recalc         = &followparent_recalc,
2141 };
2142
2143 static struct clk ocp2scp_usb_phy_ick = {
2144         .name           = "ocp2scp_usb_phy_ick",
2145         .ops            = &clkops_omap2_dflt,
2146         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2147         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2148         .clkdm_name     = "l3_init_clkdm",
2149         .parent         = &l4_div_ck,
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 static struct clk ocp_wp_noc_ick = {
2154         .name           = "ocp_wp_noc_ick",
2155         .ops            = &clkops_omap2_dflt,
2156         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2157         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2158         .clkdm_name     = "l3_instr_clkdm",
2159         .flags          = ENABLE_ON_INIT,
2160         .parent         = &l3_div_ck,
2161         .recalc         = &followparent_recalc,
2162 };
2163
2164 static struct clk rng_ick = {
2165         .name           = "rng_ick",
2166         .ops            = &clkops_omap2_dflt,
2167         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2168         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2169         .clkdm_name     = "l4_secure_clkdm",
2170         .parent         = &l4_div_ck,
2171         .recalc         = &followparent_recalc,
2172 };
2173
2174 static struct clk sha2md5_fck = {
2175         .name           = "sha2md5_fck",
2176         .ops            = &clkops_omap2_dflt,
2177         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2178         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2179         .clkdm_name     = "l4_secure_clkdm",
2180         .parent         = &l3_div_ck,
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk sl2if_ick = {
2185         .name           = "sl2if_ick",
2186         .ops            = &clkops_omap2_dflt,
2187         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2188         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2189         .clkdm_name     = "ivahd_clkdm",
2190         .parent         = &dpll_iva_m5x2_ck,
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 static struct clk slimbus1_fclk_1 = {
2195         .name           = "slimbus1_fclk_1",
2196         .ops            = &clkops_omap2_dflt,
2197         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2198         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2199         .clkdm_name     = "abe_clkdm",
2200         .parent         = &func_24m_clk,
2201         .recalc         = &followparent_recalc,
2202 };
2203
2204 static struct clk slimbus1_fclk_0 = {
2205         .name           = "slimbus1_fclk_0",
2206         .ops            = &clkops_omap2_dflt,
2207         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2208         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2209         .clkdm_name     = "abe_clkdm",
2210         .parent         = &abe_24m_fclk,
2211         .recalc         = &followparent_recalc,
2212 };
2213
2214 static struct clk slimbus1_fclk_2 = {
2215         .name           = "slimbus1_fclk_2",
2216         .ops            = &clkops_omap2_dflt,
2217         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2218         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2219         .clkdm_name     = "abe_clkdm",
2220         .parent         = &pad_clks_ck,
2221         .recalc         = &followparent_recalc,
2222 };
2223
2224 static struct clk slimbus1_slimbus_clk = {
2225         .name           = "slimbus1_slimbus_clk",
2226         .ops            = &clkops_omap2_dflt,
2227         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2228         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2229         .clkdm_name     = "abe_clkdm",
2230         .parent         = &slimbus_clk,
2231         .recalc         = &followparent_recalc,
2232 };
2233
2234 static struct clk slimbus1_fck = {
2235         .name           = "slimbus1_fck",
2236         .ops            = &clkops_omap2_dflt,
2237         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2238         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2239         .clkdm_name     = "abe_clkdm",
2240         .parent         = &ocp_abe_iclk,
2241         .recalc         = &followparent_recalc,
2242 };
2243
2244 static struct clk slimbus2_fclk_1 = {
2245         .name           = "slimbus2_fclk_1",
2246         .ops            = &clkops_omap2_dflt,
2247         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2248         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2249         .clkdm_name     = "l4_per_clkdm",
2250         .parent         = &per_abe_24m_fclk,
2251         .recalc         = &followparent_recalc,
2252 };
2253
2254 static struct clk slimbus2_fclk_0 = {
2255         .name           = "slimbus2_fclk_0",
2256         .ops            = &clkops_omap2_dflt,
2257         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2258         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2259         .clkdm_name     = "l4_per_clkdm",
2260         .parent         = &func_24mc_fclk,
2261         .recalc         = &followparent_recalc,
2262 };
2263
2264 static struct clk slimbus2_slimbus_clk = {
2265         .name           = "slimbus2_slimbus_clk",
2266         .ops            = &clkops_omap2_dflt,
2267         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2268         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2269         .clkdm_name     = "l4_per_clkdm",
2270         .parent         = &pad_slimbus_core_clks_ck,
2271         .recalc         = &followparent_recalc,
2272 };
2273
2274 static struct clk slimbus2_fck = {
2275         .name           = "slimbus2_fck",
2276         .ops            = &clkops_omap2_dflt,
2277         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2278         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2279         .clkdm_name     = "l4_per_clkdm",
2280         .parent         = &l4_div_ck,
2281         .recalc         = &followparent_recalc,
2282 };
2283
2284 static struct clk smartreflex_core_fck = {
2285         .name           = "smartreflex_core_fck",
2286         .ops            = &clkops_omap2_dflt,
2287         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2288         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2289         .clkdm_name     = "l4_ao_clkdm",
2290         .parent         = &l4_wkup_clk_mux_ck,
2291         .recalc         = &followparent_recalc,
2292 };
2293
2294 static struct clk smartreflex_iva_fck = {
2295         .name           = "smartreflex_iva_fck",
2296         .ops            = &clkops_omap2_dflt,
2297         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2298         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2299         .clkdm_name     = "l4_ao_clkdm",
2300         .parent         = &l4_wkup_clk_mux_ck,
2301         .recalc         = &followparent_recalc,
2302 };
2303
2304 static struct clk smartreflex_mpu_fck = {
2305         .name           = "smartreflex_mpu_fck",
2306         .ops            = &clkops_omap2_dflt,
2307         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2308         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2309         .clkdm_name     = "l4_ao_clkdm",
2310         .parent         = &l4_wkup_clk_mux_ck,
2311         .recalc         = &followparent_recalc,
2312 };
2313
2314 /* Merged dmt1_clk_mux into timer1 */
2315 static struct clk timer1_fck = {
2316         .name           = "timer1_fck",
2317         .parent         = &sys_clkin_ck,
2318         .clksel         = abe_dpll_bypass_clk_mux_sel,
2319         .init           = &omap2_init_clksel_parent,
2320         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2321         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2322         .ops            = &clkops_omap2_dflt,
2323         .recalc         = &omap2_clksel_recalc,
2324         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2325         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2326         .clkdm_name     = "l4_wkup_clkdm",
2327 };
2328
2329 /* Merged cm2_dm10_mux into timer10 */
2330 static struct clk timer10_fck = {
2331         .name           = "timer10_fck",
2332         .parent         = &sys_clkin_ck,
2333         .clksel         = abe_dpll_bypass_clk_mux_sel,
2334         .init           = &omap2_init_clksel_parent,
2335         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2336         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2337         .ops            = &clkops_omap2_dflt,
2338         .recalc         = &omap2_clksel_recalc,
2339         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2340         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2341         .clkdm_name     = "l4_per_clkdm",
2342 };
2343
2344 /* Merged cm2_dm11_mux into timer11 */
2345 static struct clk timer11_fck = {
2346         .name           = "timer11_fck",
2347         .parent         = &sys_clkin_ck,
2348         .clksel         = abe_dpll_bypass_clk_mux_sel,
2349         .init           = &omap2_init_clksel_parent,
2350         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2351         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2352         .ops            = &clkops_omap2_dflt,
2353         .recalc         = &omap2_clksel_recalc,
2354         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2355         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2356         .clkdm_name     = "l4_per_clkdm",
2357 };
2358
2359 /* Merged cm2_dm2_mux into timer2 */
2360 static struct clk timer2_fck = {
2361         .name           = "timer2_fck",
2362         .parent         = &sys_clkin_ck,
2363         .clksel         = abe_dpll_bypass_clk_mux_sel,
2364         .init           = &omap2_init_clksel_parent,
2365         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2366         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2367         .ops            = &clkops_omap2_dflt,
2368         .recalc         = &omap2_clksel_recalc,
2369         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2370         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2371         .clkdm_name     = "l4_per_clkdm",
2372 };
2373
2374 /* Merged cm2_dm3_mux into timer3 */
2375 static struct clk timer3_fck = {
2376         .name           = "timer3_fck",
2377         .parent         = &sys_clkin_ck,
2378         .clksel         = abe_dpll_bypass_clk_mux_sel,
2379         .init           = &omap2_init_clksel_parent,
2380         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2381         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2382         .ops            = &clkops_omap2_dflt,
2383         .recalc         = &omap2_clksel_recalc,
2384         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2385         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2386         .clkdm_name     = "l4_per_clkdm",
2387 };
2388
2389 /* Merged cm2_dm4_mux into timer4 */
2390 static struct clk timer4_fck = {
2391         .name           = "timer4_fck",
2392         .parent         = &sys_clkin_ck,
2393         .clksel         = abe_dpll_bypass_clk_mux_sel,
2394         .init           = &omap2_init_clksel_parent,
2395         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2396         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2397         .ops            = &clkops_omap2_dflt,
2398         .recalc         = &omap2_clksel_recalc,
2399         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2400         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2401         .clkdm_name     = "l4_per_clkdm",
2402 };
2403
2404 static const struct clksel timer5_sync_mux_sel[] = {
2405         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2406         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2407         { .parent = NULL },
2408 };
2409
2410 /* Merged timer5_sync_mux into timer5 */
2411 static struct clk timer5_fck = {
2412         .name           = "timer5_fck",
2413         .parent         = &syc_clk_div_ck,
2414         .clksel         = timer5_sync_mux_sel,
2415         .init           = &omap2_init_clksel_parent,
2416         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2417         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2418         .ops            = &clkops_omap2_dflt,
2419         .recalc         = &omap2_clksel_recalc,
2420         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2421         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2422         .clkdm_name     = "abe_clkdm",
2423 };
2424
2425 /* Merged timer6_sync_mux into timer6 */
2426 static struct clk timer6_fck = {
2427         .name           = "timer6_fck",
2428         .parent         = &syc_clk_div_ck,
2429         .clksel         = timer5_sync_mux_sel,
2430         .init           = &omap2_init_clksel_parent,
2431         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2432         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2433         .ops            = &clkops_omap2_dflt,
2434         .recalc         = &omap2_clksel_recalc,
2435         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2436         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2437         .clkdm_name     = "abe_clkdm",
2438 };
2439
2440 /* Merged timer7_sync_mux into timer7 */
2441 static struct clk timer7_fck = {
2442         .name           = "timer7_fck",
2443         .parent         = &syc_clk_div_ck,
2444         .clksel         = timer5_sync_mux_sel,
2445         .init           = &omap2_init_clksel_parent,
2446         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2447         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2448         .ops            = &clkops_omap2_dflt,
2449         .recalc         = &omap2_clksel_recalc,
2450         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2451         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2452         .clkdm_name     = "abe_clkdm",
2453 };
2454
2455 /* Merged timer8_sync_mux into timer8 */
2456 static struct clk timer8_fck = {
2457         .name           = "timer8_fck",
2458         .parent         = &syc_clk_div_ck,
2459         .clksel         = timer5_sync_mux_sel,
2460         .init           = &omap2_init_clksel_parent,
2461         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2462         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2463         .ops            = &clkops_omap2_dflt,
2464         .recalc         = &omap2_clksel_recalc,
2465         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2466         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2467         .clkdm_name     = "abe_clkdm",
2468 };
2469
2470 /* Merged cm2_dm9_mux into timer9 */
2471 static struct clk timer9_fck = {
2472         .name           = "timer9_fck",
2473         .parent         = &sys_clkin_ck,
2474         .clksel         = abe_dpll_bypass_clk_mux_sel,
2475         .init           = &omap2_init_clksel_parent,
2476         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2477         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2478         .ops            = &clkops_omap2_dflt,
2479         .recalc         = &omap2_clksel_recalc,
2480         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2481         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2482         .clkdm_name     = "l4_per_clkdm",
2483 };
2484
2485 static struct clk uart1_fck = {
2486         .name           = "uart1_fck",
2487         .ops            = &clkops_omap2_dflt,
2488         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2489         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2490         .clkdm_name     = "l4_per_clkdm",
2491         .parent         = &func_48m_fclk,
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk uart2_fck = {
2496         .name           = "uart2_fck",
2497         .ops            = &clkops_omap2_dflt,
2498         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2499         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2500         .clkdm_name     = "l4_per_clkdm",
2501         .parent         = &func_48m_fclk,
2502         .recalc         = &followparent_recalc,
2503 };
2504
2505 static struct clk uart3_fck = {
2506         .name           = "uart3_fck",
2507         .ops            = &clkops_omap2_dflt,
2508         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2509         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2510         .clkdm_name     = "l4_per_clkdm",
2511         .parent         = &func_48m_fclk,
2512         .recalc         = &followparent_recalc,
2513 };
2514
2515 static struct clk uart4_fck = {
2516         .name           = "uart4_fck",
2517         .ops            = &clkops_omap2_dflt,
2518         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2519         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2520         .clkdm_name     = "l4_per_clkdm",
2521         .parent         = &func_48m_fclk,
2522         .recalc         = &followparent_recalc,
2523 };
2524
2525 static struct clk usb_host_fs_fck = {
2526         .name           = "usb_host_fs_fck",
2527         .ops            = &clkops_omap2_dflt,
2528         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2529         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2530         .clkdm_name     = "l3_init_clkdm",
2531         .parent         = &func_48mc_fclk,
2532         .recalc         = &followparent_recalc,
2533 };
2534
2535 static const struct clksel utmi_p1_gfclk_sel[] = {
2536         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2537         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2538         { .parent = NULL },
2539 };
2540
2541 static struct clk utmi_p1_gfclk = {
2542         .name           = "utmi_p1_gfclk",
2543         .parent         = &init_60m_fclk,
2544         .clksel         = utmi_p1_gfclk_sel,
2545         .init           = &omap2_init_clksel_parent,
2546         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2547         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2548         .ops            = &clkops_null,
2549         .recalc         = &omap2_clksel_recalc,
2550 };
2551
2552 static struct clk usb_host_hs_utmi_p1_clk = {
2553         .name           = "usb_host_hs_utmi_p1_clk",
2554         .ops            = &clkops_omap2_dflt,
2555         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2556         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2557         .clkdm_name     = "l3_init_clkdm",
2558         .parent         = &utmi_p1_gfclk,
2559         .recalc         = &followparent_recalc,
2560 };
2561
2562 static const struct clksel utmi_p2_gfclk_sel[] = {
2563         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2564         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2565         { .parent = NULL },
2566 };
2567
2568 static struct clk utmi_p2_gfclk = {
2569         .name           = "utmi_p2_gfclk",
2570         .parent         = &init_60m_fclk,
2571         .clksel         = utmi_p2_gfclk_sel,
2572         .init           = &omap2_init_clksel_parent,
2573         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2574         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2575         .ops            = &clkops_null,
2576         .recalc         = &omap2_clksel_recalc,
2577 };
2578
2579 static struct clk usb_host_hs_utmi_p2_clk = {
2580         .name           = "usb_host_hs_utmi_p2_clk",
2581         .ops            = &clkops_omap2_dflt,
2582         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2583         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2584         .clkdm_name     = "l3_init_clkdm",
2585         .parent         = &utmi_p2_gfclk,
2586         .recalc         = &followparent_recalc,
2587 };
2588
2589 static struct clk usb_host_hs_utmi_p3_clk = {
2590         .name           = "usb_host_hs_utmi_p3_clk",
2591         .ops            = &clkops_omap2_dflt,
2592         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2593         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2594         .clkdm_name     = "l3_init_clkdm",
2595         .parent         = &init_60m_fclk,
2596         .recalc         = &followparent_recalc,
2597 };
2598
2599 static struct clk usb_host_hs_hsic480m_p1_clk = {
2600         .name           = "usb_host_hs_hsic480m_p1_clk",
2601         .ops            = &clkops_omap2_dflt,
2602         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2603         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2604         .clkdm_name     = "l3_init_clkdm",
2605         .parent         = &dpll_usb_m2_ck,
2606         .recalc         = &followparent_recalc,
2607 };
2608
2609 static struct clk usb_host_hs_hsic60m_p1_clk = {
2610         .name           = "usb_host_hs_hsic60m_p1_clk",
2611         .ops            = &clkops_omap2_dflt,
2612         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2613         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2614         .clkdm_name     = "l3_init_clkdm",
2615         .parent         = &init_60m_fclk,
2616         .recalc         = &followparent_recalc,
2617 };
2618
2619 static struct clk usb_host_hs_hsic60m_p2_clk = {
2620         .name           = "usb_host_hs_hsic60m_p2_clk",
2621         .ops            = &clkops_omap2_dflt,
2622         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2623         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2624         .clkdm_name     = "l3_init_clkdm",
2625         .parent         = &init_60m_fclk,
2626         .recalc         = &followparent_recalc,
2627 };
2628
2629 static struct clk usb_host_hs_hsic480m_p2_clk = {
2630         .name           = "usb_host_hs_hsic480m_p2_clk",
2631         .ops            = &clkops_omap2_dflt,
2632         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2633         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2634         .clkdm_name     = "l3_init_clkdm",
2635         .parent         = &dpll_usb_m2_ck,
2636         .recalc         = &followparent_recalc,
2637 };
2638
2639 static struct clk usb_host_hs_func48mclk = {
2640         .name           = "usb_host_hs_func48mclk",
2641         .ops            = &clkops_omap2_dflt,
2642         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2643         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2644         .clkdm_name     = "l3_init_clkdm",
2645         .parent         = &func_48mc_fclk,
2646         .recalc         = &followparent_recalc,
2647 };
2648
2649 static struct clk usb_host_hs_fck = {
2650         .name           = "usb_host_hs_fck",
2651         .ops            = &clkops_omap2_dflt,
2652         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2653         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2654         .clkdm_name     = "l3_init_clkdm",
2655         .parent         = &init_60m_fclk,
2656         .recalc         = &followparent_recalc,
2657 };
2658
2659 static const struct clksel otg_60m_gfclk_sel[] = {
2660         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2661         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2662         { .parent = NULL },
2663 };
2664
2665 static struct clk otg_60m_gfclk = {
2666         .name           = "otg_60m_gfclk",
2667         .parent         = &utmi_phy_clkout_ck,
2668         .clksel         = otg_60m_gfclk_sel,
2669         .init           = &omap2_init_clksel_parent,
2670         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2671         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2672         .ops            = &clkops_null,
2673         .recalc         = &omap2_clksel_recalc,
2674 };
2675
2676 static struct clk usb_otg_hs_xclk = {
2677         .name           = "usb_otg_hs_xclk",
2678         .ops            = &clkops_omap2_dflt,
2679         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2680         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2681         .clkdm_name     = "l3_init_clkdm",
2682         .parent         = &otg_60m_gfclk,
2683         .recalc         = &followparent_recalc,
2684 };
2685
2686 static struct clk usb_otg_hs_ick = {
2687         .name           = "usb_otg_hs_ick",
2688         .ops            = &clkops_omap2_dflt,
2689         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2690         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2691         .clkdm_name     = "l3_init_clkdm",
2692         .parent         = &l3_div_ck,
2693         .recalc         = &followparent_recalc,
2694 };
2695
2696 static struct clk usb_phy_cm_clk32k = {
2697         .name           = "usb_phy_cm_clk32k",
2698         .ops            = &clkops_omap2_dflt,
2699         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2700         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2701         .clkdm_name     = "l4_ao_clkdm",
2702         .parent         = &sys_32k_ck,
2703         .recalc         = &followparent_recalc,
2704 };
2705
2706 static struct clk usb_tll_hs_usb_ch2_clk = {
2707         .name           = "usb_tll_hs_usb_ch2_clk",
2708         .ops            = &clkops_omap2_dflt,
2709         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2710         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2711         .clkdm_name     = "l3_init_clkdm",
2712         .parent         = &init_60m_fclk,
2713         .recalc         = &followparent_recalc,
2714 };
2715
2716 static struct clk usb_tll_hs_usb_ch0_clk = {
2717         .name           = "usb_tll_hs_usb_ch0_clk",
2718         .ops            = &clkops_omap2_dflt,
2719         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2720         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2721         .clkdm_name     = "l3_init_clkdm",
2722         .parent         = &init_60m_fclk,
2723         .recalc         = &followparent_recalc,
2724 };
2725
2726 static struct clk usb_tll_hs_usb_ch1_clk = {
2727         .name           = "usb_tll_hs_usb_ch1_clk",
2728         .ops            = &clkops_omap2_dflt,
2729         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2730         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2731         .clkdm_name     = "l3_init_clkdm",
2732         .parent         = &init_60m_fclk,
2733         .recalc         = &followparent_recalc,
2734 };
2735
2736 static struct clk usb_tll_hs_ick = {
2737         .name           = "usb_tll_hs_ick",
2738         .ops            = &clkops_omap2_dflt,
2739         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2740         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2741         .clkdm_name     = "l3_init_clkdm",
2742         .parent         = &l4_div_ck,
2743         .recalc         = &followparent_recalc,
2744 };
2745
2746 static const struct clksel_rate div2_14to18_rates[] = {
2747         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2748         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2749         { .div = 0 },
2750 };
2751
2752 static const struct clksel usim_fclk_div[] = {
2753         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2754         { .parent = NULL },
2755 };
2756
2757 static struct clk usim_ck = {
2758         .name           = "usim_ck",
2759         .parent         = &dpll_per_m4x2_ck,
2760         .clksel         = usim_fclk_div,
2761         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2762         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2763         .ops            = &clkops_null,
2764         .recalc         = &omap2_clksel_recalc,
2765         .round_rate     = &omap2_clksel_round_rate,
2766         .set_rate       = &omap2_clksel_set_rate,
2767 };
2768
2769 static struct clk usim_fclk = {
2770         .name           = "usim_fclk",
2771         .ops            = &clkops_omap2_dflt,
2772         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2773         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2774         .clkdm_name     = "l4_wkup_clkdm",
2775         .parent         = &usim_ck,
2776         .recalc         = &followparent_recalc,
2777 };
2778
2779 static struct clk usim_fck = {
2780         .name           = "usim_fck",
2781         .ops            = &clkops_omap2_dflt,
2782         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2783         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2784         .clkdm_name     = "l4_wkup_clkdm",
2785         .parent         = &sys_32k_ck,
2786         .recalc         = &followparent_recalc,
2787 };
2788
2789 static struct clk wd_timer2_fck = {
2790         .name           = "wd_timer2_fck",
2791         .ops            = &clkops_omap2_dflt,
2792         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2793         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2794         .clkdm_name     = "l4_wkup_clkdm",
2795         .parent         = &sys_32k_ck,
2796         .recalc         = &followparent_recalc,
2797 };
2798
2799 static struct clk wd_timer3_fck = {
2800         .name           = "wd_timer3_fck",
2801         .ops            = &clkops_omap2_dflt,
2802         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2803         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2804         .clkdm_name     = "abe_clkdm",
2805         .parent         = &sys_32k_ck,
2806         .recalc         = &followparent_recalc,
2807 };
2808
2809 /* Remaining optional clocks */
2810 static const struct clksel stm_clk_div_div[] = {
2811         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2812         { .parent = NULL },
2813 };
2814
2815 static struct clk stm_clk_div_ck = {
2816         .name           = "stm_clk_div_ck",
2817         .parent         = &pmd_stm_clock_mux_ck,
2818         .clksel         = stm_clk_div_div,
2819         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2820         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2821         .ops            = &clkops_null,
2822         .recalc         = &omap2_clksel_recalc,
2823         .round_rate     = &omap2_clksel_round_rate,
2824         .set_rate       = &omap2_clksel_set_rate,
2825 };
2826
2827 static const struct clksel trace_clk_div_div[] = {
2828         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2829         { .parent = NULL },
2830 };
2831
2832 static struct clk trace_clk_div_ck = {
2833         .name           = "trace_clk_div_ck",
2834         .parent         = &pmd_trace_clk_mux_ck,
2835         .clksel         = trace_clk_div_div,
2836         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2837         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2838         .ops            = &clkops_null,
2839         .recalc         = &omap2_clksel_recalc,
2840         .round_rate     = &omap2_clksel_round_rate,
2841         .set_rate       = &omap2_clksel_set_rate,
2842 };
2843
2844 /* SCRM aux clk nodes */
2845
2846 static const struct clksel auxclk_sel[] = {
2847         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2848         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2849         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2850         { .parent = NULL },
2851 };
2852
2853 static struct clk auxclk0_ck = {
2854         .name           = "auxclk0_ck",
2855         .parent         = &sys_clkin_ck,
2856         .init           = &omap2_init_clksel_parent,
2857         .ops            = &clkops_omap2_dflt,
2858         .clksel         = auxclk_sel,
2859         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2860         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2861         .recalc         = &omap2_clksel_recalc,
2862         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2863         .enable_bit     = OMAP4_ENABLE_SHIFT,
2864 };
2865
2866 static struct clk auxclk1_ck = {
2867         .name           = "auxclk1_ck",
2868         .parent         = &sys_clkin_ck,
2869         .init           = &omap2_init_clksel_parent,
2870         .ops            = &clkops_omap2_dflt,
2871         .clksel         = auxclk_sel,
2872         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2873         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2874         .recalc         = &omap2_clksel_recalc,
2875         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2876         .enable_bit     = OMAP4_ENABLE_SHIFT,
2877 };
2878
2879 static struct clk auxclk2_ck = {
2880         .name           = "auxclk2_ck",
2881         .parent         = &sys_clkin_ck,
2882         .init           = &omap2_init_clksel_parent,
2883         .ops            = &clkops_omap2_dflt,
2884         .clksel         = auxclk_sel,
2885         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2886         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2887         .recalc         = &omap2_clksel_recalc,
2888         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2889         .enable_bit     = OMAP4_ENABLE_SHIFT,
2890 };
2891 static struct clk auxclk3_ck = {
2892         .name           = "auxclk3_ck",
2893         .parent         = &sys_clkin_ck,
2894         .init           = &omap2_init_clksel_parent,
2895         .ops            = &clkops_omap2_dflt,
2896         .clksel         = auxclk_sel,
2897         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2898         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2899         .recalc         = &omap2_clksel_recalc,
2900         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2901         .enable_bit     = OMAP4_ENABLE_SHIFT,
2902 };
2903
2904 static struct clk auxclk4_ck = {
2905         .name           = "auxclk4_ck",
2906         .parent         = &sys_clkin_ck,
2907         .init           = &omap2_init_clksel_parent,
2908         .ops            = &clkops_omap2_dflt,
2909         .clksel         = auxclk_sel,
2910         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2911         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2912         .recalc         = &omap2_clksel_recalc,
2913         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2914         .enable_bit     = OMAP4_ENABLE_SHIFT,
2915 };
2916
2917 static struct clk auxclk5_ck = {
2918         .name           = "auxclk5_ck",
2919         .parent         = &sys_clkin_ck,
2920         .init           = &omap2_init_clksel_parent,
2921         .ops            = &clkops_omap2_dflt,
2922         .clksel         = auxclk_sel,
2923         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2924         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2925         .recalc         = &omap2_clksel_recalc,
2926         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2927         .enable_bit     = OMAP4_ENABLE_SHIFT,
2928 };
2929
2930 static const struct clksel auxclkreq_sel[] = {
2931         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2932         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2933         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2934         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2935         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2936         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2937         { .parent = NULL },
2938 };
2939
2940 static struct clk auxclkreq0_ck = {
2941         .name           = "auxclkreq0_ck",
2942         .parent         = &auxclk0_ck,
2943         .init           = &omap2_init_clksel_parent,
2944         .ops            = &clkops_null,
2945         .clksel         = auxclkreq_sel,
2946         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2947         .clksel_mask    = OMAP4_MAPPING_MASK,
2948         .recalc         = &omap2_clksel_recalc,
2949 };
2950
2951 static struct clk auxclkreq1_ck = {
2952         .name           = "auxclkreq1_ck",
2953         .parent         = &auxclk1_ck,
2954         .init           = &omap2_init_clksel_parent,
2955         .ops            = &clkops_null,
2956         .clksel         = auxclkreq_sel,
2957         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2958         .clksel_mask    = OMAP4_MAPPING_MASK,
2959         .recalc         = &omap2_clksel_recalc,
2960 };
2961
2962 static struct clk auxclkreq2_ck = {
2963         .name           = "auxclkreq2_ck",
2964         .parent         = &auxclk2_ck,
2965         .init           = &omap2_init_clksel_parent,
2966         .ops            = &clkops_null,
2967         .clksel         = auxclkreq_sel,
2968         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2969         .clksel_mask    = OMAP4_MAPPING_MASK,
2970         .recalc         = &omap2_clksel_recalc,
2971 };
2972
2973 static struct clk auxclkreq3_ck = {
2974         .name           = "auxclkreq3_ck",
2975         .parent         = &auxclk3_ck,
2976         .init           = &omap2_init_clksel_parent,
2977         .ops            = &clkops_null,
2978         .clksel         = auxclkreq_sel,
2979         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2980         .clksel_mask    = OMAP4_MAPPING_MASK,
2981         .recalc         = &omap2_clksel_recalc,
2982 };
2983
2984 static struct clk auxclkreq4_ck = {
2985         .name           = "auxclkreq4_ck",
2986         .parent         = &auxclk4_ck,
2987         .init           = &omap2_init_clksel_parent,
2988         .ops            = &clkops_null,
2989         .clksel         = auxclkreq_sel,
2990         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2991         .clksel_mask    = OMAP4_MAPPING_MASK,
2992         .recalc         = &omap2_clksel_recalc,
2993 };
2994
2995 static struct clk auxclkreq5_ck = {
2996         .name           = "auxclkreq5_ck",
2997         .parent         = &auxclk5_ck,
2998         .init           = &omap2_init_clksel_parent,
2999         .ops            = &clkops_null,
3000         .clksel         = auxclkreq_sel,
3001         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
3002         .clksel_mask    = OMAP4_MAPPING_MASK,
3003         .recalc         = &omap2_clksel_recalc,
3004 };
3005
3006 /*
3007  * clkdev
3008  */
3009
3010 static struct omap_clk omap44xx_clks[] = {
3011         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3012         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3013         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3014         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3015         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3016         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3017         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3018         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3019         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3020         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3021         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3022         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3023         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3024         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3025         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3026         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3027         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3028         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3029         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3030         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3031         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3032         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3033         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3034         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3035         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3036         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3037         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3038         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3039         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3040         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3041         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3042         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3043         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3044         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3045         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3046         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3047         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3048         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3049         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3050         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3051         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3052         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3053         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3054         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3055         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3056         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3057         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3058         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3059         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3060         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3061         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3062         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3063         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3064         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3065         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3066         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3067         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3068         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3069         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3070         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3071         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3072         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3073         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
3074         CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
3075         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
3076         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3077         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3078         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3079         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3080         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3081         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3082         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3083         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3084         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3085         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3086         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3087         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3088         CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
3089         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3090         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3091         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3092         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3093         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3094         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3095         CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
3096         CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
3097         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3098         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3099         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3100         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3101         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3102         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3103         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3104         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3105         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3106         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3107         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3108         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3109         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3110         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
3111         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
3112         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
3113         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
3114         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
3115         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3116         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3117         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3118         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3119         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3120         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3121         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3122         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3123         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3124         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3125         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3126         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3127         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3128         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3129         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3130         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3131         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3132         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3133         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3134         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
3135         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3136         CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
3137         CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
3138         CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
3139         CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
3140         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3141         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3142         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3143         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3144         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3145         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3146         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3147         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3148         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3149         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3150         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
3151         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3152         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
3153         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3154         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
3155         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3156         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
3157         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3158         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
3159         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
3160         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
3161         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
3162         CLK("mmci-omap-hs.0",   "fck",                          &mmc1_fck,      CK_443X),
3163         CLK("mmci-omap-hs.1",   "fck",                          &mmc2_fck,      CK_443X),
3164         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
3165         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
3166         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
3167         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3168         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3169         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3170         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3171         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3172         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3173         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3174         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3175         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3176         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3177         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3178         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3179         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3180         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3181         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3182         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3183         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3184         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3185         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3186         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3187         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3188         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3189         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3190         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3191         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3192         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3193         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3194         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3195         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3196         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3197         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3198         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3199         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3200         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
3201         CLK("ehci-omap.0",      "fs_fck",               &usb_host_fs_fck,       CK_443X),
3202         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3203         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3204         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3205         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3206         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3207         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3208         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3209         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3210         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3211         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3212         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
3213         CLK("ehci-omap.0",      "hs_fck",               &usb_host_hs_fck,       CK_443X),
3214         CLK("ehci-omap.0",      "usbhost_ick",          &dummy_ck,              CK_443X),
3215         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3216         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3217         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
3218         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3219         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3220         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3221         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3222         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
3223         CLK("ehci-omap.0",      "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
3224         CLK("ehci-omap.0",      "usbtll_fck",           &dummy_ck,      CK_443X),
3225         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3226         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3227         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3228         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
3229         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3230         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3231         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3232         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3233         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3234         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
3235         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
3236         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
3237         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
3238         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
3239         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
3240         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
3241         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
3242         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
3243         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
3244         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
3245         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3246         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3247         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3248         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3249         CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
3250         CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
3251         CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
3252         CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
3253         CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
3254         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3255         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3256         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3257         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3258         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3259         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3260         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3261         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3262         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3263         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3264         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3265         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3266         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3267         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3268         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3269         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3270         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3271         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3272         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3273         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3274         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3275         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3276         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3277         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3278         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3279 };
3280
3281 int __init omap4xxx_clk_init(void)
3282 {
3283         struct omap_clk *c;
3284         u32 cpu_clkflg;
3285
3286         if (cpu_is_omap44xx()) {
3287                 cpu_mask = RATE_IN_4430;
3288                 cpu_clkflg = CK_443X;
3289         }
3290
3291         clk_init(&omap2_clk_functions);
3292
3293         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3294                                                                           c++)
3295                 clk_preinit(c->lk.clk);
3296
3297         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3298                                                                           c++)
3299                 if (c->cpu & cpu_clkflg) {
3300                         clkdev_add(&c->lk);
3301                         clk_register(c->lk.clk);
3302                         omap2_init_clk_clkdm(c->lk.clk);
3303                 }
3304
3305         recalculate_root_clocks();
3306
3307         /*
3308          * Only enable those clocks we will need, let the drivers
3309          * enable other clocks as necessary
3310          */
3311         clk_enable_init_clocks();
3312
3313         return 0;
3314 }