arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39 #include "scrm44xx.h"
  40
  41 /* OMAP4 modulemode control */
  42 #define OMAP4430_MODULEMODE_HWCTRL                      0
  43 #define OMAP4430_MODULEMODE_SWCTRL                      1
  44
  45 /* Root clocks */
  46
  47 static struct clk extalt_clkin_ck = {
  48         .name           = "extalt_clkin_ck",
  49         .rate           = 59000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_clks_ck = {
  54         .name           = "pad_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_omap2_dflt,
  57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  59 };
  60
  61 static struct clk pad_slimbus_core_clks_ck = {
  62         .name           = "pad_slimbus_core_clks_ck",
  63         .rate           = 12000000,
  64         .ops            = &clkops_null,
  65 };
  66
  67 static struct clk secure_32k_clk_src_ck = {
  68         .name           = "secure_32k_clk_src_ck",
  69         .rate           = 32768,
  70         .ops            = &clkops_null,
  71 };
  72
  73 static struct clk slimbus_clk = {
  74         .name           = "slimbus_clk",
  75         .rate           = 12000000,
  76         .ops            = &clkops_omap2_dflt,
  77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79 };
  80
  81 static struct clk sys_32k_ck = {
  82         .name           = "sys_32k_ck",
  83         .rate           = 32768,
  84         .ops            = &clkops_null,
  85 };
  86
  87 static struct clk virt_12000000_ck = {
  88         .name           = "virt_12000000_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 12000000,
  91 };
  92
  93 static struct clk virt_13000000_ck = {
  94         .name           = "virt_13000000_ck",
  95         .ops            = &clkops_null,
  96         .rate           = 13000000,
  97 };
  98
  99 static struct clk virt_16800000_ck = {
 100         .name           = "virt_16800000_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 16800000,
 103 };
 104
 105 static struct clk virt_19200000_ck = {
 106         .name           = "virt_19200000_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 19200000,
 109 };
 110
 111 static struct clk virt_26000000_ck = {
 112         .name           = "virt_26000000_ck",
 113         .ops            = &clkops_null,
 114         .rate           = 26000000,
 115 };
 116
 117 static struct clk virt_27000000_ck = {
 118         .name           = "virt_27000000_ck",
 119         .ops            = &clkops_null,
 120         .rate           = 27000000,
 121 };
 122
 123 static struct clk virt_38400000_ck = {
 124         .name           = "virt_38400000_ck",
 125         .ops            = &clkops_null,
 126         .rate           = 38400000,
 127 };
 128
 129 static const struct clksel_rate div_1_0_rates[] = {
 130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_1_rates[] = {
 135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_2_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_3_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_4_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_5_rates[] = {
 155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel_rate div_1_6_rates[] = {
 160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161         { .div = 0 },
 162 };
 163
 164 static const struct clksel_rate div_1_7_rates[] = {
 165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel sys_clkin_sel[] = {
 170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk sys_clkin_ck = {
 181         .name           = "sys_clkin_ck",
 182         .rate           = 38400000,
 183         .clksel         = sys_clkin_sel,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 187         .ops            = &clkops_null,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk tie_low_clock_ck = {
 192         .name           = "tie_low_clock_ck",
 193         .rate           = 0,
 194         .ops            = &clkops_null,
 195 };
 196
 197 static struct clk utmi_phy_clkout_ck = {
 198         .name           = "utmi_phy_clkout_ck",
 199         .rate           = 60000000,
 200         .ops            = &clkops_null,
 201 };
 202
 203 static struct clk xclk60mhsp1_ck = {
 204         .name           = "xclk60mhsp1_ck",
 205         .rate           = 60000000,
 206         .ops            = &clkops_null,
 207 };
 208
 209 static struct clk xclk60mhsp2_ck = {
 210         .name           = "xclk60mhsp2_ck",
 211         .rate           = 60000000,
 212         .ops            = &clkops_null,
 213 };
 214
 215 static struct clk xclk60motg_ck = {
 216         .name           = "xclk60motg_ck",
 217         .rate           = 60000000,
 218         .ops            = &clkops_null,
 219 };
 220
 221 /* Module clocks and DPLL outputs */
 222
 223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226         { .parent = NULL },
 227 };
 228
 229 static struct clk abe_dpll_bypass_clk_mux_ck = {
 230         .name           = "abe_dpll_bypass_clk_mux_ck",
 231         .parent         = &sys_clkin_ck,
 232         .ops            = &clkops_null,
 233         .recalc         = &followparent_recalc,
 234 };
 235
 236 static struct clk abe_dpll_refclk_mux_ck = {
 237         .name           = "abe_dpll_refclk_mux_ck",
 238         .parent         = &sys_clkin_ck,
 239         .clksel         = abe_dpll_bypass_clk_mux_sel,
 240         .init           = &omap2_init_clksel_parent,
 241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 243         .ops            = &clkops_null,
 244         .recalc         = &omap2_clksel_recalc,
 245 };
 246
 247 /* DPLL_ABE */
 248 static struct dpll_data dpll_abe_dd = {
 249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 251         .clk_ref        = &abe_dpll_refclk_mux_ck,
 252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 261         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 262         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 263         .min_divider    = 1,
 264 };
 265
 266
 267 static struct clk dpll_abe_ck = {
 268         .name           = "dpll_abe_ck",
 269         .parent         = &abe_dpll_refclk_mux_ck,
 270         .dpll_data      = &dpll_abe_dd,
 271         .init           = &omap2_init_dpll_parent,
 272         .ops            = &clkops_omap3_noncore_dpll_ops,
 273         .recalc         = &omap3_dpll_recalc,
 274         .round_rate     = &omap2_dpll_round_rate,
 275         .set_rate       = &omap3_noncore_dpll_set_rate,
 276 };
 277
 278 static struct clk dpll_abe_x2_ck = {
 279         .name           = "dpll_abe_x2_ck",
 280         .parent         = &dpll_abe_ck,
 281         .ops            = &clkops_null,
 282         .recalc         = &omap3_clkoutx2_recalc,
 283 };
 284
 285 static const struct clksel_rate div31_1to31_rates[] = {
 286         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 287         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 288         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 289         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 290         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 291         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 292         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 293         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 294         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 295         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 296         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 297         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 298         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 299         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 300         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 301         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 302         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 303         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 304         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 305         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 306         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 307         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 308         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 309         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 310         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 311         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 312         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 313         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 314         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 315         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 316         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 317         { .div = 0 },
 318 };
 319
 320 static const struct clksel dpll_abe_m2x2_div[] = {
 321         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 322         { .parent = NULL },
 323 };
 324
 325 static struct clk dpll_abe_m2x2_ck = {
 326         .name           = "dpll_abe_m2x2_ck",
 327         .parent         = &dpll_abe_x2_ck,
 328         .clksel         = dpll_abe_m2x2_div,
 329         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 330         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 331         .ops            = &clkops_null,
 332         .recalc         = &omap2_clksel_recalc,
 333         .round_rate     = &omap2_clksel_round_rate,
 334         .set_rate       = &omap2_clksel_set_rate,
 335 };
 336
 337 static struct clk abe_24m_fclk = {
 338         .name           = "abe_24m_fclk",
 339         .parent         = &dpll_abe_m2x2_ck,
 340         .ops            = &clkops_null,
 341         .fixed_div      = 8,
 342         .recalc         = &omap_fixed_divisor_recalc,
 343 };
 344
 345 static const struct clksel_rate div3_1to4_rates[] = {
 346         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 347         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 348         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 349         { .div = 0 },
 350 };
 351
 352 static const struct clksel abe_clk_div[] = {
 353         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 354         { .parent = NULL },
 355 };
 356
 357 static struct clk abe_clk = {
 358         .name           = "abe_clk",
 359         .parent         = &dpll_abe_m2x2_ck,
 360         .clksel         = abe_clk_div,
 361         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 362         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 363         .ops            = &clkops_null,
 364         .recalc         = &omap2_clksel_recalc,
 365         .round_rate     = &omap2_clksel_round_rate,
 366         .set_rate       = &omap2_clksel_set_rate,
 367 };
 368
 369 static const struct clksel_rate div2_1to2_rates[] = {
 370         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 371         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 372         { .div = 0 },
 373 };
 374
 375 static const struct clksel aess_fclk_div[] = {
 376         { .parent = &abe_clk, .rates = div2_1to2_rates },
 377         { .parent = NULL },
 378 };
 379
 380 static struct clk aess_fclk = {
 381         .name           = "aess_fclk",
 382         .parent         = &abe_clk,
 383         .clksel         = aess_fclk_div,
 384         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 385         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 386         .ops            = &clkops_null,
 387         .recalc         = &omap2_clksel_recalc,
 388         .round_rate     = &omap2_clksel_round_rate,
 389         .set_rate       = &omap2_clksel_set_rate,
 390 };
 391
 392 static struct clk dpll_abe_m3x2_ck = {
 393         .name           = "dpll_abe_m3x2_ck",
 394         .parent         = &dpll_abe_x2_ck,
 395         .clksel         = dpll_abe_m2x2_div,
 396         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 397         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 398         .ops            = &clkops_null,
 399         .recalc         = &omap2_clksel_recalc,
 400         .round_rate     = &omap2_clksel_round_rate,
 401         .set_rate       = &omap2_clksel_set_rate,
 402 };
 403
 404 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 405         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 406         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 407         { .parent = NULL },
 408 };
 409
 410 static struct clk core_hsd_byp_clk_mux_ck = {
 411         .name           = "core_hsd_byp_clk_mux_ck",
 412         .parent         = &sys_clkin_ck,
 413         .clksel         = core_hsd_byp_clk_mux_sel,
 414         .init           = &omap2_init_clksel_parent,
 415         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 416         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 417         .ops            = &clkops_null,
 418         .recalc         = &omap2_clksel_recalc,
 419 };
 420
 421 /* DPLL_CORE */
 422 static struct dpll_data dpll_core_dd = {
 423         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 424         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 425         .clk_ref        = &sys_clkin_ck,
 426         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 427         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 428         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 429         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 430         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 431         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 432         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 433         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 434         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 435         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 436         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 437         .min_divider    = 1,
 438 };
 439
 440
 441 static struct clk dpll_core_ck = {
 442         .name           = "dpll_core_ck",
 443         .parent         = &sys_clkin_ck,
 444         .dpll_data      = &dpll_core_dd,
 445         .init           = &omap2_init_dpll_parent,
 446         .ops            = &clkops_null,
 447         .recalc         = &omap3_dpll_recalc,
 448 };
 449
 450 static struct clk dpll_core_x2_ck = {
 451         .name           = "dpll_core_x2_ck",
 452         .parent         = &dpll_core_ck,
 453         .ops            = &clkops_null,
 454         .recalc         = &omap3_clkoutx2_recalc,
 455 };
 456
 457 static const struct clksel dpll_core_m6x2_div[] = {
 458         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 459         { .parent = NULL },
 460 };
 461
 462 static struct clk dpll_core_m6x2_ck = {
 463         .name           = "dpll_core_m6x2_ck",
 464         .parent         = &dpll_core_x2_ck,
 465         .clksel         = dpll_core_m6x2_div,
 466         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 467         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 468         .ops            = &clkops_null,
 469         .recalc         = &omap2_clksel_recalc,
 470         .round_rate     = &omap2_clksel_round_rate,
 471         .set_rate       = &omap2_clksel_set_rate,
 472 };
 473
 474 static const struct clksel dbgclk_mux_sel[] = {
 475         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 476         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 477         { .parent = NULL },
 478 };
 479
 480 static struct clk dbgclk_mux_ck = {
 481         .name           = "dbgclk_mux_ck",
 482         .parent         = &sys_clkin_ck,
 483         .ops            = &clkops_null,
 484         .recalc         = &followparent_recalc,
 485 };
 486
 487 static const struct clksel dpll_core_m2_div[] = {
 488         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 489         { .parent = NULL },
 490 };
 491
 492 static struct clk dpll_core_m2_ck = {
 493         .name           = "dpll_core_m2_ck",
 494         .parent         = &dpll_core_ck,
 495         .clksel         = dpll_core_m2_div,
 496         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 497         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 498         .ops            = &clkops_null,
 499         .recalc         = &omap2_clksel_recalc,
 500         .round_rate     = &omap2_clksel_round_rate,
 501         .set_rate       = &omap2_clksel_set_rate,
 502 };
 503
 504 static struct clk ddrphy_ck = {
 505         .name           = "ddrphy_ck",
 506         .parent         = &dpll_core_m2_ck,
 507         .ops            = &clkops_null,
 508         .fixed_div      = 2,
 509         .recalc         = &omap_fixed_divisor_recalc,
 510 };
 511
 512 static struct clk dpll_core_m5x2_ck = {
 513         .name           = "dpll_core_m5x2_ck",
 514         .parent         = &dpll_core_x2_ck,
 515         .clksel         = dpll_core_m6x2_div,
 516         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 517         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 518         .ops            = &clkops_null,
 519         .recalc         = &omap2_clksel_recalc,
 520         .round_rate     = &omap2_clksel_round_rate,
 521         .set_rate       = &omap2_clksel_set_rate,
 522 };
 523
 524 static const struct clksel div_core_div[] = {
 525         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 526         { .parent = NULL },
 527 };
 528
 529 static struct clk div_core_ck = {
 530         .name           = "div_core_ck",
 531         .parent         = &dpll_core_m5x2_ck,
 532         .clksel         = div_core_div,
 533         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 534         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 535         .ops            = &clkops_null,
 536         .recalc         = &omap2_clksel_recalc,
 537         .round_rate     = &omap2_clksel_round_rate,
 538         .set_rate       = &omap2_clksel_set_rate,
 539 };
 540
 541 static const struct clksel_rate div4_1to8_rates[] = {
 542         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 543         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 544         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 545         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 546         { .div = 0 },
 547 };
 548
 549 static const struct clksel div_iva_hs_clk_div[] = {
 550         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 551         { .parent = NULL },
 552 };
 553
 554 static struct clk div_iva_hs_clk = {
 555         .name           = "div_iva_hs_clk",
 556         .parent         = &dpll_core_m5x2_ck,
 557         .clksel         = div_iva_hs_clk_div,
 558         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 559         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 560         .ops            = &clkops_null,
 561         .recalc         = &omap2_clksel_recalc,
 562         .round_rate     = &omap2_clksel_round_rate,
 563         .set_rate       = &omap2_clksel_set_rate,
 564 };
 565
 566 static struct clk div_mpu_hs_clk = {
 567         .name           = "div_mpu_hs_clk",
 568         .parent         = &dpll_core_m5x2_ck,
 569         .clksel         = div_iva_hs_clk_div,
 570         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 571         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 572         .ops            = &clkops_null,
 573         .recalc         = &omap2_clksel_recalc,
 574         .round_rate     = &omap2_clksel_round_rate,
 575         .set_rate       = &omap2_clksel_set_rate,
 576 };
 577
 578 static struct clk dpll_core_m4x2_ck = {
 579         .name           = "dpll_core_m4x2_ck",
 580         .parent         = &dpll_core_x2_ck,
 581         .clksel         = dpll_core_m6x2_div,
 582         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 583         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 584         .ops            = &clkops_null,
 585         .recalc         = &omap2_clksel_recalc,
 586         .round_rate     = &omap2_clksel_round_rate,
 587         .set_rate       = &omap2_clksel_set_rate,
 588 };
 589
 590 static struct clk dll_clk_div_ck = {
 591         .name           = "dll_clk_div_ck",
 592         .parent         = &dpll_core_m4x2_ck,
 593         .ops            = &clkops_null,
 594         .fixed_div      = 2,
 595         .recalc         = &omap_fixed_divisor_recalc,
 596 };
 597
 598 static const struct clksel dpll_abe_m2_div[] = {
 599         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 600         { .parent = NULL },
 601 };
 602
 603 static struct clk dpll_abe_m2_ck = {
 604         .name           = "dpll_abe_m2_ck",
 605         .parent         = &dpll_abe_ck,
 606         .clksel         = dpll_abe_m2_div,
 607         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 608         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 609         .ops            = &clkops_null,
 610         .recalc         = &omap2_clksel_recalc,
 611         .round_rate     = &omap2_clksel_round_rate,
 612         .set_rate       = &omap2_clksel_set_rate,
 613 };
 614
 615 static struct clk dpll_core_m3x2_ck = {
 616         .name           = "dpll_core_m3x2_ck",
 617         .parent         = &dpll_core_x2_ck,
 618         .clksel         = dpll_core_m6x2_div,
 619         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 620         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 621         .ops            = &clkops_omap2_dflt,
 622         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 623         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 624         .recalc         = &omap2_clksel_recalc,
 625         .round_rate     = &omap2_clksel_round_rate,
 626         .set_rate       = &omap2_clksel_set_rate,
 627 };
 628
 629 static struct clk dpll_core_m7x2_ck = {
 630         .name           = "dpll_core_m7x2_ck",
 631         .parent         = &dpll_core_x2_ck,
 632         .clksel         = dpll_core_m6x2_div,
 633         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 634         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 635         .ops            = &clkops_null,
 636         .recalc         = &omap2_clksel_recalc,
 637         .round_rate     = &omap2_clksel_round_rate,
 638         .set_rate       = &omap2_clksel_set_rate,
 639 };
 640
 641 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 642         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 643         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 644         { .parent = NULL },
 645 };
 646
 647 static struct clk iva_hsd_byp_clk_mux_ck = {
 648         .name           = "iva_hsd_byp_clk_mux_ck",
 649         .parent         = &sys_clkin_ck,
 650         .clksel         = iva_hsd_byp_clk_mux_sel,
 651         .init           = &omap2_init_clksel_parent,
 652         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 653         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 654         .ops            = &clkops_null,
 655         .recalc         = &omap2_clksel_recalc,
 656 };
 657
 658 /* DPLL_IVA */
 659 static struct dpll_data dpll_iva_dd = {
 660         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 661         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 662         .clk_ref        = &sys_clkin_ck,
 663         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 664         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 665         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 666         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 667         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 668         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 669         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 670         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 671         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 672         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 673         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 674         .min_divider    = 1,
 675 };
 676
 677
 678 static struct clk dpll_iva_ck = {
 679         .name           = "dpll_iva_ck",
 680         .parent         = &sys_clkin_ck,
 681         .dpll_data      = &dpll_iva_dd,
 682         .init           = &omap2_init_dpll_parent,
 683         .ops            = &clkops_omap3_noncore_dpll_ops,
 684         .recalc         = &omap3_dpll_recalc,
 685         .round_rate     = &omap2_dpll_round_rate,
 686         .set_rate       = &omap3_noncore_dpll_set_rate,
 687 };
 688
 689 static struct clk dpll_iva_x2_ck = {
 690         .name           = "dpll_iva_x2_ck",
 691         .parent         = &dpll_iva_ck,
 692         .ops            = &clkops_null,
 693         .recalc         = &omap3_clkoutx2_recalc,
 694 };
 695
 696 static const struct clksel dpll_iva_m4x2_div[] = {
 697         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 698         { .parent = NULL },
 699 };
 700
 701 static struct clk dpll_iva_m4x2_ck = {
 702         .name           = "dpll_iva_m4x2_ck",
 703         .parent         = &dpll_iva_x2_ck,
 704         .clksel         = dpll_iva_m4x2_div,
 705         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 706         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 707         .ops            = &clkops_null,
 708         .recalc         = &omap2_clksel_recalc,
 709         .round_rate     = &omap2_clksel_round_rate,
 710         .set_rate       = &omap2_clksel_set_rate,
 711 };
 712
 713 static struct clk dpll_iva_m5x2_ck = {
 714         .name           = "dpll_iva_m5x2_ck",
 715         .parent         = &dpll_iva_x2_ck,
 716         .clksel         = dpll_iva_m4x2_div,
 717         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 718         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 719         .ops            = &clkops_null,
 720         .recalc         = &omap2_clksel_recalc,
 721         .round_rate     = &omap2_clksel_round_rate,
 722         .set_rate       = &omap2_clksel_set_rate,
 723 };
 724
 725 /* DPLL_MPU */
 726 static struct dpll_data dpll_mpu_dd = {
 727         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 728         .clk_bypass     = &div_mpu_hs_clk,
 729         .clk_ref        = &sys_clkin_ck,
 730         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 731         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 732         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 733         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 734         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 735         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 736         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 737         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 738         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 739         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 740         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 741         .min_divider    = 1,
 742 };
 743
 744
 745 static struct clk dpll_mpu_ck = {
 746         .name           = "dpll_mpu_ck",
 747         .parent         = &sys_clkin_ck,
 748         .dpll_data      = &dpll_mpu_dd,
 749         .init           = &omap2_init_dpll_parent,
 750         .ops            = &clkops_omap3_noncore_dpll_ops,
 751         .recalc         = &omap3_dpll_recalc,
 752         .round_rate     = &omap2_dpll_round_rate,
 753         .set_rate       = &omap3_noncore_dpll_set_rate,
 754 };
 755
 756 static const struct clksel dpll_mpu_m2_div[] = {
 757         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 758         { .parent = NULL },
 759 };
 760
 761 static struct clk dpll_mpu_m2_ck = {
 762         .name           = "dpll_mpu_m2_ck",
 763         .parent         = &dpll_mpu_ck,
 764         .clksel         = dpll_mpu_m2_div,
 765         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 766         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 767         .ops            = &clkops_null,
 768         .recalc         = &omap2_clksel_recalc,
 769         .round_rate     = &omap2_clksel_round_rate,
 770         .set_rate       = &omap2_clksel_set_rate,
 771 };
 772
 773 static struct clk per_hs_clk_div_ck = {
 774         .name           = "per_hs_clk_div_ck",
 775         .parent         = &dpll_abe_m3x2_ck,
 776         .ops            = &clkops_null,
 777         .fixed_div      = 2,
 778         .recalc         = &omap_fixed_divisor_recalc,
 779 };
 780
 781 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 782         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 783         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 784         { .parent = NULL },
 785 };
 786
 787 static struct clk per_hsd_byp_clk_mux_ck = {
 788         .name           = "per_hsd_byp_clk_mux_ck",
 789         .parent         = &sys_clkin_ck,
 790         .clksel         = per_hsd_byp_clk_mux_sel,
 791         .init           = &omap2_init_clksel_parent,
 792         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 793         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 794         .ops            = &clkops_null,
 795         .recalc         = &omap2_clksel_recalc,
 796 };
 797
 798 /* DPLL_PER */
 799 static struct dpll_data dpll_per_dd = {
 800         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 801         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 802         .clk_ref        = &sys_clkin_ck,
 803         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 804         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 805         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 806         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 807         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 808         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 809         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 810         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 811         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 812         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 813         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 814         .min_divider    = 1,
 815 };
 816
 817
 818 static struct clk dpll_per_ck = {
 819         .name           = "dpll_per_ck",
 820         .parent         = &sys_clkin_ck,
 821         .dpll_data      = &dpll_per_dd,
 822         .init           = &omap2_init_dpll_parent,
 823         .ops            = &clkops_omap3_noncore_dpll_ops,
 824         .recalc         = &omap3_dpll_recalc,
 825         .round_rate     = &omap2_dpll_round_rate,
 826         .set_rate       = &omap3_noncore_dpll_set_rate,
 827 };
 828
 829 static const struct clksel dpll_per_m2_div[] = {
 830         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 831         { .parent = NULL },
 832 };
 833
 834 static struct clk dpll_per_m2_ck = {
 835         .name           = "dpll_per_m2_ck",
 836         .parent         = &dpll_per_ck,
 837         .clksel         = dpll_per_m2_div,
 838         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 839         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 840         .ops            = &clkops_null,
 841         .recalc         = &omap2_clksel_recalc,
 842         .round_rate     = &omap2_clksel_round_rate,
 843         .set_rate       = &omap2_clksel_set_rate,
 844 };
 845
 846 static struct clk dpll_per_x2_ck = {
 847         .name           = "dpll_per_x2_ck",
 848         .parent         = &dpll_per_ck,
 849         .ops            = &clkops_null,
 850         .recalc         = &omap3_clkoutx2_recalc,
 851 };
 852
 853 static const struct clksel dpll_per_m2x2_div[] = {
 854         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 855         { .parent = NULL },
 856 };
 857
 858 static struct clk dpll_per_m2x2_ck = {
 859         .name           = "dpll_per_m2x2_ck",
 860         .parent         = &dpll_per_x2_ck,
 861         .clksel         = dpll_per_m2x2_div,
 862         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 863         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 864         .ops            = &clkops_null,
 865         .recalc         = &omap2_clksel_recalc,
 866         .round_rate     = &omap2_clksel_round_rate,
 867         .set_rate       = &omap2_clksel_set_rate,
 868 };
 869
 870 static struct clk dpll_per_m3x2_ck = {
 871         .name           = "dpll_per_m3x2_ck",
 872         .parent         = &dpll_per_x2_ck,
 873         .clksel         = dpll_per_m2x2_div,
 874         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 875         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 876         .ops            = &clkops_omap2_dflt,
 877         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 878         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 879         .recalc         = &omap2_clksel_recalc,
 880         .round_rate     = &omap2_clksel_round_rate,
 881         .set_rate       = &omap2_clksel_set_rate,
 882 };
 883
 884 static struct clk dpll_per_m4x2_ck = {
 885         .name           = "dpll_per_m4x2_ck",
 886         .parent         = &dpll_per_x2_ck,
 887         .clksel         = dpll_per_m2x2_div,
 888         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 889         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 890         .ops            = &clkops_null,
 891         .recalc         = &omap2_clksel_recalc,
 892         .round_rate     = &omap2_clksel_round_rate,
 893         .set_rate       = &omap2_clksel_set_rate,
 894 };
 895
 896 static struct clk dpll_per_m5x2_ck = {
 897         .name           = "dpll_per_m5x2_ck",
 898         .parent         = &dpll_per_x2_ck,
 899         .clksel         = dpll_per_m2x2_div,
 900         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 901         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 902         .ops            = &clkops_null,
 903         .recalc         = &omap2_clksel_recalc,
 904         .round_rate     = &omap2_clksel_round_rate,
 905         .set_rate       = &omap2_clksel_set_rate,
 906 };
 907
 908 static struct clk dpll_per_m6x2_ck = {
 909         .name           = "dpll_per_m6x2_ck",
 910         .parent         = &dpll_per_x2_ck,
 911         .clksel         = dpll_per_m2x2_div,
 912         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 913         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 914         .ops            = &clkops_null,
 915         .recalc         = &omap2_clksel_recalc,
 916         .round_rate     = &omap2_clksel_round_rate,
 917         .set_rate       = &omap2_clksel_set_rate,
 918 };
 919
 920 static struct clk dpll_per_m7x2_ck = {
 921         .name           = "dpll_per_m7x2_ck",
 922         .parent         = &dpll_per_x2_ck,
 923         .clksel         = dpll_per_m2x2_div,
 924         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 925         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 926         .ops            = &clkops_null,
 927         .recalc         = &omap2_clksel_recalc,
 928         .round_rate     = &omap2_clksel_round_rate,
 929         .set_rate       = &omap2_clksel_set_rate,
 930 };
 931
 932 /* DPLL_UNIPRO */
 933 static struct dpll_data dpll_unipro_dd = {
 934         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
 935         .clk_bypass     = &sys_clkin_ck,
 936         .clk_ref        = &sys_clkin_ck,
 937         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
 938         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 939         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
 940         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
 941         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 942         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 943         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 944         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 945         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 946         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 947         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
 948         .max_divider    = OMAP4430_MAX_DPLL_DIV,
 949         .min_divider    = 1,
 950 };
 951
 952
 953 static struct clk dpll_unipro_ck = {
 954         .name           = "dpll_unipro_ck",
 955         .parent         = &sys_clkin_ck,
 956         .dpll_data      = &dpll_unipro_dd,
 957         .init           = &omap2_init_dpll_parent,
 958         .ops            = &clkops_omap3_noncore_dpll_ops,
 959         .recalc         = &omap3_dpll_recalc,
 960         .round_rate     = &omap2_dpll_round_rate,
 961         .set_rate       = &omap3_noncore_dpll_set_rate,
 962 };
 963
 964 static struct clk dpll_unipro_x2_ck = {
 965         .name           = "dpll_unipro_x2_ck",
 966         .parent         = &dpll_unipro_ck,
 967         .ops            = &clkops_null,
 968         .recalc         = &omap3_clkoutx2_recalc,
 969 };
 970
 971 static const struct clksel dpll_unipro_m2x2_div[] = {
 972         { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
 973         { .parent = NULL },
 974 };
 975
 976 static struct clk dpll_unipro_m2x2_ck = {
 977         .name           = "dpll_unipro_m2x2_ck",
 978         .parent         = &dpll_unipro_x2_ck,
 979         .clksel         = dpll_unipro_m2x2_div,
 980         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 981         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 982         .ops            = &clkops_null,
 983         .recalc         = &omap2_clksel_recalc,
 984         .round_rate     = &omap2_clksel_round_rate,
 985         .set_rate       = &omap2_clksel_set_rate,
 986 };
 987
 988 static struct clk usb_hs_clk_div_ck = {
 989         .name           = "usb_hs_clk_div_ck",
 990         .parent         = &dpll_abe_m3x2_ck,
 991         .ops            = &clkops_null,
 992         .fixed_div      = 3,
 993         .recalc         = &omap_fixed_divisor_recalc,
 994 };
 995
 996 /* DPLL_USB */
 997 static struct dpll_data dpll_usb_dd = {
 998         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 999         .clk_bypass     = &usb_hs_clk_div_ck,
1000         .flags          = DPLL_J_TYPE,
1001         .clk_ref        = &sys_clkin_ck,
1002         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
1003         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
1004         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
1005         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
1006         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
1007         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
1008         .enable_mask    = OMAP4430_DPLL_EN_MASK,
1009         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
1010         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
1011         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
1012         .max_divider    = OMAP4430_MAX_DPLL_DIV,
1013         .min_divider    = 1,
1014 };
1015
1016
1017 static struct clk dpll_usb_ck = {
1018         .name           = "dpll_usb_ck",
1019         .parent         = &sys_clkin_ck,
1020         .dpll_data      = &dpll_usb_dd,
1021         .init           = &omap2_init_dpll_parent,
1022         .ops            = &clkops_omap3_noncore_dpll_ops,
1023         .recalc         = &omap3_dpll_recalc,
1024         .round_rate     = &omap2_dpll_round_rate,
1025         .set_rate       = &omap3_noncore_dpll_set_rate,
1026 };
1027
1028 static struct clk dpll_usb_clkdcoldo_ck = {
1029         .name           = "dpll_usb_clkdcoldo_ck",
1030         .parent         = &dpll_usb_ck,
1031         .ops            = &clkops_null,
1032         .recalc         = &followparent_recalc,
1033 };
1034
1035 static const struct clksel dpll_usb_m2_div[] = {
1036         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
1037         { .parent = NULL },
1038 };
1039
1040 static struct clk dpll_usb_m2_ck = {
1041         .name           = "dpll_usb_m2_ck",
1042         .parent         = &dpll_usb_ck,
1043         .clksel         = dpll_usb_m2_div,
1044         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
1045         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1046         .ops            = &clkops_null,
1047         .recalc         = &omap2_clksel_recalc,
1048         .round_rate     = &omap2_clksel_round_rate,
1049         .set_rate       = &omap2_clksel_set_rate,
1050 };
1051
1052 static const struct clksel ducati_clk_mux_sel[] = {
1053         { .parent = &div_core_ck, .rates = div_1_0_rates },
1054         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1055         { .parent = NULL },
1056 };
1057
1058 static struct clk ducati_clk_mux_ck = {
1059         .name           = "ducati_clk_mux_ck",
1060         .parent         = &div_core_ck,
1061         .clksel         = ducati_clk_mux_sel,
1062         .init           = &omap2_init_clksel_parent,
1063         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1064         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1065         .ops            = &clkops_null,
1066         .recalc         = &omap2_clksel_recalc,
1067 };
1068
1069 static struct clk func_12m_fclk = {
1070         .name           = "func_12m_fclk",
1071         .parent         = &dpll_per_m2x2_ck,
1072         .ops            = &clkops_null,
1073         .fixed_div      = 16,
1074         .recalc         = &omap_fixed_divisor_recalc,
1075 };
1076
1077 static struct clk func_24m_clk = {
1078         .name           = "func_24m_clk",
1079         .parent         = &dpll_per_m2_ck,
1080         .ops            = &clkops_null,
1081         .fixed_div      = 4,
1082         .recalc         = &omap_fixed_divisor_recalc,
1083 };
1084
1085 static struct clk func_24mc_fclk = {
1086         .name           = "func_24mc_fclk",
1087         .parent         = &dpll_per_m2x2_ck,
1088         .ops            = &clkops_null,
1089         .fixed_div      = 8,
1090         .recalc         = &omap_fixed_divisor_recalc,
1091 };
1092
1093 static const struct clksel_rate div2_4to8_rates[] = {
1094         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1095         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1096         { .div = 0 },
1097 };
1098
1099 static const struct clksel func_48m_fclk_div[] = {
1100         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1101         { .parent = NULL },
1102 };
1103
1104 static struct clk func_48m_fclk = {
1105         .name           = "func_48m_fclk",
1106         .parent         = &dpll_per_m2x2_ck,
1107         .clksel         = func_48m_fclk_div,
1108         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1109         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1110         .ops            = &clkops_null,
1111         .recalc         = &omap2_clksel_recalc,
1112         .round_rate     = &omap2_clksel_round_rate,
1113         .set_rate       = &omap2_clksel_set_rate,
1114 };
1115
1116 static struct clk func_48mc_fclk = {
1117         .name           = "func_48mc_fclk",
1118         .parent         = &dpll_per_m2x2_ck,
1119         .ops            = &clkops_null,
1120         .fixed_div      = 4,
1121         .recalc         = &omap_fixed_divisor_recalc,
1122 };
1123
1124 static const struct clksel_rate div2_2to4_rates[] = {
1125         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1126         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1127         { .div = 0 },
1128 };
1129
1130 static const struct clksel func_64m_fclk_div[] = {
1131         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1132         { .parent = NULL },
1133 };
1134
1135 static struct clk func_64m_fclk = {
1136         .name           = "func_64m_fclk",
1137         .parent         = &dpll_per_m4x2_ck,
1138         .clksel         = func_64m_fclk_div,
1139         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1140         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1141         .ops            = &clkops_null,
1142         .recalc         = &omap2_clksel_recalc,
1143         .round_rate     = &omap2_clksel_round_rate,
1144         .set_rate       = &omap2_clksel_set_rate,
1145 };
1146
1147 static const struct clksel func_96m_fclk_div[] = {
1148         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1149         { .parent = NULL },
1150 };
1151
1152 static struct clk func_96m_fclk = {
1153         .name           = "func_96m_fclk",
1154         .parent         = &dpll_per_m2x2_ck,
1155         .clksel         = func_96m_fclk_div,
1156         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1157         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1158         .ops            = &clkops_null,
1159         .recalc         = &omap2_clksel_recalc,
1160         .round_rate     = &omap2_clksel_round_rate,
1161         .set_rate       = &omap2_clksel_set_rate,
1162 };
1163
1164 static const struct clksel hsmmc6_fclk_sel[] = {
1165         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1166         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1167         { .parent = NULL },
1168 };
1169
1170 static struct clk hsmmc6_fclk = {
1171         .name           = "hsmmc6_fclk",
1172         .parent         = &func_64m_fclk,
1173         .ops            = &clkops_null,
1174         .recalc         = &followparent_recalc,
1175 };
1176
1177 static const struct clksel_rate div2_1to8_rates[] = {
1178         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1179         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1180         { .div = 0 },
1181 };
1182
1183 static const struct clksel init_60m_fclk_div[] = {
1184         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1185         { .parent = NULL },
1186 };
1187
1188 static struct clk init_60m_fclk = {
1189         .name           = "init_60m_fclk",
1190         .parent         = &dpll_usb_m2_ck,
1191         .clksel         = init_60m_fclk_div,
1192         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1193         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1194         .ops            = &clkops_null,
1195         .recalc         = &omap2_clksel_recalc,
1196         .round_rate     = &omap2_clksel_round_rate,
1197         .set_rate       = &omap2_clksel_set_rate,
1198 };
1199
1200 static const struct clksel l3_div_div[] = {
1201         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1202         { .parent = NULL },
1203 };
1204
1205 static struct clk l3_div_ck = {
1206         .name           = "l3_div_ck",
1207         .parent         = &div_core_ck,
1208         .clksel         = l3_div_div,
1209         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1210         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1211         .ops            = &clkops_null,
1212         .recalc         = &omap2_clksel_recalc,
1213         .round_rate     = &omap2_clksel_round_rate,
1214         .set_rate       = &omap2_clksel_set_rate,
1215 };
1216
1217 static const struct clksel l4_div_div[] = {
1218         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1219         { .parent = NULL },
1220 };
1221
1222 static struct clk l4_div_ck = {
1223         .name           = "l4_div_ck",
1224         .parent         = &l3_div_ck,
1225         .clksel         = l4_div_div,
1226         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1227         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1228         .ops            = &clkops_null,
1229         .recalc         = &omap2_clksel_recalc,
1230         .round_rate     = &omap2_clksel_round_rate,
1231         .set_rate       = &omap2_clksel_set_rate,
1232 };
1233
1234 static struct clk lp_clk_div_ck = {
1235         .name           = "lp_clk_div_ck",
1236         .parent         = &dpll_abe_m2x2_ck,
1237         .ops            = &clkops_null,
1238         .fixed_div      = 16,
1239         .recalc         = &omap_fixed_divisor_recalc,
1240 };
1241
1242 static const struct clksel l4_wkup_clk_mux_sel[] = {
1243         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1244         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1245         { .parent = NULL },
1246 };
1247
1248 static struct clk l4_wkup_clk_mux_ck = {
1249         .name           = "l4_wkup_clk_mux_ck",
1250         .parent         = &sys_clkin_ck,
1251         .clksel         = l4_wkup_clk_mux_sel,
1252         .init           = &omap2_init_clksel_parent,
1253         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1254         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1255         .ops            = &clkops_null,
1256         .recalc         = &omap2_clksel_recalc,
1257 };
1258
1259 static const struct clksel per_abe_nc_fclk_div[] = {
1260         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1261         { .parent = NULL },
1262 };
1263
1264 static struct clk per_abe_nc_fclk = {
1265         .name           = "per_abe_nc_fclk",
1266         .parent         = &dpll_abe_m2_ck,
1267         .clksel         = per_abe_nc_fclk_div,
1268         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1269         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1270         .ops            = &clkops_null,
1271         .recalc         = &omap2_clksel_recalc,
1272         .round_rate     = &omap2_clksel_round_rate,
1273         .set_rate       = &omap2_clksel_set_rate,
1274 };
1275
1276 static const struct clksel mcasp2_fclk_sel[] = {
1277         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1278         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1279         { .parent = NULL },
1280 };
1281
1282 static struct clk mcasp2_fclk = {
1283         .name           = "mcasp2_fclk",
1284         .parent         = &func_96m_fclk,
1285         .ops            = &clkops_null,
1286         .recalc         = &followparent_recalc,
1287 };
1288
1289 static struct clk mcasp3_fclk = {
1290         .name           = "mcasp3_fclk",
1291         .parent         = &func_96m_fclk,
1292         .ops            = &clkops_null,
1293         .recalc         = &followparent_recalc,
1294 };
1295
1296 static struct clk ocp_abe_iclk = {
1297         .name           = "ocp_abe_iclk",
1298         .parent         = &aess_fclk,
1299         .ops            = &clkops_null,
1300         .recalc         = &followparent_recalc,
1301 };
1302
1303 static struct clk per_abe_24m_fclk = {
1304         .name           = "per_abe_24m_fclk",
1305         .parent         = &dpll_abe_m2_ck,
1306         .ops            = &clkops_null,
1307         .fixed_div      = 4,
1308         .recalc         = &omap_fixed_divisor_recalc,
1309 };
1310
1311 static const struct clksel pmd_stm_clock_mux_sel[] = {
1312         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1313         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1314         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1315         { .parent = NULL },
1316 };
1317
1318 static struct clk pmd_stm_clock_mux_ck = {
1319         .name           = "pmd_stm_clock_mux_ck",
1320         .parent         = &sys_clkin_ck,
1321         .ops            = &clkops_null,
1322         .recalc         = &followparent_recalc,
1323 };
1324
1325 static struct clk pmd_trace_clk_mux_ck = {
1326         .name           = "pmd_trace_clk_mux_ck",
1327         .parent         = &sys_clkin_ck,
1328         .ops            = &clkops_null,
1329         .recalc         = &followparent_recalc,
1330 };
1331
1332 static const struct clksel syc_clk_div_div[] = {
1333         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1334         { .parent = NULL },
1335 };
1336
1337 static struct clk syc_clk_div_ck = {
1338         .name           = "syc_clk_div_ck",
1339         .parent         = &sys_clkin_ck,
1340         .clksel         = syc_clk_div_div,
1341         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1342         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1343         .ops            = &clkops_null,
1344         .recalc         = &omap2_clksel_recalc,
1345         .round_rate     = &omap2_clksel_round_rate,
1346         .set_rate       = &omap2_clksel_set_rate,
1347 };
1348
1349 /* Leaf clocks controlled by modules */
1350
1351 static struct clk aes1_fck = {
1352         .name           = "aes1_fck",
1353         .ops            = &clkops_omap2_dflt,
1354         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1355         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1356         .clkdm_name     = "l4_secure_clkdm",
1357         .parent         = &l3_div_ck,
1358         .recalc         = &followparent_recalc,
1359 };
1360
1361 static struct clk aes2_fck = {
1362         .name           = "aes2_fck",
1363         .ops            = &clkops_omap2_dflt,
1364         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1365         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1366         .clkdm_name     = "l4_secure_clkdm",
1367         .parent         = &l3_div_ck,
1368         .recalc         = &followparent_recalc,
1369 };
1370
1371 static struct clk aess_fck = {
1372         .name           = "aess_fck",
1373         .ops            = &clkops_omap2_dflt,
1374         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1375         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1376         .clkdm_name     = "abe_clkdm",
1377         .parent         = &aess_fclk,
1378         .recalc         = &followparent_recalc,
1379 };
1380
1381 static struct clk bandgap_fclk = {
1382         .name           = "bandgap_fclk",
1383         .ops            = &clkops_omap2_dflt,
1384         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1385         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1386         .clkdm_name     = "l4_wkup_clkdm",
1387         .parent         = &sys_32k_ck,
1388         .recalc         = &followparent_recalc,
1389 };
1390
1391 static struct clk des3des_fck = {
1392         .name           = "des3des_fck",
1393         .ops            = &clkops_omap2_dflt,
1394         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1395         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1396         .clkdm_name     = "l4_secure_clkdm",
1397         .parent         = &l4_div_ck,
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static const struct clksel dmic_sync_mux_sel[] = {
1402         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1403         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1404         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1405         { .parent = NULL },
1406 };
1407
1408 static struct clk dmic_sync_mux_ck = {
1409         .name           = "dmic_sync_mux_ck",
1410         .parent         = &abe_24m_fclk,
1411         .clksel         = dmic_sync_mux_sel,
1412         .init           = &omap2_init_clksel_parent,
1413         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1414         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1415         .ops            = &clkops_null,
1416         .recalc         = &omap2_clksel_recalc,
1417 };
1418
1419 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1420         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1421         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1422         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1423         { .parent = NULL },
1424 };
1425
1426 /* Merged func_dmic_abe_gfclk into dmic */
1427 static struct clk dmic_fck = {
1428         .name           = "dmic_fck",
1429         .parent         = &dmic_sync_mux_ck,
1430         .clksel         = func_dmic_abe_gfclk_sel,
1431         .init           = &omap2_init_clksel_parent,
1432         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1433         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1434         .ops            = &clkops_omap2_dflt,
1435         .recalc         = &omap2_clksel_recalc,
1436         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1437         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1438         .clkdm_name     = "abe_clkdm",
1439 };
1440
1441 static struct clk dsp_fck = {
1442         .name           = "dsp_fck",
1443         .ops            = &clkops_omap2_dflt,
1444         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1445         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1446         .clkdm_name     = "tesla_clkdm",
1447         .parent         = &dpll_iva_m4x2_ck,
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk dss_sys_clk = {
1452         .name           = "dss_sys_clk",
1453         .ops            = &clkops_omap2_dflt,
1454         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1455         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1456         .clkdm_name     = "l3_dss_clkdm",
1457         .parent         = &syc_clk_div_ck,
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk dss_tv_clk = {
1462         .name           = "dss_tv_clk",
1463         .ops            = &clkops_omap2_dflt,
1464         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1465         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1466         .clkdm_name     = "l3_dss_clkdm",
1467         .parent         = &extalt_clkin_ck,
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk dss_dss_clk = {
1472         .name           = "dss_dss_clk",
1473         .ops            = &clkops_omap2_dflt,
1474         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1475         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1476         .clkdm_name     = "l3_dss_clkdm",
1477         .parent         = &dpll_per_m5x2_ck,
1478         .recalc         = &followparent_recalc,
1479 };
1480
1481 static struct clk dss_48mhz_clk = {
1482         .name           = "dss_48mhz_clk",
1483         .ops            = &clkops_omap2_dflt,
1484         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1485         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1486         .clkdm_name     = "l3_dss_clkdm",
1487         .parent         = &func_48mc_fclk,
1488         .recalc         = &followparent_recalc,
1489 };
1490
1491 static struct clk dss_fck = {
1492         .name           = "dss_fck",
1493         .ops            = &clkops_omap2_dflt,
1494         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1495         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1496         .clkdm_name     = "l3_dss_clkdm",
1497         .parent         = &l3_div_ck,
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 static struct clk efuse_ctrl_cust_fck = {
1502         .name           = "efuse_ctrl_cust_fck",
1503         .ops            = &clkops_omap2_dflt,
1504         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1505         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1506         .clkdm_name     = "l4_cefuse_clkdm",
1507         .parent         = &sys_clkin_ck,
1508         .recalc         = &followparent_recalc,
1509 };
1510
1511 static struct clk emif1_fck = {
1512         .name           = "emif1_fck",
1513         .ops            = &clkops_omap2_dflt,
1514         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1515         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1516         .flags          = ENABLE_ON_INIT,
1517         .clkdm_name     = "l3_emif_clkdm",
1518         .parent         = &ddrphy_ck,
1519         .recalc         = &followparent_recalc,
1520 };
1521
1522 static struct clk emif2_fck = {
1523         .name           = "emif2_fck",
1524         .ops            = &clkops_omap2_dflt,
1525         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1526         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1527         .flags          = ENABLE_ON_INIT,
1528         .clkdm_name     = "l3_emif_clkdm",
1529         .parent         = &ddrphy_ck,
1530         .recalc         = &followparent_recalc,
1531 };
1532
1533 static const struct clksel fdif_fclk_div[] = {
1534         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1535         { .parent = NULL },
1536 };
1537
1538 /* Merged fdif_fclk into fdif */
1539 static struct clk fdif_fck = {
1540         .name           = "fdif_fck",
1541         .parent         = &dpll_per_m4x2_ck,
1542         .clksel         = fdif_fclk_div,
1543         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1544         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1545         .ops            = &clkops_omap2_dflt,
1546         .recalc         = &omap2_clksel_recalc,
1547         .round_rate     = &omap2_clksel_round_rate,
1548         .set_rate       = &omap2_clksel_set_rate,
1549         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1550         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1551         .clkdm_name     = "iss_clkdm",
1552 };
1553
1554 static struct clk fpka_fck = {
1555         .name           = "fpka_fck",
1556         .ops            = &clkops_omap2_dflt,
1557         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1558         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1559         .clkdm_name     = "l4_secure_clkdm",
1560         .parent         = &l4_div_ck,
1561         .recalc         = &followparent_recalc,
1562 };
1563
1564 static struct clk gpio1_dbclk = {
1565         .name           = "gpio1_dbclk",
1566         .ops            = &clkops_omap2_dflt,
1567         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1568         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1569         .clkdm_name     = "l4_wkup_clkdm",
1570         .parent         = &sys_32k_ck,
1571         .recalc         = &followparent_recalc,
1572 };
1573
1574 static struct clk gpio1_ick = {
1575         .name           = "gpio1_ick",
1576         .ops            = &clkops_omap2_dflt,
1577         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1578         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1579         .clkdm_name     = "l4_wkup_clkdm",
1580         .parent         = &l4_wkup_clk_mux_ck,
1581         .recalc         = &followparent_recalc,
1582 };
1583
1584 static struct clk gpio2_dbclk = {
1585         .name           = "gpio2_dbclk",
1586         .ops            = &clkops_omap2_dflt,
1587         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1588         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1589         .clkdm_name     = "l4_per_clkdm",
1590         .parent         = &sys_32k_ck,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 static struct clk gpio2_ick = {
1595         .name           = "gpio2_ick",
1596         .ops            = &clkops_omap2_dflt,
1597         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1598         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1599         .clkdm_name     = "l4_per_clkdm",
1600         .parent         = &l4_div_ck,
1601         .recalc         = &followparent_recalc,
1602 };
1603
1604 static struct clk gpio3_dbclk = {
1605         .name           = "gpio3_dbclk",
1606         .ops            = &clkops_omap2_dflt,
1607         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1608         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .parent         = &sys_32k_ck,
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk gpio3_ick = {
1615         .name           = "gpio3_ick",
1616         .ops            = &clkops_omap2_dflt,
1617         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1618         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1619         .clkdm_name     = "l4_per_clkdm",
1620         .parent         = &l4_div_ck,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk gpio4_dbclk = {
1625         .name           = "gpio4_dbclk",
1626         .ops            = &clkops_omap2_dflt,
1627         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1628         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1629         .clkdm_name     = "l4_per_clkdm",
1630         .parent         = &sys_32k_ck,
1631         .recalc         = &followparent_recalc,
1632 };
1633
1634 static struct clk gpio4_ick = {
1635         .name           = "gpio4_ick",
1636         .ops            = &clkops_omap2_dflt,
1637         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1638         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .parent         = &l4_div_ck,
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk gpio5_dbclk = {
1645         .name           = "gpio5_dbclk",
1646         .ops            = &clkops_omap2_dflt,
1647         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1648         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1649         .clkdm_name     = "l4_per_clkdm",
1650         .parent         = &sys_32k_ck,
1651         .recalc         = &followparent_recalc,
1652 };
1653
1654 static struct clk gpio5_ick = {
1655         .name           = "gpio5_ick",
1656         .ops            = &clkops_omap2_dflt,
1657         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1658         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1659         .clkdm_name     = "l4_per_clkdm",
1660         .parent         = &l4_div_ck,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk gpio6_dbclk = {
1665         .name           = "gpio6_dbclk",
1666         .ops            = &clkops_omap2_dflt,
1667         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1668         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1669         .clkdm_name     = "l4_per_clkdm",
1670         .parent         = &sys_32k_ck,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk gpio6_ick = {
1675         .name           = "gpio6_ick",
1676         .ops            = &clkops_omap2_dflt,
1677         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1678         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1679         .clkdm_name     = "l4_per_clkdm",
1680         .parent         = &l4_div_ck,
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 static struct clk gpmc_ick = {
1685         .name           = "gpmc_ick",
1686         .ops            = &clkops_omap2_dflt,
1687         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1688         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1689         .clkdm_name     = "l3_2_clkdm",
1690         .parent         = &l3_div_ck,
1691         .recalc         = &followparent_recalc,
1692 };
1693
1694 static const struct clksel sgx_clk_mux_sel[] = {
1695         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1696         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1697         { .parent = NULL },
1698 };
1699
1700 /* Merged sgx_clk_mux into gpu */
1701 static struct clk gpu_fck = {
1702         .name           = "gpu_fck",
1703         .parent         = &dpll_core_m7x2_ck,
1704         .clksel         = sgx_clk_mux_sel,
1705         .init           = &omap2_init_clksel_parent,
1706         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1707         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1708         .ops            = &clkops_omap2_dflt,
1709         .recalc         = &omap2_clksel_recalc,
1710         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1711         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1712         .clkdm_name     = "l3_gfx_clkdm",
1713 };
1714
1715 static struct clk hdq1w_fck = {
1716         .name           = "hdq1w_fck",
1717         .ops            = &clkops_omap2_dflt,
1718         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1719         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1720         .clkdm_name     = "l4_per_clkdm",
1721         .parent         = &func_12m_fclk,
1722         .recalc         = &followparent_recalc,
1723 };
1724
1725 static const struct clksel hsi_fclk_div[] = {
1726         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1727         { .parent = NULL },
1728 };
1729
1730 /* Merged hsi_fclk into hsi */
1731 static struct clk hsi_fck = {
1732         .name           = "hsi_fck",
1733         .parent         = &dpll_per_m2x2_ck,
1734         .clksel         = hsi_fclk_div,
1735         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1736         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1737         .ops            = &clkops_omap2_dflt,
1738         .recalc         = &omap2_clksel_recalc,
1739         .round_rate     = &omap2_clksel_round_rate,
1740         .set_rate       = &omap2_clksel_set_rate,
1741         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1742         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1743         .clkdm_name     = "l3_init_clkdm",
1744 };
1745
1746 static struct clk i2c1_fck = {
1747         .name           = "i2c1_fck",
1748         .ops            = &clkops_omap2_dflt,
1749         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1750         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1751         .clkdm_name     = "l4_per_clkdm",
1752         .parent         = &func_96m_fclk,
1753         .recalc         = &followparent_recalc,
1754 };
1755
1756 static struct clk i2c2_fck = {
1757         .name           = "i2c2_fck",
1758         .ops            = &clkops_omap2_dflt,
1759         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1760         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1761         .clkdm_name     = "l4_per_clkdm",
1762         .parent         = &func_96m_fclk,
1763         .recalc         = &followparent_recalc,
1764 };
1765
1766 static struct clk i2c3_fck = {
1767         .name           = "i2c3_fck",
1768         .ops            = &clkops_omap2_dflt,
1769         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1770         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1771         .clkdm_name     = "l4_per_clkdm",
1772         .parent         = &func_96m_fclk,
1773         .recalc         = &followparent_recalc,
1774 };
1775
1776 static struct clk i2c4_fck = {
1777         .name           = "i2c4_fck",
1778         .ops            = &clkops_omap2_dflt,
1779         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1780         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1781         .clkdm_name     = "l4_per_clkdm",
1782         .parent         = &func_96m_fclk,
1783         .recalc         = &followparent_recalc,
1784 };
1785
1786 static struct clk ipu_fck = {
1787         .name           = "ipu_fck",
1788         .ops            = &clkops_omap2_dflt,
1789         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1790         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1791         .clkdm_name     = "ducati_clkdm",
1792         .parent         = &ducati_clk_mux_ck,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk iss_ctrlclk = {
1797         .name           = "iss_ctrlclk",
1798         .ops            = &clkops_omap2_dflt,
1799         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1800         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1801         .clkdm_name     = "iss_clkdm",
1802         .parent         = &func_96m_fclk,
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk iss_fck = {
1807         .name           = "iss_fck",
1808         .ops            = &clkops_omap2_dflt,
1809         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1810         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1811         .clkdm_name     = "iss_clkdm",
1812         .parent         = &ducati_clk_mux_ck,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk iva_fck = {
1817         .name           = "iva_fck",
1818         .ops            = &clkops_omap2_dflt,
1819         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1820         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1821         .clkdm_name     = "ivahd_clkdm",
1822         .parent         = &dpll_iva_m5x2_ck,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk kbd_fck = {
1827         .name           = "kbd_fck",
1828         .ops            = &clkops_omap2_dflt,
1829         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1830         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .parent         = &sys_32k_ck,
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 static struct clk l3_instr_ick = {
1837         .name           = "l3_instr_ick",
1838         .ops            = &clkops_omap2_dflt,
1839         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1840         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1841         .clkdm_name     = "l3_instr_clkdm",
1842         .flags          = ENABLE_ON_INIT,
1843         .parent         = &l3_div_ck,
1844         .recalc         = &followparent_recalc,
1845 };
1846
1847 static struct clk l3_main_3_ick = {
1848         .name           = "l3_main_3_ick",
1849         .ops            = &clkops_omap2_dflt,
1850         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1851         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1852         .clkdm_name     = "l3_instr_clkdm",
1853         .flags          = ENABLE_ON_INIT,
1854         .parent         = &l3_div_ck,
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk mcasp_sync_mux_ck = {
1859         .name           = "mcasp_sync_mux_ck",
1860         .parent         = &abe_24m_fclk,
1861         .clksel         = dmic_sync_mux_sel,
1862         .init           = &omap2_init_clksel_parent,
1863         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1864         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1865         .ops            = &clkops_null,
1866         .recalc         = &omap2_clksel_recalc,
1867 };
1868
1869 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1870         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1871         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1872         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1873         { .parent = NULL },
1874 };
1875
1876 /* Merged func_mcasp_abe_gfclk into mcasp */
1877 static struct clk mcasp_fck = {
1878         .name           = "mcasp_fck",
1879         .parent         = &mcasp_sync_mux_ck,
1880         .clksel         = func_mcasp_abe_gfclk_sel,
1881         .init           = &omap2_init_clksel_parent,
1882         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1883         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1884         .ops            = &clkops_omap2_dflt,
1885         .recalc         = &omap2_clksel_recalc,
1886         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1887         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1888         .clkdm_name     = "abe_clkdm",
1889 };
1890
1891 static struct clk mcbsp1_sync_mux_ck = {
1892         .name           = "mcbsp1_sync_mux_ck",
1893         .parent         = &abe_24m_fclk,
1894         .clksel         = dmic_sync_mux_sel,
1895         .init           = &omap2_init_clksel_parent,
1896         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1897         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1898         .ops            = &clkops_null,
1899         .recalc         = &omap2_clksel_recalc,
1900 };
1901
1902 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1903         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1904         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1905         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1906         { .parent = NULL },
1907 };
1908
1909 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1910 static struct clk mcbsp1_fck = {
1911         .name           = "mcbsp1_fck",
1912         .parent         = &mcbsp1_sync_mux_ck,
1913         .clksel         = func_mcbsp1_gfclk_sel,
1914         .init           = &omap2_init_clksel_parent,
1915         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1916         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1917         .ops            = &clkops_omap2_dflt,
1918         .recalc         = &omap2_clksel_recalc,
1919         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1920         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1921         .clkdm_name     = "abe_clkdm",
1922 };
1923
1924 static struct clk mcbsp2_sync_mux_ck = {
1925         .name           = "mcbsp2_sync_mux_ck",
1926         .parent         = &abe_24m_fclk,
1927         .clksel         = dmic_sync_mux_sel,
1928         .init           = &omap2_init_clksel_parent,
1929         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1930         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1931         .ops            = &clkops_null,
1932         .recalc         = &omap2_clksel_recalc,
1933 };
1934
1935 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1936         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1937         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1938         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1939         { .parent = NULL },
1940 };
1941
1942 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1943 static struct clk mcbsp2_fck = {
1944         .name           = "mcbsp2_fck",
1945         .parent         = &mcbsp2_sync_mux_ck,
1946         .clksel         = func_mcbsp2_gfclk_sel,
1947         .init           = &omap2_init_clksel_parent,
1948         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1949         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1950         .ops            = &clkops_omap2_dflt,
1951         .recalc         = &omap2_clksel_recalc,
1952         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1953         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1954         .clkdm_name     = "abe_clkdm",
1955 };
1956
1957 static struct clk mcbsp3_sync_mux_ck = {
1958         .name           = "mcbsp3_sync_mux_ck",
1959         .parent         = &abe_24m_fclk,
1960         .clksel         = dmic_sync_mux_sel,
1961         .init           = &omap2_init_clksel_parent,
1962         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1963         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1964         .ops            = &clkops_null,
1965         .recalc         = &omap2_clksel_recalc,
1966 };
1967
1968 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1969         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1970         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1971         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1972         { .parent = NULL },
1973 };
1974
1975 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1976 static struct clk mcbsp3_fck = {
1977         .name           = "mcbsp3_fck",
1978         .parent         = &mcbsp3_sync_mux_ck,
1979         .clksel         = func_mcbsp3_gfclk_sel,
1980         .init           = &omap2_init_clksel_parent,
1981         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1982         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1983         .ops            = &clkops_omap2_dflt,
1984         .recalc         = &omap2_clksel_recalc,
1985         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1986         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1987         .clkdm_name     = "abe_clkdm",
1988 };
1989
1990 static struct clk mcbsp4_sync_mux_ck = {
1991         .name           = "mcbsp4_sync_mux_ck",
1992         .parent         = &func_96m_fclk,
1993         .clksel         = mcasp2_fclk_sel,
1994         .init           = &omap2_init_clksel_parent,
1995         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1996         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1997         .ops            = &clkops_null,
1998         .recalc         = &omap2_clksel_recalc,
1999 };
2000
2001 static const struct clksel per_mcbsp4_gfclk_sel[] = {
2002         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
2003         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
2004         { .parent = NULL },
2005 };
2006
2007 /* Merged per_mcbsp4_gfclk into mcbsp4 */
2008 static struct clk mcbsp4_fck = {
2009         .name           = "mcbsp4_fck",
2010         .parent         = &mcbsp4_sync_mux_ck,
2011         .clksel         = per_mcbsp4_gfclk_sel,
2012         .init           = &omap2_init_clksel_parent,
2013         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2014         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2015         .ops            = &clkops_omap2_dflt,
2016         .recalc         = &omap2_clksel_recalc,
2017         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2018         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2019         .clkdm_name     = "l4_per_clkdm",
2020 };
2021
2022 static struct clk mcpdm_fck = {
2023         .name           = "mcpdm_fck",
2024         .ops            = &clkops_omap2_dflt,
2025         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2026         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2027         .clkdm_name     = "abe_clkdm",
2028         .parent         = &pad_clks_ck,
2029         .recalc         = &followparent_recalc,
2030 };
2031
2032 static struct clk mcspi1_fck = {
2033         .name           = "mcspi1_fck",
2034         .ops            = &clkops_omap2_dflt,
2035         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2036         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2037         .clkdm_name     = "l4_per_clkdm",
2038         .parent         = &func_48m_fclk,
2039         .recalc         = &followparent_recalc,
2040 };
2041
2042 static struct clk mcspi2_fck = {
2043         .name           = "mcspi2_fck",
2044         .ops            = &clkops_omap2_dflt,
2045         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2046         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2047         .clkdm_name     = "l4_per_clkdm",
2048         .parent         = &func_48m_fclk,
2049         .recalc         = &followparent_recalc,
2050 };
2051
2052 static struct clk mcspi3_fck = {
2053         .name           = "mcspi3_fck",
2054         .ops            = &clkops_omap2_dflt,
2055         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2056         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2057         .clkdm_name     = "l4_per_clkdm",
2058         .parent         = &func_48m_fclk,
2059         .recalc         = &followparent_recalc,
2060 };
2061
2062 static struct clk mcspi4_fck = {
2063         .name           = "mcspi4_fck",
2064         .ops            = &clkops_omap2_dflt,
2065         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2066         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2067         .clkdm_name     = "l4_per_clkdm",
2068         .parent         = &func_48m_fclk,
2069         .recalc         = &followparent_recalc,
2070 };
2071
2072 /* Merged hsmmc1_fclk into mmc1 */
2073 static struct clk mmc1_fck = {
2074         .name           = "mmc1_fck",
2075         .parent         = &func_64m_fclk,
2076         .clksel         = hsmmc6_fclk_sel,
2077         .init           = &omap2_init_clksel_parent,
2078         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2079         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2080         .ops            = &clkops_omap2_dflt,
2081         .recalc         = &omap2_clksel_recalc,
2082         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2083         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2084         .clkdm_name     = "l3_init_clkdm",
2085 };
2086
2087 /* Merged hsmmc2_fclk into mmc2 */
2088 static struct clk mmc2_fck = {
2089         .name           = "mmc2_fck",
2090         .parent         = &func_64m_fclk,
2091         .clksel         = hsmmc6_fclk_sel,
2092         .init           = &omap2_init_clksel_parent,
2093         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2094         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2095         .ops            = &clkops_omap2_dflt,
2096         .recalc         = &omap2_clksel_recalc,
2097         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2098         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2099         .clkdm_name     = "l3_init_clkdm",
2100 };
2101
2102 static struct clk mmc3_fck = {
2103         .name           = "mmc3_fck",
2104         .ops            = &clkops_omap2_dflt,
2105         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2106         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2107         .clkdm_name     = "l4_per_clkdm",
2108         .parent         = &func_48m_fclk,
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk mmc4_fck = {
2113         .name           = "mmc4_fck",
2114         .ops            = &clkops_omap2_dflt,
2115         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2116         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2117         .clkdm_name     = "l4_per_clkdm",
2118         .parent         = &func_48m_fclk,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk mmc5_fck = {
2123         .name           = "mmc5_fck",
2124         .ops            = &clkops_omap2_dflt,
2125         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2126         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2127         .clkdm_name     = "l4_per_clkdm",
2128         .parent         = &func_48m_fclk,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 static struct clk ocp2scp_usb_phy_phy_48m = {
2133         .name           = "ocp2scp_usb_phy_phy_48m",
2134         .ops            = &clkops_omap2_dflt,
2135         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2136         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2137         .clkdm_name     = "l3_init_clkdm",
2138         .parent         = &func_48m_fclk,
2139         .recalc         = &followparent_recalc,
2140 };
2141
2142 static struct clk ocp2scp_usb_phy_ick = {
2143         .name           = "ocp2scp_usb_phy_ick",
2144         .ops            = &clkops_omap2_dflt,
2145         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2146         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2147         .clkdm_name     = "l3_init_clkdm",
2148         .parent         = &l4_div_ck,
2149         .recalc         = &followparent_recalc,
2150 };
2151
2152 static struct clk ocp_wp_noc_ick = {
2153         .name           = "ocp_wp_noc_ick",
2154         .ops            = &clkops_omap2_dflt,
2155         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2156         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2157         .clkdm_name     = "l3_instr_clkdm",
2158         .flags          = ENABLE_ON_INIT,
2159         .parent         = &l3_div_ck,
2160         .recalc         = &followparent_recalc,
2161 };
2162
2163 static struct clk rng_ick = {
2164         .name           = "rng_ick",
2165         .ops            = &clkops_omap2_dflt,
2166         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2167         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2168         .clkdm_name     = "l4_secure_clkdm",
2169         .parent         = &l4_div_ck,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk sha2md5_fck = {
2174         .name           = "sha2md5_fck",
2175         .ops            = &clkops_omap2_dflt,
2176         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2177         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2178         .clkdm_name     = "l4_secure_clkdm",
2179         .parent         = &l3_div_ck,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk sl2if_ick = {
2184         .name           = "sl2if_ick",
2185         .ops            = &clkops_omap2_dflt,
2186         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2187         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2188         .clkdm_name     = "ivahd_clkdm",
2189         .parent         = &dpll_iva_m5x2_ck,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk slimbus1_fclk_1 = {
2194         .name           = "slimbus1_fclk_1",
2195         .ops            = &clkops_omap2_dflt,
2196         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2197         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2198         .clkdm_name     = "abe_clkdm",
2199         .parent         = &func_24m_clk,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk slimbus1_fclk_0 = {
2204         .name           = "slimbus1_fclk_0",
2205         .ops            = &clkops_omap2_dflt,
2206         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2207         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2208         .clkdm_name     = "abe_clkdm",
2209         .parent         = &abe_24m_fclk,
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk slimbus1_fclk_2 = {
2214         .name           = "slimbus1_fclk_2",
2215         .ops            = &clkops_omap2_dflt,
2216         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2217         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2218         .clkdm_name     = "abe_clkdm",
2219         .parent         = &pad_clks_ck,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk slimbus1_slimbus_clk = {
2224         .name           = "slimbus1_slimbus_clk",
2225         .ops            = &clkops_omap2_dflt,
2226         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2227         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2228         .clkdm_name     = "abe_clkdm",
2229         .parent         = &slimbus_clk,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk slimbus1_fck = {
2234         .name           = "slimbus1_fck",
2235         .ops            = &clkops_omap2_dflt,
2236         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2237         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2238         .clkdm_name     = "abe_clkdm",
2239         .parent         = &ocp_abe_iclk,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk slimbus2_fclk_1 = {
2244         .name           = "slimbus2_fclk_1",
2245         .ops            = &clkops_omap2_dflt,
2246         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2247         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2248         .clkdm_name     = "l4_per_clkdm",
2249         .parent         = &per_abe_24m_fclk,
2250         .recalc         = &followparent_recalc,
2251 };
2252
2253 static struct clk slimbus2_fclk_0 = {
2254         .name           = "slimbus2_fclk_0",
2255         .ops            = &clkops_omap2_dflt,
2256         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2257         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2258         .clkdm_name     = "l4_per_clkdm",
2259         .parent         = &func_24mc_fclk,
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk slimbus2_slimbus_clk = {
2264         .name           = "slimbus2_slimbus_clk",
2265         .ops            = &clkops_omap2_dflt,
2266         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2267         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2268         .clkdm_name     = "l4_per_clkdm",
2269         .parent         = &pad_slimbus_core_clks_ck,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk slimbus2_fck = {
2274         .name           = "slimbus2_fck",
2275         .ops            = &clkops_omap2_dflt,
2276         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2277         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2278         .clkdm_name     = "l4_per_clkdm",
2279         .parent         = &l4_div_ck,
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk smartreflex_core_fck = {
2284         .name           = "smartreflex_core_fck",
2285         .ops            = &clkops_omap2_dflt,
2286         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2287         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2288         .clkdm_name     = "l4_ao_clkdm",
2289         .parent         = &l4_wkup_clk_mux_ck,
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 static struct clk smartreflex_iva_fck = {
2294         .name           = "smartreflex_iva_fck",
2295         .ops            = &clkops_omap2_dflt,
2296         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2297         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2298         .clkdm_name     = "l4_ao_clkdm",
2299         .parent         = &l4_wkup_clk_mux_ck,
2300         .recalc         = &followparent_recalc,
2301 };
2302
2303 static struct clk smartreflex_mpu_fck = {
2304         .name           = "smartreflex_mpu_fck",
2305         .ops            = &clkops_omap2_dflt,
2306         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2307         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2308         .clkdm_name     = "l4_ao_clkdm",
2309         .parent         = &l4_wkup_clk_mux_ck,
2310         .recalc         = &followparent_recalc,
2311 };
2312
2313 /* Merged dmt1_clk_mux into timer1 */
2314 static struct clk timer1_fck = {
2315         .name           = "timer1_fck",
2316         .parent         = &sys_clkin_ck,
2317         .clksel         = abe_dpll_bypass_clk_mux_sel,
2318         .init           = &omap2_init_clksel_parent,
2319         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2320         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2321         .ops            = &clkops_omap2_dflt,
2322         .recalc         = &omap2_clksel_recalc,
2323         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2324         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2325         .clkdm_name     = "l4_wkup_clkdm",
2326 };
2327
2328 /* Merged cm2_dm10_mux into timer10 */
2329 static struct clk timer10_fck = {
2330         .name           = "timer10_fck",
2331         .parent         = &sys_clkin_ck,
2332         .clksel         = abe_dpll_bypass_clk_mux_sel,
2333         .init           = &omap2_init_clksel_parent,
2334         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2335         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2336         .ops            = &clkops_omap2_dflt,
2337         .recalc         = &omap2_clksel_recalc,
2338         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2339         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2340         .clkdm_name     = "l4_per_clkdm",
2341 };
2342
2343 /* Merged cm2_dm11_mux into timer11 */
2344 static struct clk timer11_fck = {
2345         .name           = "timer11_fck",
2346         .parent         = &sys_clkin_ck,
2347         .clksel         = abe_dpll_bypass_clk_mux_sel,
2348         .init           = &omap2_init_clksel_parent,
2349         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2350         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2351         .ops            = &clkops_omap2_dflt,
2352         .recalc         = &omap2_clksel_recalc,
2353         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2354         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2355         .clkdm_name     = "l4_per_clkdm",
2356 };
2357
2358 /* Merged cm2_dm2_mux into timer2 */
2359 static struct clk timer2_fck = {
2360         .name           = "timer2_fck",
2361         .parent         = &sys_clkin_ck,
2362         .clksel         = abe_dpll_bypass_clk_mux_sel,
2363         .init           = &omap2_init_clksel_parent,
2364         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2365         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2366         .ops            = &clkops_omap2_dflt,
2367         .recalc         = &omap2_clksel_recalc,
2368         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2369         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2370         .clkdm_name     = "l4_per_clkdm",
2371 };
2372
2373 /* Merged cm2_dm3_mux into timer3 */
2374 static struct clk timer3_fck = {
2375         .name           = "timer3_fck",
2376         .parent         = &sys_clkin_ck,
2377         .clksel         = abe_dpll_bypass_clk_mux_sel,
2378         .init           = &omap2_init_clksel_parent,
2379         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2380         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2381         .ops            = &clkops_omap2_dflt,
2382         .recalc         = &omap2_clksel_recalc,
2383         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2384         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2385         .clkdm_name     = "l4_per_clkdm",
2386 };
2387
2388 /* Merged cm2_dm4_mux into timer4 */
2389 static struct clk timer4_fck = {
2390         .name           = "timer4_fck",
2391         .parent         = &sys_clkin_ck,
2392         .clksel         = abe_dpll_bypass_clk_mux_sel,
2393         .init           = &omap2_init_clksel_parent,
2394         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2395         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2396         .ops            = &clkops_omap2_dflt,
2397         .recalc         = &omap2_clksel_recalc,
2398         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2399         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2400         .clkdm_name     = "l4_per_clkdm",
2401 };
2402
2403 static const struct clksel timer5_sync_mux_sel[] = {
2404         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2405         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2406         { .parent = NULL },
2407 };
2408
2409 /* Merged timer5_sync_mux into timer5 */
2410 static struct clk timer5_fck = {
2411         .name           = "timer5_fck",
2412         .parent         = &syc_clk_div_ck,
2413         .clksel         = timer5_sync_mux_sel,
2414         .init           = &omap2_init_clksel_parent,
2415         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2416         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2417         .ops            = &clkops_omap2_dflt,
2418         .recalc         = &omap2_clksel_recalc,
2419         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2420         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2421         .clkdm_name     = "abe_clkdm",
2422 };
2423
2424 /* Merged timer6_sync_mux into timer6 */
2425 static struct clk timer6_fck = {
2426         .name           = "timer6_fck",
2427         .parent         = &syc_clk_div_ck,
2428         .clksel         = timer5_sync_mux_sel,
2429         .init           = &omap2_init_clksel_parent,
2430         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2431         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2432         .ops            = &clkops_omap2_dflt,
2433         .recalc         = &omap2_clksel_recalc,
2434         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2435         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2436         .clkdm_name     = "abe_clkdm",
2437 };
2438
2439 /* Merged timer7_sync_mux into timer7 */
2440 static struct clk timer7_fck = {
2441         .name           = "timer7_fck",
2442         .parent         = &syc_clk_div_ck,
2443         .clksel         = timer5_sync_mux_sel,
2444         .init           = &omap2_init_clksel_parent,
2445         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2446         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2447         .ops            = &clkops_omap2_dflt,
2448         .recalc         = &omap2_clksel_recalc,
2449         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2450         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2451         .clkdm_name     = "abe_clkdm",
2452 };
2453
2454 /* Merged timer8_sync_mux into timer8 */
2455 static struct clk timer8_fck = {
2456         .name           = "timer8_fck",
2457         .parent         = &syc_clk_div_ck,
2458         .clksel         = timer5_sync_mux_sel,
2459         .init           = &omap2_init_clksel_parent,
2460         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2461         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2462         .ops            = &clkops_omap2_dflt,
2463         .recalc         = &omap2_clksel_recalc,
2464         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2465         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2466         .clkdm_name     = "abe_clkdm",
2467 };
2468
2469 /* Merged cm2_dm9_mux into timer9 */
2470 static struct clk timer9_fck = {
2471         .name           = "timer9_fck",
2472         .parent         = &sys_clkin_ck,
2473         .clksel         = abe_dpll_bypass_clk_mux_sel,
2474         .init           = &omap2_init_clksel_parent,
2475         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2476         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2477         .ops            = &clkops_omap2_dflt,
2478         .recalc         = &omap2_clksel_recalc,
2479         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2480         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2481         .clkdm_name     = "l4_per_clkdm",
2482 };
2483
2484 static struct clk uart1_fck = {
2485         .name           = "uart1_fck",
2486         .ops            = &clkops_omap2_dflt,
2487         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2488         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2489         .clkdm_name     = "l4_per_clkdm",
2490         .parent         = &func_48m_fclk,
2491         .recalc         = &followparent_recalc,
2492 };
2493
2494 static struct clk uart2_fck = {
2495         .name           = "uart2_fck",
2496         .ops            = &clkops_omap2_dflt,
2497         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2498         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2499         .clkdm_name     = "l4_per_clkdm",
2500         .parent         = &func_48m_fclk,
2501         .recalc         = &followparent_recalc,
2502 };
2503
2504 static struct clk uart3_fck = {
2505         .name           = "uart3_fck",
2506         .ops            = &clkops_omap2_dflt,
2507         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2508         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2509         .clkdm_name     = "l4_per_clkdm",
2510         .parent         = &func_48m_fclk,
2511         .recalc         = &followparent_recalc,
2512 };
2513
2514 static struct clk uart4_fck = {
2515         .name           = "uart4_fck",
2516         .ops            = &clkops_omap2_dflt,
2517         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2518         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2519         .clkdm_name     = "l4_per_clkdm",
2520         .parent         = &func_48m_fclk,
2521         .recalc         = &followparent_recalc,
2522 };
2523
2524 static struct clk usb_host_fs_fck = {
2525         .name           = "usb_host_fs_fck",
2526         .ops            = &clkops_omap2_dflt,
2527         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2528         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2529         .clkdm_name     = "l3_init_clkdm",
2530         .parent         = &func_48mc_fclk,
2531         .recalc         = &followparent_recalc,
2532 };
2533
2534 static const struct clksel utmi_p1_gfclk_sel[] = {
2535         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2536         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2537         { .parent = NULL },
2538 };
2539
2540 static struct clk utmi_p1_gfclk = {
2541         .name           = "utmi_p1_gfclk",
2542         .parent         = &init_60m_fclk,
2543         .clksel         = utmi_p1_gfclk_sel,
2544         .init           = &omap2_init_clksel_parent,
2545         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2546         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2547         .ops            = &clkops_null,
2548         .recalc         = &omap2_clksel_recalc,
2549 };
2550
2551 static struct clk usb_host_hs_utmi_p1_clk = {
2552         .name           = "usb_host_hs_utmi_p1_clk",
2553         .ops            = &clkops_omap2_dflt,
2554         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2555         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2556         .clkdm_name     = "l3_init_clkdm",
2557         .parent         = &utmi_p1_gfclk,
2558         .recalc         = &followparent_recalc,
2559 };
2560
2561 static const struct clksel utmi_p2_gfclk_sel[] = {
2562         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2563         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2564         { .parent = NULL },
2565 };
2566
2567 static struct clk utmi_p2_gfclk = {
2568         .name           = "utmi_p2_gfclk",
2569         .parent         = &init_60m_fclk,
2570         .clksel         = utmi_p2_gfclk_sel,
2571         .init           = &omap2_init_clksel_parent,
2572         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2573         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2574         .ops            = &clkops_null,
2575         .recalc         = &omap2_clksel_recalc,
2576 };
2577
2578 static struct clk usb_host_hs_utmi_p2_clk = {
2579         .name           = "usb_host_hs_utmi_p2_clk",
2580         .ops            = &clkops_omap2_dflt,
2581         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2582         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2583         .clkdm_name     = "l3_init_clkdm",
2584         .parent         = &utmi_p2_gfclk,
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk usb_host_hs_utmi_p3_clk = {
2589         .name           = "usb_host_hs_utmi_p3_clk",
2590         .ops            = &clkops_omap2_dflt,
2591         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2592         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2593         .clkdm_name     = "l3_init_clkdm",
2594         .parent         = &init_60m_fclk,
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk usb_host_hs_hsic480m_p1_clk = {
2599         .name           = "usb_host_hs_hsic480m_p1_clk",
2600         .ops            = &clkops_omap2_dflt,
2601         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2602         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2603         .clkdm_name     = "l3_init_clkdm",
2604         .parent         = &dpll_usb_m2_ck,
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk usb_host_hs_hsic60m_p1_clk = {
2609         .name           = "usb_host_hs_hsic60m_p1_clk",
2610         .ops            = &clkops_omap2_dflt,
2611         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2612         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2613         .clkdm_name     = "l3_init_clkdm",
2614         .parent         = &init_60m_fclk,
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk usb_host_hs_hsic60m_p2_clk = {
2619         .name           = "usb_host_hs_hsic60m_p2_clk",
2620         .ops            = &clkops_omap2_dflt,
2621         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2622         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2623         .clkdm_name     = "l3_init_clkdm",
2624         .parent         = &init_60m_fclk,
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk usb_host_hs_hsic480m_p2_clk = {
2629         .name           = "usb_host_hs_hsic480m_p2_clk",
2630         .ops            = &clkops_omap2_dflt,
2631         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2632         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2633         .clkdm_name     = "l3_init_clkdm",
2634         .parent         = &dpll_usb_m2_ck,
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static struct clk usb_host_hs_func48mclk = {
2639         .name           = "usb_host_hs_func48mclk",
2640         .ops            = &clkops_omap2_dflt,
2641         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2642         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2643         .clkdm_name     = "l3_init_clkdm",
2644         .parent         = &func_48mc_fclk,
2645         .recalc         = &followparent_recalc,
2646 };
2647
2648 static struct clk usb_host_hs_fck = {
2649         .name           = "usb_host_hs_fck",
2650         .ops            = &clkops_omap2_dflt,
2651         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2652         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2653         .clkdm_name     = "l3_init_clkdm",
2654         .parent         = &init_60m_fclk,
2655         .recalc         = &followparent_recalc,
2656 };
2657
2658 static const struct clksel otg_60m_gfclk_sel[] = {
2659         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2660         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2661         { .parent = NULL },
2662 };
2663
2664 static struct clk otg_60m_gfclk = {
2665         .name           = "otg_60m_gfclk",
2666         .parent         = &utmi_phy_clkout_ck,
2667         .clksel         = otg_60m_gfclk_sel,
2668         .init           = &omap2_init_clksel_parent,
2669         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2670         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2671         .ops            = &clkops_null,
2672         .recalc         = &omap2_clksel_recalc,
2673 };
2674
2675 static struct clk usb_otg_hs_xclk = {
2676         .name           = "usb_otg_hs_xclk",
2677         .ops            = &clkops_omap2_dflt,
2678         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2679         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2680         .clkdm_name     = "l3_init_clkdm",
2681         .parent         = &otg_60m_gfclk,
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk usb_otg_hs_ick = {
2686         .name           = "usb_otg_hs_ick",
2687         .ops            = &clkops_omap2_dflt,
2688         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2689         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2690         .clkdm_name     = "l3_init_clkdm",
2691         .parent         = &l3_div_ck,
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk usb_phy_cm_clk32k = {
2696         .name           = "usb_phy_cm_clk32k",
2697         .ops            = &clkops_omap2_dflt,
2698         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2699         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2700         .clkdm_name     = "l4_ao_clkdm",
2701         .parent         = &sys_32k_ck,
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk usb_tll_hs_usb_ch2_clk = {
2706         .name           = "usb_tll_hs_usb_ch2_clk",
2707         .ops            = &clkops_omap2_dflt,
2708         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2709         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2710         .clkdm_name     = "l3_init_clkdm",
2711         .parent         = &init_60m_fclk,
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk usb_tll_hs_usb_ch0_clk = {
2716         .name           = "usb_tll_hs_usb_ch0_clk",
2717         .ops            = &clkops_omap2_dflt,
2718         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2719         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2720         .clkdm_name     = "l3_init_clkdm",
2721         .parent         = &init_60m_fclk,
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static struct clk usb_tll_hs_usb_ch1_clk = {
2726         .name           = "usb_tll_hs_usb_ch1_clk",
2727         .ops            = &clkops_omap2_dflt,
2728         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2729         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2730         .clkdm_name     = "l3_init_clkdm",
2731         .parent         = &init_60m_fclk,
2732         .recalc         = &followparent_recalc,
2733 };
2734
2735 static struct clk usb_tll_hs_ick = {
2736         .name           = "usb_tll_hs_ick",
2737         .ops            = &clkops_omap2_dflt,
2738         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2739         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2740         .clkdm_name     = "l3_init_clkdm",
2741         .parent         = &l4_div_ck,
2742         .recalc         = &followparent_recalc,
2743 };
2744
2745 static const struct clksel_rate div2_14to18_rates[] = {
2746         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2747         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2748         { .div = 0 },
2749 };
2750
2751 static const struct clksel usim_fclk_div[] = {
2752         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2753         { .parent = NULL },
2754 };
2755
2756 static struct clk usim_ck = {
2757         .name           = "usim_ck",
2758         .parent         = &dpll_per_m4x2_ck,
2759         .clksel         = usim_fclk_div,
2760         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2761         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2762         .ops            = &clkops_null,
2763         .recalc         = &omap2_clksel_recalc,
2764         .round_rate     = &omap2_clksel_round_rate,
2765         .set_rate       = &omap2_clksel_set_rate,
2766 };
2767
2768 static struct clk usim_fclk = {
2769         .name           = "usim_fclk",
2770         .ops            = &clkops_omap2_dflt,
2771         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2772         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2773         .clkdm_name     = "l4_wkup_clkdm",
2774         .parent         = &usim_ck,
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk usim_fck = {
2779         .name           = "usim_fck",
2780         .ops            = &clkops_omap2_dflt,
2781         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2782         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2783         .clkdm_name     = "l4_wkup_clkdm",
2784         .parent         = &sys_32k_ck,
2785         .recalc         = &followparent_recalc,
2786 };
2787
2788 static struct clk wd_timer2_fck = {
2789         .name           = "wd_timer2_fck",
2790         .ops            = &clkops_omap2_dflt,
2791         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2792         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2793         .clkdm_name     = "l4_wkup_clkdm",
2794         .parent         = &sys_32k_ck,
2795         .recalc         = &followparent_recalc,
2796 };
2797
2798 static struct clk wd_timer3_fck = {
2799         .name           = "wd_timer3_fck",
2800         .ops            = &clkops_omap2_dflt,
2801         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2802         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2803         .clkdm_name     = "abe_clkdm",
2804         .parent         = &sys_32k_ck,
2805         .recalc         = &followparent_recalc,
2806 };
2807
2808 /* Remaining optional clocks */
2809 static const struct clksel stm_clk_div_div[] = {
2810         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2811         { .parent = NULL },
2812 };
2813
2814 static struct clk stm_clk_div_ck = {
2815         .name           = "stm_clk_div_ck",
2816         .parent         = &pmd_stm_clock_mux_ck,
2817         .clksel         = stm_clk_div_div,
2818         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2819         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2820         .ops            = &clkops_null,
2821         .recalc         = &omap2_clksel_recalc,
2822         .round_rate     = &omap2_clksel_round_rate,
2823         .set_rate       = &omap2_clksel_set_rate,
2824 };
2825
2826 static const struct clksel trace_clk_div_div[] = {
2827         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2828         { .parent = NULL },
2829 };
2830
2831 static struct clk trace_clk_div_ck = {
2832         .name           = "trace_clk_div_ck",
2833         .parent         = &pmd_trace_clk_mux_ck,
2834         .clksel         = trace_clk_div_div,
2835         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2836         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2837         .ops            = &clkops_null,
2838         .recalc         = &omap2_clksel_recalc,
2839         .round_rate     = &omap2_clksel_round_rate,
2840         .set_rate       = &omap2_clksel_set_rate,
2841 };
2842
2843 /* SCRM aux clk nodes */
2844
2845 static const struct clksel auxclk_sel[] = {
2846         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2847         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2848         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2849         { .parent = NULL },
2850 };
2851
2852 static struct clk auxclk0_ck = {
2853         .name           = "auxclk0_ck",
2854         .parent         = &sys_clkin_ck,
2855         .init           = &omap2_init_clksel_parent,
2856         .ops            = &clkops_omap2_dflt,
2857         .clksel         = auxclk_sel,
2858         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2859         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2860         .recalc         = &omap2_clksel_recalc,
2861         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2862         .enable_bit     = OMAP4_ENABLE_SHIFT,
2863 };
2864
2865 static struct clk auxclk1_ck = {
2866         .name           = "auxclk1_ck",
2867         .parent         = &sys_clkin_ck,
2868         .init           = &omap2_init_clksel_parent,
2869         .ops            = &clkops_omap2_dflt,
2870         .clksel         = auxclk_sel,
2871         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2872         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2873         .recalc         = &omap2_clksel_recalc,
2874         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2875         .enable_bit     = OMAP4_ENABLE_SHIFT,
2876 };
2877
2878 static struct clk auxclk2_ck = {
2879         .name           = "auxclk2_ck",
2880         .parent         = &sys_clkin_ck,
2881         .init           = &omap2_init_clksel_parent,
2882         .ops            = &clkops_omap2_dflt,
2883         .clksel         = auxclk_sel,
2884         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2885         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2886         .recalc         = &omap2_clksel_recalc,
2887         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2888         .enable_bit     = OMAP4_ENABLE_SHIFT,
2889 };
2890 static struct clk auxclk3_ck = {
2891         .name           = "auxclk3_ck",
2892         .parent         = &sys_clkin_ck,
2893         .init           = &omap2_init_clksel_parent,
2894         .ops            = &clkops_omap2_dflt,
2895         .clksel         = auxclk_sel,
2896         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2897         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2898         .recalc         = &omap2_clksel_recalc,
2899         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2900         .enable_bit     = OMAP4_ENABLE_SHIFT,
2901 };
2902
2903 static struct clk auxclk4_ck = {
2904         .name           = "auxclk4_ck",
2905         .parent         = &sys_clkin_ck,
2906         .init           = &omap2_init_clksel_parent,
2907         .ops            = &clkops_omap2_dflt,
2908         .clksel         = auxclk_sel,
2909         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2910         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2911         .recalc         = &omap2_clksel_recalc,
2912         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2913         .enable_bit     = OMAP4_ENABLE_SHIFT,
2914 };
2915
2916 static struct clk auxclk5_ck = {
2917         .name           = "auxclk5_ck",
2918         .parent         = &sys_clkin_ck,
2919         .init           = &omap2_init_clksel_parent,
2920         .ops            = &clkops_omap2_dflt,
2921         .clksel         = auxclk_sel,
2922         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
2923         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2924         .recalc         = &omap2_clksel_recalc,
2925         .enable_reg     = OMAP4_SCRM_AUXCLK5,
2926         .enable_bit     = OMAP4_ENABLE_SHIFT,
2927 };
2928
2929 static const struct clksel auxclkreq_sel[] = {
2930         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2931         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2932         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2933         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2934         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2935         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2936         { .parent = NULL },
2937 };
2938
2939 static struct clk auxclkreq0_ck = {
2940         .name           = "auxclkreq0_ck",
2941         .parent         = &auxclk0_ck,
2942         .init           = &omap2_init_clksel_parent,
2943         .ops            = &clkops_null,
2944         .clksel         = auxclkreq_sel,
2945         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
2946         .clksel_mask    = OMAP4_MAPPING_MASK,
2947         .recalc         = &omap2_clksel_recalc,
2948 };
2949
2950 static struct clk auxclkreq1_ck = {
2951         .name           = "auxclkreq1_ck",
2952         .parent         = &auxclk1_ck,
2953         .init           = &omap2_init_clksel_parent,
2954         .ops            = &clkops_null,
2955         .clksel         = auxclkreq_sel,
2956         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
2957         .clksel_mask    = OMAP4_MAPPING_MASK,
2958         .recalc         = &omap2_clksel_recalc,
2959 };
2960
2961 static struct clk auxclkreq2_ck = {
2962         .name           = "auxclkreq2_ck",
2963         .parent         = &auxclk2_ck,
2964         .init           = &omap2_init_clksel_parent,
2965         .ops            = &clkops_null,
2966         .clksel         = auxclkreq_sel,
2967         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
2968         .clksel_mask    = OMAP4_MAPPING_MASK,
2969         .recalc         = &omap2_clksel_recalc,
2970 };
2971
2972 static struct clk auxclkreq3_ck = {
2973         .name           = "auxclkreq3_ck",
2974         .parent         = &auxclk3_ck,
2975         .init           = &omap2_init_clksel_parent,
2976         .ops            = &clkops_null,
2977         .clksel         = auxclkreq_sel,
2978         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
2979         .clksel_mask    = OMAP4_MAPPING_MASK,
2980         .recalc         = &omap2_clksel_recalc,
2981 };
2982
2983 static struct clk auxclkreq4_ck = {
2984         .name           = "auxclkreq4_ck",
2985         .parent         = &auxclk4_ck,
2986         .init           = &omap2_init_clksel_parent,
2987         .ops            = &clkops_null,
2988         .clksel         = auxclkreq_sel,
2989         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
2990         .clksel_mask    = OMAP4_MAPPING_MASK,
2991         .recalc         = &omap2_clksel_recalc,
2992 };
2993
2994 static struct clk auxclkreq5_ck = {
2995         .name           = "auxclkreq5_ck",
2996         .parent         = &auxclk5_ck,
2997         .init           = &omap2_init_clksel_parent,
2998         .ops            = &clkops_null,
2999         .clksel         = auxclkreq_sel,
3000         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
3001         .clksel_mask    = OMAP4_MAPPING_MASK,
3002         .recalc         = &omap2_clksel_recalc,
3003 };
3004
3005 /*
3006  * clkdev
3007  */
3008
3009 static struct omap_clk omap44xx_clks[] = {
3010         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3011         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3012         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3013         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3014         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3015         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3016         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3017         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3018         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3019         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3020         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3021         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3022         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3023         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3024         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3025         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3026         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3027         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3028         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3029         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3030         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3031         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3032         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3033         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3034         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3035         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3036         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3037         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3038         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3039         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3040         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3041         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3042         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3043         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3044         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3045         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3046         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3047         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3048         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3049         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3050         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3051         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3052         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3053         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3054         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3055         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3056         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3057         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3058         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3059         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3060         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3061         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3062         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3063         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3064         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3065         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3066         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3067         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3068         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3069         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3070         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3071         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3072         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
3073         CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
3074         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
3075         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3076         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3077         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3078         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3079         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3080         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3081         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3082         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3083         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3084         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3085         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3086         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3087         CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
3088         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3089         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3090         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3091         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3092         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3093         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3094         CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
3095         CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
3096         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3097         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3098         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3099         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3100         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3101         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3102         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3103         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3104         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3105         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3106         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3107         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3108         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3109         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
3110         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
3111         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
3112         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
3113         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
3114         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3115         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3116         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3117         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3118         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3119         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3120         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3121         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3122         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3123         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3124         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3125         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3126         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3127         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3128         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3129         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3130         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3131         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3132         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3133         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
3134         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3135         CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
3136         CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
3137         CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
3138         CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
3139         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3140         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3141         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3142         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3143         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3144         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3145         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3146         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3147         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3148         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3149         CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_fck,    CK_443X),
3150         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3151         CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_fck,    CK_443X),
3152         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3153         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
3154         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3155         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
3156         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3157         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
3158         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
3159         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
3160         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
3161         CLK("mmci-omap-hs.0",   "fck",                          &mmc1_fck,      CK_443X),
3162         CLK("mmci-omap-hs.1",   "fck",                          &mmc2_fck,      CK_443X),
3163         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
3164         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
3165         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
3166         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3167         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3168         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3169         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3170         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3171         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3172         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3173         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3174         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3175         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3176         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3177         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3178         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3179         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3180         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3181         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3182         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3183         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3184         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3185         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3186         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3187         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3188         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3189         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3190         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3191         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3192         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3193         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3194         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3195         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3196         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3197         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3198         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3199         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
3200         CLK("ehci-omap.0",      "fs_fck",               &usb_host_fs_fck,       CK_443X),
3201         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3202         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3203         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3204         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3205         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3206         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3207         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3208         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3209         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3210         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3211         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
3212         CLK("ehci-omap.0",      "hs_fck",               &usb_host_hs_fck,       CK_443X),
3213         CLK("ehci-omap.0",      "usbhost_ick",          &dummy_ck,              CK_443X),
3214         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3215         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3216         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
3217         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3218         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3219         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3220         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3221         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
3222         CLK("ehci-omap.0",      "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
3223         CLK("ehci-omap.0",      "usbtll_fck",           &dummy_ck,      CK_443X),
3224         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3225         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3226         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3227         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
3228         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3229         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3230         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3231         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3232         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3233         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
3234         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
3235         CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
3236         CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
3237         CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
3238         CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
3239         CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
3240         CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
3241         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
3242         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
3243         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
3244         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3245         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3246         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3247         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3248         CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
3249         CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
3250         CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
3251         CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
3252         CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
3253         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3254         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3255         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3256         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3257         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3258         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3259         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3260         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3261         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3262         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3263         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3264         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3265         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3266         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3267         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3268         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3269         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3270         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3271         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3272         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3273         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3274         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3275         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3276         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3277         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3278 };
3279
3280 int __init omap4xxx_clk_init(void)
3281 {
3282         struct omap_clk *c;
3283         u32 cpu_clkflg;
3284
3285         if (cpu_is_omap44xx()) {
3286                 cpu_mask = RATE_IN_4430;
3287                 cpu_clkflg = CK_443X;
3288         }
3289
3290         clk_init(&omap2_clk_functions);
3291
3292         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3293                                                                           c++)
3294                 clk_preinit(c->lk.clk);
3295
3296         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3297                                                                           c++)
3298                 if (c->cpu & cpu_clkflg) {
3299                         clkdev_add(&c->lk);
3300                         clk_register(c->lk.clk);
3301                         omap2_init_clk_clkdm(c->lk.clk);
3302                 }
3303
3304         recalculate_root_clocks();
3305
3306         /*
3307          * Only enable those clocks we will need, let the drivers
3308          * enable other clocks as necessary
3309          */
3310         clk_enable_init_clocks();
3311
3312         return 0;
3313 }