arch/arm/mach-omap2/clock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX Some of the ES1 clocks have been removed/changed; once support
  22  * is added for discriminating clocks by ES level, these should be added back
  23  * in.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/clk.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "clock44xx.h"
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39 #include "scrm44xx.h"
  40
  41 /* OMAP4 modulemode control */
  42 #define OMAP4430_MODULEMODE_HWCTRL                      0
  43 #define OMAP4430_MODULEMODE_SWCTRL                      1
  44
  45 /* Root clocks */
  46
  47 static struct clk extalt_clkin_ck = {
  48         .name           = "extalt_clkin_ck",
  49         .rate           = 59000000,
  50         .ops            = &clkops_null,
  51 };
  52
  53 static struct clk pad_clks_ck = {
  54         .name           = "pad_clks_ck",
  55         .rate           = 12000000,
  56         .ops            = &clkops_omap2_dflt,
  57         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  58         .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
  59 };
  60
  61 static struct clk pad_slimbus_core_clks_ck = {
  62         .name           = "pad_slimbus_core_clks_ck",
  63         .rate           = 12000000,
  64         .ops            = &clkops_null,
  65 };
  66
  67 static struct clk secure_32k_clk_src_ck = {
  68         .name           = "secure_32k_clk_src_ck",
  69         .rate           = 32768,
  70         .ops            = &clkops_null,
  71 };
  72
  73 static struct clk slimbus_clk = {
  74         .name           = "slimbus_clk",
  75         .rate           = 12000000,
  76         .ops            = &clkops_omap2_dflt,
  77         .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
  78         .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  79 };
  80
  81 static struct clk sys_32k_ck = {
  82         .name           = "sys_32k_ck",
  83         .rate           = 32768,
  84         .ops            = &clkops_null,
  85 };
  86
  87 static struct clk virt_12000000_ck = {
  88         .name           = "virt_12000000_ck",
  89         .ops            = &clkops_null,
  90         .rate           = 12000000,
  91 };
  92
  93 static struct clk virt_13000000_ck = {
  94         .name           = "virt_13000000_ck",
  95         .ops            = &clkops_null,
  96         .rate           = 13000000,
  97 };
  98
  99 static struct clk virt_16800000_ck = {
 100         .name           = "virt_16800000_ck",
 101         .ops            = &clkops_null,
 102         .rate           = 16800000,
 103 };
 104
 105 static struct clk virt_19200000_ck = {
 106         .name           = "virt_19200000_ck",
 107         .ops            = &clkops_null,
 108         .rate           = 19200000,
 109 };
 110
 111 static struct clk virt_26000000_ck = {
 112         .name           = "virt_26000000_ck",
 113         .ops            = &clkops_null,
 114         .rate           = 26000000,
 115 };
 116
 117 static struct clk virt_27000000_ck = {
 118         .name           = "virt_27000000_ck",
 119         .ops            = &clkops_null,
 120         .rate           = 27000000,
 121 };
 122
 123 static struct clk virt_38400000_ck = {
 124         .name           = "virt_38400000_ck",
 125         .ops            = &clkops_null,
 126         .rate           = 38400000,
 127 };
 128
 129 static const struct clksel_rate div_1_0_rates[] = {
 130         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 131         { .div = 0 },
 132 };
 133
 134 static const struct clksel_rate div_1_1_rates[] = {
 135         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 136         { .div = 0 },
 137 };
 138
 139 static const struct clksel_rate div_1_2_rates[] = {
 140         { .div = 1, .val = 2, .flags = RATE_IN_4430 },
 141         { .div = 0 },
 142 };
 143
 144 static const struct clksel_rate div_1_3_rates[] = {
 145         { .div = 1, .val = 3, .flags = RATE_IN_4430 },
 146         { .div = 0 },
 147 };
 148
 149 static const struct clksel_rate div_1_4_rates[] = {
 150         { .div = 1, .val = 4, .flags = RATE_IN_4430 },
 151         { .div = 0 },
 152 };
 153
 154 static const struct clksel_rate div_1_5_rates[] = {
 155         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
 156         { .div = 0 },
 157 };
 158
 159 static const struct clksel_rate div_1_6_rates[] = {
 160         { .div = 1, .val = 6, .flags = RATE_IN_4430 },
 161         { .div = 0 },
 162 };
 163
 164 static const struct clksel_rate div_1_7_rates[] = {
 165         { .div = 1, .val = 7, .flags = RATE_IN_4430 },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel sys_clkin_sel[] = {
 170         { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
 171         { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
 172         { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
 173         { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
 174         { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
 175         { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
 176         { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk sys_clkin_ck = {
 181         .name           = "sys_clkin_ck",
 182         .rate           = 38400000,
 183         .clksel         = sys_clkin_sel,
 184         .init           = &omap2_init_clksel_parent,
 185         .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
 186         .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
 187         .ops            = &clkops_null,
 188         .recalc         = &omap2_clksel_recalc,
 189 };
 190
 191 static struct clk tie_low_clock_ck = {
 192         .name           = "tie_low_clock_ck",
 193         .rate           = 0,
 194         .ops            = &clkops_null,
 195 };
 196
 197 static struct clk utmi_phy_clkout_ck = {
 198         .name           = "utmi_phy_clkout_ck",
 199         .rate           = 60000000,
 200         .ops            = &clkops_null,
 201 };
 202
 203 static struct clk xclk60mhsp1_ck = {
 204         .name           = "xclk60mhsp1_ck",
 205         .rate           = 60000000,
 206         .ops            = &clkops_null,
 207 };
 208
 209 static struct clk xclk60mhsp2_ck = {
 210         .name           = "xclk60mhsp2_ck",
 211         .rate           = 60000000,
 212         .ops            = &clkops_null,
 213 };
 214
 215 static struct clk xclk60motg_ck = {
 216         .name           = "xclk60motg_ck",
 217         .rate           = 60000000,
 218         .ops            = &clkops_null,
 219 };
 220
 221 /* Module clocks and DPLL outputs */
 222
 223 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
 224         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 225         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
 226         { .parent = NULL },
 227 };
 228
 229 static struct clk abe_dpll_bypass_clk_mux_ck = {
 230         .name           = "abe_dpll_bypass_clk_mux_ck",
 231         .parent         = &sys_clkin_ck,
 232         .ops            = &clkops_null,
 233         .recalc         = &followparent_recalc,
 234 };
 235
 236 static struct clk abe_dpll_refclk_mux_ck = {
 237         .name           = "abe_dpll_refclk_mux_ck",
 238         .parent         = &sys_clkin_ck,
 239         .clksel         = abe_dpll_bypass_clk_mux_sel,
 240         .init           = &omap2_init_clksel_parent,
 241         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
 242         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
 243         .ops            = &clkops_null,
 244         .recalc         = &omap2_clksel_recalc,
 245 };
 246
 247 /* DPLL_ABE */
 248 static struct dpll_data dpll_abe_dd = {
 249         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 250         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 251         .clk_ref        = &abe_dpll_refclk_mux_ck,
 252         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 253         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 254         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 255         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 256         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 257         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 258         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 259         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 260         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 261         .max_multiplier = 2047,
 262         .max_divider    = 128,
 263         .min_divider    = 1,
 264 };
 265
 266
 267 static struct clk dpll_abe_ck = {
 268         .name           = "dpll_abe_ck",
 269         .parent         = &abe_dpll_refclk_mux_ck,
 270         .dpll_data      = &dpll_abe_dd,
 271         .init           = &omap2_init_dpll_parent,
 272         .ops            = &clkops_omap3_noncore_dpll_ops,
 273         .recalc         = &omap4_dpll_regm4xen_recalc,
 274         .round_rate     = &omap4_dpll_regm4xen_round_rate,
 275         .set_rate       = &omap3_noncore_dpll_set_rate,
 276 };
 277
 278 static struct clk dpll_abe_x2_ck = {
 279         .name           = "dpll_abe_x2_ck",
 280         .parent         = &dpll_abe_ck,
 281         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 282         .flags          = CLOCK_CLKOUTX2,
 283         .ops            = &clkops_omap4_dpllmx_ops,
 284         .recalc         = &omap3_clkoutx2_recalc,
 285 };
 286
 287 static const struct clksel_rate div31_1to31_rates[] = {
 288         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
 289         { .div = 2, .val = 2, .flags = RATE_IN_4430 },
 290         { .div = 3, .val = 3, .flags = RATE_IN_4430 },
 291         { .div = 4, .val = 4, .flags = RATE_IN_4430 },
 292         { .div = 5, .val = 5, .flags = RATE_IN_4430 },
 293         { .div = 6, .val = 6, .flags = RATE_IN_4430 },
 294         { .div = 7, .val = 7, .flags = RATE_IN_4430 },
 295         { .div = 8, .val = 8, .flags = RATE_IN_4430 },
 296         { .div = 9, .val = 9, .flags = RATE_IN_4430 },
 297         { .div = 10, .val = 10, .flags = RATE_IN_4430 },
 298         { .div = 11, .val = 11, .flags = RATE_IN_4430 },
 299         { .div = 12, .val = 12, .flags = RATE_IN_4430 },
 300         { .div = 13, .val = 13, .flags = RATE_IN_4430 },
 301         { .div = 14, .val = 14, .flags = RATE_IN_4430 },
 302         { .div = 15, .val = 15, .flags = RATE_IN_4430 },
 303         { .div = 16, .val = 16, .flags = RATE_IN_4430 },
 304         { .div = 17, .val = 17, .flags = RATE_IN_4430 },
 305         { .div = 18, .val = 18, .flags = RATE_IN_4430 },
 306         { .div = 19, .val = 19, .flags = RATE_IN_4430 },
 307         { .div = 20, .val = 20, .flags = RATE_IN_4430 },
 308         { .div = 21, .val = 21, .flags = RATE_IN_4430 },
 309         { .div = 22, .val = 22, .flags = RATE_IN_4430 },
 310         { .div = 23, .val = 23, .flags = RATE_IN_4430 },
 311         { .div = 24, .val = 24, .flags = RATE_IN_4430 },
 312         { .div = 25, .val = 25, .flags = RATE_IN_4430 },
 313         { .div = 26, .val = 26, .flags = RATE_IN_4430 },
 314         { .div = 27, .val = 27, .flags = RATE_IN_4430 },
 315         { .div = 28, .val = 28, .flags = RATE_IN_4430 },
 316         { .div = 29, .val = 29, .flags = RATE_IN_4430 },
 317         { .div = 30, .val = 30, .flags = RATE_IN_4430 },
 318         { .div = 31, .val = 31, .flags = RATE_IN_4430 },
 319         { .div = 0 },
 320 };
 321
 322 static const struct clksel dpll_abe_m2x2_div[] = {
 323         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
 324         { .parent = NULL },
 325 };
 326
 327 static struct clk dpll_abe_m2x2_ck = {
 328         .name           = "dpll_abe_m2x2_ck",
 329         .parent         = &dpll_abe_x2_ck,
 330         .clksel         = dpll_abe_m2x2_div,
 331         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 332         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 333         .ops            = &clkops_omap4_dpllmx_ops,
 334         .recalc         = &omap2_clksel_recalc,
 335         .round_rate     = &omap2_clksel_round_rate,
 336         .set_rate       = &omap2_clksel_set_rate,
 337 };
 338
 339 static struct clk abe_24m_fclk = {
 340         .name           = "abe_24m_fclk",
 341         .parent         = &dpll_abe_m2x2_ck,
 342         .ops            = &clkops_null,
 343         .fixed_div      = 8,
 344         .recalc         = &omap_fixed_divisor_recalc,
 345 };
 346
 347 static const struct clksel_rate div3_1to4_rates[] = {
 348         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 349         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 350         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 351         { .div = 0 },
 352 };
 353
 354 static const struct clksel abe_clk_div[] = {
 355         { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
 356         { .parent = NULL },
 357 };
 358
 359 static struct clk abe_clk = {
 360         .name           = "abe_clk",
 361         .parent         = &dpll_abe_m2x2_ck,
 362         .clksel         = abe_clk_div,
 363         .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
 364         .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
 365         .ops            = &clkops_null,
 366         .recalc         = &omap2_clksel_recalc,
 367         .round_rate     = &omap2_clksel_round_rate,
 368         .set_rate       = &omap2_clksel_set_rate,
 369 };
 370
 371 static const struct clksel_rate div2_1to2_rates[] = {
 372         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 373         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 374         { .div = 0 },
 375 };
 376
 377 static const struct clksel aess_fclk_div[] = {
 378         { .parent = &abe_clk, .rates = div2_1to2_rates },
 379         { .parent = NULL },
 380 };
 381
 382 static struct clk aess_fclk = {
 383         .name           = "aess_fclk",
 384         .parent         = &abe_clk,
 385         .clksel         = aess_fclk_div,
 386         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 387         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
 388         .ops            = &clkops_null,
 389         .recalc         = &omap2_clksel_recalc,
 390         .round_rate     = &omap2_clksel_round_rate,
 391         .set_rate       = &omap2_clksel_set_rate,
 392 };
 393
 394 static struct clk dpll_abe_m3x2_ck = {
 395         .name           = "dpll_abe_m3x2_ck",
 396         .parent         = &dpll_abe_x2_ck,
 397         .clksel         = dpll_abe_m2x2_div,
 398         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
 399         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 400         .ops            = &clkops_omap4_dpllmx_ops,
 401         .recalc         = &omap2_clksel_recalc,
 402         .round_rate     = &omap2_clksel_round_rate,
 403         .set_rate       = &omap2_clksel_set_rate,
 404 };
 405
 406 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
 407         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 408         { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
 409         { .parent = NULL },
 410 };
 411
 412 static struct clk core_hsd_byp_clk_mux_ck = {
 413         .name           = "core_hsd_byp_clk_mux_ck",
 414         .parent         = &sys_clkin_ck,
 415         .clksel         = core_hsd_byp_clk_mux_sel,
 416         .init           = &omap2_init_clksel_parent,
 417         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
 418         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 419         .ops            = &clkops_null,
 420         .recalc         = &omap2_clksel_recalc,
 421 };
 422
 423 /* DPLL_CORE */
 424 static struct dpll_data dpll_core_dd = {
 425         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 426         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 427         .clk_ref        = &sys_clkin_ck,
 428         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 429         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 430         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 431         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 432         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 433         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 434         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 435         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 436         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 437         .max_multiplier = 2047,
 438         .max_divider    = 128,
 439         .min_divider    = 1,
 440 };
 441
 442
 443 static struct clk dpll_core_ck = {
 444         .name           = "dpll_core_ck",
 445         .parent         = &sys_clkin_ck,
 446         .dpll_data      = &dpll_core_dd,
 447         .init           = &omap2_init_dpll_parent,
 448         .ops            = &clkops_omap3_core_dpll_ops,
 449         .recalc         = &omap3_dpll_recalc,
 450 };
 451
 452 static struct clk dpll_core_x2_ck = {
 453         .name           = "dpll_core_x2_ck",
 454         .parent         = &dpll_core_ck,
 455         .flags          = CLOCK_CLKOUTX2,
 456         .ops            = &clkops_null,
 457         .recalc         = &omap3_clkoutx2_recalc,
 458 };
 459
 460 static const struct clksel dpll_core_m6x2_div[] = {
 461         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 462         { .parent = NULL },
 463 };
 464
 465 static struct clk dpll_core_m6x2_ck = {
 466         .name           = "dpll_core_m6x2_ck",
 467         .parent         = &dpll_core_x2_ck,
 468         .clksel         = dpll_core_m6x2_div,
 469         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
 470         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 471         .ops            = &clkops_omap4_dpllmx_ops,
 472         .recalc         = &omap2_clksel_recalc,
 473         .round_rate     = &omap2_clksel_round_rate,
 474         .set_rate       = &omap2_clksel_set_rate,
 475 };
 476
 477 static const struct clksel dbgclk_mux_sel[] = {
 478         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 479         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
 480         { .parent = NULL },
 481 };
 482
 483 static struct clk dbgclk_mux_ck = {
 484         .name           = "dbgclk_mux_ck",
 485         .parent         = &sys_clkin_ck,
 486         .ops            = &clkops_null,
 487         .recalc         = &followparent_recalc,
 488 };
 489
 490 static const struct clksel dpll_core_m2_div[] = {
 491         { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
 492         { .parent = NULL },
 493 };
 494
 495 static struct clk dpll_core_m2_ck = {
 496         .name           = "dpll_core_m2_ck",
 497         .parent         = &dpll_core_ck,
 498         .clksel         = dpll_core_m2_div,
 499         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
 500         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 501         .ops            = &clkops_omap4_dpllmx_ops,
 502         .recalc         = &omap2_clksel_recalc,
 503         .round_rate     = &omap2_clksel_round_rate,
 504         .set_rate       = &omap2_clksel_set_rate,
 505 };
 506
 507 static struct clk ddrphy_ck = {
 508         .name           = "ddrphy_ck",
 509         .parent         = &dpll_core_m2_ck,
 510         .ops            = &clkops_null,
 511         .fixed_div      = 2,
 512         .recalc         = &omap_fixed_divisor_recalc,
 513 };
 514
 515 static struct clk dpll_core_m5x2_ck = {
 516         .name           = "dpll_core_m5x2_ck",
 517         .parent         = &dpll_core_x2_ck,
 518         .clksel         = dpll_core_m6x2_div,
 519         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
 520         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 521         .ops            = &clkops_omap4_dpllmx_ops,
 522         .recalc         = &omap2_clksel_recalc,
 523         .round_rate     = &omap2_clksel_round_rate,
 524         .set_rate       = &omap2_clksel_set_rate,
 525 };
 526
 527 static const struct clksel div_core_div[] = {
 528         { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 529         { .parent = NULL },
 530 };
 531
 532 static struct clk div_core_ck = {
 533         .name           = "div_core_ck",
 534         .parent         = &dpll_core_m5x2_ck,
 535         .clksel         = div_core_div,
 536         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
 537         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
 538         .ops            = &clkops_null,
 539         .recalc         = &omap2_clksel_recalc,
 540         .round_rate     = &omap2_clksel_round_rate,
 541         .set_rate       = &omap2_clksel_set_rate,
 542 };
 543
 544 static const struct clksel_rate div4_1to8_rates[] = {
 545         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
 546         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
 547         { .div = 4, .val = 2, .flags = RATE_IN_4430 },
 548         { .div = 8, .val = 3, .flags = RATE_IN_4430 },
 549         { .div = 0 },
 550 };
 551
 552 static const struct clksel div_iva_hs_clk_div[] = {
 553         { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 554         { .parent = NULL },
 555 };
 556
 557 static struct clk div_iva_hs_clk = {
 558         .name           = "div_iva_hs_clk",
 559         .parent         = &dpll_core_m5x2_ck,
 560         .clksel         = div_iva_hs_clk_div,
 561         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
 562         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 563         .ops            = &clkops_null,
 564         .recalc         = &omap2_clksel_recalc,
 565         .round_rate     = &omap2_clksel_round_rate,
 566         .set_rate       = &omap2_clksel_set_rate,
 567 };
 568
 569 static struct clk div_mpu_hs_clk = {
 570         .name           = "div_mpu_hs_clk",
 571         .parent         = &dpll_core_m5x2_ck,
 572         .clksel         = div_iva_hs_clk_div,
 573         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
 574         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
 575         .ops            = &clkops_null,
 576         .recalc         = &omap2_clksel_recalc,
 577         .round_rate     = &omap2_clksel_round_rate,
 578         .set_rate       = &omap2_clksel_set_rate,
 579 };
 580
 581 static struct clk dpll_core_m4x2_ck = {
 582         .name           = "dpll_core_m4x2_ck",
 583         .parent         = &dpll_core_x2_ck,
 584         .clksel         = dpll_core_m6x2_div,
 585         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
 586         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 587         .ops            = &clkops_omap4_dpllmx_ops,
 588         .recalc         = &omap2_clksel_recalc,
 589         .round_rate     = &omap2_clksel_round_rate,
 590         .set_rate       = &omap2_clksel_set_rate,
 591 };
 592
 593 static struct clk dll_clk_div_ck = {
 594         .name           = "dll_clk_div_ck",
 595         .parent         = &dpll_core_m4x2_ck,
 596         .ops            = &clkops_null,
 597         .fixed_div      = 2,
 598         .recalc         = &omap_fixed_divisor_recalc,
 599 };
 600
 601 static const struct clksel dpll_abe_m2_div[] = {
 602         { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
 603         { .parent = NULL },
 604 };
 605
 606 static struct clk dpll_abe_m2_ck = {
 607         .name           = "dpll_abe_m2_ck",
 608         .parent         = &dpll_abe_ck,
 609         .clksel         = dpll_abe_m2_div,
 610         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 611         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 612         .ops            = &clkops_omap4_dpllmx_ops,
 613         .recalc         = &omap2_clksel_recalc,
 614         .round_rate     = &omap2_clksel_round_rate,
 615         .set_rate       = &omap2_clksel_set_rate,
 616 };
 617
 618 static struct clk dpll_core_m3x2_ck = {
 619         .name           = "dpll_core_m3x2_ck",
 620         .parent         = &dpll_core_x2_ck,
 621         .clksel         = dpll_core_m6x2_div,
 622         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 623         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 624         .ops            = &clkops_omap2_dflt,
 625         .recalc         = &omap2_clksel_recalc,
 626         .round_rate     = &omap2_clksel_round_rate,
 627         .set_rate       = &omap2_clksel_set_rate,
 628         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
 629         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 630 };
 631
 632 static struct clk dpll_core_m7x2_ck = {
 633         .name           = "dpll_core_m7x2_ck",
 634         .parent         = &dpll_core_x2_ck,
 635         .clksel         = dpll_core_m6x2_div,
 636         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
 637         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 638         .ops            = &clkops_omap4_dpllmx_ops,
 639         .recalc         = &omap2_clksel_recalc,
 640         .round_rate     = &omap2_clksel_round_rate,
 641         .set_rate       = &omap2_clksel_set_rate,
 642 };
 643
 644 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 645         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 646         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
 647         { .parent = NULL },
 648 };
 649
 650 static struct clk iva_hsd_byp_clk_mux_ck = {
 651         .name           = "iva_hsd_byp_clk_mux_ck",
 652         .parent         = &sys_clkin_ck,
 653         .clksel         = iva_hsd_byp_clk_mux_sel,
 654         .init           = &omap2_init_clksel_parent,
 655         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
 656         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 657         .ops            = &clkops_null,
 658         .recalc         = &omap2_clksel_recalc,
 659 };
 660
 661 /* DPLL_IVA */
 662 static struct dpll_data dpll_iva_dd = {
 663         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 664         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 665         .clk_ref        = &sys_clkin_ck,
 666         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 667         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 668         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 669         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 670         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 671         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 672         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 673         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 674         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 675         .max_multiplier = 2047,
 676         .max_divider    = 128,
 677         .min_divider    = 1,
 678 };
 679
 680
 681 static struct clk dpll_iva_ck = {
 682         .name           = "dpll_iva_ck",
 683         .parent         = &sys_clkin_ck,
 684         .dpll_data      = &dpll_iva_dd,
 685         .init           = &omap2_init_dpll_parent,
 686         .ops            = &clkops_omap3_noncore_dpll_ops,
 687         .recalc         = &omap3_dpll_recalc,
 688         .round_rate     = &omap2_dpll_round_rate,
 689         .set_rate       = &omap3_noncore_dpll_set_rate,
 690 };
 691
 692 static struct clk dpll_iva_x2_ck = {
 693         .name           = "dpll_iva_x2_ck",
 694         .parent         = &dpll_iva_ck,
 695         .flags          = CLOCK_CLKOUTX2,
 696         .ops            = &clkops_null,
 697         .recalc         = &omap3_clkoutx2_recalc,
 698 };
 699
 700 static const struct clksel dpll_iva_m4x2_div[] = {
 701         { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
 702         { .parent = NULL },
 703 };
 704
 705 static struct clk dpll_iva_m4x2_ck = {
 706         .name           = "dpll_iva_m4x2_ck",
 707         .parent         = &dpll_iva_x2_ck,
 708         .clksel         = dpll_iva_m4x2_div,
 709         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
 710         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 711         .ops            = &clkops_omap4_dpllmx_ops,
 712         .recalc         = &omap2_clksel_recalc,
 713         .round_rate     = &omap2_clksel_round_rate,
 714         .set_rate       = &omap2_clksel_set_rate,
 715 };
 716
 717 static struct clk dpll_iva_m5x2_ck = {
 718         .name           = "dpll_iva_m5x2_ck",
 719         .parent         = &dpll_iva_x2_ck,
 720         .clksel         = dpll_iva_m4x2_div,
 721         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
 722         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 723         .ops            = &clkops_omap4_dpllmx_ops,
 724         .recalc         = &omap2_clksel_recalc,
 725         .round_rate     = &omap2_clksel_round_rate,
 726         .set_rate       = &omap2_clksel_set_rate,
 727 };
 728
 729 /* DPLL_MPU */
 730 static struct dpll_data dpll_mpu_dd = {
 731         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 732         .clk_bypass     = &div_mpu_hs_clk,
 733         .clk_ref        = &sys_clkin_ck,
 734         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 735         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 736         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 737         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 738         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 739         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 740         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 741         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 742         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 743         .max_multiplier = 2047,
 744         .max_divider    = 128,
 745         .min_divider    = 1,
 746 };
 747
 748
 749 static struct clk dpll_mpu_ck = {
 750         .name           = "dpll_mpu_ck",
 751         .parent         = &sys_clkin_ck,
 752         .dpll_data      = &dpll_mpu_dd,
 753         .init           = &omap2_init_dpll_parent,
 754         .ops            = &clkops_omap3_noncore_dpll_ops,
 755         .recalc         = &omap3_dpll_recalc,
 756         .round_rate     = &omap2_dpll_round_rate,
 757         .set_rate       = &omap3_noncore_dpll_set_rate,
 758 };
 759
 760 static const struct clksel dpll_mpu_m2_div[] = {
 761         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
 762         { .parent = NULL },
 763 };
 764
 765 static struct clk dpll_mpu_m2_ck = {
 766         .name           = "dpll_mpu_m2_ck",
 767         .parent         = &dpll_mpu_ck,
 768         .clksel         = dpll_mpu_m2_div,
 769         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
 770         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 771         .ops            = &clkops_omap4_dpllmx_ops,
 772         .recalc         = &omap2_clksel_recalc,
 773         .round_rate     = &omap2_clksel_round_rate,
 774         .set_rate       = &omap2_clksel_set_rate,
 775 };
 776
 777 static struct clk per_hs_clk_div_ck = {
 778         .name           = "per_hs_clk_div_ck",
 779         .parent         = &dpll_abe_m3x2_ck,
 780         .ops            = &clkops_null,
 781         .fixed_div      = 2,
 782         .recalc         = &omap_fixed_divisor_recalc,
 783 };
 784
 785 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
 786         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 787         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
 788         { .parent = NULL },
 789 };
 790
 791 static struct clk per_hsd_byp_clk_mux_ck = {
 792         .name           = "per_hsd_byp_clk_mux_ck",
 793         .parent         = &sys_clkin_ck,
 794         .clksel         = per_hsd_byp_clk_mux_sel,
 795         .init           = &omap2_init_clksel_parent,
 796         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
 797         .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
 798         .ops            = &clkops_null,
 799         .recalc         = &omap2_clksel_recalc,
 800 };
 801
 802 /* DPLL_PER */
 803 static struct dpll_data dpll_per_dd = {
 804         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 805         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 806         .clk_ref        = &sys_clkin_ck,
 807         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 808         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 809         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 810         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 811         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 812         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 813         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 814         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 815         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 816         .max_multiplier = 2047,
 817         .max_divider    = 128,
 818         .min_divider    = 1,
 819 };
 820
 821
 822 static struct clk dpll_per_ck = {
 823         .name           = "dpll_per_ck",
 824         .parent         = &sys_clkin_ck,
 825         .dpll_data      = &dpll_per_dd,
 826         .init           = &omap2_init_dpll_parent,
 827         .ops            = &clkops_omap3_noncore_dpll_ops,
 828         .recalc         = &omap3_dpll_recalc,
 829         .round_rate     = &omap2_dpll_round_rate,
 830         .set_rate       = &omap3_noncore_dpll_set_rate,
 831 };
 832
 833 static const struct clksel dpll_per_m2_div[] = {
 834         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
 835         { .parent = NULL },
 836 };
 837
 838 static struct clk dpll_per_m2_ck = {
 839         .name           = "dpll_per_m2_ck",
 840         .parent         = &dpll_per_ck,
 841         .clksel         = dpll_per_m2_div,
 842         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 843         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 844         .ops            = &clkops_omap4_dpllmx_ops,
 845         .recalc         = &omap2_clksel_recalc,
 846         .round_rate     = &omap2_clksel_round_rate,
 847         .set_rate       = &omap2_clksel_set_rate,
 848 };
 849
 850 static struct clk dpll_per_x2_ck = {
 851         .name           = "dpll_per_x2_ck",
 852         .parent         = &dpll_per_ck,
 853         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 854         .flags          = CLOCK_CLKOUTX2,
 855         .ops            = &clkops_omap4_dpllmx_ops,
 856         .recalc         = &omap3_clkoutx2_recalc,
 857 };
 858
 859 static const struct clksel dpll_per_m2x2_div[] = {
 860         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 861         { .parent = NULL },
 862 };
 863
 864 static struct clk dpll_per_m2x2_ck = {
 865         .name           = "dpll_per_m2x2_ck",
 866         .parent         = &dpll_per_x2_ck,
 867         .clksel         = dpll_per_m2x2_div,
 868         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 869         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
 870         .ops            = &clkops_omap4_dpllmx_ops,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate,
 874 };
 875
 876 static struct clk dpll_per_m3x2_ck = {
 877         .name           = "dpll_per_m3x2_ck",
 878         .parent         = &dpll_per_x2_ck,
 879         .clksel         = dpll_per_m2x2_div,
 880         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 881         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 882         .ops            = &clkops_omap2_dflt,
 883         .recalc         = &omap2_clksel_recalc,
 884         .round_rate     = &omap2_clksel_round_rate,
 885         .set_rate       = &omap2_clksel_set_rate,
 886         .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
 887         .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
 888 };
 889
 890 static struct clk dpll_per_m4x2_ck = {
 891         .name           = "dpll_per_m4x2_ck",
 892         .parent         = &dpll_per_x2_ck,
 893         .clksel         = dpll_per_m2x2_div,
 894         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
 895         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
 896         .ops            = &clkops_omap4_dpllmx_ops,
 897         .recalc         = &omap2_clksel_recalc,
 898         .round_rate     = &omap2_clksel_round_rate,
 899         .set_rate       = &omap2_clksel_set_rate,
 900 };
 901
 902 static struct clk dpll_per_m5x2_ck = {
 903         .name           = "dpll_per_m5x2_ck",
 904         .parent         = &dpll_per_x2_ck,
 905         .clksel         = dpll_per_m2x2_div,
 906         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
 907         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
 908         .ops            = &clkops_omap4_dpllmx_ops,
 909         .recalc         = &omap2_clksel_recalc,
 910         .round_rate     = &omap2_clksel_round_rate,
 911         .set_rate       = &omap2_clksel_set_rate,
 912 };
 913
 914 static struct clk dpll_per_m6x2_ck = {
 915         .name           = "dpll_per_m6x2_ck",
 916         .parent         = &dpll_per_x2_ck,
 917         .clksel         = dpll_per_m2x2_div,
 918         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
 919         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
 920         .ops            = &clkops_omap4_dpllmx_ops,
 921         .recalc         = &omap2_clksel_recalc,
 922         .round_rate     = &omap2_clksel_round_rate,
 923         .set_rate       = &omap2_clksel_set_rate,
 924 };
 925
 926 static struct clk dpll_per_m7x2_ck = {
 927         .name           = "dpll_per_m7x2_ck",
 928         .parent         = &dpll_per_x2_ck,
 929         .clksel         = dpll_per_m2x2_div,
 930         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
 931         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
 932         .ops            = &clkops_omap4_dpllmx_ops,
 933         .recalc         = &omap2_clksel_recalc,
 934         .round_rate     = &omap2_clksel_round_rate,
 935         .set_rate       = &omap2_clksel_set_rate,
 936 };
 937
 938 static struct clk usb_hs_clk_div_ck = {
 939         .name           = "usb_hs_clk_div_ck",
 940         .parent         = &dpll_abe_m3x2_ck,
 941         .ops            = &clkops_null,
 942         .fixed_div      = 3,
 943         .recalc         = &omap_fixed_divisor_recalc,
 944 };
 945
 946 /* DPLL_USB */
 947 static struct dpll_data dpll_usb_dd = {
 948         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 949         .clk_bypass     = &usb_hs_clk_div_ck,
 950         .flags          = DPLL_J_TYPE,
 951         .clk_ref        = &sys_clkin_ck,
 952         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 953         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 954         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 955         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 956         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 957         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 958         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 959         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 960         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 961         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 962         .max_multiplier = 4095,
 963         .max_divider    = 256,
 964         .min_divider    = 1,
 965 };
 966
 967
 968 static struct clk dpll_usb_ck = {
 969         .name           = "dpll_usb_ck",
 970         .parent         = &sys_clkin_ck,
 971         .dpll_data      = &dpll_usb_dd,
 972         .init           = &omap2_init_dpll_parent,
 973         .ops            = &clkops_omap3_noncore_dpll_ops,
 974         .recalc         = &omap3_dpll_recalc,
 975         .round_rate     = &omap2_dpll_round_rate,
 976         .set_rate       = &omap3_noncore_dpll_set_rate,
 977 };
 978
 979 static struct clk dpll_usb_clkdcoldo_ck = {
 980         .name           = "dpll_usb_clkdcoldo_ck",
 981         .parent         = &dpll_usb_ck,
 982         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 983         .ops            = &clkops_omap4_dpllmx_ops,
 984         .recalc         = &followparent_recalc,
 985 };
 986
 987 static const struct clksel dpll_usb_m2_div[] = {
 988         { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
 989         { .parent = NULL },
 990 };
 991
 992 static struct clk dpll_usb_m2_ck = {
 993         .name           = "dpll_usb_m2_ck",
 994         .parent         = &dpll_usb_ck,
 995         .clksel         = dpll_usb_m2_div,
 996         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
 997         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
 998         .ops            = &clkops_omap4_dpllmx_ops,
 999         .recalc         = &omap2_clksel_recalc,
1000         .round_rate     = &omap2_clksel_round_rate,
1001         .set_rate       = &omap2_clksel_set_rate,
1002 };
1003
1004 static const struct clksel ducati_clk_mux_sel[] = {
1005         { .parent = &div_core_ck, .rates = div_1_0_rates },
1006         { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1007         { .parent = NULL },
1008 };
1009
1010 static struct clk ducati_clk_mux_ck = {
1011         .name           = "ducati_clk_mux_ck",
1012         .parent         = &div_core_ck,
1013         .clksel         = ducati_clk_mux_sel,
1014         .init           = &omap2_init_clksel_parent,
1015         .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1016         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1017         .ops            = &clkops_null,
1018         .recalc         = &omap2_clksel_recalc,
1019 };
1020
1021 static struct clk func_12m_fclk = {
1022         .name           = "func_12m_fclk",
1023         .parent         = &dpll_per_m2x2_ck,
1024         .ops            = &clkops_null,
1025         .fixed_div      = 16,
1026         .recalc         = &omap_fixed_divisor_recalc,
1027 };
1028
1029 static struct clk func_24m_clk = {
1030         .name           = "func_24m_clk",
1031         .parent         = &dpll_per_m2_ck,
1032         .ops            = &clkops_null,
1033         .fixed_div      = 4,
1034         .recalc         = &omap_fixed_divisor_recalc,
1035 };
1036
1037 static struct clk func_24mc_fclk = {
1038         .name           = "func_24mc_fclk",
1039         .parent         = &dpll_per_m2x2_ck,
1040         .ops            = &clkops_null,
1041         .fixed_div      = 8,
1042         .recalc         = &omap_fixed_divisor_recalc,
1043 };
1044
1045 static const struct clksel_rate div2_4to8_rates[] = {
1046         { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1047         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1048         { .div = 0 },
1049 };
1050
1051 static const struct clksel func_48m_fclk_div[] = {
1052         { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1053         { .parent = NULL },
1054 };
1055
1056 static struct clk func_48m_fclk = {
1057         .name           = "func_48m_fclk",
1058         .parent         = &dpll_per_m2x2_ck,
1059         .clksel         = func_48m_fclk_div,
1060         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1061         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1062         .ops            = &clkops_null,
1063         .recalc         = &omap2_clksel_recalc,
1064         .round_rate     = &omap2_clksel_round_rate,
1065         .set_rate       = &omap2_clksel_set_rate,
1066 };
1067
1068 static struct clk func_48mc_fclk = {
1069         .name           = "func_48mc_fclk",
1070         .parent         = &dpll_per_m2x2_ck,
1071         .ops            = &clkops_null,
1072         .fixed_div      = 4,
1073         .recalc         = &omap_fixed_divisor_recalc,
1074 };
1075
1076 static const struct clksel_rate div2_2to4_rates[] = {
1077         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1078         { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1079         { .div = 0 },
1080 };
1081
1082 static const struct clksel func_64m_fclk_div[] = {
1083         { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1084         { .parent = NULL },
1085 };
1086
1087 static struct clk func_64m_fclk = {
1088         .name           = "func_64m_fclk",
1089         .parent         = &dpll_per_m4x2_ck,
1090         .clksel         = func_64m_fclk_div,
1091         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1092         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1093         .ops            = &clkops_null,
1094         .recalc         = &omap2_clksel_recalc,
1095         .round_rate     = &omap2_clksel_round_rate,
1096         .set_rate       = &omap2_clksel_set_rate,
1097 };
1098
1099 static const struct clksel func_96m_fclk_div[] = {
1100         { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1101         { .parent = NULL },
1102 };
1103
1104 static struct clk func_96m_fclk = {
1105         .name           = "func_96m_fclk",
1106         .parent         = &dpll_per_m2x2_ck,
1107         .clksel         = func_96m_fclk_div,
1108         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1109         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1110         .ops            = &clkops_null,
1111         .recalc         = &omap2_clksel_recalc,
1112         .round_rate     = &omap2_clksel_round_rate,
1113         .set_rate       = &omap2_clksel_set_rate,
1114 };
1115
1116 static const struct clksel_rate div2_1to8_rates[] = {
1117         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1118         { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1119         { .div = 0 },
1120 };
1121
1122 static const struct clksel init_60m_fclk_div[] = {
1123         { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1124         { .parent = NULL },
1125 };
1126
1127 static struct clk init_60m_fclk = {
1128         .name           = "init_60m_fclk",
1129         .parent         = &dpll_usb_m2_ck,
1130         .clksel         = init_60m_fclk_div,
1131         .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
1132         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1133         .ops            = &clkops_null,
1134         .recalc         = &omap2_clksel_recalc,
1135         .round_rate     = &omap2_clksel_round_rate,
1136         .set_rate       = &omap2_clksel_set_rate,
1137 };
1138
1139 static const struct clksel l3_div_div[] = {
1140         { .parent = &div_core_ck, .rates = div2_1to2_rates },
1141         { .parent = NULL },
1142 };
1143
1144 static struct clk l3_div_ck = {
1145         .name           = "l3_div_ck",
1146         .parent         = &div_core_ck,
1147         .clksel         = l3_div_div,
1148         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1149         .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
1150         .ops            = &clkops_null,
1151         .recalc         = &omap2_clksel_recalc,
1152         .round_rate     = &omap2_clksel_round_rate,
1153         .set_rate       = &omap2_clksel_set_rate,
1154 };
1155
1156 static const struct clksel l4_div_div[] = {
1157         { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1158         { .parent = NULL },
1159 };
1160
1161 static struct clk l4_div_ck = {
1162         .name           = "l4_div_ck",
1163         .parent         = &l3_div_ck,
1164         .clksel         = l4_div_div,
1165         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
1166         .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
1167         .ops            = &clkops_null,
1168         .recalc         = &omap2_clksel_recalc,
1169         .round_rate     = &omap2_clksel_round_rate,
1170         .set_rate       = &omap2_clksel_set_rate,
1171 };
1172
1173 static struct clk lp_clk_div_ck = {
1174         .name           = "lp_clk_div_ck",
1175         .parent         = &dpll_abe_m2x2_ck,
1176         .ops            = &clkops_null,
1177         .fixed_div      = 16,
1178         .recalc         = &omap_fixed_divisor_recalc,
1179 };
1180
1181 static const struct clksel l4_wkup_clk_mux_sel[] = {
1182         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1183         { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1184         { .parent = NULL },
1185 };
1186
1187 static struct clk l4_wkup_clk_mux_ck = {
1188         .name           = "l4_wkup_clk_mux_ck",
1189         .parent         = &sys_clkin_ck,
1190         .clksel         = l4_wkup_clk_mux_sel,
1191         .init           = &omap2_init_clksel_parent,
1192         .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
1193         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1194         .ops            = &clkops_null,
1195         .recalc         = &omap2_clksel_recalc,
1196 };
1197
1198 static const struct clksel_rate div2_2to1_rates[] = {
1199         { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1200         { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1201         { .div = 0 },
1202 };
1203
1204 static const struct clksel ocp_abe_iclk_div[] = {
1205         { .parent = &aess_fclk, .rates = div2_2to1_rates },
1206         { .parent = NULL },
1207 };
1208
1209 static struct clk ocp_abe_iclk = {
1210         .name           = "ocp_abe_iclk",
1211         .parent         = &aess_fclk,
1212         .clksel         = ocp_abe_iclk_div,
1213         .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1214         .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1215         .ops            = &clkops_null,
1216         .recalc         = &omap2_clksel_recalc,
1217 };
1218
1219 static struct clk per_abe_24m_fclk = {
1220         .name           = "per_abe_24m_fclk",
1221         .parent         = &dpll_abe_m2_ck,
1222         .ops            = &clkops_null,
1223         .fixed_div      = 4,
1224         .recalc         = &omap_fixed_divisor_recalc,
1225 };
1226
1227 static const struct clksel per_abe_nc_fclk_div[] = {
1228         { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1229         { .parent = NULL },
1230 };
1231
1232 static struct clk per_abe_nc_fclk = {
1233         .name           = "per_abe_nc_fclk",
1234         .parent         = &dpll_abe_m2_ck,
1235         .clksel         = per_abe_nc_fclk_div,
1236         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
1237         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
1238         .ops            = &clkops_null,
1239         .recalc         = &omap2_clksel_recalc,
1240         .round_rate     = &omap2_clksel_round_rate,
1241         .set_rate       = &omap2_clksel_set_rate,
1242 };
1243
1244 static const struct clksel pmd_stm_clock_mux_sel[] = {
1245         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1246         { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1247         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1248         { .parent = NULL },
1249 };
1250
1251 static struct clk pmd_stm_clock_mux_ck = {
1252         .name           = "pmd_stm_clock_mux_ck",
1253         .parent         = &sys_clkin_ck,
1254         .ops            = &clkops_null,
1255         .recalc         = &followparent_recalc,
1256 };
1257
1258 static struct clk pmd_trace_clk_mux_ck = {
1259         .name           = "pmd_trace_clk_mux_ck",
1260         .parent         = &sys_clkin_ck,
1261         .ops            = &clkops_null,
1262         .recalc         = &followparent_recalc,
1263 };
1264
1265 static const struct clksel syc_clk_div_div[] = {
1266         { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1267         { .parent = NULL },
1268 };
1269
1270 static struct clk syc_clk_div_ck = {
1271         .name           = "syc_clk_div_ck",
1272         .parent         = &sys_clkin_ck,
1273         .clksel         = syc_clk_div_div,
1274         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1275         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
1276         .ops            = &clkops_null,
1277         .recalc         = &omap2_clksel_recalc,
1278         .round_rate     = &omap2_clksel_round_rate,
1279         .set_rate       = &omap2_clksel_set_rate,
1280 };
1281
1282 /* Leaf clocks controlled by modules */
1283
1284 static struct clk aes1_fck = {
1285         .name           = "aes1_fck",
1286         .ops            = &clkops_omap2_dflt,
1287         .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1288         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1289         .clkdm_name     = "l4_secure_clkdm",
1290         .parent         = &l3_div_ck,
1291         .recalc         = &followparent_recalc,
1292 };
1293
1294 static struct clk aes2_fck = {
1295         .name           = "aes2_fck",
1296         .ops            = &clkops_omap2_dflt,
1297         .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1298         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1299         .clkdm_name     = "l4_secure_clkdm",
1300         .parent         = &l3_div_ck,
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk aess_fck = {
1305         .name           = "aess_fck",
1306         .ops            = &clkops_omap2_dflt,
1307         .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1308         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1309         .clkdm_name     = "abe_clkdm",
1310         .parent         = &aess_fclk,
1311         .recalc         = &followparent_recalc,
1312 };
1313
1314 static struct clk bandgap_fclk = {
1315         .name           = "bandgap_fclk",
1316         .ops            = &clkops_omap2_dflt,
1317         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1318         .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1319         .clkdm_name     = "l4_wkup_clkdm",
1320         .parent         = &sys_32k_ck,
1321         .recalc         = &followparent_recalc,
1322 };
1323
1324 static struct clk des3des_fck = {
1325         .name           = "des3des_fck",
1326         .ops            = &clkops_omap2_dflt,
1327         .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1328         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1329         .clkdm_name     = "l4_secure_clkdm",
1330         .parent         = &l4_div_ck,
1331         .recalc         = &followparent_recalc,
1332 };
1333
1334 static const struct clksel dmic_sync_mux_sel[] = {
1335         { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1336         { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1337         { .parent = &func_24m_clk, .rates = div_1_2_rates },
1338         { .parent = NULL },
1339 };
1340
1341 static struct clk dmic_sync_mux_ck = {
1342         .name           = "dmic_sync_mux_ck",
1343         .parent         = &abe_24m_fclk,
1344         .clksel         = dmic_sync_mux_sel,
1345         .init           = &omap2_init_clksel_parent,
1346         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1347         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1348         .ops            = &clkops_null,
1349         .recalc         = &omap2_clksel_recalc,
1350 };
1351
1352 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1353         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1354         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1355         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1356         { .parent = NULL },
1357 };
1358
1359 /* Merged func_dmic_abe_gfclk into dmic */
1360 static struct clk dmic_fck = {
1361         .name           = "dmic_fck",
1362         .parent         = &dmic_sync_mux_ck,
1363         .clksel         = func_dmic_abe_gfclk_sel,
1364         .init           = &omap2_init_clksel_parent,
1365         .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1366         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1367         .ops            = &clkops_omap2_dflt,
1368         .recalc         = &omap2_clksel_recalc,
1369         .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1370         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1371         .clkdm_name     = "abe_clkdm",
1372 };
1373
1374 static struct clk dsp_fck = {
1375         .name           = "dsp_fck",
1376         .ops            = &clkops_omap2_dflt,
1377         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1378         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1379         .clkdm_name     = "tesla_clkdm",
1380         .parent         = &dpll_iva_m4x2_ck,
1381         .recalc         = &followparent_recalc,
1382 };
1383
1384 static struct clk dss_sys_clk = {
1385         .name           = "dss_sys_clk",
1386         .ops            = &clkops_omap2_dflt,
1387         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1388         .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1389         .clkdm_name     = "l3_dss_clkdm",
1390         .parent         = &syc_clk_div_ck,
1391         .recalc         = &followparent_recalc,
1392 };
1393
1394 static struct clk dss_tv_clk = {
1395         .name           = "dss_tv_clk",
1396         .ops            = &clkops_omap2_dflt,
1397         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1398         .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1399         .clkdm_name     = "l3_dss_clkdm",
1400         .parent         = &extalt_clkin_ck,
1401         .recalc         = &followparent_recalc,
1402 };
1403
1404 static struct clk dss_dss_clk = {
1405         .name           = "dss_dss_clk",
1406         .ops            = &clkops_omap2_dflt,
1407         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1408         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1409         .clkdm_name     = "l3_dss_clkdm",
1410         .parent         = &dpll_per_m5x2_ck,
1411         .recalc         = &followparent_recalc,
1412 };
1413
1414 static const struct clksel_rate div3_8to32_rates[] = {
1415         { .div = 8, .val = 0, .flags = RATE_IN_4460 },
1416         { .div = 16, .val = 1, .flags = RATE_IN_4460 },
1417         { .div = 32, .val = 2, .flags = RATE_IN_4460 },
1418         { .div = 0 },
1419 };
1420
1421 static const struct clksel div_ts_div[] = {
1422         { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1423         { .parent = NULL },
1424 };
1425
1426 static struct clk div_ts_ck = {
1427         .name           = "div_ts_ck",
1428         .parent         = &l4_wkup_clk_mux_ck,
1429         .clksel         = div_ts_div,
1430         .clksel_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1431         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1432         .ops            = &clkops_null,
1433         .recalc         = &omap2_clksel_recalc,
1434         .round_rate     = &omap2_clksel_round_rate,
1435         .set_rate       = &omap2_clksel_set_rate,
1436 };
1437
1438 static struct clk bandgap_ts_fclk = {
1439         .name           = "bandgap_ts_fclk",
1440         .ops            = &clkops_omap2_dflt,
1441         .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1442         .enable_bit     = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1443         .clkdm_name     = "l4_wkup_clkdm",
1444         .parent         = &div_ts_ck,
1445         .recalc         = &followparent_recalc,
1446 };
1447
1448 static struct clk dss_48mhz_clk = {
1449         .name           = "dss_48mhz_clk",
1450         .ops            = &clkops_omap2_dflt,
1451         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1452         .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1453         .clkdm_name     = "l3_dss_clkdm",
1454         .parent         = &func_48mc_fclk,
1455         .recalc         = &followparent_recalc,
1456 };
1457
1458 static struct clk dss_fck = {
1459         .name           = "dss_fck",
1460         .ops            = &clkops_omap2_dflt,
1461         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
1462         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1463         .clkdm_name     = "l3_dss_clkdm",
1464         .parent         = &l3_div_ck,
1465         .recalc         = &followparent_recalc,
1466 };
1467
1468 static struct clk efuse_ctrl_cust_fck = {
1469         .name           = "efuse_ctrl_cust_fck",
1470         .ops            = &clkops_omap2_dflt,
1471         .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1472         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1473         .clkdm_name     = "l4_cefuse_clkdm",
1474         .parent         = &sys_clkin_ck,
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 static struct clk emif1_fck = {
1479         .name           = "emif1_fck",
1480         .ops            = &clkops_omap2_dflt,
1481         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1482         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1483         .flags          = ENABLE_ON_INIT,
1484         .clkdm_name     = "l3_emif_clkdm",
1485         .parent         = &ddrphy_ck,
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static struct clk emif2_fck = {
1490         .name           = "emif2_fck",
1491         .ops            = &clkops_omap2_dflt,
1492         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1493         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1494         .flags          = ENABLE_ON_INIT,
1495         .clkdm_name     = "l3_emif_clkdm",
1496         .parent         = &ddrphy_ck,
1497         .recalc         = &followparent_recalc,
1498 };
1499
1500 static const struct clksel fdif_fclk_div[] = {
1501         { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1502         { .parent = NULL },
1503 };
1504
1505 /* Merged fdif_fclk into fdif */
1506 static struct clk fdif_fck = {
1507         .name           = "fdif_fck",
1508         .parent         = &dpll_per_m4x2_ck,
1509         .clksel         = fdif_fclk_div,
1510         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1511         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
1512         .ops            = &clkops_omap2_dflt,
1513         .recalc         = &omap2_clksel_recalc,
1514         .round_rate     = &omap2_clksel_round_rate,
1515         .set_rate       = &omap2_clksel_set_rate,
1516         .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1517         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1518         .clkdm_name     = "iss_clkdm",
1519 };
1520
1521 static struct clk fpka_fck = {
1522         .name           = "fpka_fck",
1523         .ops            = &clkops_omap2_dflt,
1524         .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1525         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1526         .clkdm_name     = "l4_secure_clkdm",
1527         .parent         = &l4_div_ck,
1528         .recalc         = &followparent_recalc,
1529 };
1530
1531 static struct clk gpio1_dbclk = {
1532         .name           = "gpio1_dbclk",
1533         .ops            = &clkops_omap2_dflt,
1534         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1535         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1536         .clkdm_name     = "l4_wkup_clkdm",
1537         .parent         = &sys_32k_ck,
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk gpio1_ick = {
1542         .name           = "gpio1_ick",
1543         .ops            = &clkops_omap2_dflt,
1544         .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1545         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1546         .clkdm_name     = "l4_wkup_clkdm",
1547         .parent         = &l4_wkup_clk_mux_ck,
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk gpio2_dbclk = {
1552         .name           = "gpio2_dbclk",
1553         .ops            = &clkops_omap2_dflt,
1554         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1555         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1556         .clkdm_name     = "l4_per_clkdm",
1557         .parent         = &sys_32k_ck,
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk gpio2_ick = {
1562         .name           = "gpio2_ick",
1563         .ops            = &clkops_omap2_dflt,
1564         .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1565         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1566         .clkdm_name     = "l4_per_clkdm",
1567         .parent         = &l4_div_ck,
1568         .recalc         = &followparent_recalc,
1569 };
1570
1571 static struct clk gpio3_dbclk = {
1572         .name           = "gpio3_dbclk",
1573         .ops            = &clkops_omap2_dflt,
1574         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1575         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1576         .clkdm_name     = "l4_per_clkdm",
1577         .parent         = &sys_32k_ck,
1578         .recalc         = &followparent_recalc,
1579 };
1580
1581 static struct clk gpio3_ick = {
1582         .name           = "gpio3_ick",
1583         .ops            = &clkops_omap2_dflt,
1584         .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1585         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1586         .clkdm_name     = "l4_per_clkdm",
1587         .parent         = &l4_div_ck,
1588         .recalc         = &followparent_recalc,
1589 };
1590
1591 static struct clk gpio4_dbclk = {
1592         .name           = "gpio4_dbclk",
1593         .ops            = &clkops_omap2_dflt,
1594         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1595         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1596         .clkdm_name     = "l4_per_clkdm",
1597         .parent         = &sys_32k_ck,
1598         .recalc         = &followparent_recalc,
1599 };
1600
1601 static struct clk gpio4_ick = {
1602         .name           = "gpio4_ick",
1603         .ops            = &clkops_omap2_dflt,
1604         .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1605         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1606         .clkdm_name     = "l4_per_clkdm",
1607         .parent         = &l4_div_ck,
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 static struct clk gpio5_dbclk = {
1612         .name           = "gpio5_dbclk",
1613         .ops            = &clkops_omap2_dflt,
1614         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1615         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1616         .clkdm_name     = "l4_per_clkdm",
1617         .parent         = &sys_32k_ck,
1618         .recalc         = &followparent_recalc,
1619 };
1620
1621 static struct clk gpio5_ick = {
1622         .name           = "gpio5_ick",
1623         .ops            = &clkops_omap2_dflt,
1624         .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1625         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1626         .clkdm_name     = "l4_per_clkdm",
1627         .parent         = &l4_div_ck,
1628         .recalc         = &followparent_recalc,
1629 };
1630
1631 static struct clk gpio6_dbclk = {
1632         .name           = "gpio6_dbclk",
1633         .ops            = &clkops_omap2_dflt,
1634         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1635         .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1636         .clkdm_name     = "l4_per_clkdm",
1637         .parent         = &sys_32k_ck,
1638         .recalc         = &followparent_recalc,
1639 };
1640
1641 static struct clk gpio6_ick = {
1642         .name           = "gpio6_ick",
1643         .ops            = &clkops_omap2_dflt,
1644         .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1645         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1646         .clkdm_name     = "l4_per_clkdm",
1647         .parent         = &l4_div_ck,
1648         .recalc         = &followparent_recalc,
1649 };
1650
1651 static struct clk gpmc_ick = {
1652         .name           = "gpmc_ick",
1653         .ops            = &clkops_omap2_dflt,
1654         .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1655         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1656         .flags          = ENABLE_ON_INIT,
1657         .clkdm_name     = "l3_2_clkdm",
1658         .parent         = &l3_div_ck,
1659         .recalc         = &followparent_recalc,
1660 };
1661
1662 static const struct clksel sgx_clk_mux_sel[] = {
1663         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1664         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1665         { .parent = NULL },
1666 };
1667
1668 /* Merged sgx_clk_mux into gpu */
1669 static struct clk gpu_fck = {
1670         .name           = "gpu_fck",
1671         .parent         = &dpll_core_m7x2_ck,
1672         .clksel         = sgx_clk_mux_sel,
1673         .init           = &omap2_init_clksel_parent,
1674         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1675         .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1676         .ops            = &clkops_omap2_dflt,
1677         .recalc         = &omap2_clksel_recalc,
1678         .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
1679         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1680         .clkdm_name     = "l3_gfx_clkdm",
1681 };
1682
1683 static struct clk hdq1w_fck = {
1684         .name           = "hdq1w_fck",
1685         .ops            = &clkops_omap2_dflt,
1686         .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1687         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1688         .clkdm_name     = "l4_per_clkdm",
1689         .parent         = &func_12m_fclk,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static const struct clksel hsi_fclk_div[] = {
1694         { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1695         { .parent = NULL },
1696 };
1697
1698 /* Merged hsi_fclk into hsi */
1699 static struct clk hsi_fck = {
1700         .name           = "hsi_fck",
1701         .parent         = &dpll_per_m2x2_ck,
1702         .clksel         = hsi_fclk_div,
1703         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1704         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
1705         .ops            = &clkops_omap2_dflt,
1706         .recalc         = &omap2_clksel_recalc,
1707         .round_rate     = &omap2_clksel_round_rate,
1708         .set_rate       = &omap2_clksel_set_rate,
1709         .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1710         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1711         .clkdm_name     = "l3_init_clkdm",
1712 };
1713
1714 static struct clk i2c1_fck = {
1715         .name           = "i2c1_fck",
1716         .ops            = &clkops_omap2_dflt,
1717         .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1718         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1719         .clkdm_name     = "l4_per_clkdm",
1720         .parent         = &func_96m_fclk,
1721         .recalc         = &followparent_recalc,
1722 };
1723
1724 static struct clk i2c2_fck = {
1725         .name           = "i2c2_fck",
1726         .ops            = &clkops_omap2_dflt,
1727         .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1728         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1729         .clkdm_name     = "l4_per_clkdm",
1730         .parent         = &func_96m_fclk,
1731         .recalc         = &followparent_recalc,
1732 };
1733
1734 static struct clk i2c3_fck = {
1735         .name           = "i2c3_fck",
1736         .ops            = &clkops_omap2_dflt,
1737         .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1738         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1739         .clkdm_name     = "l4_per_clkdm",
1740         .parent         = &func_96m_fclk,
1741         .recalc         = &followparent_recalc,
1742 };
1743
1744 static struct clk i2c4_fck = {
1745         .name           = "i2c4_fck",
1746         .ops            = &clkops_omap2_dflt,
1747         .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1748         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1749         .clkdm_name     = "l4_per_clkdm",
1750         .parent         = &func_96m_fclk,
1751         .recalc         = &followparent_recalc,
1752 };
1753
1754 static struct clk ipu_fck = {
1755         .name           = "ipu_fck",
1756         .ops            = &clkops_omap2_dflt,
1757         .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1758         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1759         .clkdm_name     = "ducati_clkdm",
1760         .parent         = &ducati_clk_mux_ck,
1761         .recalc         = &followparent_recalc,
1762 };
1763
1764 static struct clk iss_ctrlclk = {
1765         .name           = "iss_ctrlclk",
1766         .ops            = &clkops_omap2_dflt,
1767         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1768         .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1769         .clkdm_name     = "iss_clkdm",
1770         .parent         = &func_96m_fclk,
1771         .recalc         = &followparent_recalc,
1772 };
1773
1774 static struct clk iss_fck = {
1775         .name           = "iss_fck",
1776         .ops            = &clkops_omap2_dflt,
1777         .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
1778         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1779         .clkdm_name     = "iss_clkdm",
1780         .parent         = &ducati_clk_mux_ck,
1781         .recalc         = &followparent_recalc,
1782 };
1783
1784 static struct clk iva_fck = {
1785         .name           = "iva_fck",
1786         .ops            = &clkops_omap2_dflt,
1787         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1788         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1789         .clkdm_name     = "ivahd_clkdm",
1790         .parent         = &dpll_iva_m5x2_ck,
1791         .recalc         = &followparent_recalc,
1792 };
1793
1794 static struct clk kbd_fck = {
1795         .name           = "kbd_fck",
1796         .ops            = &clkops_omap2_dflt,
1797         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1798         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1799         .clkdm_name     = "l4_wkup_clkdm",
1800         .parent         = &sys_32k_ck,
1801         .recalc         = &followparent_recalc,
1802 };
1803
1804 static struct clk l3_instr_ick = {
1805         .name           = "l3_instr_ick",
1806         .ops            = &clkops_omap2_dflt,
1807         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1808         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1809         .flags          = ENABLE_ON_INIT,
1810         .clkdm_name     = "l3_instr_clkdm",
1811         .parent         = &l3_div_ck,
1812         .recalc         = &followparent_recalc,
1813 };
1814
1815 static struct clk l3_main_3_ick = {
1816         .name           = "l3_main_3_ick",
1817         .ops            = &clkops_omap2_dflt,
1818         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1819         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
1820         .flags          = ENABLE_ON_INIT,
1821         .clkdm_name     = "l3_instr_clkdm",
1822         .parent         = &l3_div_ck,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcasp_sync_mux_ck = {
1827         .name           = "mcasp_sync_mux_ck",
1828         .parent         = &abe_24m_fclk,
1829         .clksel         = dmic_sync_mux_sel,
1830         .init           = &omap2_init_clksel_parent,
1831         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1832         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1833         .ops            = &clkops_null,
1834         .recalc         = &omap2_clksel_recalc,
1835 };
1836
1837 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1838         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1839         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1840         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1841         { .parent = NULL },
1842 };
1843
1844 /* Merged func_mcasp_abe_gfclk into mcasp */
1845 static struct clk mcasp_fck = {
1846         .name           = "mcasp_fck",
1847         .parent         = &mcasp_sync_mux_ck,
1848         .clksel         = func_mcasp_abe_gfclk_sel,
1849         .init           = &omap2_init_clksel_parent,
1850         .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1851         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1852         .ops            = &clkops_omap2_dflt,
1853         .recalc         = &omap2_clksel_recalc,
1854         .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1855         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1856         .clkdm_name     = "abe_clkdm",
1857 };
1858
1859 static struct clk mcbsp1_sync_mux_ck = {
1860         .name           = "mcbsp1_sync_mux_ck",
1861         .parent         = &abe_24m_fclk,
1862         .clksel         = dmic_sync_mux_sel,
1863         .init           = &omap2_init_clksel_parent,
1864         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1865         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1866         .ops            = &clkops_null,
1867         .recalc         = &omap2_clksel_recalc,
1868 };
1869
1870 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1871         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1872         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1873         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1874         { .parent = NULL },
1875 };
1876
1877 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1878 static struct clk mcbsp1_fck = {
1879         .name           = "mcbsp1_fck",
1880         .parent         = &mcbsp1_sync_mux_ck,
1881         .clksel         = func_mcbsp1_gfclk_sel,
1882         .init           = &omap2_init_clksel_parent,
1883         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1884         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1885         .ops            = &clkops_omap2_dflt,
1886         .recalc         = &omap2_clksel_recalc,
1887         .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1888         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1889         .clkdm_name     = "abe_clkdm",
1890 };
1891
1892 static struct clk mcbsp2_sync_mux_ck = {
1893         .name           = "mcbsp2_sync_mux_ck",
1894         .parent         = &abe_24m_fclk,
1895         .clksel         = dmic_sync_mux_sel,
1896         .init           = &omap2_init_clksel_parent,
1897         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1898         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1899         .ops            = &clkops_null,
1900         .recalc         = &omap2_clksel_recalc,
1901 };
1902
1903 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1904         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1905         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1906         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1907         { .parent = NULL },
1908 };
1909
1910 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1911 static struct clk mcbsp2_fck = {
1912         .name           = "mcbsp2_fck",
1913         .parent         = &mcbsp2_sync_mux_ck,
1914         .clksel         = func_mcbsp2_gfclk_sel,
1915         .init           = &omap2_init_clksel_parent,
1916         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1917         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1918         .ops            = &clkops_omap2_dflt,
1919         .recalc         = &omap2_clksel_recalc,
1920         .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1921         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1922         .clkdm_name     = "abe_clkdm",
1923 };
1924
1925 static struct clk mcbsp3_sync_mux_ck = {
1926         .name           = "mcbsp3_sync_mux_ck",
1927         .parent         = &abe_24m_fclk,
1928         .clksel         = dmic_sync_mux_sel,
1929         .init           = &omap2_init_clksel_parent,
1930         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1931         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1932         .ops            = &clkops_null,
1933         .recalc         = &omap2_clksel_recalc,
1934 };
1935
1936 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1937         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1938         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1939         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1940         { .parent = NULL },
1941 };
1942
1943 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1944 static struct clk mcbsp3_fck = {
1945         .name           = "mcbsp3_fck",
1946         .parent         = &mcbsp3_sync_mux_ck,
1947         .clksel         = func_mcbsp3_gfclk_sel,
1948         .init           = &omap2_init_clksel_parent,
1949         .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1950         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
1951         .ops            = &clkops_omap2_dflt,
1952         .recalc         = &omap2_clksel_recalc,
1953         .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1954         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1955         .clkdm_name     = "abe_clkdm",
1956 };
1957
1958 static const struct clksel mcbsp4_sync_mux_sel[] = {
1959         { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1960         { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1961         { .parent = NULL },
1962 };
1963
1964 static struct clk mcbsp4_sync_mux_ck = {
1965         .name           = "mcbsp4_sync_mux_ck",
1966         .parent         = &func_96m_fclk,
1967         .clksel         = mcbsp4_sync_mux_sel,
1968         .init           = &omap2_init_clksel_parent,
1969         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1970         .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1971         .ops            = &clkops_null,
1972         .recalc         = &omap2_clksel_recalc,
1973 };
1974
1975 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1976         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1977         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1978         { .parent = NULL },
1979 };
1980
1981 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1982 static struct clk mcbsp4_fck = {
1983         .name           = "mcbsp4_fck",
1984         .parent         = &mcbsp4_sync_mux_ck,
1985         .clksel         = per_mcbsp4_gfclk_sel,
1986         .init           = &omap2_init_clksel_parent,
1987         .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1988         .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1989         .ops            = &clkops_omap2_dflt,
1990         .recalc         = &omap2_clksel_recalc,
1991         .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1992         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
1993         .clkdm_name     = "l4_per_clkdm",
1994 };
1995
1996 static struct clk mcpdm_fck = {
1997         .name           = "mcpdm_fck",
1998         .ops            = &clkops_omap2_dflt,
1999         .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2000         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2001         .clkdm_name     = "abe_clkdm",
2002         .parent         = &pad_clks_ck,
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk mcspi1_fck = {
2007         .name           = "mcspi1_fck",
2008         .ops            = &clkops_omap2_dflt,
2009         .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2010         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2011         .clkdm_name     = "l4_per_clkdm",
2012         .parent         = &func_48m_fclk,
2013         .recalc         = &followparent_recalc,
2014 };
2015
2016 static struct clk mcspi2_fck = {
2017         .name           = "mcspi2_fck",
2018         .ops            = &clkops_omap2_dflt,
2019         .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2020         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2021         .clkdm_name     = "l4_per_clkdm",
2022         .parent         = &func_48m_fclk,
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 static struct clk mcspi3_fck = {
2027         .name           = "mcspi3_fck",
2028         .ops            = &clkops_omap2_dflt,
2029         .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2030         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2031         .clkdm_name     = "l4_per_clkdm",
2032         .parent         = &func_48m_fclk,
2033         .recalc         = &followparent_recalc,
2034 };
2035
2036 static struct clk mcspi4_fck = {
2037         .name           = "mcspi4_fck",
2038         .ops            = &clkops_omap2_dflt,
2039         .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2040         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2041         .clkdm_name     = "l4_per_clkdm",
2042         .parent         = &func_48m_fclk,
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static const struct clksel hsmmc1_fclk_sel[] = {
2047         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2048         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2049         { .parent = NULL },
2050 };
2051
2052 /* Merged hsmmc1_fclk into mmc1 */
2053 static struct clk mmc1_fck = {
2054         .name           = "mmc1_fck",
2055         .parent         = &func_64m_fclk,
2056         .clksel         = hsmmc1_fclk_sel,
2057         .init           = &omap2_init_clksel_parent,
2058         .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2059         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2060         .ops            = &clkops_omap2_dflt,
2061         .recalc         = &omap2_clksel_recalc,
2062         .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2063         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2064         .clkdm_name     = "l3_init_clkdm",
2065 };
2066
2067 /* Merged hsmmc2_fclk into mmc2 */
2068 static struct clk mmc2_fck = {
2069         .name           = "mmc2_fck",
2070         .parent         = &func_64m_fclk,
2071         .clksel         = hsmmc1_fclk_sel,
2072         .init           = &omap2_init_clksel_parent,
2073         .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2074         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2075         .ops            = &clkops_omap2_dflt,
2076         .recalc         = &omap2_clksel_recalc,
2077         .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2078         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2079         .clkdm_name     = "l3_init_clkdm",
2080 };
2081
2082 static struct clk mmc3_fck = {
2083         .name           = "mmc3_fck",
2084         .ops            = &clkops_omap2_dflt,
2085         .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2086         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2087         .clkdm_name     = "l4_per_clkdm",
2088         .parent         = &func_48m_fclk,
2089         .recalc         = &followparent_recalc,
2090 };
2091
2092 static struct clk mmc4_fck = {
2093         .name           = "mmc4_fck",
2094         .ops            = &clkops_omap2_dflt,
2095         .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2096         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2097         .clkdm_name     = "l4_per_clkdm",
2098         .parent         = &func_48m_fclk,
2099         .recalc         = &followparent_recalc,
2100 };
2101
2102 static struct clk mmc5_fck = {
2103         .name           = "mmc5_fck",
2104         .ops            = &clkops_omap2_dflt,
2105         .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2106         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2107         .clkdm_name     = "l4_per_clkdm",
2108         .parent         = &func_48m_fclk,
2109         .recalc         = &followparent_recalc,
2110 };
2111
2112 static struct clk ocp2scp_usb_phy_phy_48m = {
2113         .name           = "ocp2scp_usb_phy_phy_48m",
2114         .ops            = &clkops_omap2_dflt,
2115         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2116         .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2117         .clkdm_name     = "l3_init_clkdm",
2118         .parent         = &func_48m_fclk,
2119         .recalc         = &followparent_recalc,
2120 };
2121
2122 static struct clk ocp2scp_usb_phy_ick = {
2123         .name           = "ocp2scp_usb_phy_ick",
2124         .ops            = &clkops_omap2_dflt,
2125         .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2126         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2127         .clkdm_name     = "l3_init_clkdm",
2128         .parent         = &l4_div_ck,
2129         .recalc         = &followparent_recalc,
2130 };
2131
2132 static struct clk ocp_wp_noc_ick = {
2133         .name           = "ocp_wp_noc_ick",
2134         .ops            = &clkops_omap2_dflt,
2135         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2136         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2137         .flags          = ENABLE_ON_INIT,
2138         .clkdm_name     = "l3_instr_clkdm",
2139         .parent         = &l3_div_ck,
2140         .recalc         = &followparent_recalc,
2141 };
2142
2143 static struct clk rng_ick = {
2144         .name           = "rng_ick",
2145         .ops            = &clkops_omap2_dflt,
2146         .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2147         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2148         .clkdm_name     = "l4_secure_clkdm",
2149         .parent         = &l4_div_ck,
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 static struct clk sha2md5_fck = {
2154         .name           = "sha2md5_fck",
2155         .ops            = &clkops_omap2_dflt,
2156         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2157         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2158         .clkdm_name     = "l4_secure_clkdm",
2159         .parent         = &l3_div_ck,
2160         .recalc         = &followparent_recalc,
2161 };
2162
2163 static struct clk sl2if_ick = {
2164         .name           = "sl2if_ick",
2165         .ops            = &clkops_omap2_dflt,
2166         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2167         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2168         .clkdm_name     = "ivahd_clkdm",
2169         .parent         = &dpll_iva_m5x2_ck,
2170         .recalc         = &followparent_recalc,
2171 };
2172
2173 static struct clk slimbus1_fclk_1 = {
2174         .name           = "slimbus1_fclk_1",
2175         .ops            = &clkops_omap2_dflt,
2176         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2177         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2178         .clkdm_name     = "abe_clkdm",
2179         .parent         = &func_24m_clk,
2180         .recalc         = &followparent_recalc,
2181 };
2182
2183 static struct clk slimbus1_fclk_0 = {
2184         .name           = "slimbus1_fclk_0",
2185         .ops            = &clkops_omap2_dflt,
2186         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2187         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2188         .clkdm_name     = "abe_clkdm",
2189         .parent         = &abe_24m_fclk,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk slimbus1_fclk_2 = {
2194         .name           = "slimbus1_fclk_2",
2195         .ops            = &clkops_omap2_dflt,
2196         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2197         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2198         .clkdm_name     = "abe_clkdm",
2199         .parent         = &pad_clks_ck,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk slimbus1_slimbus_clk = {
2204         .name           = "slimbus1_slimbus_clk",
2205         .ops            = &clkops_omap2_dflt,
2206         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2207         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2208         .clkdm_name     = "abe_clkdm",
2209         .parent         = &slimbus_clk,
2210         .recalc         = &followparent_recalc,
2211 };
2212
2213 static struct clk slimbus1_fck = {
2214         .name           = "slimbus1_fck",
2215         .ops            = &clkops_omap2_dflt,
2216         .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2217         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2218         .clkdm_name     = "abe_clkdm",
2219         .parent         = &ocp_abe_iclk,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk slimbus2_fclk_1 = {
2224         .name           = "slimbus2_fclk_1",
2225         .ops            = &clkops_omap2_dflt,
2226         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2227         .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2228         .clkdm_name     = "l4_per_clkdm",
2229         .parent         = &per_abe_24m_fclk,
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk slimbus2_fclk_0 = {
2234         .name           = "slimbus2_fclk_0",
2235         .ops            = &clkops_omap2_dflt,
2236         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2237         .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2238         .clkdm_name     = "l4_per_clkdm",
2239         .parent         = &func_24mc_fclk,
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk slimbus2_slimbus_clk = {
2244         .name           = "slimbus2_slimbus_clk",
2245         .ops            = &clkops_omap2_dflt,
2246         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2247         .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2248         .clkdm_name     = "l4_per_clkdm",
2249         .parent         = &pad_slimbus_core_clks_ck,
2250         .recalc         = &followparent_recalc,
2251 };
2252
2253 static struct clk slimbus2_fck = {
2254         .name           = "slimbus2_fck",
2255         .ops            = &clkops_omap2_dflt,
2256         .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2257         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2258         .clkdm_name     = "l4_per_clkdm",
2259         .parent         = &l4_div_ck,
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk smartreflex_core_fck = {
2264         .name           = "smartreflex_core_fck",
2265         .ops            = &clkops_omap2_dflt,
2266         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2267         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2268         .clkdm_name     = "l4_ao_clkdm",
2269         .parent         = &l4_wkup_clk_mux_ck,
2270         .recalc         = &followparent_recalc,
2271 };
2272
2273 static struct clk smartreflex_iva_fck = {
2274         .name           = "smartreflex_iva_fck",
2275         .ops            = &clkops_omap2_dflt,
2276         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2277         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2278         .clkdm_name     = "l4_ao_clkdm",
2279         .parent         = &l4_wkup_clk_mux_ck,
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk smartreflex_mpu_fck = {
2284         .name           = "smartreflex_mpu_fck",
2285         .ops            = &clkops_omap2_dflt,
2286         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2287         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2288         .clkdm_name     = "l4_ao_clkdm",
2289         .parent         = &l4_wkup_clk_mux_ck,
2290         .recalc         = &followparent_recalc,
2291 };
2292
2293 /* Merged dmt1_clk_mux into timer1 */
2294 static struct clk timer1_fck = {
2295         .name           = "timer1_fck",
2296         .parent         = &sys_clkin_ck,
2297         .clksel         = abe_dpll_bypass_clk_mux_sel,
2298         .init           = &omap2_init_clksel_parent,
2299         .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2300         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2301         .ops            = &clkops_omap2_dflt,
2302         .recalc         = &omap2_clksel_recalc,
2303         .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2304         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2305         .clkdm_name     = "l4_wkup_clkdm",
2306 };
2307
2308 /* Merged cm2_dm10_mux into timer10 */
2309 static struct clk timer10_fck = {
2310         .name           = "timer10_fck",
2311         .parent         = &sys_clkin_ck,
2312         .clksel         = abe_dpll_bypass_clk_mux_sel,
2313         .init           = &omap2_init_clksel_parent,
2314         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2315         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2316         .ops            = &clkops_omap2_dflt,
2317         .recalc         = &omap2_clksel_recalc,
2318         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2319         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2320         .clkdm_name     = "l4_per_clkdm",
2321 };
2322
2323 /* Merged cm2_dm11_mux into timer11 */
2324 static struct clk timer11_fck = {
2325         .name           = "timer11_fck",
2326         .parent         = &sys_clkin_ck,
2327         .clksel         = abe_dpll_bypass_clk_mux_sel,
2328         .init           = &omap2_init_clksel_parent,
2329         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2330         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2331         .ops            = &clkops_omap2_dflt,
2332         .recalc         = &omap2_clksel_recalc,
2333         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2334         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2335         .clkdm_name     = "l4_per_clkdm",
2336 };
2337
2338 /* Merged cm2_dm2_mux into timer2 */
2339 static struct clk timer2_fck = {
2340         .name           = "timer2_fck",
2341         .parent         = &sys_clkin_ck,
2342         .clksel         = abe_dpll_bypass_clk_mux_sel,
2343         .init           = &omap2_init_clksel_parent,
2344         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2345         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2346         .ops            = &clkops_omap2_dflt,
2347         .recalc         = &omap2_clksel_recalc,
2348         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2349         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2350         .clkdm_name     = "l4_per_clkdm",
2351 };
2352
2353 /* Merged cm2_dm3_mux into timer3 */
2354 static struct clk timer3_fck = {
2355         .name           = "timer3_fck",
2356         .parent         = &sys_clkin_ck,
2357         .clksel         = abe_dpll_bypass_clk_mux_sel,
2358         .init           = &omap2_init_clksel_parent,
2359         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2360         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2361         .ops            = &clkops_omap2_dflt,
2362         .recalc         = &omap2_clksel_recalc,
2363         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2364         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2365         .clkdm_name     = "l4_per_clkdm",
2366 };
2367
2368 /* Merged cm2_dm4_mux into timer4 */
2369 static struct clk timer4_fck = {
2370         .name           = "timer4_fck",
2371         .parent         = &sys_clkin_ck,
2372         .clksel         = abe_dpll_bypass_clk_mux_sel,
2373         .init           = &omap2_init_clksel_parent,
2374         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2375         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2376         .ops            = &clkops_omap2_dflt,
2377         .recalc         = &omap2_clksel_recalc,
2378         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2379         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2380         .clkdm_name     = "l4_per_clkdm",
2381 };
2382
2383 static const struct clksel timer5_sync_mux_sel[] = {
2384         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2385         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2386         { .parent = NULL },
2387 };
2388
2389 /* Merged timer5_sync_mux into timer5 */
2390 static struct clk timer5_fck = {
2391         .name           = "timer5_fck",
2392         .parent         = &syc_clk_div_ck,
2393         .clksel         = timer5_sync_mux_sel,
2394         .init           = &omap2_init_clksel_parent,
2395         .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2396         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2397         .ops            = &clkops_omap2_dflt,
2398         .recalc         = &omap2_clksel_recalc,
2399         .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2400         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2401         .clkdm_name     = "abe_clkdm",
2402 };
2403
2404 /* Merged timer6_sync_mux into timer6 */
2405 static struct clk timer6_fck = {
2406         .name           = "timer6_fck",
2407         .parent         = &syc_clk_div_ck,
2408         .clksel         = timer5_sync_mux_sel,
2409         .init           = &omap2_init_clksel_parent,
2410         .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2411         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2412         .ops            = &clkops_omap2_dflt,
2413         .recalc         = &omap2_clksel_recalc,
2414         .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2415         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2416         .clkdm_name     = "abe_clkdm",
2417 };
2418
2419 /* Merged timer7_sync_mux into timer7 */
2420 static struct clk timer7_fck = {
2421         .name           = "timer7_fck",
2422         .parent         = &syc_clk_div_ck,
2423         .clksel         = timer5_sync_mux_sel,
2424         .init           = &omap2_init_clksel_parent,
2425         .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2426         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2427         .ops            = &clkops_omap2_dflt,
2428         .recalc         = &omap2_clksel_recalc,
2429         .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2430         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2431         .clkdm_name     = "abe_clkdm",
2432 };
2433
2434 /* Merged timer8_sync_mux into timer8 */
2435 static struct clk timer8_fck = {
2436         .name           = "timer8_fck",
2437         .parent         = &syc_clk_div_ck,
2438         .clksel         = timer5_sync_mux_sel,
2439         .init           = &omap2_init_clksel_parent,
2440         .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2441         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2442         .ops            = &clkops_omap2_dflt,
2443         .recalc         = &omap2_clksel_recalc,
2444         .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2445         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2446         .clkdm_name     = "abe_clkdm",
2447 };
2448
2449 /* Merged cm2_dm9_mux into timer9 */
2450 static struct clk timer9_fck = {
2451         .name           = "timer9_fck",
2452         .parent         = &sys_clkin_ck,
2453         .clksel         = abe_dpll_bypass_clk_mux_sel,
2454         .init           = &omap2_init_clksel_parent,
2455         .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2456         .clksel_mask    = OMAP4430_CLKSEL_MASK,
2457         .ops            = &clkops_omap2_dflt,
2458         .recalc         = &omap2_clksel_recalc,
2459         .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2460         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2461         .clkdm_name     = "l4_per_clkdm",
2462 };
2463
2464 static struct clk uart1_fck = {
2465         .name           = "uart1_fck",
2466         .ops            = &clkops_omap2_dflt,
2467         .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2468         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2469         .clkdm_name     = "l4_per_clkdm",
2470         .parent         = &func_48m_fclk,
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 static struct clk uart2_fck = {
2475         .name           = "uart2_fck",
2476         .ops            = &clkops_omap2_dflt,
2477         .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2478         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2479         .clkdm_name     = "l4_per_clkdm",
2480         .parent         = &func_48m_fclk,
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk uart3_fck = {
2485         .name           = "uart3_fck",
2486         .ops            = &clkops_omap2_dflt,
2487         .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2488         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2489         .clkdm_name     = "l4_per_clkdm",
2490         .parent         = &func_48m_fclk,
2491         .recalc         = &followparent_recalc,
2492 };
2493
2494 static struct clk uart4_fck = {
2495         .name           = "uart4_fck",
2496         .ops            = &clkops_omap2_dflt,
2497         .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2498         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2499         .clkdm_name     = "l4_per_clkdm",
2500         .parent         = &func_48m_fclk,
2501         .recalc         = &followparent_recalc,
2502 };
2503
2504 static struct clk usb_host_fs_fck = {
2505         .name           = "usb_host_fs_fck",
2506         .ops            = &clkops_omap2_dflt,
2507         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2508         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2509         .clkdm_name     = "l3_init_clkdm",
2510         .parent         = &func_48mc_fclk,
2511         .recalc         = &followparent_recalc,
2512 };
2513
2514 static const struct clksel utmi_p1_gfclk_sel[] = {
2515         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2516         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2517         { .parent = NULL },
2518 };
2519
2520 static struct clk utmi_p1_gfclk = {
2521         .name           = "utmi_p1_gfclk",
2522         .parent         = &init_60m_fclk,
2523         .clksel         = utmi_p1_gfclk_sel,
2524         .init           = &omap2_init_clksel_parent,
2525         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2526         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
2527         .ops            = &clkops_null,
2528         .recalc         = &omap2_clksel_recalc,
2529 };
2530
2531 static struct clk usb_host_hs_utmi_p1_clk = {
2532         .name           = "usb_host_hs_utmi_p1_clk",
2533         .ops            = &clkops_omap2_dflt,
2534         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2535         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2536         .clkdm_name     = "l3_init_clkdm",
2537         .parent         = &utmi_p1_gfclk,
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static const struct clksel utmi_p2_gfclk_sel[] = {
2542         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2543         { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2544         { .parent = NULL },
2545 };
2546
2547 static struct clk utmi_p2_gfclk = {
2548         .name           = "utmi_p2_gfclk",
2549         .parent         = &init_60m_fclk,
2550         .clksel         = utmi_p2_gfclk_sel,
2551         .init           = &omap2_init_clksel_parent,
2552         .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2553         .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
2554         .ops            = &clkops_null,
2555         .recalc         = &omap2_clksel_recalc,
2556 };
2557
2558 static struct clk usb_host_hs_utmi_p2_clk = {
2559         .name           = "usb_host_hs_utmi_p2_clk",
2560         .ops            = &clkops_omap2_dflt,
2561         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2562         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2563         .clkdm_name     = "l3_init_clkdm",
2564         .parent         = &utmi_p2_gfclk,
2565         .recalc         = &followparent_recalc,
2566 };
2567
2568 static struct clk usb_host_hs_utmi_p3_clk = {
2569         .name           = "usb_host_hs_utmi_p3_clk",
2570         .ops            = &clkops_omap2_dflt,
2571         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2572         .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2573         .clkdm_name     = "l3_init_clkdm",
2574         .parent         = &init_60m_fclk,
2575         .recalc         = &followparent_recalc,
2576 };
2577
2578 static struct clk usb_host_hs_hsic480m_p1_clk = {
2579         .name           = "usb_host_hs_hsic480m_p1_clk",
2580         .ops            = &clkops_omap2_dflt,
2581         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2582         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2583         .clkdm_name     = "l3_init_clkdm",
2584         .parent         = &dpll_usb_m2_ck,
2585         .recalc         = &followparent_recalc,
2586 };
2587
2588 static struct clk usb_host_hs_hsic60m_p1_clk = {
2589         .name           = "usb_host_hs_hsic60m_p1_clk",
2590         .ops            = &clkops_omap2_dflt,
2591         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2592         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2593         .clkdm_name     = "l3_init_clkdm",
2594         .parent         = &init_60m_fclk,
2595         .recalc         = &followparent_recalc,
2596 };
2597
2598 static struct clk usb_host_hs_hsic60m_p2_clk = {
2599         .name           = "usb_host_hs_hsic60m_p2_clk",
2600         .ops            = &clkops_omap2_dflt,
2601         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2602         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2603         .clkdm_name     = "l3_init_clkdm",
2604         .parent         = &init_60m_fclk,
2605         .recalc         = &followparent_recalc,
2606 };
2607
2608 static struct clk usb_host_hs_hsic480m_p2_clk = {
2609         .name           = "usb_host_hs_hsic480m_p2_clk",
2610         .ops            = &clkops_omap2_dflt,
2611         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2612         .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2613         .clkdm_name     = "l3_init_clkdm",
2614         .parent         = &dpll_usb_m2_ck,
2615         .recalc         = &followparent_recalc,
2616 };
2617
2618 static struct clk usb_host_hs_func48mclk = {
2619         .name           = "usb_host_hs_func48mclk",
2620         .ops            = &clkops_omap2_dflt,
2621         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2622         .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2623         .clkdm_name     = "l3_init_clkdm",
2624         .parent         = &func_48mc_fclk,
2625         .recalc         = &followparent_recalc,
2626 };
2627
2628 static struct clk usb_host_hs_fck = {
2629         .name           = "usb_host_hs_fck",
2630         .ops            = &clkops_omap2_dflt,
2631         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2632         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2633         .clkdm_name     = "l3_init_clkdm",
2634         .parent         = &init_60m_fclk,
2635         .recalc         = &followparent_recalc,
2636 };
2637
2638 static const struct clksel otg_60m_gfclk_sel[] = {
2639         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2640         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2641         { .parent = NULL },
2642 };
2643
2644 static struct clk otg_60m_gfclk = {
2645         .name           = "otg_60m_gfclk",
2646         .parent         = &utmi_phy_clkout_ck,
2647         .clksel         = otg_60m_gfclk_sel,
2648         .init           = &omap2_init_clksel_parent,
2649         .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2650         .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
2651         .ops            = &clkops_null,
2652         .recalc         = &omap2_clksel_recalc,
2653 };
2654
2655 static struct clk usb_otg_hs_xclk = {
2656         .name           = "usb_otg_hs_xclk",
2657         .ops            = &clkops_omap2_dflt,
2658         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2659         .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2660         .clkdm_name     = "l3_init_clkdm",
2661         .parent         = &otg_60m_gfclk,
2662         .recalc         = &followparent_recalc,
2663 };
2664
2665 static struct clk usb_otg_hs_ick = {
2666         .name           = "usb_otg_hs_ick",
2667         .ops            = &clkops_omap2_dflt,
2668         .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2669         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2670         .clkdm_name     = "l3_init_clkdm",
2671         .parent         = &l3_div_ck,
2672         .recalc         = &followparent_recalc,
2673 };
2674
2675 static struct clk usb_phy_cm_clk32k = {
2676         .name           = "usb_phy_cm_clk32k",
2677         .ops            = &clkops_omap2_dflt,
2678         .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2679         .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2680         .clkdm_name     = "l4_ao_clkdm",
2681         .parent         = &sys_32k_ck,
2682         .recalc         = &followparent_recalc,
2683 };
2684
2685 static struct clk usb_tll_hs_usb_ch2_clk = {
2686         .name           = "usb_tll_hs_usb_ch2_clk",
2687         .ops            = &clkops_omap2_dflt,
2688         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2689         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2690         .clkdm_name     = "l3_init_clkdm",
2691         .parent         = &init_60m_fclk,
2692         .recalc         = &followparent_recalc,
2693 };
2694
2695 static struct clk usb_tll_hs_usb_ch0_clk = {
2696         .name           = "usb_tll_hs_usb_ch0_clk",
2697         .ops            = &clkops_omap2_dflt,
2698         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2699         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2700         .clkdm_name     = "l3_init_clkdm",
2701         .parent         = &init_60m_fclk,
2702         .recalc         = &followparent_recalc,
2703 };
2704
2705 static struct clk usb_tll_hs_usb_ch1_clk = {
2706         .name           = "usb_tll_hs_usb_ch1_clk",
2707         .ops            = &clkops_omap2_dflt,
2708         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2709         .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2710         .clkdm_name     = "l3_init_clkdm",
2711         .parent         = &init_60m_fclk,
2712         .recalc         = &followparent_recalc,
2713 };
2714
2715 static struct clk usb_tll_hs_ick = {
2716         .name           = "usb_tll_hs_ick",
2717         .ops            = &clkops_omap2_dflt,
2718         .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2719         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2720         .clkdm_name     = "l3_init_clkdm",
2721         .parent         = &l4_div_ck,
2722         .recalc         = &followparent_recalc,
2723 };
2724
2725 static const struct clksel_rate div2_14to18_rates[] = {
2726         { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2727         { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2728         { .div = 0 },
2729 };
2730
2731 static const struct clksel usim_fclk_div[] = {
2732         { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2733         { .parent = NULL },
2734 };
2735
2736 static struct clk usim_ck = {
2737         .name           = "usim_ck",
2738         .parent         = &dpll_per_m4x2_ck,
2739         .clksel         = usim_fclk_div,
2740         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2741         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
2742         .ops            = &clkops_null,
2743         .recalc         = &omap2_clksel_recalc,
2744         .round_rate     = &omap2_clksel_round_rate,
2745         .set_rate       = &omap2_clksel_set_rate,
2746 };
2747
2748 static struct clk usim_fclk = {
2749         .name           = "usim_fclk",
2750         .ops            = &clkops_omap2_dflt,
2751         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2752         .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2753         .clkdm_name     = "l4_wkup_clkdm",
2754         .parent         = &usim_ck,
2755         .recalc         = &followparent_recalc,
2756 };
2757
2758 static struct clk usim_fck = {
2759         .name           = "usim_fck",
2760         .ops            = &clkops_omap2_dflt,
2761         .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2762         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
2763         .clkdm_name     = "l4_wkup_clkdm",
2764         .parent         = &sys_32k_ck,
2765         .recalc         = &followparent_recalc,
2766 };
2767
2768 static struct clk wd_timer2_fck = {
2769         .name           = "wd_timer2_fck",
2770         .ops            = &clkops_omap2_dflt,
2771         .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2772         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2773         .clkdm_name     = "l4_wkup_clkdm",
2774         .parent         = &sys_32k_ck,
2775         .recalc         = &followparent_recalc,
2776 };
2777
2778 static struct clk wd_timer3_fck = {
2779         .name           = "wd_timer3_fck",
2780         .ops            = &clkops_omap2_dflt,
2781         .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2782         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
2783         .clkdm_name     = "abe_clkdm",
2784         .parent         = &sys_32k_ck,
2785         .recalc         = &followparent_recalc,
2786 };
2787
2788 /* Remaining optional clocks */
2789 static const struct clksel stm_clk_div_div[] = {
2790         { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2791         { .parent = NULL },
2792 };
2793
2794 static struct clk stm_clk_div_ck = {
2795         .name           = "stm_clk_div_ck",
2796         .parent         = &pmd_stm_clock_mux_ck,
2797         .clksel         = stm_clk_div_div,
2798         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2799         .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2800         .ops            = &clkops_null,
2801         .recalc         = &omap2_clksel_recalc,
2802         .round_rate     = &omap2_clksel_round_rate,
2803         .set_rate       = &omap2_clksel_set_rate,
2804 };
2805
2806 static const struct clksel trace_clk_div_div[] = {
2807         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2808         { .parent = NULL },
2809 };
2810
2811 static struct clk trace_clk_div_ck = {
2812         .name           = "trace_clk_div_ck",
2813         .parent         = &pmd_trace_clk_mux_ck,
2814         .clksel         = trace_clk_div_div,
2815         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2816         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2817         .ops            = &clkops_null,
2818         .recalc         = &omap2_clksel_recalc,
2819         .round_rate     = &omap2_clksel_round_rate,
2820         .set_rate       = &omap2_clksel_set_rate,
2821 };
2822
2823 /* SCRM aux clk nodes */
2824
2825 static const struct clksel auxclk_src_sel[] = {
2826         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2827         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2828         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2829         { .parent = NULL },
2830 };
2831
2832 static const struct clksel_rate div16_1to16_rates[] = {
2833         { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2834         { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2835         { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2836         { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2837         { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2838         { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2839         { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2840         { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2841         { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2842         { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2843         { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2844         { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2845         { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2846         { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2847         { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2848         { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2849         { .div = 0 },
2850 };
2851
2852 static struct clk auxclk0_src_ck = {
2853         .name           = "auxclk0_src_ck",
2854         .parent         = &sys_clkin_ck,
2855         .init           = &omap2_init_clksel_parent,
2856         .ops            = &clkops_omap2_dflt,
2857         .clksel         = auxclk_src_sel,
2858         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2859         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2860         .recalc         = &omap2_clksel_recalc,
2861         .enable_reg     = OMAP4_SCRM_AUXCLK0,
2862         .enable_bit     = OMAP4_ENABLE_SHIFT,
2863 };
2864
2865 static const struct clksel auxclk0_sel[] = {
2866         { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2867         { .parent = NULL },
2868 };
2869
2870 static struct clk auxclk0_ck = {
2871         .name           = "auxclk0_ck",
2872         .parent         = &auxclk0_src_ck,
2873         .clksel         = auxclk0_sel,
2874         .clksel_reg     = OMAP4_SCRM_AUXCLK0,
2875         .clksel_mask    = OMAP4_CLKDIV_MASK,
2876         .ops            = &clkops_null,
2877         .recalc         = &omap2_clksel_recalc,
2878         .round_rate     = &omap2_clksel_round_rate,
2879         .set_rate       = &omap2_clksel_set_rate,
2880 };
2881
2882 static struct clk auxclk1_src_ck = {
2883         .name           = "auxclk1_src_ck",
2884         .parent         = &sys_clkin_ck,
2885         .init           = &omap2_init_clksel_parent,
2886         .ops            = &clkops_omap2_dflt,
2887         .clksel         = auxclk_src_sel,
2888         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2889         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2890         .recalc         = &omap2_clksel_recalc,
2891         .enable_reg     = OMAP4_SCRM_AUXCLK1,
2892         .enable_bit     = OMAP4_ENABLE_SHIFT,
2893 };
2894
2895 static const struct clksel auxclk1_sel[] = {
2896         { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2897         { .parent = NULL },
2898 };
2899
2900 static struct clk auxclk1_ck = {
2901         .name           = "auxclk1_ck",
2902         .parent         = &auxclk1_src_ck,
2903         .clksel         = auxclk1_sel,
2904         .clksel_reg     = OMAP4_SCRM_AUXCLK1,
2905         .clksel_mask    = OMAP4_CLKDIV_MASK,
2906         .ops            = &clkops_null,
2907         .recalc         = &omap2_clksel_recalc,
2908         .round_rate     = &omap2_clksel_round_rate,
2909         .set_rate       = &omap2_clksel_set_rate,
2910 };
2911
2912 static struct clk auxclk2_src_ck = {
2913         .name           = "auxclk2_src_ck",
2914         .parent         = &sys_clkin_ck,
2915         .init           = &omap2_init_clksel_parent,
2916         .ops            = &clkops_omap2_dflt,
2917         .clksel         = auxclk_src_sel,
2918         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2919         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2920         .recalc         = &omap2_clksel_recalc,
2921         .enable_reg     = OMAP4_SCRM_AUXCLK2,
2922         .enable_bit     = OMAP4_ENABLE_SHIFT,
2923 };
2924
2925 static const struct clksel auxclk2_sel[] = {
2926         { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2927         { .parent = NULL },
2928 };
2929
2930 static struct clk auxclk2_ck = {
2931         .name           = "auxclk2_ck",
2932         .parent         = &auxclk2_src_ck,
2933         .clksel         = auxclk2_sel,
2934         .clksel_reg     = OMAP4_SCRM_AUXCLK2,
2935         .clksel_mask    = OMAP4_CLKDIV_MASK,
2936         .ops            = &clkops_null,
2937         .recalc         = &omap2_clksel_recalc,
2938         .round_rate     = &omap2_clksel_round_rate,
2939         .set_rate       = &omap2_clksel_set_rate,
2940 };
2941
2942 static struct clk auxclk3_src_ck = {
2943         .name           = "auxclk3_src_ck",
2944         .parent         = &sys_clkin_ck,
2945         .init           = &omap2_init_clksel_parent,
2946         .ops            = &clkops_omap2_dflt,
2947         .clksel         = auxclk_src_sel,
2948         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2949         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2950         .recalc         = &omap2_clksel_recalc,
2951         .enable_reg     = OMAP4_SCRM_AUXCLK3,
2952         .enable_bit     = OMAP4_ENABLE_SHIFT,
2953 };
2954
2955 static const struct clksel auxclk3_sel[] = {
2956         { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2957         { .parent = NULL },
2958 };
2959
2960 static struct clk auxclk3_ck = {
2961         .name           = "auxclk3_ck",
2962         .parent         = &auxclk3_src_ck,
2963         .clksel         = auxclk3_sel,
2964         .clksel_reg     = OMAP4_SCRM_AUXCLK3,
2965         .clksel_mask    = OMAP4_CLKDIV_MASK,
2966         .ops            = &clkops_null,
2967         .recalc         = &omap2_clksel_recalc,
2968         .round_rate     = &omap2_clksel_round_rate,
2969         .set_rate       = &omap2_clksel_set_rate,
2970 };
2971
2972 static struct clk auxclk4_src_ck = {
2973         .name           = "auxclk4_src_ck",
2974         .parent         = &sys_clkin_ck,
2975         .init           = &omap2_init_clksel_parent,
2976         .ops            = &clkops_omap2_dflt,
2977         .clksel         = auxclk_src_sel,
2978         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2979         .clksel_mask    = OMAP4_SRCSELECT_MASK,
2980         .recalc         = &omap2_clksel_recalc,
2981         .enable_reg     = OMAP4_SCRM_AUXCLK4,
2982         .enable_bit     = OMAP4_ENABLE_SHIFT,
2983 };
2984
2985 static const struct clksel auxclk4_sel[] = {
2986         { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2987         { .parent = NULL },
2988 };
2989
2990 static struct clk auxclk4_ck = {
2991         .name           = "auxclk4_ck",
2992         .parent         = &auxclk4_src_ck,
2993         .clksel         = auxclk4_sel,
2994         .clksel_reg     = OMAP4_SCRM_AUXCLK4,
2995         .clksel_mask    = OMAP4_CLKDIV_MASK,
2996         .ops            = &clkops_null,
2997         .recalc         = &omap2_clksel_recalc,
2998         .round_rate     = &omap2_clksel_round_rate,
2999         .set_rate       = &omap2_clksel_set_rate,
3000 };
3001
3002 static struct clk auxclk5_src_ck = {
3003         .name           = "auxclk5_src_ck",
3004         .parent         = &sys_clkin_ck,
3005         .init           = &omap2_init_clksel_parent,
3006         .ops            = &clkops_omap2_dflt,
3007         .clksel         = auxclk_src_sel,
3008         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
3009         .clksel_mask    = OMAP4_SRCSELECT_MASK,
3010         .recalc         = &omap2_clksel_recalc,
3011         .enable_reg     = OMAP4_SCRM_AUXCLK5,
3012         .enable_bit     = OMAP4_ENABLE_SHIFT,
3013 };
3014
3015 static const struct clksel auxclk5_sel[] = {
3016         { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3017         { .parent = NULL },
3018 };
3019
3020 static struct clk auxclk5_ck = {
3021         .name           = "auxclk5_ck",
3022         .parent         = &auxclk5_src_ck,
3023         .clksel         = auxclk5_sel,
3024         .clksel_reg     = OMAP4_SCRM_AUXCLK5,
3025         .clksel_mask    = OMAP4_CLKDIV_MASK,
3026         .ops            = &clkops_null,
3027         .recalc         = &omap2_clksel_recalc,
3028         .round_rate     = &omap2_clksel_round_rate,
3029         .set_rate       = &omap2_clksel_set_rate,
3030 };
3031
3032 static const struct clksel auxclkreq_sel[] = {
3033         { .parent = &auxclk0_ck, .rates = div_1_0_rates },
3034         { .parent = &auxclk1_ck, .rates = div_1_1_rates },
3035         { .parent = &auxclk2_ck, .rates = div_1_2_rates },
3036         { .parent = &auxclk3_ck, .rates = div_1_3_rates },
3037         { .parent = &auxclk4_ck, .rates = div_1_4_rates },
3038         { .parent = &auxclk5_ck, .rates = div_1_5_rates },
3039         { .parent = NULL },
3040 };
3041
3042 static struct clk auxclkreq0_ck = {
3043         .name           = "auxclkreq0_ck",
3044         .parent         = &auxclk0_ck,
3045         .init           = &omap2_init_clksel_parent,
3046         .ops            = &clkops_null,
3047         .clksel         = auxclkreq_sel,
3048         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
3049         .clksel_mask    = OMAP4_MAPPING_MASK,
3050         .recalc         = &omap2_clksel_recalc,
3051 };
3052
3053 static struct clk auxclkreq1_ck = {
3054         .name           = "auxclkreq1_ck",
3055         .parent         = &auxclk1_ck,
3056         .init           = &omap2_init_clksel_parent,
3057         .ops            = &clkops_null,
3058         .clksel         = auxclkreq_sel,
3059         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
3060         .clksel_mask    = OMAP4_MAPPING_MASK,
3061         .recalc         = &omap2_clksel_recalc,
3062 };
3063
3064 static struct clk auxclkreq2_ck = {
3065         .name           = "auxclkreq2_ck",
3066         .parent         = &auxclk2_ck,
3067         .init           = &omap2_init_clksel_parent,
3068         .ops            = &clkops_null,
3069         .clksel         = auxclkreq_sel,
3070         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
3071         .clksel_mask    = OMAP4_MAPPING_MASK,
3072         .recalc         = &omap2_clksel_recalc,
3073 };
3074
3075 static struct clk auxclkreq3_ck = {
3076         .name           = "auxclkreq3_ck",
3077         .parent         = &auxclk3_ck,
3078         .init           = &omap2_init_clksel_parent,
3079         .ops            = &clkops_null,
3080         .clksel         = auxclkreq_sel,
3081         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
3082         .clksel_mask    = OMAP4_MAPPING_MASK,
3083         .recalc         = &omap2_clksel_recalc,
3084 };
3085
3086 static struct clk auxclkreq4_ck = {
3087         .name           = "auxclkreq4_ck",
3088         .parent         = &auxclk4_ck,
3089         .init           = &omap2_init_clksel_parent,
3090         .ops            = &clkops_null,
3091         .clksel         = auxclkreq_sel,
3092         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
3093         .clksel_mask    = OMAP4_MAPPING_MASK,
3094         .recalc         = &omap2_clksel_recalc,
3095 };
3096
3097 static struct clk auxclkreq5_ck = {
3098         .name           = "auxclkreq5_ck",
3099         .parent         = &auxclk5_ck,
3100         .init           = &omap2_init_clksel_parent,
3101         .ops            = &clkops_null,
3102         .clksel         = auxclkreq_sel,
3103         .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
3104         .clksel_mask    = OMAP4_MAPPING_MASK,
3105         .recalc         = &omap2_clksel_recalc,
3106 };
3107
3108 /*
3109  * clkdev
3110  */
3111
3112 static struct omap_clk omap44xx_clks[] = {
3113         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
3114         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
3115         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
3116         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
3117         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
3118         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
3119         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
3120         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
3121         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
3122         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
3123         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
3124         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
3125         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
3126         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
3127         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
3128         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
3129         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
3130         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
3131         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
3132         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
3133         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
3134         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
3135         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
3136         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
3137         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
3138         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
3139         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
3140         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
3141         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
3142         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
3143         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
3144         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
3145         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
3146         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
3147         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
3148         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
3149         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
3150         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
3151         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
3152         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
3153         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
3154         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
3155         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
3156         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
3157         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
3158         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
3159         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
3160         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
3161         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
3162         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
3163         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
3164         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
3165         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
3166         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
3167         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
3168         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
3169         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
3170         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
3171         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
3172         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
3173         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
3174         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
3175         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
3176         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
3177         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
3178         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
3179         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
3180         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
3181         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
3182         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
3183         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
3184         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
3185         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
3186         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
3187         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
3188         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
3189         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
3190         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
3191         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
3192         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
3193         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
3194         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
3195         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
3196         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
3197         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
3198         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
3199         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
3200         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
3201         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
3202         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
3203         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
3204         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
3205         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
3206         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
3207         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
3208         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
3209         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
3210         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
3211         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
3212         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
3213         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
3214         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
3215         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
3216         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
3217         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
3218         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
3219         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
3220         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
3221         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
3222         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
3223         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
3224         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
3225         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
3226         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
3227         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
3228         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
3229         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
3230         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
3231         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
3232         CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
3233         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
3234         CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
3235         CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
3236         CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
3237         CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
3238         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
3239         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
3240         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
3241         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
3242         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
3243         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
3244         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
3245         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
3246         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
3247         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
3248         CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
3249         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
3250         CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
3251         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
3252         CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
3253         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
3254         CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
3255         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
3256         CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
3257         CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
3258         CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
3259         CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
3260         CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
3261         CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
3262         CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
3263         CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
3264         CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
3265         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
3266         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
3267         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
3268         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
3269         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
3270         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
3271         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
3272         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
3273         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
3274         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
3275         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
3276         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
3277         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
3278         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
3279         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
3280         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
3281         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
3282         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
3283         CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
3284         CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
3285         CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
3286         CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
3287         CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
3288         CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
3289         CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
3290         CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
3291         CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
3292         CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
3293         CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
3294         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
3295         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
3296         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
3297         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
3298         CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
3299         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
3300         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
3301         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
3302         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
3303         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
3304         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
3305         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
3306         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
3307         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
3308         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
3309         CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
3310         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
3311         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
3312         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
3313         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
3314         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
3315         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
3316         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
3317         CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
3318         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
3319         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
3320         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
3321         CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
3322         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
3323         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
3324         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
3325         CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
3326         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
3327         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
3328         CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
3329         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
3330         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
3331         CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
3332         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
3333         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
3334         CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
3335         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
3336         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
3337         CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
3338         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
3339         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
3340         CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
3341         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
3342         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
3343         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
3344         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
3345         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
3346         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
3347         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
3348         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
3349         CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
3350         CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
3351         CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
3352         CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
3353         CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
3354         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
3355         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
3356         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
3357         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
3358         CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
3359         CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
3360         CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
3361         CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
3362         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
3363         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
3364         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
3365         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
3366         CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
3367         CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
3368         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
3369         CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
3370         CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
3371         CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
3372         CLK("omap_timer.4",     "32k_ck",       &sys_32k_ck,    CK_443X),
3373         CLK("omap_timer.5",     "32k_ck",       &sys_32k_ck,    CK_443X),
3374         CLK("omap_timer.6",     "32k_ck",       &sys_32k_ck,    CK_443X),
3375         CLK("omap_timer.7",     "32k_ck",       &sys_32k_ck,    CK_443X),
3376         CLK("omap_timer.8",     "32k_ck",       &sys_32k_ck,    CK_443X),
3377         CLK("omap_timer.9",     "32k_ck",       &sys_32k_ck,    CK_443X),
3378         CLK("omap_timer.10",    "32k_ck",       &sys_32k_ck,    CK_443X),
3379         CLK("omap_timer.11",    "32k_ck",       &sys_32k_ck,    CK_443X),
3380         CLK("omap_timer.1",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3381         CLK("omap_timer.2",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3382         CLK("omap_timer.3",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3383         CLK("omap_timer.4",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3384         CLK("omap_timer.9",     "sys_ck",       &sys_clkin_ck,  CK_443X),
3385         CLK("omap_timer.10",    "sys_ck",       &sys_clkin_ck,  CK_443X),
3386         CLK("omap_timer.11",    "sys_ck",       &sys_clkin_ck,  CK_443X),
3387         CLK("omap_timer.5",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3388         CLK("omap_timer.6",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3389         CLK("omap_timer.7",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3390         CLK("omap_timer.8",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
3391 };
3392
3393 int __init omap4xxx_clk_init(void)
3394 {
3395         struct omap_clk *c;
3396         u32 cpu_clkflg;
3397
3398         if (cpu_is_omap443x()) {
3399                 cpu_mask = RATE_IN_4430;
3400                 cpu_clkflg = CK_443X;
3401         } else if (cpu_is_omap446x()) {
3402                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3403                 cpu_clkflg = CK_446X | CK_443X;
3404         } else {
3405                 return 0;
3406         }
3407
3408         clk_init(&omap2_clk_functions);
3409
3410         /*
3411          * Must stay commented until all OMAP SoC drivers are
3412          * converted to runtime PM, or drivers may start crashing
3413          *
3414          * omap2_clk_disable_clkdm_control();
3415          */
3416
3417         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3418                                                                           c++)
3419                 clk_preinit(c->lk.clk);
3420
3421         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3422                                                                           c++)
3423                 if (c->cpu & cpu_clkflg) {
3424                         clkdev_add(&c->lk);
3425                         clk_register(c->lk.clk);
3426                         omap2_init_clk_clkdm(c->lk.clk);
3427                 }
3428
3429         /* Disable autoidle on all clocks; let the PM code enable it later */
3430         omap_clk_disable_autoidle_all();
3431
3432         recalculate_root_clocks();
3433
3434         /*
3435          * Only enable those clocks we will need, let the drivers
3436          * enable other clocks as necessary
3437          */
3438         clk_enable_init_clocks();
3439
3440         return 0;
3441 }